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authorJoe Perches <joe@perches.com>2010-11-29 02:41:58 -0500
committerDavid S. Miller <davem@davemloft.net>2010-11-29 14:44:54 -0500
commitc41d41e1687dcf344f55dd15c7121532e5c195d4 (patch)
tree3b712dd2f626232e5294ca883824d9aaae7897c7 /drivers/net/forcedeth.c
parent1d397f3698ec438c3c14abf45bfac88cca1882d9 (diff)
forcedeth: Add function init_realtek_8211b
Deduplicate the code use for the init/reset of this device. Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/forcedeth.c')
-rw-r--r--drivers/net/forcedeth.c105
1 files changed, 32 insertions, 73 deletions
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index c3a9783b7c46..300748ccc5c1 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -1181,6 +1181,33 @@ static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1181 return 0; 1181 return 0;
1182} 1182}
1183 1183
1184static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np)
1185{
1186 static const struct {
1187 int reg;
1188 int init;
1189 } ri[] = {
1190 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1191 { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 },
1192 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 },
1193 { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 },
1194 { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 },
1195 { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 },
1196 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1197 };
1198 int i;
1199
1200 for (i = 0; i < ARRAY_SIZE(ri); i++) {
1201 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init)) {
1202 netdev_info(dev, "%s: phy init failed\n",
1203 pci_name(np->pci_dev));
1204 return PHY_ERROR;
1205 }
1206 }
1207
1208 return 0;
1209}
1210
1184static int phy_init(struct net_device *dev) 1211static int phy_init(struct net_device *dev)
1185{ 1212{
1186 struct fe_priv *np = get_nvpriv(dev); 1213 struct fe_priv *np = get_nvpriv(dev);
@@ -1200,44 +1227,10 @@ static int phy_init(struct net_device *dev)
1200 if (np->phy_oui == PHY_OUI_REALTEK) { 1227 if (np->phy_oui == PHY_OUI_REALTEK) {
1201 if (np->phy_model == PHY_MODEL_REALTEK_8211 && 1228 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1202 np->phy_rev == PHY_REV_REALTEK_8211B) { 1229 np->phy_rev == PHY_REV_REALTEK_8211B) {
1203 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { 1230 if (init_realtek_8211b(dev, np))
1204 netdev_info(dev, "%s: phy init failed\n",
1205 pci_name(np->pci_dev));
1206 return PHY_ERROR;
1207 }
1208 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1209 netdev_info(dev, "%s: phy init failed\n",
1210 pci_name(np->pci_dev));
1211 return PHY_ERROR;
1212 }
1213 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1214 netdev_info(dev, "%s: phy init failed\n",
1215 pci_name(np->pci_dev));
1216 return PHY_ERROR;
1217 }
1218 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1219 netdev_info(dev, "%s: phy init failed\n",
1220 pci_name(np->pci_dev));
1221 return PHY_ERROR;
1222 }
1223 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1224 netdev_info(dev, "%s: phy init failed\n",
1225 pci_name(np->pci_dev));
1226 return PHY_ERROR;
1227 }
1228 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1229 netdev_info(dev, "%s: phy init failed\n",
1230 pci_name(np->pci_dev));
1231 return PHY_ERROR;
1232 }
1233 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1234 netdev_info(dev, "%s: phy init failed\n",
1235 pci_name(np->pci_dev));
1236 return PHY_ERROR; 1231 return PHY_ERROR;
1237 } 1232 } else if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1238 } 1233 np->phy_rev == PHY_REV_REALTEK_8211C) {
1239 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1240 np->phy_rev == PHY_REV_REALTEK_8211C) {
1241 u32 powerstate = readl(base + NvRegPowerState2); 1234 u32 powerstate = readl(base + NvRegPowerState2);
1242 1235
1243 /* need to perform hw phy reset */ 1236 /* need to perform hw phy reset */
@@ -1459,43 +1452,9 @@ static int phy_init(struct net_device *dev)
1459 if (np->phy_model == PHY_MODEL_REALTEK_8211 && 1452 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1460 np->phy_rev == PHY_REV_REALTEK_8211B) { 1453 np->phy_rev == PHY_REV_REALTEK_8211B) {
1461 /* reset could have cleared these out, set them back */ 1454 /* reset could have cleared these out, set them back */
1462 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { 1455 if (init_realtek_8211b(dev, np))
1463 netdev_info(dev, "%s: phy init failed\n",
1464 pci_name(np->pci_dev));
1465 return PHY_ERROR; 1456 return PHY_ERROR;
1466 } 1457 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1467 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1468 netdev_info(dev, "%s: phy init failed\n",
1469 pci_name(np->pci_dev));
1470 return PHY_ERROR;
1471 }
1472 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1473 netdev_info(dev, "%s: phy init failed\n",
1474 pci_name(np->pci_dev));
1475 return PHY_ERROR;
1476 }
1477 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1478 netdev_info(dev, "%s: phy init failed\n",
1479 pci_name(np->pci_dev));
1480 return PHY_ERROR;
1481 }
1482 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1483 netdev_info(dev, "%s: phy init failed\n",
1484 pci_name(np->pci_dev));
1485 return PHY_ERROR;
1486 }
1487 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1488 netdev_info(dev, "%s: phy init failed\n",
1489 pci_name(np->pci_dev));
1490 return PHY_ERROR;
1491 }
1492 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1493 netdev_info(dev, "%s: phy init failed\n",
1494 pci_name(np->pci_dev));
1495 return PHY_ERROR;
1496 }
1497 }
1498 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1499 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) { 1458 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1500 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); 1459 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1501 phy_reserved |= PHY_REALTEK_INIT7; 1460 phy_reserved |= PHY_REALTEK_INIT7;