Merge branch 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/netdev-2.6

* 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/netdev-2.6: (37 commits)
  forcedeth bug fix: realtek phy
  forcedeth bug fix: vitesse phy
  forcedeth bug fix: cicada phy
  atl1: reorder atl1_main functions
  atl1: fix excessively indented code
  atl1: cleanup atl1_main
  atl1: header file cleanup
  atl1: remove irq_sem
  cdc-subset to support new vendor/product ID
  8139cp: implement the missing dev->tx_timeout
  myri10ge: Remove nonsensical limit in the tx done routine
  gianfar: kill unused header
  EP93XX_ETH must select MII
  macb: Add multicast capability
  macb: Use generic PHY layer
  s390: add barriers to qeth driver
  s390: scatter-gather for inbound traffic in qeth driver
  eHEA: Introducing support vor DLPAR memory add
  Fix a potential NULL pointer dereference in free_shared_mem() in drivers/net/s2io.c
  [PATCH] softmac: Fix ESSID problem
  ...

1 files changed, 152 insertions, 10 deletions

diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index 67046e8c21eb..136827f8dc2e 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -550,6 +550,8 @@ union ring_type {
 /* PHY defines */
 #define PHY_OUI_MARVELL 0x5043
 #define PHY_OUI_CICADA  0x03f1
+#define PHY_OUI_VITESSE 0x01c1
+#define PHY_OUI_REALTEK 0x01c1
 #define PHYID1_OUI_MASK 0x03ff
 #define PHYID1_OUI_SHFT 6
 #define PHYID2_OUI_MASK 0xfc00
@@ -557,12 +559,36 @@ union ring_type {
 #define PHYID2_MODEL_MASK               0x03f0
 #define PHY_MODEL_MARVELL_E3016         0x220
 #define PHY_MARVELL_E3016_INITMASK      0x0300
-#define PHY_INIT1       0x0f000
-#define PHY_INIT2       0x0e00
-#define PHY_INIT3       0x01000
-#define PHY_INIT4       0x0200
-#define PHY_INIT5       0x0004
-#define PHY_INIT6       0x02000
+#define PHY_CICADA_INIT1        0x0f000
+#define PHY_CICADA_INIT2        0x0e00
+#define PHY_CICADA_INIT3        0x01000
+#define PHY_CICADA_INIT4        0x0200
+#define PHY_CICADA_INIT5        0x0004
+#define PHY_CICADA_INIT6        0x02000
+#define PHY_VITESSE_INIT_REG1   0x1f
+#define PHY_VITESSE_INIT_REG2   0x10
+#define PHY_VITESSE_INIT_REG3   0x11
+#define PHY_VITESSE_INIT_REG4   0x12
+#define PHY_VITESSE_INIT_MSK1   0xc
+#define PHY_VITESSE_INIT_MSK2   0x0180
+#define PHY_VITESSE_INIT1       0x52b5
+#define PHY_VITESSE_INIT2       0xaf8a
+#define PHY_VITESSE_INIT3       0x8
+#define PHY_VITESSE_INIT4       0x8f8a
+#define PHY_VITESSE_INIT5       0xaf86
+#define PHY_VITESSE_INIT6       0x8f86
+#define PHY_VITESSE_INIT7       0xaf82
+#define PHY_VITESSE_INIT8       0x0100
+#define PHY_VITESSE_INIT9       0x8f82
+#define PHY_VITESSE_INIT10      0x0
+#define PHY_REALTEK_INIT_REG1   0x1f
+#define PHY_REALTEK_INIT_REG2   0x19
+#define PHY_REALTEK_INIT_REG3   0x13
+#define PHY_REALTEK_INIT1       0x0000
+#define PHY_REALTEK_INIT2       0x8e00
+#define PHY_REALTEK_INIT3       0x0001
+#define PHY_REALTEK_INIT4       0xad17
+
 #define PHY_GIGABIT     0x0100
 
 #define PHY_TIMEOUT     0x1
@@ -1096,6 +1122,28 @@ static int phy_init(struct net_device *dev)
                         return PHY_ERROR;
                 }
         }
+        if (np->phy_oui == PHY_OUI_REALTEK) {
+                if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
+                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                        return PHY_ERROR;
+                }
+                if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
+                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                        return PHY_ERROR;
+                }
+                if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
+                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                        return PHY_ERROR;
+                }
+                if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
+                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                        return PHY_ERROR;
+                }
+                if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
+                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                        return PHY_ERROR;
+                }
+        }
 
         /* set advertise register */
         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
@@ -1141,14 +1189,14 @@ static int phy_init(struct net_device *dev)
         /* phy vendor specific configuration */
         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
-                phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
-                phy_reserved |= (PHY_INIT3 | PHY_INIT4);
+                phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
+                phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
                         return PHY_ERROR;
                 }
                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
-                phy_reserved |= PHY_INIT5;
+                phy_reserved |= PHY_CICADA_INIT5;
                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
                         return PHY_ERROR;
@@ -1156,12 +1204,106 @@ static int phy_init(struct net_device *dev)
         }
         if (np->phy_oui == PHY_OUI_CICADA) {
                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
-                phy_reserved |= PHY_INIT6;
+                phy_reserved |= PHY_CICADA_INIT6;
                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
                         return PHY_ERROR;
                 }
         }
+        if (np->phy_oui == PHY_OUI_VITESSE) {
+                if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
+                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                        return PHY_ERROR;
+                }
+                if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
+                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                        return PHY_ERROR;
+                }
+                phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
+                if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
+                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                        return PHY_ERROR;
+                }
+                phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
+                phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
+                phy_reserved |= PHY_VITESSE_INIT3;
+                if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
+                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                        return PHY_ERROR;
+                }
+                if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
+                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                        return PHY_ERROR;
+                }
+                if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
+                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                        return PHY_ERROR;
+                }
+                phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
+                phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
+                phy_reserved |= PHY_VITESSE_INIT3;
+                if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
+                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                        return PHY_ERROR;
+                }
+                phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
+                if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
+                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                        return PHY_ERROR;
+                }
+                if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
+                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                        return PHY_ERROR;
+                }
+                if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
+                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                        return PHY_ERROR;
+                }
+                phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
+                if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
+                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                        return PHY_ERROR;
+                }
+                phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
+                phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
+                phy_reserved |= PHY_VITESSE_INIT8;
+                if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
+                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                        return PHY_ERROR;
+                }
+                if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
+                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                        return PHY_ERROR;
+                }
+                if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
+                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                        return PHY_ERROR;
+                }
+        }
+        if (np->phy_oui == PHY_OUI_REALTEK) {
+                /* reset could have cleared these out, set them back */
+                if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
+                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                        return PHY_ERROR;
+                }
+                if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
+                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                        return PHY_ERROR;
+                }
+                if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
+                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                        return PHY_ERROR;
+                }
+                if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
+                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                        return PHY_ERROR;
+                }
+                if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
+                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                        return PHY_ERROR;
+                }
+        }
+
         /* some phys clear out pause advertisment on reset, set it back */
         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);