diff options
author | Joe Perches <joe@perches.com> | 2010-11-29 02:41:57 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2010-11-29 14:44:54 -0500 |
commit | 1d397f3698ec438c3c14abf45bfac88cca1882d9 (patch) | |
tree | f402bc9ea3872a331257b51cbead33c0b4fb9fb8 /drivers/net/forcedeth.c | |
parent | 294a554e274f961ac33c7d739d5b912bd0005f5b (diff) |
forcedeth: Convert pr_<level> to netdev_<level>
Use netdev_<level> when a struct net_device * is available.
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/forcedeth.c')
-rw-r--r-- | drivers/net/forcedeth.c | 293 |
1 files changed, 161 insertions, 132 deletions
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c index 1c6f4ef9f928..c3a9783b7c46 100644 --- a/drivers/net/forcedeth.c +++ b/drivers/net/forcedeth.c | |||
@@ -1192,8 +1192,8 @@ static int phy_init(struct net_device *dev) | |||
1192 | reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); | 1192 | reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); |
1193 | reg &= ~PHY_MARVELL_E3016_INITMASK; | 1193 | reg &= ~PHY_MARVELL_E3016_INITMASK; |
1194 | if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) { | 1194 | if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) { |
1195 | pr_info("%s: phy write to errata reg failed\n", | 1195 | netdev_info(dev, "%s: phy write to errata reg failed\n", |
1196 | pci_name(np->pci_dev)); | 1196 | pci_name(np->pci_dev)); |
1197 | return PHY_ERROR; | 1197 | return PHY_ERROR; |
1198 | } | 1198 | } |
1199 | } | 1199 | } |
@@ -1201,38 +1201,38 @@ static int phy_init(struct net_device *dev) | |||
1201 | if (np->phy_model == PHY_MODEL_REALTEK_8211 && | 1201 | if (np->phy_model == PHY_MODEL_REALTEK_8211 && |
1202 | np->phy_rev == PHY_REV_REALTEK_8211B) { | 1202 | np->phy_rev == PHY_REV_REALTEK_8211B) { |
1203 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | 1203 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { |
1204 | pr_info("%s: phy init failed\n", | 1204 | netdev_info(dev, "%s: phy init failed\n", |
1205 | pci_name(np->pci_dev)); | 1205 | pci_name(np->pci_dev)); |
1206 | return PHY_ERROR; | 1206 | return PHY_ERROR; |
1207 | } | 1207 | } |
1208 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) { | 1208 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) { |
1209 | pr_info("%s: phy init failed\n", | 1209 | netdev_info(dev, "%s: phy init failed\n", |
1210 | pci_name(np->pci_dev)); | 1210 | pci_name(np->pci_dev)); |
1211 | return PHY_ERROR; | 1211 | return PHY_ERROR; |
1212 | } | 1212 | } |
1213 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) { | 1213 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) { |
1214 | pr_info("%s: phy init failed\n", | 1214 | netdev_info(dev, "%s: phy init failed\n", |
1215 | pci_name(np->pci_dev)); | 1215 | pci_name(np->pci_dev)); |
1216 | return PHY_ERROR; | 1216 | return PHY_ERROR; |
1217 | } | 1217 | } |
1218 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) { | 1218 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) { |
1219 | pr_info("%s: phy init failed\n", | 1219 | netdev_info(dev, "%s: phy init failed\n", |
1220 | pci_name(np->pci_dev)); | 1220 | pci_name(np->pci_dev)); |
1221 | return PHY_ERROR; | 1221 | return PHY_ERROR; |
1222 | } | 1222 | } |
1223 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) { | 1223 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) { |
1224 | pr_info("%s: phy init failed\n", | 1224 | netdev_info(dev, "%s: phy init failed\n", |
1225 | pci_name(np->pci_dev)); | 1225 | pci_name(np->pci_dev)); |
1226 | return PHY_ERROR; | 1226 | return PHY_ERROR; |
1227 | } | 1227 | } |
1228 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) { | 1228 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) { |
1229 | pr_info("%s: phy init failed\n", | 1229 | netdev_info(dev, "%s: phy init failed\n", |
1230 | pci_name(np->pci_dev)); | 1230 | pci_name(np->pci_dev)); |
1231 | return PHY_ERROR; | 1231 | return PHY_ERROR; |
1232 | } | 1232 | } |
1233 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | 1233 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { |
1234 | pr_info("%s: phy init failed\n", | 1234 | netdev_info(dev, "%s: phy init failed\n", |
1235 | pci_name(np->pci_dev)); | 1235 | pci_name(np->pci_dev)); |
1236 | return PHY_ERROR; | 1236 | return PHY_ERROR; |
1237 | } | 1237 | } |
1238 | } | 1238 | } |
@@ -1252,27 +1252,27 @@ static int phy_init(struct net_device *dev) | |||
1252 | reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); | 1252 | reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); |
1253 | reg |= PHY_REALTEK_INIT9; | 1253 | reg |= PHY_REALTEK_INIT9; |
1254 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) { | 1254 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) { |
1255 | pr_info("%s: phy init failed\n", | 1255 | netdev_info(dev, "%s: phy init failed\n", |
1256 | pci_name(np->pci_dev)); | 1256 | pci_name(np->pci_dev)); |
1257 | return PHY_ERROR; | 1257 | return PHY_ERROR; |
1258 | } | 1258 | } |
1259 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) { | 1259 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) { |
1260 | pr_info("%s: phy init failed\n", | 1260 | netdev_info(dev, "%s: phy init failed\n", |
1261 | pci_name(np->pci_dev)); | 1261 | pci_name(np->pci_dev)); |
1262 | return PHY_ERROR; | 1262 | return PHY_ERROR; |
1263 | } | 1263 | } |
1264 | reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ); | 1264 | reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ); |
1265 | if (!(reg & PHY_REALTEK_INIT11)) { | 1265 | if (!(reg & PHY_REALTEK_INIT11)) { |
1266 | reg |= PHY_REALTEK_INIT11; | 1266 | reg |= PHY_REALTEK_INIT11; |
1267 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) { | 1267 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) { |
1268 | pr_info("%s: phy init failed\n", | 1268 | netdev_info(dev, "%s: phy init failed\n", |
1269 | pci_name(np->pci_dev)); | 1269 | pci_name(np->pci_dev)); |
1270 | return PHY_ERROR; | 1270 | return PHY_ERROR; |
1271 | } | 1271 | } |
1272 | } | 1272 | } |
1273 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | 1273 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { |
1274 | pr_info("%s: phy init failed\n", | 1274 | netdev_info(dev, "%s: phy init failed\n", |
1275 | pci_name(np->pci_dev)); | 1275 | pci_name(np->pci_dev)); |
1276 | return PHY_ERROR; | 1276 | return PHY_ERROR; |
1277 | } | 1277 | } |
1278 | } | 1278 | } |
@@ -1281,8 +1281,8 @@ static int phy_init(struct net_device *dev) | |||
1281 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); | 1281 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); |
1282 | phy_reserved |= PHY_REALTEK_INIT7; | 1282 | phy_reserved |= PHY_REALTEK_INIT7; |
1283 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) { | 1283 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) { |
1284 | pr_info("%s: phy init failed\n", | 1284 | netdev_info(dev, "%s: phy init failed\n", |
1285 | pci_name(np->pci_dev)); | 1285 | pci_name(np->pci_dev)); |
1286 | return PHY_ERROR; | 1286 | return PHY_ERROR; |
1287 | } | 1287 | } |
1288 | } | 1288 | } |
@@ -1293,8 +1293,8 @@ static int phy_init(struct net_device *dev) | |||
1293 | reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | 1293 | reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
1294 | reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP); | 1294 | reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP); |
1295 | if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { | 1295 | if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { |
1296 | pr_info("%s: phy write to advertise failed\n", | 1296 | netdev_info(dev, "%s: phy write to advertise failed\n", |
1297 | pci_name(np->pci_dev)); | 1297 | pci_name(np->pci_dev)); |
1298 | return PHY_ERROR; | 1298 | return PHY_ERROR; |
1299 | } | 1299 | } |
1300 | 1300 | ||
@@ -1313,7 +1313,8 @@ static int phy_init(struct net_device *dev) | |||
1313 | mii_control_1000 &= ~ADVERTISE_1000FULL; | 1313 | mii_control_1000 &= ~ADVERTISE_1000FULL; |
1314 | 1314 | ||
1315 | if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) { | 1315 | if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) { |
1316 | pr_info("%s: phy init failed\n", pci_name(np->pci_dev)); | 1316 | netdev_info(dev, "%s: phy init failed\n", |
1317 | pci_name(np->pci_dev)); | ||
1317 | return PHY_ERROR; | 1318 | return PHY_ERROR; |
1318 | } | 1319 | } |
1319 | } else | 1320 | } else |
@@ -1328,7 +1329,8 @@ static int phy_init(struct net_device *dev) | |||
1328 | /* start autoneg since we already performed hw reset above */ | 1329 | /* start autoneg since we already performed hw reset above */ |
1329 | mii_control |= BMCR_ANRESTART; | 1330 | mii_control |= BMCR_ANRESTART; |
1330 | if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { | 1331 | if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { |
1331 | pr_info("%s: phy init failed\n", pci_name(np->pci_dev)); | 1332 | netdev_info(dev, "%s: phy init failed\n", |
1333 | pci_name(np->pci_dev)); | ||
1332 | return PHY_ERROR; | 1334 | return PHY_ERROR; |
1333 | } | 1335 | } |
1334 | } else { | 1336 | } else { |
@@ -1336,7 +1338,8 @@ static int phy_init(struct net_device *dev) | |||
1336 | * (certain phys need bmcr to be setup with reset) | 1338 | * (certain phys need bmcr to be setup with reset) |
1337 | */ | 1339 | */ |
1338 | if (phy_reset(dev, mii_control)) { | 1340 | if (phy_reset(dev, mii_control)) { |
1339 | pr_info("%s: phy reset failed\n", pci_name(np->pci_dev)); | 1341 | netdev_info(dev, "%s: phy reset failed\n", |
1342 | pci_name(np->pci_dev)); | ||
1340 | return PHY_ERROR; | 1343 | return PHY_ERROR; |
1341 | } | 1344 | } |
1342 | } | 1345 | } |
@@ -1347,13 +1350,15 @@ static int phy_init(struct net_device *dev) | |||
1347 | phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2); | 1350 | phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2); |
1348 | phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4); | 1351 | phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4); |
1349 | if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) { | 1352 | if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) { |
1350 | pr_info("%s: phy init failed\n", pci_name(np->pci_dev)); | 1353 | netdev_info(dev, "%s: phy init failed\n", |
1354 | pci_name(np->pci_dev)); | ||
1351 | return PHY_ERROR; | 1355 | return PHY_ERROR; |
1352 | } | 1356 | } |
1353 | phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); | 1357 | phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); |
1354 | phy_reserved |= PHY_CICADA_INIT5; | 1358 | phy_reserved |= PHY_CICADA_INIT5; |
1355 | if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) { | 1359 | if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) { |
1356 | pr_info("%s: phy init failed\n", pci_name(np->pci_dev)); | 1360 | netdev_info(dev, "%s: phy init failed\n", |
1361 | pci_name(np->pci_dev)); | ||
1357 | return PHY_ERROR; | 1362 | return PHY_ERROR; |
1358 | } | 1363 | } |
1359 | } | 1364 | } |
@@ -1361,77 +1366,92 @@ static int phy_init(struct net_device *dev) | |||
1361 | phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ); | 1366 | phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ); |
1362 | phy_reserved |= PHY_CICADA_INIT6; | 1367 | phy_reserved |= PHY_CICADA_INIT6; |
1363 | if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) { | 1368 | if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) { |
1364 | pr_info("%s: phy init failed\n", pci_name(np->pci_dev)); | 1369 | netdev_info(dev, "%s: phy init failed\n", |
1370 | pci_name(np->pci_dev)); | ||
1365 | return PHY_ERROR; | 1371 | return PHY_ERROR; |
1366 | } | 1372 | } |
1367 | } | 1373 | } |
1368 | if (np->phy_oui == PHY_OUI_VITESSE) { | 1374 | if (np->phy_oui == PHY_OUI_VITESSE) { |
1369 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) { | 1375 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) { |
1370 | pr_info("%s: phy init failed\n", pci_name(np->pci_dev)); | 1376 | netdev_info(dev, "%s: phy init failed\n", |
1377 | pci_name(np->pci_dev)); | ||
1371 | return PHY_ERROR; | 1378 | return PHY_ERROR; |
1372 | } | 1379 | } |
1373 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) { | 1380 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) { |
1374 | pr_info("%s: phy init failed\n", pci_name(np->pci_dev)); | 1381 | netdev_info(dev, "%s: phy init failed\n", |
1382 | pci_name(np->pci_dev)); | ||
1375 | return PHY_ERROR; | 1383 | return PHY_ERROR; |
1376 | } | 1384 | } |
1377 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); | 1385 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); |
1378 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { | 1386 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { |
1379 | pr_info("%s: phy init failed\n", pci_name(np->pci_dev)); | 1387 | netdev_info(dev, "%s: phy init failed\n", |
1388 | pci_name(np->pci_dev)); | ||
1380 | return PHY_ERROR; | 1389 | return PHY_ERROR; |
1381 | } | 1390 | } |
1382 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); | 1391 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); |
1383 | phy_reserved &= ~PHY_VITESSE_INIT_MSK1; | 1392 | phy_reserved &= ~PHY_VITESSE_INIT_MSK1; |
1384 | phy_reserved |= PHY_VITESSE_INIT3; | 1393 | phy_reserved |= PHY_VITESSE_INIT3; |
1385 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { | 1394 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { |
1386 | pr_info("%s: phy init failed\n", pci_name(np->pci_dev)); | 1395 | netdev_info(dev, "%s: phy init failed\n", |
1396 | pci_name(np->pci_dev)); | ||
1387 | return PHY_ERROR; | 1397 | return PHY_ERROR; |
1388 | } | 1398 | } |
1389 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) { | 1399 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) { |
1390 | pr_info("%s: phy init failed\n", pci_name(np->pci_dev)); | 1400 | netdev_info(dev, "%s: phy init failed\n", |
1401 | pci_name(np->pci_dev)); | ||
1391 | return PHY_ERROR; | 1402 | return PHY_ERROR; |
1392 | } | 1403 | } |
1393 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) { | 1404 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) { |
1394 | pr_info("%s: phy init failed\n", pci_name(np->pci_dev)); | 1405 | netdev_info(dev, "%s: phy init failed\n", |
1406 | pci_name(np->pci_dev)); | ||
1395 | return PHY_ERROR; | 1407 | return PHY_ERROR; |
1396 | } | 1408 | } |
1397 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); | 1409 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); |
1398 | phy_reserved &= ~PHY_VITESSE_INIT_MSK1; | 1410 | phy_reserved &= ~PHY_VITESSE_INIT_MSK1; |
1399 | phy_reserved |= PHY_VITESSE_INIT3; | 1411 | phy_reserved |= PHY_VITESSE_INIT3; |
1400 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { | 1412 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { |
1401 | pr_info("%s: phy init failed\n", pci_name(np->pci_dev)); | 1413 | netdev_info(dev, "%s: phy init failed\n", |
1414 | pci_name(np->pci_dev)); | ||
1402 | return PHY_ERROR; | 1415 | return PHY_ERROR; |
1403 | } | 1416 | } |
1404 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); | 1417 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); |
1405 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { | 1418 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { |
1406 | pr_info("%s: phy init failed\n", pci_name(np->pci_dev)); | 1419 | netdev_info(dev, "%s: phy init failed\n", |
1420 | pci_name(np->pci_dev)); | ||
1407 | return PHY_ERROR; | 1421 | return PHY_ERROR; |
1408 | } | 1422 | } |
1409 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) { | 1423 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) { |
1410 | pr_info("%s: phy init failed\n", pci_name(np->pci_dev)); | 1424 | netdev_info(dev, "%s: phy init failed\n", |
1425 | pci_name(np->pci_dev)); | ||
1411 | return PHY_ERROR; | 1426 | return PHY_ERROR; |
1412 | } | 1427 | } |
1413 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) { | 1428 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) { |
1414 | pr_info("%s: phy init failed\n", pci_name(np->pci_dev)); | 1429 | netdev_info(dev, "%s: phy init failed\n", |
1430 | pci_name(np->pci_dev)); | ||
1415 | return PHY_ERROR; | 1431 | return PHY_ERROR; |
1416 | } | 1432 | } |
1417 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); | 1433 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); |
1418 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { | 1434 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { |
1419 | pr_info("%s: phy init failed\n", pci_name(np->pci_dev)); | 1435 | netdev_info(dev, "%s: phy init failed\n", |
1436 | pci_name(np->pci_dev)); | ||
1420 | return PHY_ERROR; | 1437 | return PHY_ERROR; |
1421 | } | 1438 | } |
1422 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); | 1439 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); |
1423 | phy_reserved &= ~PHY_VITESSE_INIT_MSK2; | 1440 | phy_reserved &= ~PHY_VITESSE_INIT_MSK2; |
1424 | phy_reserved |= PHY_VITESSE_INIT8; | 1441 | phy_reserved |= PHY_VITESSE_INIT8; |
1425 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { | 1442 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { |
1426 | pr_info("%s: phy init failed\n", pci_name(np->pci_dev)); | 1443 | netdev_info(dev, "%s: phy init failed\n", |
1444 | pci_name(np->pci_dev)); | ||
1427 | return PHY_ERROR; | 1445 | return PHY_ERROR; |
1428 | } | 1446 | } |
1429 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) { | 1447 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) { |
1430 | pr_info("%s: phy init failed\n", pci_name(np->pci_dev)); | 1448 | netdev_info(dev, "%s: phy init failed\n", |
1449 | pci_name(np->pci_dev)); | ||
1431 | return PHY_ERROR; | 1450 | return PHY_ERROR; |
1432 | } | 1451 | } |
1433 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) { | 1452 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) { |
1434 | pr_info("%s: phy init failed\n", pci_name(np->pci_dev)); | 1453 | netdev_info(dev, "%s: phy init failed\n", |
1454 | pci_name(np->pci_dev)); | ||
1435 | return PHY_ERROR; | 1455 | return PHY_ERROR; |
1436 | } | 1456 | } |
1437 | } | 1457 | } |
@@ -1440,38 +1460,38 @@ static int phy_init(struct net_device *dev) | |||
1440 | np->phy_rev == PHY_REV_REALTEK_8211B) { | 1460 | np->phy_rev == PHY_REV_REALTEK_8211B) { |
1441 | /* reset could have cleared these out, set them back */ | 1461 | /* reset could have cleared these out, set them back */ |
1442 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | 1462 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { |
1443 | pr_info("%s: phy init failed\n", | 1463 | netdev_info(dev, "%s: phy init failed\n", |
1444 | pci_name(np->pci_dev)); | 1464 | pci_name(np->pci_dev)); |
1445 | return PHY_ERROR; | 1465 | return PHY_ERROR; |
1446 | } | 1466 | } |
1447 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) { | 1467 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) { |
1448 | pr_info("%s: phy init failed\n", | 1468 | netdev_info(dev, "%s: phy init failed\n", |
1449 | pci_name(np->pci_dev)); | 1469 | pci_name(np->pci_dev)); |
1450 | return PHY_ERROR; | 1470 | return PHY_ERROR; |
1451 | } | 1471 | } |
1452 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) { | 1472 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) { |
1453 | pr_info("%s: phy init failed\n", | 1473 | netdev_info(dev, "%s: phy init failed\n", |
1454 | pci_name(np->pci_dev)); | 1474 | pci_name(np->pci_dev)); |
1455 | return PHY_ERROR; | 1475 | return PHY_ERROR; |
1456 | } | 1476 | } |
1457 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) { | 1477 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) { |
1458 | pr_info("%s: phy init failed\n", | 1478 | netdev_info(dev, "%s: phy init failed\n", |
1459 | pci_name(np->pci_dev)); | 1479 | pci_name(np->pci_dev)); |
1460 | return PHY_ERROR; | 1480 | return PHY_ERROR; |
1461 | } | 1481 | } |
1462 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) { | 1482 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) { |
1463 | pr_info("%s: phy init failed\n", | 1483 | netdev_info(dev, "%s: phy init failed\n", |
1464 | pci_name(np->pci_dev)); | 1484 | pci_name(np->pci_dev)); |
1465 | return PHY_ERROR; | 1485 | return PHY_ERROR; |
1466 | } | 1486 | } |
1467 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) { | 1487 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) { |
1468 | pr_info("%s: phy init failed\n", | 1488 | netdev_info(dev, "%s: phy init failed\n", |
1469 | pci_name(np->pci_dev)); | 1489 | pci_name(np->pci_dev)); |
1470 | return PHY_ERROR; | 1490 | return PHY_ERROR; |
1471 | } | 1491 | } |
1472 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | 1492 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { |
1473 | pr_info("%s: phy init failed\n", | 1493 | netdev_info(dev, "%s: phy init failed\n", |
1474 | pci_name(np->pci_dev)); | 1494 | pci_name(np->pci_dev)); |
1475 | return PHY_ERROR; | 1495 | return PHY_ERROR; |
1476 | } | 1496 | } |
1477 | } | 1497 | } |
@@ -1480,28 +1500,28 @@ static int phy_init(struct net_device *dev) | |||
1480 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); | 1500 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); |
1481 | phy_reserved |= PHY_REALTEK_INIT7; | 1501 | phy_reserved |= PHY_REALTEK_INIT7; |
1482 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) { | 1502 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) { |
1483 | pr_info("%s: phy init failed\n", | 1503 | netdev_info(dev, "%s: phy init failed\n", |
1484 | pci_name(np->pci_dev)); | 1504 | pci_name(np->pci_dev)); |
1485 | return PHY_ERROR; | 1505 | return PHY_ERROR; |
1486 | } | 1506 | } |
1487 | } | 1507 | } |
1488 | if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) { | 1508 | if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) { |
1489 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) { | 1509 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) { |
1490 | pr_info("%s: phy init failed\n", | 1510 | netdev_info(dev, "%s: phy init failed\n", |
1491 | pci_name(np->pci_dev)); | 1511 | pci_name(np->pci_dev)); |
1492 | return PHY_ERROR; | 1512 | return PHY_ERROR; |
1493 | } | 1513 | } |
1494 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ); | 1514 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ); |
1495 | phy_reserved &= ~PHY_REALTEK_INIT_MSK1; | 1515 | phy_reserved &= ~PHY_REALTEK_INIT_MSK1; |
1496 | phy_reserved |= PHY_REALTEK_INIT3; | 1516 | phy_reserved |= PHY_REALTEK_INIT3; |
1497 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) { | 1517 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) { |
1498 | pr_info("%s: phy init failed\n", | 1518 | netdev_info(dev, "%s: phy init failed\n", |
1499 | pci_name(np->pci_dev)); | 1519 | pci_name(np->pci_dev)); |
1500 | return PHY_ERROR; | 1520 | return PHY_ERROR; |
1501 | } | 1521 | } |
1502 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | 1522 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { |
1503 | pr_info("%s: phy init failed\n", | 1523 | netdev_info(dev, "%s: phy init failed\n", |
1504 | pci_name(np->pci_dev)); | 1524 | pci_name(np->pci_dev)); |
1505 | return PHY_ERROR; | 1525 | return PHY_ERROR; |
1506 | } | 1526 | } |
1507 | } | 1527 | } |
@@ -1560,7 +1580,8 @@ static void nv_stop_rx(struct net_device *dev) | |||
1560 | writel(rx_ctrl, base + NvRegReceiverControl); | 1580 | writel(rx_ctrl, base + NvRegReceiverControl); |
1561 | if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0, | 1581 | if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0, |
1562 | NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX)) | 1582 | NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX)) |
1563 | pr_info("%s: ReceiverStatus remained busy\n", __func__); | 1583 | netdev_info(dev, "%s: ReceiverStatus remained busy\n", |
1584 | __func__); | ||
1564 | 1585 | ||
1565 | udelay(NV_RXSTOP_DELAY2); | 1586 | udelay(NV_RXSTOP_DELAY2); |
1566 | if (!np->mac_in_use) | 1587 | if (!np->mac_in_use) |
@@ -1595,7 +1616,8 @@ static void nv_stop_tx(struct net_device *dev) | |||
1595 | writel(tx_ctrl, base + NvRegTransmitterControl); | 1616 | writel(tx_ctrl, base + NvRegTransmitterControl); |
1596 | if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0, | 1617 | if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0, |
1597 | NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX)) | 1618 | NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX)) |
1598 | pr_info("%s: TransmitterStatus remained busy\n", __func__); | 1619 | netdev_info(dev, "%s: TransmitterStatus remained busy\n", |
1620 | __func__); | ||
1599 | 1621 | ||
1600 | udelay(NV_TXSTOP_DELAY2); | 1622 | udelay(NV_TXSTOP_DELAY2); |
1601 | if (!np->mac_in_use) | 1623 | if (!np->mac_in_use) |
@@ -2520,46 +2542,49 @@ static void nv_tx_timeout(struct net_device *dev) | |||
2520 | else | 2542 | else |
2521 | status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; | 2543 | status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; |
2522 | 2544 | ||
2523 | pr_info("%s: Got tx_timeout. irq: %08x\n", dev->name, status); | 2545 | netdev_info(dev, "Got tx_timeout. irq: %08x\n", status); |
2524 | 2546 | ||
2525 | pr_info("%s: Ring at %lx\n", dev->name, (unsigned long)np->ring_addr); | 2547 | netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr); |
2526 | pr_info("%s: Dumping tx registers\n", dev->name); | 2548 | netdev_info(dev, "Dumping tx registers\n"); |
2527 | for (i = 0; i <= np->register_size; i += 32) { | 2549 | for (i = 0; i <= np->register_size; i += 32) { |
2528 | pr_info("%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n", | 2550 | netdev_info(dev, |
2529 | i, | 2551 | "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n", |
2530 | readl(base + i + 0), readl(base + i + 4), | 2552 | i, |
2531 | readl(base + i + 8), readl(base + i + 12), | 2553 | readl(base + i + 0), readl(base + i + 4), |
2532 | readl(base + i + 16), readl(base + i + 20), | 2554 | readl(base + i + 8), readl(base + i + 12), |
2533 | readl(base + i + 24), readl(base + i + 28)); | 2555 | readl(base + i + 16), readl(base + i + 20), |
2534 | } | 2556 | readl(base + i + 24), readl(base + i + 28)); |
2535 | pr_info("%s: Dumping tx ring\n", dev->name); | 2557 | } |
2558 | netdev_info(dev, "Dumping tx ring\n"); | ||
2536 | for (i = 0; i < np->tx_ring_size; i += 4) { | 2559 | for (i = 0; i < np->tx_ring_size; i += 4) { |
2537 | if (!nv_optimized(np)) { | 2560 | if (!nv_optimized(np)) { |
2538 | pr_info("%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n", | 2561 | netdev_info(dev, |
2539 | i, | 2562 | "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n", |
2540 | le32_to_cpu(np->tx_ring.orig[i].buf), | 2563 | i, |
2541 | le32_to_cpu(np->tx_ring.orig[i].flaglen), | 2564 | le32_to_cpu(np->tx_ring.orig[i].buf), |
2542 | le32_to_cpu(np->tx_ring.orig[i+1].buf), | 2565 | le32_to_cpu(np->tx_ring.orig[i].flaglen), |
2543 | le32_to_cpu(np->tx_ring.orig[i+1].flaglen), | 2566 | le32_to_cpu(np->tx_ring.orig[i+1].buf), |
2544 | le32_to_cpu(np->tx_ring.orig[i+2].buf), | 2567 | le32_to_cpu(np->tx_ring.orig[i+1].flaglen), |
2545 | le32_to_cpu(np->tx_ring.orig[i+2].flaglen), | 2568 | le32_to_cpu(np->tx_ring.orig[i+2].buf), |
2546 | le32_to_cpu(np->tx_ring.orig[i+3].buf), | 2569 | le32_to_cpu(np->tx_ring.orig[i+2].flaglen), |
2547 | le32_to_cpu(np->tx_ring.orig[i+3].flaglen)); | 2570 | le32_to_cpu(np->tx_ring.orig[i+3].buf), |
2571 | le32_to_cpu(np->tx_ring.orig[i+3].flaglen)); | ||
2548 | } else { | 2572 | } else { |
2549 | pr_info("%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n", | 2573 | netdev_info(dev, |
2550 | i, | 2574 | "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n", |
2551 | le32_to_cpu(np->tx_ring.ex[i].bufhigh), | 2575 | i, |
2552 | le32_to_cpu(np->tx_ring.ex[i].buflow), | 2576 | le32_to_cpu(np->tx_ring.ex[i].bufhigh), |
2553 | le32_to_cpu(np->tx_ring.ex[i].flaglen), | 2577 | le32_to_cpu(np->tx_ring.ex[i].buflow), |
2554 | le32_to_cpu(np->tx_ring.ex[i+1].bufhigh), | 2578 | le32_to_cpu(np->tx_ring.ex[i].flaglen), |
2555 | le32_to_cpu(np->tx_ring.ex[i+1].buflow), | 2579 | le32_to_cpu(np->tx_ring.ex[i+1].bufhigh), |
2556 | le32_to_cpu(np->tx_ring.ex[i+1].flaglen), | 2580 | le32_to_cpu(np->tx_ring.ex[i+1].buflow), |
2557 | le32_to_cpu(np->tx_ring.ex[i+2].bufhigh), | 2581 | le32_to_cpu(np->tx_ring.ex[i+1].flaglen), |
2558 | le32_to_cpu(np->tx_ring.ex[i+2].buflow), | 2582 | le32_to_cpu(np->tx_ring.ex[i+2].bufhigh), |
2559 | le32_to_cpu(np->tx_ring.ex[i+2].flaglen), | 2583 | le32_to_cpu(np->tx_ring.ex[i+2].buflow), |
2560 | le32_to_cpu(np->tx_ring.ex[i+3].bufhigh), | 2584 | le32_to_cpu(np->tx_ring.ex[i+2].flaglen), |
2561 | le32_to_cpu(np->tx_ring.ex[i+3].buflow), | 2585 | le32_to_cpu(np->tx_ring.ex[i+3].bufhigh), |
2562 | le32_to_cpu(np->tx_ring.ex[i+3].flaglen)); | 2586 | le32_to_cpu(np->tx_ring.ex[i+3].buflow), |
2587 | le32_to_cpu(np->tx_ring.ex[i+3].flaglen)); | ||
2563 | } | 2588 | } |
2564 | } | 2589 | } |
2565 | 2590 | ||
@@ -3332,14 +3357,14 @@ static void nv_linkchange(struct net_device *dev) | |||
3332 | if (nv_update_linkspeed(dev)) { | 3357 | if (nv_update_linkspeed(dev)) { |
3333 | if (!netif_carrier_ok(dev)) { | 3358 | if (!netif_carrier_ok(dev)) { |
3334 | netif_carrier_on(dev); | 3359 | netif_carrier_on(dev); |
3335 | pr_info("%s: link up\n", dev->name); | 3360 | netdev_info(dev, "link up\n"); |
3336 | nv_txrx_gate(dev, false); | 3361 | nv_txrx_gate(dev, false); |
3337 | nv_start_rx(dev); | 3362 | nv_start_rx(dev); |
3338 | } | 3363 | } |
3339 | } else { | 3364 | } else { |
3340 | if (netif_carrier_ok(dev)) { | 3365 | if (netif_carrier_ok(dev)) { |
3341 | netif_carrier_off(dev); | 3366 | netif_carrier_off(dev); |
3342 | pr_info("%s: link down\n", dev->name); | 3367 | netdev_info(dev, "link down\n"); |
3343 | nv_txrx_gate(dev, true); | 3368 | nv_txrx_gate(dev, true); |
3344 | nv_stop_rx(dev); | 3369 | nv_stop_rx(dev); |
3345 | } | 3370 | } |
@@ -3788,8 +3813,9 @@ static int nv_request_irq(struct net_device *dev, int intr_test) | |||
3788 | sprintf(np->name_rx, "%s-rx", dev->name); | 3813 | sprintf(np->name_rx, "%s-rx", dev->name); |
3789 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, | 3814 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, |
3790 | nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) { | 3815 | nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) { |
3791 | pr_info("request_irq failed for rx %d\n", | 3816 | netdev_info(dev, |
3792 | ret); | 3817 | "request_irq failed for rx %d\n", |
3818 | ret); | ||
3793 | pci_disable_msix(np->pci_dev); | 3819 | pci_disable_msix(np->pci_dev); |
3794 | np->msi_flags &= ~NV_MSI_X_ENABLED; | 3820 | np->msi_flags &= ~NV_MSI_X_ENABLED; |
3795 | goto out_err; | 3821 | goto out_err; |
@@ -3798,8 +3824,9 @@ static int nv_request_irq(struct net_device *dev, int intr_test) | |||
3798 | sprintf(np->name_tx, "%s-tx", dev->name); | 3824 | sprintf(np->name_tx, "%s-tx", dev->name); |
3799 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, | 3825 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, |
3800 | nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) { | 3826 | nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) { |
3801 | pr_info("request_irq failed for tx %d\n", | 3827 | netdev_info(dev, |
3802 | ret); | 3828 | "request_irq failed for tx %d\n", |
3829 | ret); | ||
3803 | pci_disable_msix(np->pci_dev); | 3830 | pci_disable_msix(np->pci_dev); |
3804 | np->msi_flags &= ~NV_MSI_X_ENABLED; | 3831 | np->msi_flags &= ~NV_MSI_X_ENABLED; |
3805 | goto out_free_rx; | 3832 | goto out_free_rx; |
@@ -3808,8 +3835,9 @@ static int nv_request_irq(struct net_device *dev, int intr_test) | |||
3808 | sprintf(np->name_other, "%s-other", dev->name); | 3835 | sprintf(np->name_other, "%s-other", dev->name); |
3809 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, | 3836 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, |
3810 | nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) { | 3837 | nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) { |
3811 | pr_info("request_irq failed for link %d\n", | 3838 | netdev_info(dev, |
3812 | ret); | 3839 | "request_irq failed for link %d\n", |
3840 | ret); | ||
3813 | pci_disable_msix(np->pci_dev); | 3841 | pci_disable_msix(np->pci_dev); |
3814 | np->msi_flags &= ~NV_MSI_X_ENABLED; | 3842 | np->msi_flags &= ~NV_MSI_X_ENABLED; |
3815 | goto out_free_tx; | 3843 | goto out_free_tx; |
@@ -3823,7 +3851,9 @@ static int nv_request_irq(struct net_device *dev, int intr_test) | |||
3823 | } else { | 3851 | } else { |
3824 | /* Request irq for all interrupts */ | 3852 | /* Request irq for all interrupts */ |
3825 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) { | 3853 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) { |
3826 | pr_info("request_irq failed %d\n", ret); | 3854 | netdev_info(dev, |
3855 | "request_irq failed %d\n", | ||
3856 | ret); | ||
3827 | pci_disable_msix(np->pci_dev); | 3857 | pci_disable_msix(np->pci_dev); |
3828 | np->msi_flags &= ~NV_MSI_X_ENABLED; | 3858 | np->msi_flags &= ~NV_MSI_X_ENABLED; |
3829 | goto out_err; | 3859 | goto out_err; |
@@ -3841,7 +3871,8 @@ static int nv_request_irq(struct net_device *dev, int intr_test) | |||
3841 | np->msi_flags |= NV_MSI_ENABLED; | 3871 | np->msi_flags |= NV_MSI_ENABLED; |
3842 | dev->irq = np->pci_dev->irq; | 3872 | dev->irq = np->pci_dev->irq; |
3843 | if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) { | 3873 | if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) { |
3844 | pr_info("request_irq failed %d\n", ret); | 3874 | netdev_info(dev, "request_irq failed %d\n", |
3875 | ret); | ||
3845 | pci_disable_msi(np->pci_dev); | 3876 | pci_disable_msi(np->pci_dev); |
3846 | np->msi_flags &= ~NV_MSI_ENABLED; | 3877 | np->msi_flags &= ~NV_MSI_ENABLED; |
3847 | dev->irq = np->pci_dev->irq; | 3878 | dev->irq = np->pci_dev->irq; |
@@ -3926,7 +3957,7 @@ static void nv_do_nic_poll(unsigned long data) | |||
3926 | 3957 | ||
3927 | if (np->recover_error) { | 3958 | if (np->recover_error) { |
3928 | np->recover_error = 0; | 3959 | np->recover_error = 0; |
3929 | pr_info("%s: MAC in recoverable error state\n", dev->name); | 3960 | netdev_info(dev, "MAC in recoverable error state\n"); |
3930 | if (netif_running(dev)) { | 3961 | if (netif_running(dev)) { |
3931 | netif_tx_lock_bh(dev); | 3962 | netif_tx_lock_bh(dev); |
3932 | netif_addr_lock(dev); | 3963 | netif_addr_lock(dev); |
@@ -4222,14 +4253,14 @@ static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |||
4222 | } | 4253 | } |
4223 | 4254 | ||
4224 | if (netif_running(dev)) | 4255 | if (netif_running(dev)) |
4225 | pr_info("%s: link down\n", dev->name); | 4256 | netdev_info(dev, "link down\n"); |
4226 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | 4257 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
4227 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { | 4258 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { |
4228 | bmcr |= BMCR_ANENABLE; | 4259 | bmcr |= BMCR_ANENABLE; |
4229 | /* reset the phy in order for settings to stick, | 4260 | /* reset the phy in order for settings to stick, |
4230 | * and cause autoneg to start */ | 4261 | * and cause autoneg to start */ |
4231 | if (phy_reset(dev, bmcr)) { | 4262 | if (phy_reset(dev, bmcr)) { |
4232 | pr_info("%s: phy reset failed\n", dev->name); | 4263 | netdev_info(dev, "phy reset failed\n"); |
4233 | return -EINVAL; | 4264 | return -EINVAL; |
4234 | } | 4265 | } |
4235 | } else { | 4266 | } else { |
@@ -4278,7 +4309,7 @@ static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |||
4278 | if (np->phy_oui == PHY_OUI_MARVELL) { | 4309 | if (np->phy_oui == PHY_OUI_MARVELL) { |
4279 | /* reset the phy in order for forced mode settings to stick */ | 4310 | /* reset the phy in order for forced mode settings to stick */ |
4280 | if (phy_reset(dev, bmcr)) { | 4311 | if (phy_reset(dev, bmcr)) { |
4281 | pr_info("%s: phy reset failed\n", dev->name); | 4312 | netdev_info(dev, "phy reset failed\n"); |
4282 | return -EINVAL; | 4313 | return -EINVAL; |
4283 | } | 4314 | } |
4284 | } else { | 4315 | } else { |
@@ -4340,7 +4371,7 @@ static int nv_nway_reset(struct net_device *dev) | |||
4340 | spin_unlock(&np->lock); | 4371 | spin_unlock(&np->lock); |
4341 | netif_addr_unlock(dev); | 4372 | netif_addr_unlock(dev); |
4342 | netif_tx_unlock_bh(dev); | 4373 | netif_tx_unlock_bh(dev); |
4343 | pr_info("%s: link down\n", dev->name); | 4374 | netdev_info(dev, "link down\n"); |
4344 | } | 4375 | } |
4345 | 4376 | ||
4346 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | 4377 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
@@ -4348,7 +4379,7 @@ static int nv_nway_reset(struct net_device *dev) | |||
4348 | bmcr |= BMCR_ANENABLE; | 4379 | bmcr |= BMCR_ANENABLE; |
4349 | /* reset the phy in order for settings to stick*/ | 4380 | /* reset the phy in order for settings to stick*/ |
4350 | if (phy_reset(dev, bmcr)) { | 4381 | if (phy_reset(dev, bmcr)) { |
4351 | pr_info("%s: phy reset failed\n", dev->name); | 4382 | netdev_info(dev, "phy reset failed\n"); |
4352 | return -EINVAL; | 4383 | return -EINVAL; |
4353 | } | 4384 | } |
4354 | } else { | 4385 | } else { |
@@ -4521,13 +4552,11 @@ static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* | |||
4521 | 4552 | ||
4522 | if ((!np->autoneg && np->duplex == 0) || | 4553 | if ((!np->autoneg && np->duplex == 0) || |
4523 | (np->autoneg && !pause->autoneg && np->duplex == 0)) { | 4554 | (np->autoneg && !pause->autoneg && np->duplex == 0)) { |
4524 | pr_info("%s: can not set pause settings when forced link is in half duplex\n", | 4555 | netdev_info(dev, "can not set pause settings when forced link is in half duplex\n"); |
4525 | dev->name); | ||
4526 | return -EINVAL; | 4556 | return -EINVAL; |
4527 | } | 4557 | } |
4528 | if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) { | 4558 | if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) { |
4529 | pr_info("%s: hardware does not support tx pause frames\n", | 4559 | netdev_info(dev, "hardware does not support tx pause frames\n"); |
4530 | dev->name); | ||
4531 | return -EINVAL; | 4560 | return -EINVAL; |
4532 | } | 4561 | } |
4533 | 4562 | ||
@@ -4562,7 +4591,7 @@ static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* | |||
4562 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); | 4591 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); |
4563 | 4592 | ||
4564 | if (netif_running(dev)) | 4593 | if (netif_running(dev)) |
4565 | pr_info("%s: link down\n", dev->name); | 4594 | netdev_info(dev, "link down\n"); |
4566 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | 4595 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
4567 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | 4596 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); |
4568 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | 4597 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); |
@@ -4824,8 +4853,7 @@ static int nv_loopback_test(struct net_device *dev) | |||
4824 | pkt_len = ETH_DATA_LEN; | 4853 | pkt_len = ETH_DATA_LEN; |
4825 | tx_skb = dev_alloc_skb(pkt_len); | 4854 | tx_skb = dev_alloc_skb(pkt_len); |
4826 | if (!tx_skb) { | 4855 | if (!tx_skb) { |
4827 | pr_err("dev_alloc_skb() failed during loopback test of %s\n", | 4856 | netdev_err(dev, "dev_alloc_skb() failed during loopback test\n"); |
4828 | dev->name); | ||
4829 | ret = 0; | 4857 | ret = 0; |
4830 | goto out; | 4858 | goto out; |
4831 | } | 4859 | } |
@@ -5188,7 +5216,8 @@ static int nv_open(struct net_device *dev) | |||
5188 | if (reg_delay(dev, NvRegUnknownSetupReg5, | 5216 | if (reg_delay(dev, NvRegUnknownSetupReg5, |
5189 | NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31, | 5217 | NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31, |
5190 | NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX)) | 5218 | NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX)) |
5191 | pr_info("%s: SetupReg5, Bit 31 remained off\n", __func__); | 5219 | netdev_info(dev, |
5220 | "%s: SetupReg5, Bit 31 remained off\n", __func__); | ||
5192 | 5221 | ||
5193 | writel(0, base + NvRegMIIMask); | 5222 | writel(0, base + NvRegMIIMask); |
5194 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | 5223 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
@@ -5277,7 +5306,7 @@ static int nv_open(struct net_device *dev) | |||
5277 | if (ret) { | 5306 | if (ret) { |
5278 | netif_carrier_on(dev); | 5307 | netif_carrier_on(dev); |
5279 | } else { | 5308 | } else { |
5280 | pr_info("%s: no link during initialization\n", dev->name); | 5309 | netdev_info(dev, "no link during initialization\n"); |
5281 | netif_carrier_off(dev); | 5310 | netif_carrier_off(dev); |
5282 | } | 5311 | } |
5283 | if (oom) | 5312 | if (oom) |