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authorAyaz Abdulla <aabdulla@nvidia.com>2006-07-06 16:46:25 -0400
committerJeff Garzik <jeff@garzik.org>2006-07-12 17:38:20 -0400
commit95d161cbab9d4da8b3c2d179ae11825e1294989e (patch)
tree7d354fb522e14e6a4263fd91cf78487bed5b3798 /drivers/net/forcedeth.c
parent9744e218aad2ef4569b0de960ff193fb50f5d6e0 (diff)
[PATCH] forcedeth: watermark fixup
This patch defines the watermark registers and fixes up the use of this register. Signed-Off-By: Ayaz Abdulla <aabdulla@nvidia.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/forcedeth.c')
-rw-r--r--drivers/net/forcedeth.c23
1 files changed, 19 insertions, 4 deletions
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index 1a315d09d95e..11b8f1b43dd5 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -271,8 +271,10 @@ enum {
271#define NVREG_LINKSPEED_MASK (0xFFF) 271#define NVREG_LINKSPEED_MASK (0xFFF)
272 NvRegUnknownSetupReg5 = 0x130, 272 NvRegUnknownSetupReg5 = 0x130,
273#define NVREG_UNKSETUP5_BIT31 (1<<31) 273#define NVREG_UNKSETUP5_BIT31 (1<<31)
274 NvRegUnknownSetupReg3 = 0x13c, 274 NvRegTxWatermark = 0x13c,
275#define NVREG_UNKSETUP3_VAL1 0x200010 275#define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
276#define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
277#define NVREG_TX_WM_DESC2_3_1000 0xfe08000
276 NvRegTxRxControl = 0x144, 278 NvRegTxRxControl = 0x144,
277#define NVREG_TXRXCTL_KICK 0x0001 279#define NVREG_TXRXCTL_KICK 0x0001
278#define NVREG_TXRXCTL_BIT1 0x0002 280#define NVREG_TXRXCTL_BIT1 0x0002
@@ -660,7 +662,7 @@ static const struct register_test nv_registers_test[] = {
660 { NvRegMisc1, 0x03c }, 662 { NvRegMisc1, 0x03c },
661 { NvRegOffloadConfig, 0x03ff }, 663 { NvRegOffloadConfig, 0x03ff },
662 { NvRegMulticastAddrA, 0xffffffff }, 664 { NvRegMulticastAddrA, 0xffffffff },
663 { NvRegUnknownSetupReg3, 0x0ff }, 665 { NvRegTxWatermark, 0x0ff },
664 { NvRegWakeUpFlags, 0x07777 }, 666 { NvRegWakeUpFlags, 0x07777 },
665 { 0,0 } 667 { 0,0 }
666}; 668};
@@ -2257,6 +2259,16 @@ set_speed:
2257 } 2259 }
2258 writel(txreg, base + NvRegTxDeferral); 2260 writel(txreg, base + NvRegTxDeferral);
2259 2261
2262 if (np->desc_ver == DESC_VER_1) {
2263 txreg = NVREG_TX_WM_DESC1_DEFAULT;
2264 } else {
2265 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2266 txreg = NVREG_TX_WM_DESC2_3_1000;
2267 else
2268 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
2269 }
2270 writel(txreg, base + NvRegTxWatermark);
2271
2260 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD), 2272 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2261 base + NvRegMisc1); 2273 base + NvRegMisc1);
2262 pci_push(base); 2274 pci_push(base);
@@ -3922,7 +3934,10 @@ static int nv_open(struct net_device *dev)
3922 3934
3923 /* 5) continue setup */ 3935 /* 5) continue setup */
3924 writel(np->linkspeed, base + NvRegLinkSpeed); 3936 writel(np->linkspeed, base + NvRegLinkSpeed);
3925 writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3); 3937 if (np->desc_ver == DESC_VER_1)
3938 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
3939 else
3940 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
3926 writel(np->txrxctl_bits, base + NvRegTxRxControl); 3941 writel(np->txrxctl_bits, base + NvRegTxRxControl);
3927 writel(np->vlanctl_bits, base + NvRegVlanControl); 3942 writel(np->vlanctl_bits, base + NvRegVlanControl);
3928 pci_push(base); 3943 pci_push(base);