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authorAyaz Abdulla <aabdulla@nvidia.com>2008-08-06 12:11:42 -0400
committerJeff Garzik <jgarzik@redhat.com>2008-08-07 02:11:00 -0400
commit9c6624352cdba7ef4859dae44eb48d538ac78d1b (patch)
tree9e078a9342bb8c24b8f15cf9fb76406b3ff6a479 /drivers/net/forcedeth.c
parent1ef6841b4c4d9cc26e53271016c1d432ea65ed24 (diff)
forcedeth: add new tx stat counters
This patch adds support for new tx statistic counters in the hardware - unicast, multicast, and broadcast Signed-off-by: Ayaz Abdulla <aabdulla@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/net/forcedeth.c')
-rw-r--r--drivers/net/forcedeth.c89
1 files changed, 56 insertions, 33 deletions
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index a39ed1365d61..3749a9970896 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -77,26 +77,27 @@
77 * Hardware access: 77 * Hardware access:
78 */ 78 */
79 79
80#define DEV_NEED_TIMERIRQ 0x00001 /* set the timer irq flag in the irq mask */ 80#define DEV_NEED_TIMERIRQ 0x000001 /* set the timer irq flag in the irq mask */
81#define DEV_NEED_LINKTIMER 0x00002 /* poll link settings. Relies on the timer irq */ 81#define DEV_NEED_LINKTIMER 0x000002 /* poll link settings. Relies on the timer irq */
82#define DEV_HAS_LARGEDESC 0x00004 /* device supports jumbo frames and needs packet format 2 */ 82#define DEV_HAS_LARGEDESC 0x000004 /* device supports jumbo frames and needs packet format 2 */
83#define DEV_HAS_HIGH_DMA 0x00008 /* device supports 64bit dma */ 83#define DEV_HAS_HIGH_DMA 0x000008 /* device supports 64bit dma */
84#define DEV_HAS_CHECKSUM 0x00010 /* device supports tx and rx checksum offloads */ 84#define DEV_HAS_CHECKSUM 0x000010 /* device supports tx and rx checksum offloads */
85#define DEV_HAS_VLAN 0x00020 /* device supports vlan tagging and striping */ 85#define DEV_HAS_VLAN 0x000020 /* device supports vlan tagging and striping */
86#define DEV_HAS_MSI 0x00040 /* device supports MSI */ 86#define DEV_HAS_MSI 0x000040 /* device supports MSI */
87#define DEV_HAS_MSI_X 0x00080 /* device supports MSI-X */ 87#define DEV_HAS_MSI_X 0x000080 /* device supports MSI-X */
88#define DEV_HAS_POWER_CNTRL 0x00100 /* device supports power savings */ 88#define DEV_HAS_POWER_CNTRL 0x000100 /* device supports power savings */
89#define DEV_HAS_STATISTICS_V1 0x00200 /* device supports hw statistics version 1 */ 89#define DEV_HAS_STATISTICS_V1 0x000200 /* device supports hw statistics version 1 */
90#define DEV_HAS_STATISTICS_V2 0x00400 /* device supports hw statistics version 2 */ 90#define DEV_HAS_STATISTICS_V2 0x000400 /* device supports hw statistics version 2 */
91#define DEV_HAS_TEST_EXTENDED 0x00800 /* device supports extended diagnostic test */ 91#define DEV_HAS_STATISTICS_V3 0x000800 /* device supports hw statistics version 3 */
92#define DEV_HAS_MGMT_UNIT 0x01000 /* device supports management unit */ 92#define DEV_HAS_TEST_EXTENDED 0x001000 /* device supports extended diagnostic test */
93#define DEV_HAS_CORRECT_MACADDR 0x02000 /* device supports correct mac address order */ 93#define DEV_HAS_MGMT_UNIT 0x002000 /* device supports management unit */
94#define DEV_HAS_COLLISION_FIX 0x04000 /* device supports tx collision fix */ 94#define DEV_HAS_CORRECT_MACADDR 0x004000 /* device supports correct mac address order */
95#define DEV_HAS_PAUSEFRAME_TX_V1 0x08000 /* device supports tx pause frames version 1 */ 95#define DEV_HAS_COLLISION_FIX 0x008000 /* device supports tx collision fix */
96#define DEV_HAS_PAUSEFRAME_TX_V2 0x10000 /* device supports tx pause frames version 2 */ 96#define DEV_HAS_PAUSEFRAME_TX_V1 0x010000 /* device supports tx pause frames version 1 */
97#define DEV_HAS_PAUSEFRAME_TX_V3 0x20000 /* device supports tx pause frames version 3 */ 97#define DEV_HAS_PAUSEFRAME_TX_V2 0x020000 /* device supports tx pause frames version 2 */
98#define DEV_NEED_TX_LIMIT 0x40000 /* device needs to limit tx */ 98#define DEV_HAS_PAUSEFRAME_TX_V3 0x040000 /* device supports tx pause frames version 3 */
99#define DEV_HAS_GEAR_MODE 0x80000 /* device supports gear mode */ 99#define DEV_NEED_TX_LIMIT 0x080000 /* device needs to limit tx */
100#define DEV_HAS_GEAR_MODE 0x100000 /* device supports gear mode */
100 101
101enum { 102enum {
102 NvRegIrqStatus = 0x000, 103 NvRegIrqStatus = 0x000,
@@ -270,6 +271,9 @@ enum {
270#define NVREG_MIICTL_WRITE 0x00400 271#define NVREG_MIICTL_WRITE 0x00400
271#define NVREG_MIICTL_ADDRSHIFT 5 272#define NVREG_MIICTL_ADDRSHIFT 5
272 NvRegMIIData = 0x194, 273 NvRegMIIData = 0x194,
274 NvRegTxUnicast = 0x1a0,
275 NvRegTxMulticast = 0x1a4,
276 NvRegTxBroadcast = 0x1a8,
273 NvRegWakeUpFlags = 0x200, 277 NvRegWakeUpFlags = 0x200,
274#define NVREG_WAKEUPFLAGS_VAL 0x7770 278#define NVREG_WAKEUPFLAGS_VAL 0x7770
275#define NVREG_WAKEUPFLAGS_BUSYSHIFT 24 279#define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
@@ -618,7 +622,12 @@ static const struct nv_ethtool_str nv_estats_str[] = {
618 { "rx_bytes" }, 622 { "rx_bytes" },
619 { "tx_pause" }, 623 { "tx_pause" },
620 { "rx_pause" }, 624 { "rx_pause" },
621 { "rx_drop_frame" } 625 { "rx_drop_frame" },
626
627 /* version 3 stats */
628 { "tx_unicast" },
629 { "tx_multicast" },
630 { "tx_broadcast" }
622}; 631};
623 632
624struct nv_ethtool_stats { 633struct nv_ethtool_stats {
@@ -654,9 +663,15 @@ struct nv_ethtool_stats {
654 u64 tx_pause; 663 u64 tx_pause;
655 u64 rx_pause; 664 u64 rx_pause;
656 u64 rx_drop_frame; 665 u64 rx_drop_frame;
666
667 /* version 3 stats */
668 u64 tx_unicast;
669 u64 tx_multicast;
670 u64 tx_broadcast;
657}; 671};
658 672
659#define NV_DEV_STATISTICS_V2_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64)) 673#define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
674#define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
660#define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6) 675#define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
661 676
662/* diagnostics */ 677/* diagnostics */
@@ -1630,6 +1645,12 @@ static void nv_get_hw_stats(struct net_device *dev)
1630 np->estats.rx_pause += readl(base + NvRegRxPause); 1645 np->estats.rx_pause += readl(base + NvRegRxPause);
1631 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame); 1646 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1632 } 1647 }
1648
1649 if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1650 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1651 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1652 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1653 }
1633} 1654}
1634 1655
1635/* 1656/*
@@ -1643,7 +1664,7 @@ static struct net_device_stats *nv_get_stats(struct net_device *dev)
1643 struct fe_priv *np = netdev_priv(dev); 1664 struct fe_priv *np = netdev_priv(dev);
1644 1665
1645 /* If the nic supports hw counters then retrieve latest values */ 1666 /* If the nic supports hw counters then retrieve latest values */
1646 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2)) { 1667 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
1647 nv_get_hw_stats(dev); 1668 nv_get_hw_stats(dev);
1648 1669
1649 /* copy to net_device stats */ 1670 /* copy to net_device stats */
@@ -4742,6 +4763,8 @@ static int nv_get_sset_count(struct net_device *dev, int sset)
4742 return NV_DEV_STATISTICS_V1_COUNT; 4763 return NV_DEV_STATISTICS_V1_COUNT;
4743 else if (np->driver_data & DEV_HAS_STATISTICS_V2) 4764 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4744 return NV_DEV_STATISTICS_V2_COUNT; 4765 return NV_DEV_STATISTICS_V2_COUNT;
4766 else if (np->driver_data & DEV_HAS_STATISTICS_V3)
4767 return NV_DEV_STATISTICS_V3_COUNT;
4745 else 4768 else
4746 return 0; 4769 return 0;
4747 default: 4770 default:
@@ -5326,7 +5349,7 @@ static int nv_open(struct net_device *dev)
5326 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); 5349 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5327 5350
5328 /* start statistics timer */ 5351 /* start statistics timer */
5329 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2)) 5352 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5330 mod_timer(&np->stats_poll, 5353 mod_timer(&np->stats_poll,
5331 round_jiffies(jiffies + STATS_INTERVAL)); 5354 round_jiffies(jiffies + STATS_INTERVAL));
5332 5355
@@ -5430,7 +5453,7 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
5430 if (err < 0) 5453 if (err < 0)
5431 goto out_disable; 5454 goto out_disable;
5432 5455
5433 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2)) 5456 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5434 np->register_size = NV_PCI_REGSZ_VER3; 5457 np->register_size = NV_PCI_REGSZ_VER3;
5435 else if (id->driver_data & DEV_HAS_STATISTICS_V1) 5458 else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5436 np->register_size = NV_PCI_REGSZ_VER2; 5459 np->register_size = NV_PCI_REGSZ_VER2;
@@ -6085,35 +6108,35 @@ static struct pci_device_id pci_tbl[] = {
6085 }, 6108 },
6086 { /* MCP77 Ethernet Controller */ 6109 { /* MCP77 Ethernet Controller */
6087 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32), 6110 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32),
6088 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6111 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6089 }, 6112 },
6090 { /* MCP77 Ethernet Controller */ 6113 { /* MCP77 Ethernet Controller */
6091 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33), 6114 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33),
6092 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6115 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6093 }, 6116 },
6094 { /* MCP77 Ethernet Controller */ 6117 { /* MCP77 Ethernet Controller */
6095 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34), 6118 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34),
6096 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6119 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6097 }, 6120 },
6098 { /* MCP77 Ethernet Controller */ 6121 { /* MCP77 Ethernet Controller */
6099 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35), 6122 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35),
6100 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6123 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6101 }, 6124 },
6102 { /* MCP79 Ethernet Controller */ 6125 { /* MCP79 Ethernet Controller */
6103 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36), 6126 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36),
6104 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6127 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6105 }, 6128 },
6106 { /* MCP79 Ethernet Controller */ 6129 { /* MCP79 Ethernet Controller */
6107 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37), 6130 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37),
6108 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6131 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6109 }, 6132 },
6110 { /* MCP79 Ethernet Controller */ 6133 { /* MCP79 Ethernet Controller */
6111 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38), 6134 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38),
6112 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6135 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6113 }, 6136 },
6114 { /* MCP79 Ethernet Controller */ 6137 { /* MCP79 Ethernet Controller */
6115 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39), 6138 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39),
6116 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6139 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6117 }, 6140 },
6118 {0,}, 6141 {0,},
6119}; 6142};