fec: switch to writel/readl

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: David S. Miller <davem@davemloft.net>
author: Sascha Hauer <s.hauer@pengutronix.de> 2009-04-14 23:11:30 -0400
committer: David S. Miller <davem@davemloft.net> 2009-04-16 05:34:47 -0400
commit: f44d6305280378cb34319e0118e18d84cc7ac773 (patch)
tree: c9c0b254dff43a48769aad1fe28b208b63b643fe /drivers/net/fec.h
parent: 2160187a0a1cdeeeff1d41f53333bea91c82f259 (diff)
1 files changed, 46 insertions, 73 deletions
diff --git a/drivers/net/fec.h b/drivers/net/fec.h
index 76c64c92e190..5474ba39d46c 100644
--- a/drivers/net/fec.h
+++ b/drivers/net/fec.h
@@ -20,82 +20,55 @@
 *      registers in the same peripheral device on different models
 *      of the ColdFire!
 */
-typedef struct fec {
+#define FEC_IEVENT              0x004 /* Interrupt event reg */
-        unsigned long   fec_reserved0;
+#define FEC_IMASK               0x008 /* Interrupt mask reg */
-        unsigned long   fec_ievent;             /* Interrupt event reg */
+#define FEC_R_DES_ACTIVE        0x010 /* Receive descriptor reg */
-        unsigned long   fec_imask;              /* Interrupt mask reg */
+#define FEC_X_DES_ACTIVE        0x014 /* Transmit descriptor reg */
-        unsigned long   fec_reserved1;
+#define FEC_ECNTRL              0x024 /* Ethernet control reg */
-        unsigned long   fec_r_des_active;       /* Receive descriptor reg */
+#define FEC_MII_DATA            0x040 /* MII manage frame reg */
-        unsigned long   fec_x_des_active;       /* Transmit descriptor reg */
+#define FEC_MII_SPEED           0x044 /* MII speed control reg */
-        unsigned long   fec_reserved2[3];
+#define FEC_MIB_CTRLSTAT        0x064 /* MIB control/status reg */
-        unsigned long   fec_ecntrl;             /* Ethernet control reg */
+#define FEC_R_CNTRL             0x084 /* Receive control reg */
-        unsigned long   fec_reserved3[6];
+#define FEC_X_CNTRL             0x0c4 /* Transmit Control reg */
-        unsigned long   fec_mii_data;           /* MII manage frame reg */
+#define FEC_ADDR_LOW            0x0e4 /* Low 32bits MAC address */
-        unsigned long   fec_mii_speed;          /* MII speed control reg */
+#define FEC_ADDR_HIGH           0x0e8 /* High 16bits MAC address */
-        unsigned long   fec_reserved4[7];
+#define FEC_OPD                 0x0ec /* Opcode + Pause duration */
-        unsigned long   fec_mib_ctrlstat;       /* MIB control/status reg */
+#define FEC_HASH_TABLE_HIGH     0x118 /* High 32bits hash table */
-        unsigned long   fec_reserved5[7];
+#define FEC_HASH_TABLE_LOW      0x11c /* Low 32bits hash table */
-        unsigned long   fec_r_cntrl;            /* Receive control reg */
+#define FEC_GRP_HASH_TABLE_HIGH 0x120 /* High 32bits hash table */
-        unsigned long   fec_reserved6[15];
+#define FEC_GRP_HASH_TABLE_LOW  0x124 /* Low 32bits hash table */
-        unsigned long   fec_x_cntrl;            /* Transmit Control reg */
+#define FEC_X_WMRK              0x144 /* FIFO transmit water mark */
-        unsigned long   fec_reserved7[7];
+#define FEC_R_BOUND             0x14c /* FIFO receive bound reg */
-        unsigned long   fec_addr_low;           /* Low 32bits MAC address */
+#define FEC_R_FSTART            0x150 /* FIFO receive start reg */
-        unsigned long   fec_addr_high;          /* High 16bits MAC address */
+#define FEC_R_DES_START         0x180 /* Receive descriptor ring */
-        unsigned long   fec_opd;                /* Opcode + Pause duration */
+#define FEC_X_DES_START         0x184 /* Transmit descriptor ring */
-        unsigned long   fec_reserved8[10];
+#define FEC_R_BUFF_SIZE         0x188 /* Maximum receive buff size */
-        unsigned long   fec_hash_table_high;    /* High 32bits hash table */
-        unsigned long   fec_hash_table_low;     /* Low 32bits hash table */
-        unsigned long   fec_grp_hash_table_high;/* High 32bits hash table */
-        unsigned long   fec_grp_hash_table_low; /* Low 32bits hash table */
-        unsigned long   fec_reserved9[7];
-        unsigned long   fec_x_wmrk;             /* FIFO transmit water mark */
-        unsigned long   fec_reserved10;
-        unsigned long   fec_r_bound;            /* FIFO receive bound reg */
-        unsigned long   fec_r_fstart;           /* FIFO receive start reg */
-        unsigned long   fec_reserved11[11];
-        unsigned long   fec_r_des_start;        /* Receive descriptor ring */
-        unsigned long   fec_x_des_start;        /* Transmit descriptor ring */
-        unsigned long   fec_r_buff_size;        /* Maximum receive buff size */
-} fec_t;
 #else
-/*
+#define FEC_ECNTRL;             0x000 /* Ethernet control reg */
- *      Define device register set address map.
+#define FEC_IEVENT;             0x004 /* Interrupt even reg */
- */
+#define FEC_IMASK;              0x008 /* Interrupt mask reg */
-typedef struct fec {
+#define FEC_IVEC;               0x00c /* Interrupt vec status reg */
-        unsigned long   fec_ecntrl;             /* Ethernet control reg */
+#define FEC_R_DES_ACTIVE;       0x010 /* Receive descriptor reg */
-        unsigned long   fec_ievent;             /* Interrupt even reg */
+#define FEC_X_DES_ACTIVE;       0x01c /* Transmit descriptor reg */
-        unsigned long   fec_imask;              /* Interrupt mask reg */
+#define FEC_MII_DATA            0x040 /* MII manage frame reg */
-        unsigned long   fec_ivec;               /* Interrupt vec status reg */
+#define FEC_MII_SPEED           0x044 /* MII speed control reg */
-        unsigned long   fec_r_des_active;       /* Receive descriptor reg */
+#define FEC_R_BOUND             0x08c /* FIFO receive bound reg */
-        unsigned long   fec_x_des_active;       /* Transmit descriptor reg */
+#define FEC_R_FSTART            0x090 /* FIFO receive start reg */
-        unsigned long   fec_reserved1[10];
+#define FEC_X_WMRK              0x0a4 /* FIFO transmit water mark */
-        unsigned long   fec_mii_data;           /* MII manage frame reg */
+#define FEC_X_FSTART            0x0ac /* FIFO transmit start reg */
-        unsigned long   fec_mii_speed;          /* MII speed control reg */
+#define FEC_R_CNTRL             0x104 /* Receive control reg */
-        unsigned long   fec_reserved2[17];
+#define FEC_MAX_FRM_LEN         0x108 /* Maximum frame length reg */
-        unsigned long   fec_r_bound;            /* FIFO receive bound reg */
+#define FEC_X_CNTRL             0x144 /* Transmit Control reg */
-        unsigned long   fec_r_fstart;           /* FIFO receive start reg */
+#define FEC_ADDR_LOW            0x3c0 /* Low 32bits MAC address */
-        unsigned long   fec_reserved3[4];
+#define FEC_ADDR_HIGH           0x3c4 /* High 16bits MAC address */
-        unsigned long   fec_x_wmrk;             /* FIFO transmit water mark */
+#define FEC_GRP_HASH_TABLE_HIGH 0x3c8 /* High 32bits hash table */
-        unsigned long   fec_reserved4;
+#define FEC_GRP_HASH_TABLE_LOW  0x3cc /* Low 32bits hash table */
-        unsigned long   fec_x_fstart;           /* FIFO transmit start reg */
+#define FEC_R_DES_START         0x3d0 /* Receive descriptor ring */
-        unsigned long   fec_reserved5[21];
+#define FEC_X_DES_START         0x3d4 /* Transmit descriptor ring */
-        unsigned long   fec_r_cntrl;            /* Receive control reg */
+#define FEC_R_BUFF_SIZE         0x3d8 /* Maximum receive buff size */
-        unsigned long   fec_max_frm_len;        /* Maximum frame length reg */
+#define FEC_FIFO_RAM            0x400 /* FIFO RAM buffer */
-        unsigned long   fec_reserved6[14];
-        unsigned long   fec_x_cntrl;            /* Transmit Control reg */
-        unsigned long   fec_reserved7[158];
-        unsigned long   fec_addr_low;           /* Low 32bits MAC address */
-        unsigned long   fec_addr_high;          /* High 16bits MAC address */
-        unsigned long   fec_grp_hash_table_high;/* High 32bits hash table */
-        unsigned long   fec_grp_hash_table_low; /* Low 32bits hash table */
-        unsigned long   fec_r_des_start;        /* Receive descriptor ring */
-        unsigned long   fec_x_des_start;        /* Transmit descriptor ring */
-        unsigned long   fec_r_buff_size;        /* Maximum receive buff size */
-        unsigned long   reserved8[9];
-        unsigned long   fec_fifo_ram[112];      /* FIFO RAM buffer */
-} fec_t;
 #endif /* CONFIG_M5272 */
author	Sascha Hauer <s.hauer@pengutronix.de>	2009-04-14 23:11:30 -0400
committer	David S. Miller <davem@davemloft.net>	2009-04-16 05:34:47 -0400
commit	f44d6305280378cb34319e0118e18d84cc7ac773 (patch)
tree	c9c0b254dff43a48769aad1fe28b208b63b643fe /drivers/net/fec.h
parent	2160187a0a1cdeeeff1d41f53333bea91c82f259 (diff)

diff --git a/drivers/net/fec.h b/drivers/net/fec.h index 76c64c92e190..5474ba39d46c 100644 --- a/drivers/net/fec.h +++ b/drivers/net/fec.h
@@ -20,82 +20,55 @@
20	* registers in the same peripheral device on different models	20	* registers in the same peripheral device on different models
21	* of the ColdFire!	21	* of the ColdFire!
22	*/	22	*/
23	typedef struct fec {	23	#define FEC_IEVENT 0x004 /* Interrupt event reg */
24	unsigned long fec_reserved0;	24	#define FEC_IMASK 0x008 /* Interrupt mask reg */
25	unsigned long fec_ievent; /* Interrupt event reg */	25	#define FEC_R_DES_ACTIVE 0x010 /* Receive descriptor reg */
26	unsigned long fec_imask; /* Interrupt mask reg */	26	#define FEC_X_DES_ACTIVE 0x014 /* Transmit descriptor reg */
27	unsigned long fec_reserved1;	27	#define FEC_ECNTRL 0x024 /* Ethernet control reg */
28	unsigned long fec_r_des_active; /* Receive descriptor reg */	28	#define FEC_MII_DATA 0x040 /* MII manage frame reg */
29	unsigned long fec_x_des_active; /* Transmit descriptor reg */	29	#define FEC_MII_SPEED 0x044 /* MII speed control reg */
30	unsigned long fec_reserved2[3];	30	#define FEC_MIB_CTRLSTAT 0x064 /* MIB control/status reg */
31	unsigned long fec_ecntrl; /* Ethernet control reg */	31	#define FEC_R_CNTRL 0x084 /* Receive control reg */
32	unsigned long fec_reserved3[6];	32	#define FEC_X_CNTRL 0x0c4 /* Transmit Control reg */
33	unsigned long fec_mii_data; /* MII manage frame reg */	33	#define FEC_ADDR_LOW 0x0e4 /* Low 32bits MAC address */
34	unsigned long fec_mii_speed; /* MII speed control reg */	34	#define FEC_ADDR_HIGH 0x0e8 /* High 16bits MAC address */
35	unsigned long fec_reserved4[7];	35	#define FEC_OPD 0x0ec /* Opcode + Pause duration */
36	unsigned long fec_mib_ctrlstat; /* MIB control/status reg */	36	#define FEC_HASH_TABLE_HIGH 0x118 /* High 32bits hash table */
37	unsigned long fec_reserved5[7];	37	#define FEC_HASH_TABLE_LOW 0x11c /* Low 32bits hash table */
38	unsigned long fec_r_cntrl; /* Receive control reg */	38	#define FEC_GRP_HASH_TABLE_HIGH 0x120 /* High 32bits hash table */
39	unsigned long fec_reserved6[15];	39	#define FEC_GRP_HASH_TABLE_LOW 0x124 /* Low 32bits hash table */
40	unsigned long fec_x_cntrl; /* Transmit Control reg */	40	#define FEC_X_WMRK 0x144 /* FIFO transmit water mark */
41	unsigned long fec_reserved7[7];	41	#define FEC_R_BOUND 0x14c /* FIFO receive bound reg */
42	unsigned long fec_addr_low; /* Low 32bits MAC address */	42	#define FEC_R_FSTART 0x150 /* FIFO receive start reg */
43	unsigned long fec_addr_high; /* High 16bits MAC address */	43	#define FEC_R_DES_START 0x180 /* Receive descriptor ring */
44	unsigned long fec_opd; /* Opcode + Pause duration */	44	#define FEC_X_DES_START 0x184 /* Transmit descriptor ring */
45	unsigned long fec_reserved8[10];	45	#define FEC_R_BUFF_SIZE 0x188 /* Maximum receive buff size */
46	unsigned long fec_hash_table_high; /* High 32bits hash table */
47	unsigned long fec_hash_table_low; /* Low 32bits hash table */
48	unsigned long fec_grp_hash_table_high;/* High 32bits hash table */
49	unsigned long fec_grp_hash_table_low; /* Low 32bits hash table */
50	unsigned long fec_reserved9[7];
51	unsigned long fec_x_wmrk; /* FIFO transmit water mark */
52	unsigned long fec_reserved10;
53	unsigned long fec_r_bound; /* FIFO receive bound reg */
54	unsigned long fec_r_fstart; /* FIFO receive start reg */
55	unsigned long fec_reserved11[11];
56	unsigned long fec_r_des_start; /* Receive descriptor ring */
57	unsigned long fec_x_des_start; /* Transmit descriptor ring */
58	unsigned long fec_r_buff_size; /* Maximum receive buff size */
59	} fec_t;
60		46
61	#else	47	#else
62		48
63	/*	49	#define FEC_ECNTRL; 0x000 /* Ethernet control reg */
64	* Define device register set address map.	50	#define FEC_IEVENT; 0x004 /* Interrupt even reg */
65	*/	51	#define FEC_IMASK; 0x008 /* Interrupt mask reg */
66	typedef struct fec {	52	#define FEC_IVEC; 0x00c /* Interrupt vec status reg */
67	unsigned long fec_ecntrl; /* Ethernet control reg */	53	#define FEC_R_DES_ACTIVE; 0x010 /* Receive descriptor reg */
68	unsigned long fec_ievent; /* Interrupt even reg */	54	#define FEC_X_DES_ACTIVE; 0x01c /* Transmit descriptor reg */
69	unsigned long fec_imask; /* Interrupt mask reg */	55	#define FEC_MII_DATA 0x040 /* MII manage frame reg */
70	unsigned long fec_ivec; /* Interrupt vec status reg */	56	#define FEC_MII_SPEED 0x044 /* MII speed control reg */
71	unsigned long fec_r_des_active; /* Receive descriptor reg */	57	#define FEC_R_BOUND 0x08c /* FIFO receive bound reg */
72	unsigned long fec_x_des_active; /* Transmit descriptor reg */	58	#define FEC_R_FSTART 0x090 /* FIFO receive start reg */
73	unsigned long fec_reserved1[10];	59	#define FEC_X_WMRK 0x0a4 /* FIFO transmit water mark */
74	unsigned long fec_mii_data; /* MII manage frame reg */	60	#define FEC_X_FSTART 0x0ac /* FIFO transmit start reg */
75	unsigned long fec_mii_speed; /* MII speed control reg */	61	#define FEC_R_CNTRL 0x104 /* Receive control reg */
76	unsigned long fec_reserved2[17];	62	#define FEC_MAX_FRM_LEN 0x108 /* Maximum frame length reg */
77	unsigned long fec_r_bound; /* FIFO receive bound reg */	63	#define FEC_X_CNTRL 0x144 /* Transmit Control reg */
78	unsigned long fec_r_fstart; /* FIFO receive start reg */	64	#define FEC_ADDR_LOW 0x3c0 /* Low 32bits MAC address */
79	unsigned long fec_reserved3[4];	65	#define FEC_ADDR_HIGH 0x3c4 /* High 16bits MAC address */
80	unsigned long fec_x_wmrk; /* FIFO transmit water mark */	66	#define FEC_GRP_HASH_TABLE_HIGH 0x3c8 /* High 32bits hash table */
81	unsigned long fec_reserved4;	67	#define FEC_GRP_HASH_TABLE_LOW 0x3cc /* Low 32bits hash table */
82	unsigned long fec_x_fstart; /* FIFO transmit start reg */	68	#define FEC_R_DES_START 0x3d0 /* Receive descriptor ring */
83	unsigned long fec_reserved5[21];	69	#define FEC_X_DES_START 0x3d4 /* Transmit descriptor ring */
84	unsigned long fec_r_cntrl; /* Receive control reg */	70	#define FEC_R_BUFF_SIZE 0x3d8 /* Maximum receive buff size */
85	unsigned long fec_max_frm_len; /* Maximum frame length reg */	71	#define FEC_FIFO_RAM 0x400 /* FIFO RAM buffer */
86	unsigned long fec_reserved6[14];
87	unsigned long fec_x_cntrl; /* Transmit Control reg */
88	unsigned long fec_reserved7[158];
89	unsigned long fec_addr_low; /* Low 32bits MAC address */
90	unsigned long fec_addr_high; /* High 16bits MAC address */
91	unsigned long fec_grp_hash_table_high;/* High 32bits hash table */
92	unsigned long fec_grp_hash_table_low; /* Low 32bits hash table */
93	unsigned long fec_r_des_start; /* Receive descriptor ring */
94	unsigned long fec_x_des_start; /* Transmit descriptor ring */
95	unsigned long fec_r_buff_size; /* Maximum receive buff size */
96	unsigned long reserved8[9];
97	unsigned long fec_fifo_ram[112]; /* FIFO RAM buffer */
98	} fec_t;
99		72
100	#endif /* CONFIG_M5272 */	73	#endif /* CONFIG_M5272 */
101		74