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authorUwe Kleine-König <u.kleine-koenig@pengutronix.de>2011-01-19 14:47:04 -0500
committerUwe Kleine-König <u.kleine-koenig@pengutronix.de>2011-02-15 03:26:30 -0500
commit45993653bd5935dbf975bc26a834f2ff23c9f914 (patch)
treefc2a34c1e236a52d4ac83c24d2fa8a8f91c53a90 /drivers/net/fec.c
parentdb8880bc92657559320ba8384acb2547d4255521 (diff)
net/fec: reorder functions a bit allows removing forward declarations
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Diffstat (limited to 'drivers/net/fec.c')
-rw-r--r--drivers/net/fec.c353
1 files changed, 174 insertions, 179 deletions
diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index 4c888f1825a3..3f5dfe2e41ac 100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -205,13 +205,6 @@ struct fec_enet_private {
205 struct completion mdio_done; 205 struct completion mdio_done;
206}; 206};
207 207
208static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
209static void fec_enet_tx(struct net_device *ndev);
210static void fec_enet_rx(struct net_device *ndev);
211static int fec_enet_close(struct net_device *ndev);
212static void fec_restart(struct net_device *ndev, int duplex);
213static void fec_stop(struct net_device *ndev);
214
215/* FEC MII MMFR bits definition */ 208/* FEC MII MMFR bits definition */
216#define FEC_MMFR_ST (1 << 30) 209#define FEC_MMFR_ST (1 << 30)
217#define FEC_MMFR_OP_READ (2 << 28) 210#define FEC_MMFR_OP_READ (2 << 28)
@@ -335,54 +328,160 @@ fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
335 return NETDEV_TX_OK; 328 return NETDEV_TX_OK;
336} 329}
337 330
331/* This function is called to start or restart the FEC during a link
332 * change. This only happens when switching between half and full
333 * duplex.
334 */
338static void 335static void
339fec_timeout(struct net_device *ndev) 336fec_restart(struct net_device *ndev, int duplex)
340{ 337{
341 struct fec_enet_private *fep = netdev_priv(ndev); 338 struct fec_enet_private *fep = netdev_priv(ndev);
339 const struct platform_device_id *id_entry =
340 platform_get_device_id(fep->pdev);
341 int i;
342 u32 val, temp_mac[2];
342 343
343 ndev->stats.tx_errors++; 344 /* Whack a reset. We should wait for this. */
345 writel(1, fep->hwp + FEC_ECNTRL);
346 udelay(10);
344 347
345 fec_restart(ndev, fep->full_duplex); 348 /*
346 netif_wake_queue(ndev); 349 * enet-mac reset will reset mac address registers too,
347} 350 * so need to reconfigure it.
351 */
352 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
353 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
354 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
355 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
356 }
348 357
349static irqreturn_t 358 /* Clear any outstanding interrupt. */
350fec_enet_interrupt(int irq, void *dev_id) 359 writel(0xffc00000, fep->hwp + FEC_IEVENT);
351{
352 struct net_device *ndev = dev_id;
353 struct fec_enet_private *fep = netdev_priv(ndev);
354 uint int_events;
355 irqreturn_t ret = IRQ_NONE;
356 360
357 do { 361 /* Reset all multicast. */
358 int_events = readl(fep->hwp + FEC_IEVENT); 362 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
359 writel(int_events, fep->hwp + FEC_IEVENT); 363 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
364#ifndef CONFIG_M5272
365 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
366 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
367#endif
360 368
361 if (int_events & FEC_ENET_RXF) { 369 /* Set maximum receive buffer size. */
362 ret = IRQ_HANDLED; 370 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
363 fec_enet_rx(ndev);
364 }
365 371
366 /* Transmit OK, or non-fatal error. Update the buffer 372 /* Set receive and transmit descriptor base. */
367 * descriptors. FEC handles all errors, we just discover 373 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
368 * them as part of the transmit process. 374 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE,
369 */ 375 fep->hwp + FEC_X_DES_START);
370 if (int_events & FEC_ENET_TXF) { 376
371 ret = IRQ_HANDLED; 377 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
372 fec_enet_tx(ndev); 378 fep->cur_rx = fep->rx_bd_base;
379
380 /* Reset SKB transmit buffers. */
381 fep->skb_cur = fep->skb_dirty = 0;
382 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
383 if (fep->tx_skbuff[i]) {
384 dev_kfree_skb_any(fep->tx_skbuff[i]);
385 fep->tx_skbuff[i] = NULL;
373 } 386 }
387 }
374 388
375 if (int_events & FEC_ENET_MII) { 389 /* Enable MII mode */
376 ret = IRQ_HANDLED; 390 if (duplex) {
377 complete(&fep->mdio_done); 391 /* MII enable / FD enable */
392 writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL);
393 writel(0x04, fep->hwp + FEC_X_CNTRL);
394 } else {
395 /* MII enable / No Rcv on Xmit */
396 writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL);
397 writel(0x0, fep->hwp + FEC_X_CNTRL);
398 }
399 fep->full_duplex = duplex;
400
401 /* Set MII speed */
402 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
403
404 /*
405 * The phy interface and speed need to get configured
406 * differently on enet-mac.
407 */
408 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
409 val = readl(fep->hwp + FEC_R_CNTRL);
410
411 /* MII or RMII */
412 if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
413 val |= (1 << 8);
414 else
415 val &= ~(1 << 8);
416
417 /* 10M or 100M */
418 if (fep->phy_dev && fep->phy_dev->speed == SPEED_100)
419 val &= ~(1 << 9);
420 else
421 val |= (1 << 9);
422
423 writel(val, fep->hwp + FEC_R_CNTRL);
424 } else {
425#ifdef FEC_MIIGSK_ENR
426 if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) {
427 /* disable the gasket and wait */
428 writel(0, fep->hwp + FEC_MIIGSK_ENR);
429 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
430 udelay(1);
431
432 /*
433 * configure the gasket:
434 * RMII, 50 MHz, no loopback, no echo
435 */
436 writel(1, fep->hwp + FEC_MIIGSK_CFGR);
437
438 /* re-enable the gasket */
439 writel(2, fep->hwp + FEC_MIIGSK_ENR);
378 } 440 }
379 } while (int_events); 441#endif
442 }
380 443
381 return ret; 444 /* And last, enable the transmit and receive processing */
445 writel(2, fep->hwp + FEC_ECNTRL);
446 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
447
448 /* Enable interrupts we wish to service */
449 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
450}
451
452static void
453fec_stop(struct net_device *ndev)
454{
455 struct fec_enet_private *fep = netdev_priv(ndev);
456
457 /* We cannot expect a graceful transmit stop without link !!! */
458 if (fep->link) {
459 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
460 udelay(10);
461 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
462 printk("fec_stop : Graceful transmit stop did not complete !\n");
463 }
464
465 /* Whack a reset. We should wait for this. */
466 writel(1, fep->hwp + FEC_ECNTRL);
467 udelay(10);
468 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
469 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
382} 470}
383 471
384 472
385static void 473static void
474fec_timeout(struct net_device *ndev)
475{
476 struct fec_enet_private *fep = netdev_priv(ndev);
477
478 ndev->stats.tx_errors++;
479
480 fec_restart(ndev, fep->full_duplex);
481 netif_wake_queue(ndev);
482}
483
484static void
386fec_enet_tx(struct net_device *ndev) 485fec_enet_tx(struct net_device *ndev)
387{ 486{
388 struct fec_enet_private *fep; 487 struct fec_enet_private *fep;
@@ -576,6 +675,43 @@ rx_processing_done:
576 spin_unlock(&fep->hw_lock); 675 spin_unlock(&fep->hw_lock);
577} 676}
578 677
678static irqreturn_t
679fec_enet_interrupt(int irq, void *dev_id)
680{
681 struct net_device *ndev = dev_id;
682 struct fec_enet_private *fep = netdev_priv(ndev);
683 uint int_events;
684 irqreturn_t ret = IRQ_NONE;
685
686 do {
687 int_events = readl(fep->hwp + FEC_IEVENT);
688 writel(int_events, fep->hwp + FEC_IEVENT);
689
690 if (int_events & FEC_ENET_RXF) {
691 ret = IRQ_HANDLED;
692 fec_enet_rx(ndev);
693 }
694
695 /* Transmit OK, or non-fatal error. Update the buffer
696 * descriptors. FEC handles all errors, we just discover
697 * them as part of the transmit process.
698 */
699 if (int_events & FEC_ENET_TXF) {
700 ret = IRQ_HANDLED;
701 fec_enet_tx(ndev);
702 }
703
704 if (int_events & FEC_ENET_MII) {
705 ret = IRQ_HANDLED;
706 complete(&fep->mdio_done);
707 }
708 } while (int_events);
709
710 return ret;
711}
712
713
714
579/* ------------------------------------------------------------------------- */ 715/* ------------------------------------------------------------------------- */
580static void __inline__ fec_get_mac(struct net_device *ndev) 716static void __inline__ fec_get_mac(struct net_device *ndev)
581{ 717{
@@ -1217,147 +1353,6 @@ static int fec_enet_init(struct net_device *ndev)
1217 return 0; 1353 return 0;
1218} 1354}
1219 1355
1220/* This function is called to start or restart the FEC during a link
1221 * change. This only happens when switching between half and full
1222 * duplex.
1223 */
1224static void
1225fec_restart(struct net_device *ndev, int duplex)
1226{
1227 struct fec_enet_private *fep = netdev_priv(ndev);
1228 const struct platform_device_id *id_entry =
1229 platform_get_device_id(fep->pdev);
1230 int i;
1231 u32 val, temp_mac[2];
1232
1233 /* Whack a reset. We should wait for this. */
1234 writel(1, fep->hwp + FEC_ECNTRL);
1235 udelay(10);
1236
1237 /*
1238 * enet-mac reset will reset mac address registers too,
1239 * so need to reconfigure it.
1240 */
1241 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
1242 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
1243 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
1244 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
1245 }
1246
1247 /* Clear any outstanding interrupt. */
1248 writel(0xffc00000, fep->hwp + FEC_IEVENT);
1249
1250 /* Reset all multicast. */
1251 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1252 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1253#ifndef CONFIG_M5272
1254 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1255 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1256#endif
1257
1258 /* Set maximum receive buffer size. */
1259 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
1260
1261 /* Set receive and transmit descriptor base. */
1262 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
1263 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE,
1264 fep->hwp + FEC_X_DES_START);
1265
1266 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
1267 fep->cur_rx = fep->rx_bd_base;
1268
1269 /* Reset SKB transmit buffers. */
1270 fep->skb_cur = fep->skb_dirty = 0;
1271 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
1272 if (fep->tx_skbuff[i]) {
1273 dev_kfree_skb_any(fep->tx_skbuff[i]);
1274 fep->tx_skbuff[i] = NULL;
1275 }
1276 }
1277
1278 /* Enable MII mode */
1279 if (duplex) {
1280 /* MII enable / FD enable */
1281 writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL);
1282 writel(0x04, fep->hwp + FEC_X_CNTRL);
1283 } else {
1284 /* MII enable / No Rcv on Xmit */
1285 writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL);
1286 writel(0x0, fep->hwp + FEC_X_CNTRL);
1287 }
1288 fep->full_duplex = duplex;
1289
1290 /* Set MII speed */
1291 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1292
1293 /*
1294 * The phy interface and speed need to get configured
1295 * differently on enet-mac.
1296 */
1297 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
1298 val = readl(fep->hwp + FEC_R_CNTRL);
1299
1300 /* MII or RMII */
1301 if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1302 val |= (1 << 8);
1303 else
1304 val &= ~(1 << 8);
1305
1306 /* 10M or 100M */
1307 if (fep->phy_dev && fep->phy_dev->speed == SPEED_100)
1308 val &= ~(1 << 9);
1309 else
1310 val |= (1 << 9);
1311
1312 writel(val, fep->hwp + FEC_R_CNTRL);
1313 } else {
1314#ifdef FEC_MIIGSK_ENR
1315 if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) {
1316 /* disable the gasket and wait */
1317 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1318 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1319 udelay(1);
1320
1321 /*
1322 * configure the gasket:
1323 * RMII, 50 MHz, no loopback, no echo
1324 */
1325 writel(1, fep->hwp + FEC_MIIGSK_CFGR);
1326
1327 /* re-enable the gasket */
1328 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1329 }
1330#endif
1331 }
1332
1333 /* And last, enable the transmit and receive processing */
1334 writel(2, fep->hwp + FEC_ECNTRL);
1335 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
1336
1337 /* Enable interrupts we wish to service */
1338 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1339}
1340
1341static void
1342fec_stop(struct net_device *ndev)
1343{
1344 struct fec_enet_private *fep = netdev_priv(ndev);
1345
1346 /* We cannot expect a graceful transmit stop without link !!! */
1347 if (fep->link) {
1348 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1349 udelay(10);
1350 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1351 printk("fec_stop : Graceful transmit stop did not complete !\n");
1352 }
1353
1354 /* Whack a reset. We should wait for this. */
1355 writel(1, fep->hwp + FEC_ECNTRL);
1356 udelay(10);
1357 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1358 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1359}
1360
1361static int __devinit 1356static int __devinit
1362fec_probe(struct platform_device *pdev) 1357fec_probe(struct platform_device *pdev)
1363{ 1358{
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-07 17:43:59 -0500