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authorLinus Torvalds <torvalds@g5.osdl.org>2006-09-24 13:15:13 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-09-24 13:15:13 -0400
commita319a2773a13bab56a0d0b3744ba8703324313b5 (patch)
treef02c86acabd1031439fd422a167784007e84ebb1 /drivers/net/ewrk3.h
parente18fa700c9a31360bc8f193aa543b7ef7b39a06b (diff)
parent183798799216fad36c7219fe8d4d6dee6b8fa755 (diff)
Merge branch 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/netdev-2.6
* 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/netdev-2.6: (217 commits) net/ieee80211: fix more crypto-related build breakage [PATCH] Spidernet: add ethtool -S (show statistics) [NET] GT96100: Delete bitrotting ethernet driver [PATCH] mv643xx_eth: restrict to 32-bit PPC_MULTIPLATFORM [PATCH] Cirrus Logic ep93xx ethernet driver r8169: the MMIO region of the 8167 stands behin BAR#1 e1000, ixgb: Remove pointless wrappers [PATCH] Remove powerpc specific parts of 3c509 driver [PATCH] s2io: Switch to pci_get_device [PATCH] gt96100: move to pci_get_device API [PATCH] ehea: bugfix for register access functions [PATCH] e1000 disable device on PCI error drivers/net/phy/fixed: #if 0 some incomplete code drivers/net: const-ify ethtool_ops declarations [PATCH] ethtool: allow const ethtool_ops [PATCH] sky2: big endian [PATCH] sky2: fiber support [PATCH] sky2: tx pause bug fix drivers/net: Trim trailing whitespace [PATCH] ehea: IBM eHEA Ethernet Device Driver ... Manually resolved conflicts in drivers/net/ixgb/ixgb_main.c and drivers/net/sky2.c related to CHECKSUM_HW/CHECKSUM_PARTIAL changes by commit 84fa7933a33f806bbbaae6775e87459b1ec584c0 that just happened to be next to unrelated changes in this update.
Diffstat (limited to 'drivers/net/ewrk3.h')
-rw-r--r--drivers/net/ewrk3.h30
1 files changed, 15 insertions, 15 deletions
diff --git a/drivers/net/ewrk3.h b/drivers/net/ewrk3.h
index fb74bd053672..8e0ee906567b 100644
--- a/drivers/net/ewrk3.h
+++ b/drivers/net/ewrk3.h
@@ -63,7 +63,7 @@
63*/ 63*/
64#define CSR_RA 0x80 /* Runt Accept */ 64#define CSR_RA 0x80 /* Runt Accept */
65#define CSR_PME 0x40 /* Promiscuous Mode Enable */ 65#define CSR_PME 0x40 /* Promiscuous Mode Enable */
66#define CSR_MCE 0x20 /* Multicast Enable */ 66#define CSR_MCE 0x20 /* Multicast Enable */
67#define CSR_TNE 0x08 /* TX Done Queue Not Empty */ 67#define CSR_TNE 0x08 /* TX Done Queue Not Empty */
68#define CSR_RNE 0x04 /* RX Queue Not Empty */ 68#define CSR_RNE 0x04 /* RX Queue Not Empty */
69#define CSR_TXD 0x02 /* TX Disable */ 69#define CSR_TXD 0x02 /* TX Disable */
@@ -127,7 +127,7 @@
127#define CMR_DRAM 0x02 /* 0-> 1DRAM, 1-> 2 DRAM on board */ 127#define CMR_DRAM 0x02 /* 0-> 1DRAM, 1-> 2 DRAM on board */
128#define CMR_0WS 0x01 /* Zero Wait State */ 128#define CMR_0WS 0x01 /* Zero Wait State */
129 129
130/* 130/*
131** MAC Receive Status Register bit definitions 131** MAC Receive Status Register bit definitions
132*/ 132*/
133 133
@@ -138,7 +138,7 @@
138#define R_CRC 0x02 /* CRC error */ 138#define R_CRC 0x02 /* CRC error */
139#define R_PLL 0x01 /* Phase Lock Lost */ 139#define R_PLL 0x01 /* Phase Lock Lost */
140 140
141/* 141/*
142** MAC Transmit Control Register bit definitions 142** MAC Transmit Control Register bit definitions
143*/ 143*/
144 144
@@ -150,7 +150,7 @@
150#define TCR_IFC 0x02 /* Insert Frame Check */ 150#define TCR_IFC 0x02 /* Insert Frame Check */
151#define TCR_ISA 0x01 /* Insert Source Address */ 151#define TCR_ISA 0x01 /* Insert Source Address */
152 152
153/* 153/*
154** MAC Transmit Status Register bit definitions 154** MAC Transmit Status Register bit definitions
155*/ 155*/
156 156
@@ -168,15 +168,15 @@
168#define T_XUR 0x03 /* Excessive Underruns */ 168#define T_XUR 0x03 /* Excessive Underruns */
169#define T_TXE 0x7f /* TX Errors */ 169#define T_TXE 0x7f /* TX Errors */
170 170
171/* 171/*
172** EISA Configuration Register bit definitions 172** EISA Configuration Register bit definitions
173*/ 173*/
174 174
175#define EISA_ID iobase + 0x0c80 /* EISA ID Registers */ 175#define EISA_ID iobase + 0x0c80 /* EISA ID Registers */
176#define EISA_ID0 iobase + 0x0c80 /* EISA ID Register 0 */ 176#define EISA_ID0 iobase + 0x0c80 /* EISA ID Register 0 */
177#define EISA_ID1 iobase + 0x0c81 /* EISA ID Register 1 */ 177#define EISA_ID1 iobase + 0x0c81 /* EISA ID Register 1 */
178#define EISA_ID2 iobase + 0x0c82 /* EISA ID Register 2 */ 178#define EISA_ID2 iobase + 0x0c82 /* EISA ID Register 2 */
179#define EISA_ID3 iobase + 0x0c83 /* EISA ID Register 3 */ 179#define EISA_ID3 iobase + 0x0c83 /* EISA ID Register 3 */
180#define EISA_CR iobase + 0x0c84 /* EISA Control Register */ 180#define EISA_CR iobase + 0x0c84 /* EISA Control Register */
181 181
182/* 182/*
@@ -223,7 +223,7 @@
223/* 223/*
224** EEPROM MISCELLANEOUS FLAGS 224** EEPROM MISCELLANEOUS FLAGS
225*/ 225*/
226#define RBE_SHADOW 0x0100 /* Remote Boot Enable Shadow */ 226#define RBE_SHADOW 0x0100 /* Remote Boot Enable Shadow */
227#define READ_AHEAD 0x0080 /* Read Ahead feature */ 227#define READ_AHEAD 0x0080 /* Read Ahead feature */
228#define IRQ_SEL2 0x0070 /* IRQ line selection (LeMAC2) */ 228#define IRQ_SEL2 0x0070 /* IRQ line selection (LeMAC2) */
229#define IRQ_SEL 0x0060 /* IRQ line selection */ 229#define IRQ_SEL 0x0060 /* IRQ line selection */
@@ -242,7 +242,7 @@
242/* 242/*
243** EEPROM SW FLAGS 243** EEPROM SW FLAGS
244*/ 244*/
245#define SW_SQE 0x10 /* Signal Quality Error */ 245#define SW_SQE 0x10 /* Signal Quality Error */
246#define SW_LAB 0x08 /* Less Aggressive Backoff */ 246#define SW_LAB 0x08 /* Less Aggressive Backoff */
247#define SW_INIT 0x04 /* Initialized */ 247#define SW_INIT 0x04 /* Initialized */
248#define SW_TIMEOUT 0x02 /* 0:2.5 mins, 1: 30 secs */ 248#define SW_TIMEOUT 0x02 /* 0:2.5 mins, 1: 30 secs */
@@ -299,8 +299,8 @@ struct ewrk3_ioctl {
299 unsigned char __user *data; /* Pointer to the data buffer */ 299 unsigned char __user *data; /* Pointer to the data buffer */
300}; 300};
301 301
302/* 302/*
303** Recognised commands for the driver 303** Recognised commands for the driver
304*/ 304*/
305#define EWRK3_GET_HWADDR 0x01 /* Get the hardware address */ 305#define EWRK3_GET_HWADDR 0x01 /* Get the hardware address */
306#define EWRK3_SET_HWADDR 0x02 /* Get the hardware address */ 306#define EWRK3_SET_HWADDR 0x02 /* Get the hardware address */