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authorRasesh Mody <rmody@brocade.com>2011-08-08 12:21:41 -0400
committerDavid S. Miller <davem@davemloft.net>2011-08-11 10:30:13 -0400
commite827e3262234144d9f978dcf66b8ed806140bb3f (patch)
tree4438ffbc063fae0d926733dfe352485a00220a80 /drivers/net/ethernet
parentf6d46a2ea909f96a318635674f4924b816c161c4 (diff)
bna: Remove Obsolete Files
Change details: - Removec bfi_ll.h bna_hw.h bna_ctrl.c and bna_txrx.c due to ENET, MSGQ and TXRX changes for new FW Driver interface and TX RX re-design. Signed-off-by: Rasesh Mody <rmody@brocade.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet')
-rw-r--r--drivers/net/ethernet/brocade/bna/bfi_ll.h438
-rw-r--r--drivers/net/ethernet/brocade/bna/bna.h1
-rw-r--r--drivers/net/ethernet/brocade/bna/bna_ctrl.c3078
-rw-r--r--drivers/net/ethernet/brocade/bna/bna_hw.h1492
-rw-r--r--drivers/net/ethernet/brocade/bna/bna_txrx.c4185
5 files changed, 0 insertions, 9194 deletions
diff --git a/drivers/net/ethernet/brocade/bna/bfi_ll.h b/drivers/net/ethernet/brocade/bna/bfi_ll.h
deleted file mode 100644
index bee4d054066a..000000000000
--- a/drivers/net/ethernet/brocade/bna/bfi_ll.h
+++ /dev/null
@@ -1,438 +0,0 @@
1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18#ifndef __BFI_LL_H__
19#define __BFI_LL_H__
20
21#include "bfi.h"
22
23#pragma pack(1)
24
25/**
26 * @brief
27 * "enums" for all LL mailbox messages other than IOC
28 */
29enum {
30 BFI_LL_H2I_MAC_UCAST_SET_REQ = 1,
31 BFI_LL_H2I_MAC_UCAST_ADD_REQ = 2,
32 BFI_LL_H2I_MAC_UCAST_DEL_REQ = 3,
33
34 BFI_LL_H2I_MAC_MCAST_ADD_REQ = 4,
35 BFI_LL_H2I_MAC_MCAST_DEL_REQ = 5,
36 BFI_LL_H2I_MAC_MCAST_FILTER_REQ = 6,
37 BFI_LL_H2I_MAC_MCAST_DEL_ALL_REQ = 7,
38
39 BFI_LL_H2I_PORT_ADMIN_REQ = 8,
40 BFI_LL_H2I_STATS_GET_REQ = 9,
41 BFI_LL_H2I_STATS_CLEAR_REQ = 10,
42
43 BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ = 11,
44 BFI_LL_H2I_RXF_DEFAULT_SET_REQ = 12,
45
46 BFI_LL_H2I_TXQ_STOP_REQ = 13,
47 BFI_LL_H2I_RXQ_STOP_REQ = 14,
48
49 BFI_LL_H2I_DIAG_LOOPBACK_REQ = 15,
50
51 BFI_LL_H2I_SET_PAUSE_REQ = 16,
52 BFI_LL_H2I_MTU_INFO_REQ = 17,
53
54 BFI_LL_H2I_RX_REQ = 18,
55} ;
56
57enum {
58 BFI_LL_I2H_MAC_UCAST_SET_RSP = BFA_I2HM(1),
59 BFI_LL_I2H_MAC_UCAST_ADD_RSP = BFA_I2HM(2),
60 BFI_LL_I2H_MAC_UCAST_DEL_RSP = BFA_I2HM(3),
61
62 BFI_LL_I2H_MAC_MCAST_ADD_RSP = BFA_I2HM(4),
63 BFI_LL_I2H_MAC_MCAST_DEL_RSP = BFA_I2HM(5),
64 BFI_LL_I2H_MAC_MCAST_FILTER_RSP = BFA_I2HM(6),
65 BFI_LL_I2H_MAC_MCAST_DEL_ALL_RSP = BFA_I2HM(7),
66
67 BFI_LL_I2H_PORT_ADMIN_RSP = BFA_I2HM(8),
68 BFI_LL_I2H_STATS_GET_RSP = BFA_I2HM(9),
69 BFI_LL_I2H_STATS_CLEAR_RSP = BFA_I2HM(10),
70
71 BFI_LL_I2H_RXF_PROMISCUOUS_SET_RSP = BFA_I2HM(11),
72 BFI_LL_I2H_RXF_DEFAULT_SET_RSP = BFA_I2HM(12),
73
74 BFI_LL_I2H_TXQ_STOP_RSP = BFA_I2HM(13),
75 BFI_LL_I2H_RXQ_STOP_RSP = BFA_I2HM(14),
76
77 BFI_LL_I2H_DIAG_LOOPBACK_RSP = BFA_I2HM(15),
78
79 BFI_LL_I2H_SET_PAUSE_RSP = BFA_I2HM(16),
80
81 BFI_LL_I2H_MTU_INFO_RSP = BFA_I2HM(17),
82 BFI_LL_I2H_RX_RSP = BFA_I2HM(18),
83
84 BFI_LL_I2H_LINK_DOWN_AEN = BFA_I2HM(19),
85 BFI_LL_I2H_LINK_UP_AEN = BFA_I2HM(20),
86
87 BFI_LL_I2H_PORT_ENABLE_AEN = BFA_I2HM(21),
88 BFI_LL_I2H_PORT_DISABLE_AEN = BFA_I2HM(22),
89} ;
90
91/**
92 * @brief bfi_ll_mac_addr_req is used by:
93 * BFI_LL_H2I_MAC_UCAST_SET_REQ
94 * BFI_LL_H2I_MAC_UCAST_ADD_REQ
95 * BFI_LL_H2I_MAC_UCAST_DEL_REQ
96 * BFI_LL_H2I_MAC_MCAST_ADD_REQ
97 * BFI_LL_H2I_MAC_MCAST_DEL_REQ
98 */
99struct bfi_ll_mac_addr_req {
100 struct bfi_mhdr mh; /*!< common msg header */
101 u8 rxf_id;
102 u8 rsvd1[3];
103 mac_t mac_addr;
104 u8 rsvd2[2];
105};
106
107/**
108 * @brief bfi_ll_mcast_filter_req is used by:
109 * BFI_LL_H2I_MAC_MCAST_FILTER_REQ
110 */
111struct bfi_ll_mcast_filter_req {
112 struct bfi_mhdr mh; /*!< common msg header */
113 u8 rxf_id;
114 u8 enable;
115 u8 rsvd[2];
116};
117
118/**
119 * @brief bfi_ll_mcast_del_all is used by:
120 * BFI_LL_H2I_MAC_MCAST_DEL_ALL_REQ
121 */
122struct bfi_ll_mcast_del_all_req {
123 struct bfi_mhdr mh; /*!< common msg header */
124 u8 rxf_id;
125 u8 rsvd[3];
126};
127
128/**
129 * @brief bfi_ll_q_stop_req is used by:
130 * BFI_LL_H2I_TXQ_STOP_REQ
131 * BFI_LL_H2I_RXQ_STOP_REQ
132 */
133struct bfi_ll_q_stop_req {
134 struct bfi_mhdr mh; /*!< common msg header */
135 u32 q_id_mask[2]; /* !< bit-mask for queue ids */
136};
137
138/**
139 * @brief bfi_ll_stats_req is used by:
140 * BFI_LL_I2H_STATS_GET_REQ
141 * BFI_LL_I2H_STATS_CLEAR_REQ
142 */
143struct bfi_ll_stats_req {
144 struct bfi_mhdr mh; /*!< common msg header */
145 u16 stats_mask; /* !< bit-mask for non-function statistics */
146 u8 rsvd[2];
147 u32 rxf_id_mask[2]; /* !< bit-mask for RxF Statistics */
148 u32 txf_id_mask[2]; /* !< bit-mask for TxF Statistics */
149 union bfi_addr_u host_buffer; /* !< where statistics are returned */
150};
151
152/**
153 * @brief defines for "stats_mask" above.
154 */
155#define BFI_LL_STATS_MAC (1 << 0) /* !< MAC Statistics */
156#define BFI_LL_STATS_BPC (1 << 1) /* !< Pause Stats from BPC */
157#define BFI_LL_STATS_RAD (1 << 2) /* !< Rx Admission Statistics */
158#define BFI_LL_STATS_RX_FC (1 << 3) /* !< Rx FC Stats from RxA */
159#define BFI_LL_STATS_TX_FC (1 << 4) /* !< Tx FC Stats from TxA */
160
161#define BFI_LL_STATS_ALL 0x1f
162
163/**
164 * @brief bfi_ll_port_admin_req
165 */
166struct bfi_ll_port_admin_req {
167 struct bfi_mhdr mh; /*!< common msg header */
168 u8 up;
169 u8 rsvd[3];
170};
171
172/**
173 * @brief bfi_ll_rxf_req is used by:
174 * BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ
175 * BFI_LL_H2I_RXF_DEFAULT_SET_REQ
176 */
177struct bfi_ll_rxf_req {
178 struct bfi_mhdr mh; /*!< common msg header */
179 u8 rxf_id;
180 u8 enable;
181 u8 rsvd[2];
182};
183
184/**
185 * @brief bfi_ll_rxf_multi_req is used by:
186 * BFI_LL_H2I_RX_REQ
187 */
188struct bfi_ll_rxf_multi_req {
189 struct bfi_mhdr mh; /*!< common msg header */
190 u32 rxf_id_mask[2];
191 u8 enable;
192 u8 rsvd[3];
193};
194
195/**
196 * @brief enum for Loopback opmodes
197 */
198enum {
199 BFI_LL_DIAG_LB_OPMODE_EXT = 0,
200 BFI_LL_DIAG_LB_OPMODE_CBL = 1,
201};
202
203/**
204 * @brief bfi_ll_set_pause_req is used by:
205 * BFI_LL_H2I_SET_PAUSE_REQ
206 */
207struct bfi_ll_set_pause_req {
208 struct bfi_mhdr mh;
209 u8 tx_pause; /* 1 = enable, 0 = disable */
210 u8 rx_pause; /* 1 = enable, 0 = disable */
211 u8 rsvd[2];
212};
213
214/**
215 * @brief bfi_ll_mtu_info_req is used by:
216 * BFI_LL_H2I_MTU_INFO_REQ
217 */
218struct bfi_ll_mtu_info_req {
219 struct bfi_mhdr mh;
220 u16 mtu;
221 u8 rsvd[2];
222};
223
224/**
225 * @brief
226 * Response header format used by all responses
227 * For both responses and asynchronous notifications
228 */
229struct bfi_ll_rsp {
230 struct bfi_mhdr mh; /*!< common msg header */
231 u8 error;
232 u8 rsvd[3];
233};
234
235/**
236 * @brief bfi_ll_cee_aen is used by:
237 * BFI_LL_I2H_LINK_DOWN_AEN
238 * BFI_LL_I2H_LINK_UP_AEN
239 */
240struct bfi_ll_aen {
241 struct bfi_mhdr mh; /*!< common msg header */
242 u32 reason;
243 u8 cee_linkup;
244 u8 prio_map; /*!< LL priority bit-map */
245 u8 rsvd[2];
246};
247
248/**
249 * @brief
250 * The following error codes can be returned
251 * by the mbox commands
252 */
253enum {
254 BFI_LL_CMD_OK = 0,
255 BFI_LL_CMD_FAIL = 1,
256 BFI_LL_CMD_DUP_ENTRY = 2, /* !< Duplicate entry in CAM */
257 BFI_LL_CMD_CAM_FULL = 3, /* !< CAM is full */
258 BFI_LL_CMD_NOT_OWNER = 4, /* !< Not permitted, b'cos not owner */
259 BFI_LL_CMD_NOT_EXEC = 5, /* !< Was not sent to f/w at all */
260 BFI_LL_CMD_WAITING = 6, /* !< Waiting for completion (VMware) */
261 BFI_LL_CMD_PORT_DISABLED = 7, /* !< port in disabled state */
262} ;
263
264/* Statistics */
265#define BFI_LL_TXF_ID_MAX 64
266#define BFI_LL_RXF_ID_MAX 64
267
268/* TxF Frame Statistics */
269struct bfi_ll_stats_txf {
270 u64 ucast_octets;
271 u64 ucast;
272 u64 ucast_vlan;
273
274 u64 mcast_octets;
275 u64 mcast;
276 u64 mcast_vlan;
277
278 u64 bcast_octets;
279 u64 bcast;
280 u64 bcast_vlan;
281
282 u64 errors;
283 u64 filter_vlan; /* frames filtered due to VLAN */
284 u64 filter_mac_sa; /* frames filtered due to SA check */
285};
286
287/* RxF Frame Statistics */
288struct bfi_ll_stats_rxf {
289 u64 ucast_octets;
290 u64 ucast;
291 u64 ucast_vlan;
292
293 u64 mcast_octets;
294 u64 mcast;
295 u64 mcast_vlan;
296
297 u64 bcast_octets;
298 u64 bcast;
299 u64 bcast_vlan;
300 u64 frame_drops;
301};
302
303/* FC Tx Frame Statistics */
304struct bfi_ll_stats_fc_tx {
305 u64 txf_ucast_octets;
306 u64 txf_ucast;
307 u64 txf_ucast_vlan;
308
309 u64 txf_mcast_octets;
310 u64 txf_mcast;
311 u64 txf_mcast_vlan;
312
313 u64 txf_bcast_octets;
314 u64 txf_bcast;
315 u64 txf_bcast_vlan;
316
317 u64 txf_parity_errors;
318 u64 txf_timeout;
319 u64 txf_fid_parity_errors;
320};
321
322/* FC Rx Frame Statistics */
323struct bfi_ll_stats_fc_rx {
324 u64 rxf_ucast_octets;
325 u64 rxf_ucast;
326 u64 rxf_ucast_vlan;
327
328 u64 rxf_mcast_octets;
329 u64 rxf_mcast;
330 u64 rxf_mcast_vlan;
331
332 u64 rxf_bcast_octets;
333 u64 rxf_bcast;
334 u64 rxf_bcast_vlan;
335};
336
337/* RAD Frame Statistics */
338struct bfi_ll_stats_rad {
339 u64 rx_frames;
340 u64 rx_octets;
341 u64 rx_vlan_frames;
342
343 u64 rx_ucast;
344 u64 rx_ucast_octets;
345 u64 rx_ucast_vlan;
346
347 u64 rx_mcast;
348 u64 rx_mcast_octets;
349 u64 rx_mcast_vlan;
350
351 u64 rx_bcast;
352 u64 rx_bcast_octets;
353 u64 rx_bcast_vlan;
354
355 u64 rx_drops;
356};
357
358/* BPC Tx Registers */
359struct bfi_ll_stats_bpc {
360 /* transmit stats */
361 u64 tx_pause[8];
362 u64 tx_zero_pause[8]; /*!< Pause cancellation */
363 /*!<Pause initiation rather than retention */
364 u64 tx_first_pause[8];
365
366 /* receive stats */
367 u64 rx_pause[8];
368 u64 rx_zero_pause[8]; /*!< Pause cancellation */
369 /*!<Pause initiation rather than retention */
370 u64 rx_first_pause[8];
371};
372
373/* MAC Rx Statistics */
374struct bfi_ll_stats_mac {
375 u64 frame_64; /* both rx and tx counter */
376 u64 frame_65_127; /* both rx and tx counter */
377 u64 frame_128_255; /* both rx and tx counter */
378 u64 frame_256_511; /* both rx and tx counter */
379 u64 frame_512_1023; /* both rx and tx counter */
380 u64 frame_1024_1518; /* both rx and tx counter */
381 u64 frame_1519_1522; /* both rx and tx counter */
382
383 /* receive stats */
384 u64 rx_bytes;
385 u64 rx_packets;
386 u64 rx_fcs_error;
387 u64 rx_multicast;
388 u64 rx_broadcast;
389 u64 rx_control_frames;
390 u64 rx_pause;
391 u64 rx_unknown_opcode;
392 u64 rx_alignment_error;
393 u64 rx_frame_length_error;
394 u64 rx_code_error;
395 u64 rx_carrier_sense_error;
396 u64 rx_undersize;
397 u64 rx_oversize;
398 u64 rx_fragments;
399 u64 rx_jabber;
400 u64 rx_drop;
401
402 /* transmit stats */
403 u64 tx_bytes;
404 u64 tx_packets;
405 u64 tx_multicast;
406 u64 tx_broadcast;
407 u64 tx_pause;
408 u64 tx_deferral;
409 u64 tx_excessive_deferral;
410 u64 tx_single_collision;
411 u64 tx_muliple_collision;
412 u64 tx_late_collision;
413 u64 tx_excessive_collision;
414 u64 tx_total_collision;
415 u64 tx_pause_honored;
416 u64 tx_drop;
417 u64 tx_jabber;
418 u64 tx_fcs_error;
419 u64 tx_control_frame;
420 u64 tx_oversize;
421 u64 tx_undersize;
422 u64 tx_fragments;
423};
424
425/* Complete statistics */
426struct bfi_ll_stats {
427 struct bfi_ll_stats_mac mac_stats;
428 struct bfi_ll_stats_bpc bpc_stats;
429 struct bfi_ll_stats_rad rad_stats;
430 struct bfi_ll_stats_fc_rx fc_rx_stats;
431 struct bfi_ll_stats_fc_tx fc_tx_stats;
432 struct bfi_ll_stats_rxf rxf_stats[BFI_LL_RXF_ID_MAX];
433 struct bfi_ll_stats_txf txf_stats[BFI_LL_TXF_ID_MAX];
434};
435
436#pragma pack()
437
438#endif /* __BFI_LL_H__ */
diff --git a/drivers/net/ethernet/brocade/bna/bna.h b/drivers/net/ethernet/brocade/bna/bna.h
index 1f1fa936894c..2a587c5fdc20 100644
--- a/drivers/net/ethernet/brocade/bna/bna.h
+++ b/drivers/net/ethernet/brocade/bna/bna.h
@@ -16,7 +16,6 @@
16#include "bfa_cs.h" 16#include "bfa_cs.h"
17#include "bfa_ioc.h" 17#include "bfa_ioc.h"
18#include "cna.h" 18#include "cna.h"
19#include "bfi_ll.h"
20#include "bna_types.h" 19#include "bna_types.h"
21 20
22extern const u32 bna_napi_dim_vector[][BNA_BIAS_T_MAX]; 21extern const u32 bna_napi_dim_vector[][BNA_BIAS_T_MAX];
diff --git a/drivers/net/ethernet/brocade/bna/bna_ctrl.c b/drivers/net/ethernet/brocade/bna/bna_ctrl.c
deleted file mode 100644
index 7d9551778274..000000000000
--- a/drivers/net/ethernet/brocade/bna/bna_ctrl.c
+++ /dev/null
@@ -1,3078 +0,0 @@
1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18#include "bna.h"
19#include "bfa_cs.h"
20
21static void bna_device_cb_port_stopped(void *arg, enum bna_cb_status status);
22
23static void
24bna_port_cb_link_up(struct bna_port *port, struct bfi_ll_aen *aen,
25 int status)
26{
27 int i;
28 u8 prio_map;
29
30 port->llport.link_status = BNA_LINK_UP;
31 if (aen->cee_linkup)
32 port->llport.link_status = BNA_CEE_UP;
33
34 /* Compute the priority */
35 prio_map = aen->prio_map;
36 if (prio_map) {
37 for (i = 0; i < 8; i++) {
38 if ((prio_map >> i) & 0x1)
39 break;
40 }
41 port->priority = i;
42 } else
43 port->priority = 0;
44
45 /* Dispatch events */
46 bna_tx_mod_cee_link_status(&port->bna->tx_mod, aen->cee_linkup);
47 bna_tx_mod_prio_changed(&port->bna->tx_mod, port->priority);
48 port->link_cbfn(port->bna->bnad, port->llport.link_status);
49}
50
51static void
52bna_port_cb_link_down(struct bna_port *port, int status)
53{
54 port->llport.link_status = BNA_LINK_DOWN;
55
56 /* Dispatch events */
57 bna_tx_mod_cee_link_status(&port->bna->tx_mod, BNA_LINK_DOWN);
58 port->link_cbfn(port->bna->bnad, BNA_LINK_DOWN);
59}
60
61static inline int
62llport_can_be_up(struct bna_llport *llport)
63{
64 int ready = 0;
65 if (llport->type == BNA_PORT_T_REGULAR)
66 ready = ((llport->flags & BNA_LLPORT_F_ADMIN_UP) &&
67 (llport->flags & BNA_LLPORT_F_RX_STARTED) &&
68 (llport->flags & BNA_LLPORT_F_PORT_ENABLED));
69 else
70 ready = ((llport->flags & BNA_LLPORT_F_ADMIN_UP) &&
71 (llport->flags & BNA_LLPORT_F_RX_STARTED) &&
72 !(llport->flags & BNA_LLPORT_F_PORT_ENABLED));
73 return ready;
74}
75
76#define llport_is_up llport_can_be_up
77
78enum bna_llport_event {
79 LLPORT_E_START = 1,
80 LLPORT_E_STOP = 2,
81 LLPORT_E_FAIL = 3,
82 LLPORT_E_UP = 4,
83 LLPORT_E_DOWN = 5,
84 LLPORT_E_FWRESP_UP_OK = 6,
85 LLPORT_E_FWRESP_UP_FAIL = 7,
86 LLPORT_E_FWRESP_DOWN = 8
87};
88
89static void
90bna_llport_cb_port_enabled(struct bna_llport *llport)
91{
92 llport->flags |= BNA_LLPORT_F_PORT_ENABLED;
93
94 if (llport_can_be_up(llport))
95 bfa_fsm_send_event(llport, LLPORT_E_UP);
96}
97
98static void
99bna_llport_cb_port_disabled(struct bna_llport *llport)
100{
101 int llport_up = llport_is_up(llport);
102
103 llport->flags &= ~BNA_LLPORT_F_PORT_ENABLED;
104
105 if (llport_up)
106 bfa_fsm_send_event(llport, LLPORT_E_DOWN);
107}
108
109/**
110 * MBOX
111 */
112static int
113bna_is_aen(u8 msg_id)
114{
115 switch (msg_id) {
116 case BFI_LL_I2H_LINK_DOWN_AEN:
117 case BFI_LL_I2H_LINK_UP_AEN:
118 case BFI_LL_I2H_PORT_ENABLE_AEN:
119 case BFI_LL_I2H_PORT_DISABLE_AEN:
120 return 1;
121
122 default:
123 return 0;
124 }
125}
126
127static void
128bna_mbox_aen_callback(struct bna *bna, struct bfi_mbmsg *msg)
129{
130 struct bfi_ll_aen *aen = (struct bfi_ll_aen *)(msg);
131
132 switch (aen->mh.msg_id) {
133 case BFI_LL_I2H_LINK_UP_AEN:
134 bna_port_cb_link_up(&bna->port, aen, aen->reason);
135 break;
136 case BFI_LL_I2H_LINK_DOWN_AEN:
137 bna_port_cb_link_down(&bna->port, aen->reason);
138 break;
139 case BFI_LL_I2H_PORT_ENABLE_AEN:
140 bna_llport_cb_port_enabled(&bna->port.llport);
141 break;
142 case BFI_LL_I2H_PORT_DISABLE_AEN:
143 bna_llport_cb_port_disabled(&bna->port.llport);
144 break;
145 default:
146 break;
147 }
148}
149
150static void
151bna_ll_isr(void *llarg, struct bfi_mbmsg *msg)
152{
153 struct bna *bna = (struct bna *)(llarg);
154 struct bfi_ll_rsp *mb_rsp = (struct bfi_ll_rsp *)(msg);
155 struct bfi_mhdr *cmd_h, *rsp_h;
156 struct bna_mbox_qe *mb_qe = NULL;
157 int to_post = 0;
158 u8 aen = 0;
159 char message[BNA_MESSAGE_SIZE];
160
161 aen = bna_is_aen(mb_rsp->mh.msg_id);
162
163 if (!aen) {
164 mb_qe = bfa_q_first(&bna->mbox_mod.posted_q);
165 cmd_h = (struct bfi_mhdr *)(&mb_qe->cmd.msg[0]);
166 rsp_h = (struct bfi_mhdr *)(&mb_rsp->mh);
167
168 if ((BFA_I2HM(cmd_h->msg_id) == rsp_h->msg_id) &&
169 (cmd_h->mtag.i2htok == rsp_h->mtag.i2htok)) {
170 /* Remove the request from posted_q, update state */
171 list_del(&mb_qe->qe);
172 bna->mbox_mod.msg_pending--;
173 if (list_empty(&bna->mbox_mod.posted_q))
174 bna->mbox_mod.state = BNA_MBOX_FREE;
175 else
176 to_post = 1;
177
178 /* Dispatch the cbfn */
179 if (mb_qe->cbfn)
180 mb_qe->cbfn(mb_qe->cbarg, mb_rsp->error);
181
182 /* Post the next entry, if needed */
183 if (to_post) {
184 mb_qe = bfa_q_first(&bna->mbox_mod.posted_q);
185 bfa_nw_ioc_mbox_queue(&bna->device.ioc,
186 &mb_qe->cmd, NULL,
187 NULL);
188 }
189 } else {
190 snprintf(message, BNA_MESSAGE_SIZE,
191 "No matching rsp for [%d:%d:%d]\n",
192 mb_rsp->mh.msg_class, mb_rsp->mh.msg_id,
193 mb_rsp->mh.mtag.i2htok);
194 pr_info("%s", message);
195 }
196
197 } else
198 bna_mbox_aen_callback(bna, msg);
199}
200
201static void
202bna_err_handler(struct bna *bna, u32 intr_status)
203{
204 u32 init_halt;
205
206 if (intr_status & __HALT_STATUS_BITS) {
207 init_halt = readl(bna->device.ioc.ioc_regs.ll_halt);
208 init_halt &= ~__FW_INIT_HALT_P;
209 writel(init_halt, bna->device.ioc.ioc_regs.ll_halt);
210 }
211
212 bfa_nw_ioc_error_isr(&bna->device.ioc);
213}
214
215void
216bna_mbox_handler(struct bna *bna, u32 intr_status)
217{
218 if (BNA_IS_ERR_INTR(intr_status)) {
219 bna_err_handler(bna, intr_status);
220 return;
221 }
222 if (BNA_IS_MBOX_INTR(intr_status))
223 bfa_nw_ioc_mbox_isr(&bna->device.ioc);
224}
225
226void
227bna_mbox_send(struct bna *bna, struct bna_mbox_qe *mbox_qe)
228{
229 struct bfi_mhdr *mh;
230
231 mh = (struct bfi_mhdr *)(&mbox_qe->cmd.msg[0]);
232
233 mh->mtag.i2htok = htons(bna->mbox_mod.msg_ctr);
234 bna->mbox_mod.msg_ctr++;
235 bna->mbox_mod.msg_pending++;
236 if (bna->mbox_mod.state == BNA_MBOX_FREE) {
237 list_add_tail(&mbox_qe->qe, &bna->mbox_mod.posted_q);
238 bfa_nw_ioc_mbox_queue(&bna->device.ioc, &mbox_qe->cmd,
239 NULL, NULL);
240 bna->mbox_mod.state = BNA_MBOX_POSTED;
241 } else {
242 list_add_tail(&mbox_qe->qe, &bna->mbox_mod.posted_q);
243 }
244}
245
246static void
247bna_mbox_flush_q(struct bna *bna, struct list_head *q)
248{
249 struct bna_mbox_qe *mb_qe = NULL;
250 struct list_head *mb_q;
251 void (*cbfn)(void *arg, int status);
252 void *cbarg;
253
254 mb_q = &bna->mbox_mod.posted_q;
255
256 while (!list_empty(mb_q)) {
257 bfa_q_deq(mb_q, &mb_qe);
258 cbfn = mb_qe->cbfn;
259 cbarg = mb_qe->cbarg;
260 bfa_q_qe_init(mb_qe);
261 bna->mbox_mod.msg_pending--;
262
263 if (cbfn)
264 cbfn(cbarg, BNA_CB_NOT_EXEC);
265 }
266
267 bna->mbox_mod.state = BNA_MBOX_FREE;
268}
269
270static void
271bna_mbox_mod_start(struct bna_mbox_mod *mbox_mod)
272{
273}
274
275static void
276bna_mbox_mod_stop(struct bna_mbox_mod *mbox_mod)
277{
278 bna_mbox_flush_q(mbox_mod->bna, &mbox_mod->posted_q);
279}
280
281static void
282bna_mbox_mod_init(struct bna_mbox_mod *mbox_mod, struct bna *bna)
283{
284 bfa_nw_ioc_mbox_regisr(&bna->device.ioc, BFI_MC_LL, bna_ll_isr, bna);
285 mbox_mod->state = BNA_MBOX_FREE;
286 mbox_mod->msg_ctr = mbox_mod->msg_pending = 0;
287 INIT_LIST_HEAD(&mbox_mod->posted_q);
288 mbox_mod->bna = bna;
289}
290
291static void
292bna_mbox_mod_uninit(struct bna_mbox_mod *mbox_mod)
293{
294 mbox_mod->bna = NULL;
295}
296
297/**
298 * LLPORT
299 */
300#define call_llport_stop_cbfn(llport, status)\
301do {\
302 if ((llport)->stop_cbfn)\
303 (llport)->stop_cbfn(&(llport)->bna->port, status);\
304 (llport)->stop_cbfn = NULL;\
305} while (0)
306
307static void bna_fw_llport_up(struct bna_llport *llport);
308static void bna_fw_cb_llport_up(void *arg, int status);
309static void bna_fw_llport_down(struct bna_llport *llport);
310static void bna_fw_cb_llport_down(void *arg, int status);
311static void bna_llport_start(struct bna_llport *llport);
312static void bna_llport_stop(struct bna_llport *llport);
313static void bna_llport_fail(struct bna_llport *llport);
314
315enum bna_llport_state {
316 BNA_LLPORT_STOPPED = 1,
317 BNA_LLPORT_DOWN = 2,
318 BNA_LLPORT_UP_RESP_WAIT = 3,
319 BNA_LLPORT_DOWN_RESP_WAIT = 4,
320 BNA_LLPORT_UP = 5,
321 BNA_LLPORT_LAST_RESP_WAIT = 6
322};
323
324bfa_fsm_state_decl(bna_llport, stopped, struct bna_llport,
325 enum bna_llport_event);
326bfa_fsm_state_decl(bna_llport, down, struct bna_llport,
327 enum bna_llport_event);
328bfa_fsm_state_decl(bna_llport, up_resp_wait, struct bna_llport,
329 enum bna_llport_event);
330bfa_fsm_state_decl(bna_llport, down_resp_wait, struct bna_llport,
331 enum bna_llport_event);
332bfa_fsm_state_decl(bna_llport, up, struct bna_llport,
333 enum bna_llport_event);
334bfa_fsm_state_decl(bna_llport, last_resp_wait, struct bna_llport,
335 enum bna_llport_event);
336
337static struct bfa_sm_table llport_sm_table[] = {
338 {BFA_SM(bna_llport_sm_stopped), BNA_LLPORT_STOPPED},
339 {BFA_SM(bna_llport_sm_down), BNA_LLPORT_DOWN},
340 {BFA_SM(bna_llport_sm_up_resp_wait), BNA_LLPORT_UP_RESP_WAIT},
341 {BFA_SM(bna_llport_sm_down_resp_wait), BNA_LLPORT_DOWN_RESP_WAIT},
342 {BFA_SM(bna_llport_sm_up), BNA_LLPORT_UP},
343 {BFA_SM(bna_llport_sm_last_resp_wait), BNA_LLPORT_LAST_RESP_WAIT}
344};
345
346static void
347bna_llport_sm_stopped_entry(struct bna_llport *llport)
348{
349 llport->bna->port.link_cbfn((llport)->bna->bnad, BNA_LINK_DOWN);
350 call_llport_stop_cbfn(llport, BNA_CB_SUCCESS);
351}
352
353static void
354bna_llport_sm_stopped(struct bna_llport *llport,
355 enum bna_llport_event event)
356{
357 switch (event) {
358 case LLPORT_E_START:
359 bfa_fsm_set_state(llport, bna_llport_sm_down);
360 break;
361
362 case LLPORT_E_STOP:
363 call_llport_stop_cbfn(llport, BNA_CB_SUCCESS);
364 break;
365
366 case LLPORT_E_FAIL:
367 break;
368
369 case LLPORT_E_DOWN:
370 /* This event is received due to Rx objects failing */
371 /* No-op */
372 break;
373
374 case LLPORT_E_FWRESP_UP_OK:
375 case LLPORT_E_FWRESP_DOWN:
376 /**
377 * These events are received due to flushing of mbox when
378 * device fails
379 */
380 /* No-op */
381 break;
382
383 default:
384 bfa_sm_fault(event);
385 }
386}
387
388static void
389bna_llport_sm_down_entry(struct bna_llport *llport)
390{
391 bnad_cb_port_link_status((llport)->bna->bnad, BNA_LINK_DOWN);
392}
393
394static void
395bna_llport_sm_down(struct bna_llport *llport,
396 enum bna_llport_event event)
397{
398 switch (event) {
399 case LLPORT_E_STOP:
400 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
401 break;
402
403 case LLPORT_E_FAIL:
404 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
405 break;
406
407 case LLPORT_E_UP:
408 bfa_fsm_set_state(llport, bna_llport_sm_up_resp_wait);
409 bna_fw_llport_up(llport);
410 break;
411
412 default:
413 bfa_sm_fault(event);
414 }
415}
416
417static void
418bna_llport_sm_up_resp_wait_entry(struct bna_llport *llport)
419{
420 BUG_ON(!llport_can_be_up(llport));
421 /**
422 * NOTE: Do not call bna_fw_llport_up() here. That will over step
423 * mbox due to down_resp_wait -> up_resp_wait transition on event
424 * LLPORT_E_UP
425 */
426}
427
428static void
429bna_llport_sm_up_resp_wait(struct bna_llport *llport,
430 enum bna_llport_event event)
431{
432 switch (event) {
433 case LLPORT_E_STOP:
434 bfa_fsm_set_state(llport, bna_llport_sm_last_resp_wait);
435 break;
436
437 case LLPORT_E_FAIL:
438 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
439 break;
440
441 case LLPORT_E_DOWN:
442 bfa_fsm_set_state(llport, bna_llport_sm_down_resp_wait);
443 break;
444
445 case LLPORT_E_FWRESP_UP_OK:
446 bfa_fsm_set_state(llport, bna_llport_sm_up);
447 break;
448
449 case LLPORT_E_FWRESP_UP_FAIL:
450 bfa_fsm_set_state(llport, bna_llport_sm_down);
451 break;
452
453 case LLPORT_E_FWRESP_DOWN:
454 /* down_resp_wait -> up_resp_wait transition on LLPORT_E_UP */
455 bna_fw_llport_up(llport);
456 break;
457
458 default:
459 bfa_sm_fault(event);
460 }
461}
462
463static void
464bna_llport_sm_down_resp_wait_entry(struct bna_llport *llport)
465{
466 /**
467 * NOTE: Do not call bna_fw_llport_down() here. That will over step
468 * mbox due to up_resp_wait -> down_resp_wait transition on event
469 * LLPORT_E_DOWN
470 */
471}
472
473static void
474bna_llport_sm_down_resp_wait(struct bna_llport *llport,
475 enum bna_llport_event event)
476{
477 switch (event) {
478 case LLPORT_E_STOP:
479 bfa_fsm_set_state(llport, bna_llport_sm_last_resp_wait);
480 break;
481
482 case LLPORT_E_FAIL:
483 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
484 break;
485
486 case LLPORT_E_UP:
487 bfa_fsm_set_state(llport, bna_llport_sm_up_resp_wait);
488 break;
489
490 case LLPORT_E_FWRESP_UP_OK:
491 /* up_resp_wait->down_resp_wait transition on LLPORT_E_DOWN */
492 bna_fw_llport_down(llport);
493 break;
494
495 case LLPORT_E_FWRESP_UP_FAIL:
496 case LLPORT_E_FWRESP_DOWN:
497 bfa_fsm_set_state(llport, bna_llport_sm_down);
498 break;
499
500 default:
501 bfa_sm_fault(event);
502 }
503}
504
505static void
506bna_llport_sm_up_entry(struct bna_llport *llport)
507{
508}
509
510static void
511bna_llport_sm_up(struct bna_llport *llport,
512 enum bna_llport_event event)
513{
514 switch (event) {
515 case LLPORT_E_STOP:
516 bfa_fsm_set_state(llport, bna_llport_sm_last_resp_wait);
517 bna_fw_llport_down(llport);
518 break;
519
520 case LLPORT_E_FAIL:
521 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
522 break;
523
524 case LLPORT_E_DOWN:
525 bfa_fsm_set_state(llport, bna_llport_sm_down_resp_wait);
526 bna_fw_llport_down(llport);
527 break;
528
529 default:
530 bfa_sm_fault(event);
531 }
532}
533
534static void
535bna_llport_sm_last_resp_wait_entry(struct bna_llport *llport)
536{
537}
538
539static void
540bna_llport_sm_last_resp_wait(struct bna_llport *llport,
541 enum bna_llport_event event)
542{
543 switch (event) {
544 case LLPORT_E_FAIL:
545 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
546 break;
547
548 case LLPORT_E_DOWN:
549 /**
550 * This event is received due to Rx objects stopping in
551 * parallel to llport
552 */
553 /* No-op */
554 break;
555
556 case LLPORT_E_FWRESP_UP_OK:
557 /* up_resp_wait->last_resp_wait transition on LLPORT_T_STOP */
558 bna_fw_llport_down(llport);
559 break;
560
561 case LLPORT_E_FWRESP_UP_FAIL:
562 case LLPORT_E_FWRESP_DOWN:
563 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
564 break;
565
566 default:
567 bfa_sm_fault(event);
568 }
569}
570
571static void
572bna_fw_llport_admin_up(struct bna_llport *llport)
573{
574 struct bfi_ll_port_admin_req ll_req;
575
576 memset(&ll_req, 0, sizeof(ll_req));
577 ll_req.mh.msg_class = BFI_MC_LL;
578 ll_req.mh.msg_id = BFI_LL_H2I_PORT_ADMIN_REQ;
579 ll_req.mh.mtag.h2i.lpu_id = 0;
580
581 ll_req.up = BNA_STATUS_T_ENABLED;
582
583 bna_mbox_qe_fill(&llport->mbox_qe, &ll_req, sizeof(ll_req),
584 bna_fw_cb_llport_up, llport);
585
586 bna_mbox_send(llport->bna, &llport->mbox_qe);
587}
588
589static void
590bna_fw_llport_up(struct bna_llport *llport)
591{
592 if (llport->type == BNA_PORT_T_REGULAR)
593 bna_fw_llport_admin_up(llport);
594}
595
596static void
597bna_fw_cb_llport_up(void *arg, int status)
598{
599 struct bna_llport *llport = (struct bna_llport *)arg;
600
601 bfa_q_qe_init(&llport->mbox_qe.qe);
602 if (status == BFI_LL_CMD_FAIL) {
603 if (llport->type == BNA_PORT_T_REGULAR)
604 llport->flags &= ~BNA_LLPORT_F_PORT_ENABLED;
605 else
606 llport->flags &= ~BNA_LLPORT_F_ADMIN_UP;
607 bfa_fsm_send_event(llport, LLPORT_E_FWRESP_UP_FAIL);
608 } else
609 bfa_fsm_send_event(llport, LLPORT_E_FWRESP_UP_OK);
610}
611
612static void
613bna_fw_llport_admin_down(struct bna_llport *llport)
614{
615 struct bfi_ll_port_admin_req ll_req;
616
617 memset(&ll_req, 0, sizeof(ll_req));
618 ll_req.mh.msg_class = BFI_MC_LL;
619 ll_req.mh.msg_id = BFI_LL_H2I_PORT_ADMIN_REQ;
620 ll_req.mh.mtag.h2i.lpu_id = 0;
621
622 ll_req.up = BNA_STATUS_T_DISABLED;
623
624 bna_mbox_qe_fill(&llport->mbox_qe, &ll_req, sizeof(ll_req),
625 bna_fw_cb_llport_down, llport);
626
627 bna_mbox_send(llport->bna, &llport->mbox_qe);
628}
629
630static void
631bna_fw_llport_down(struct bna_llport *llport)
632{
633 if (llport->type == BNA_PORT_T_REGULAR)
634 bna_fw_llport_admin_down(llport);
635}
636
637static void
638bna_fw_cb_llport_down(void *arg, int status)
639{
640 struct bna_llport *llport = (struct bna_llport *)arg;
641
642 bfa_q_qe_init(&llport->mbox_qe.qe);
643 bfa_fsm_send_event(llport, LLPORT_E_FWRESP_DOWN);
644}
645
646static void
647bna_port_cb_llport_stopped(struct bna_port *port,
648 enum bna_cb_status status)
649{
650 bfa_wc_down(&port->chld_stop_wc);
651}
652
653static void
654bna_llport_init(struct bna_llport *llport, struct bna *bna)
655{
656 llport->flags |= BNA_LLPORT_F_ADMIN_UP;
657 llport->flags |= BNA_LLPORT_F_PORT_ENABLED;
658 llport->type = BNA_PORT_T_REGULAR;
659 llport->bna = bna;
660
661 llport->link_status = BNA_LINK_DOWN;
662
663 llport->rx_started_count = 0;
664
665 llport->stop_cbfn = NULL;
666
667 bfa_q_qe_init(&llport->mbox_qe.qe);
668
669 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
670}
671
672static void
673bna_llport_uninit(struct bna_llport *llport)
674{
675 llport->flags &= ~BNA_LLPORT_F_ADMIN_UP;
676 llport->flags &= ~BNA_LLPORT_F_PORT_ENABLED;
677
678 llport->bna = NULL;
679}
680
681static void
682bna_llport_start(struct bna_llport *llport)
683{
684 bfa_fsm_send_event(llport, LLPORT_E_START);
685}
686
687static void
688bna_llport_stop(struct bna_llport *llport)
689{
690 llport->stop_cbfn = bna_port_cb_llport_stopped;
691
692 bfa_fsm_send_event(llport, LLPORT_E_STOP);
693}
694
695static void
696bna_llport_fail(struct bna_llport *llport)
697{
698 /* Reset the physical port status to enabled */
699 llport->flags |= BNA_LLPORT_F_PORT_ENABLED;
700 bfa_fsm_send_event(llport, LLPORT_E_FAIL);
701}
702
703static int
704bna_llport_state_get(struct bna_llport *llport)
705{
706 return bfa_sm_to_state(llport_sm_table, llport->fsm);
707}
708
709void
710bna_llport_rx_started(struct bna_llport *llport)
711{
712 llport->rx_started_count++;
713
714 if (llport->rx_started_count == 1) {
715
716 llport->flags |= BNA_LLPORT_F_RX_STARTED;
717
718 if (llport_can_be_up(llport))
719 bfa_fsm_send_event(llport, LLPORT_E_UP);
720 }
721}
722
723void
724bna_llport_rx_stopped(struct bna_llport *llport)
725{
726 int llport_up = llport_is_up(llport);
727
728 llport->rx_started_count--;
729
730 if (llport->rx_started_count == 0) {
731
732 llport->flags &= ~BNA_LLPORT_F_RX_STARTED;
733
734 if (llport_up)
735 bfa_fsm_send_event(llport, LLPORT_E_DOWN);
736 }
737}
738
739/**
740 * PORT
741 */
742#define bna_port_chld_start(port)\
743do {\
744 enum bna_tx_type tx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
745 BNA_TX_T_REGULAR : BNA_TX_T_LOOPBACK;\
746 enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
747 BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
748 bna_llport_start(&(port)->llport);\
749 bna_tx_mod_start(&(port)->bna->tx_mod, tx_type);\
750 bna_rx_mod_start(&(port)->bna->rx_mod, rx_type);\
751} while (0)
752
753#define bna_port_chld_stop(port)\
754do {\
755 enum bna_tx_type tx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
756 BNA_TX_T_REGULAR : BNA_TX_T_LOOPBACK;\
757 enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
758 BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
759 bfa_wc_up(&(port)->chld_stop_wc);\
760 bfa_wc_up(&(port)->chld_stop_wc);\
761 bfa_wc_up(&(port)->chld_stop_wc);\
762 bna_llport_stop(&(port)->llport);\
763 bna_tx_mod_stop(&(port)->bna->tx_mod, tx_type);\
764 bna_rx_mod_stop(&(port)->bna->rx_mod, rx_type);\
765} while (0)
766
767#define bna_port_chld_fail(port)\
768do {\
769 bna_llport_fail(&(port)->llport);\
770 bna_tx_mod_fail(&(port)->bna->tx_mod);\
771 bna_rx_mod_fail(&(port)->bna->rx_mod);\
772} while (0)
773
774#define bna_port_rx_start(port)\
775do {\
776 enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
777 BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
778 bna_rx_mod_start(&(port)->bna->rx_mod, rx_type);\
779} while (0)
780
781#define bna_port_rx_stop(port)\
782do {\
783 enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
784 BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
785 bfa_wc_up(&(port)->chld_stop_wc);\
786 bna_rx_mod_stop(&(port)->bna->rx_mod, rx_type);\
787} while (0)
788
789#define call_port_stop_cbfn(port, status)\
790do {\
791 if ((port)->stop_cbfn)\
792 (port)->stop_cbfn((port)->stop_cbarg, status);\
793 (port)->stop_cbfn = NULL;\
794 (port)->stop_cbarg = NULL;\
795} while (0)
796
797#define call_port_pause_cbfn(port, status)\
798do {\
799 if ((port)->pause_cbfn)\
800 (port)->pause_cbfn((port)->bna->bnad, status);\
801 (port)->pause_cbfn = NULL;\
802} while (0)
803
804#define call_port_mtu_cbfn(port, status)\
805do {\
806 if ((port)->mtu_cbfn)\
807 (port)->mtu_cbfn((port)->bna->bnad, status);\
808 (port)->mtu_cbfn = NULL;\
809} while (0)
810
811static void bna_fw_pause_set(struct bna_port *port);
812static void bna_fw_cb_pause_set(void *arg, int status);
813static void bna_fw_mtu_set(struct bna_port *port);
814static void bna_fw_cb_mtu_set(void *arg, int status);
815
816enum bna_port_event {
817 PORT_E_START = 1,
818 PORT_E_STOP = 2,
819 PORT_E_FAIL = 3,
820 PORT_E_PAUSE_CFG = 4,
821 PORT_E_MTU_CFG = 5,
822 PORT_E_CHLD_STOPPED = 6,
823 PORT_E_FWRESP_PAUSE = 7,
824 PORT_E_FWRESP_MTU = 8
825};
826
827enum bna_port_state {
828 BNA_PORT_STOPPED = 1,
829 BNA_PORT_MTU_INIT_WAIT = 2,
830 BNA_PORT_PAUSE_INIT_WAIT = 3,
831 BNA_PORT_LAST_RESP_WAIT = 4,
832 BNA_PORT_STARTED = 5,
833 BNA_PORT_PAUSE_CFG_WAIT = 6,
834 BNA_PORT_RX_STOP_WAIT = 7,
835 BNA_PORT_MTU_CFG_WAIT = 8,
836 BNA_PORT_CHLD_STOP_WAIT = 9
837};
838
839bfa_fsm_state_decl(bna_port, stopped, struct bna_port,
840 enum bna_port_event);
841bfa_fsm_state_decl(bna_port, mtu_init_wait, struct bna_port,
842 enum bna_port_event);
843bfa_fsm_state_decl(bna_port, pause_init_wait, struct bna_port,
844 enum bna_port_event);
845bfa_fsm_state_decl(bna_port, last_resp_wait, struct bna_port,
846 enum bna_port_event);
847bfa_fsm_state_decl(bna_port, started, struct bna_port,
848 enum bna_port_event);
849bfa_fsm_state_decl(bna_port, pause_cfg_wait, struct bna_port,
850 enum bna_port_event);
851bfa_fsm_state_decl(bna_port, rx_stop_wait, struct bna_port,
852 enum bna_port_event);
853bfa_fsm_state_decl(bna_port, mtu_cfg_wait, struct bna_port,
854 enum bna_port_event);
855bfa_fsm_state_decl(bna_port, chld_stop_wait, struct bna_port,
856 enum bna_port_event);
857
858static struct bfa_sm_table port_sm_table[] = {
859 {BFA_SM(bna_port_sm_stopped), BNA_PORT_STOPPED},
860 {BFA_SM(bna_port_sm_mtu_init_wait), BNA_PORT_MTU_INIT_WAIT},
861 {BFA_SM(bna_port_sm_pause_init_wait), BNA_PORT_PAUSE_INIT_WAIT},
862 {BFA_SM(bna_port_sm_last_resp_wait), BNA_PORT_LAST_RESP_WAIT},
863 {BFA_SM(bna_port_sm_started), BNA_PORT_STARTED},
864 {BFA_SM(bna_port_sm_pause_cfg_wait), BNA_PORT_PAUSE_CFG_WAIT},
865 {BFA_SM(bna_port_sm_rx_stop_wait), BNA_PORT_RX_STOP_WAIT},
866 {BFA_SM(bna_port_sm_mtu_cfg_wait), BNA_PORT_MTU_CFG_WAIT},
867 {BFA_SM(bna_port_sm_chld_stop_wait), BNA_PORT_CHLD_STOP_WAIT}
868};
869
870static void
871bna_port_sm_stopped_entry(struct bna_port *port)
872{
873 call_port_pause_cbfn(port, BNA_CB_SUCCESS);
874 call_port_mtu_cbfn(port, BNA_CB_SUCCESS);
875 call_port_stop_cbfn(port, BNA_CB_SUCCESS);
876}
877
878static void
879bna_port_sm_stopped(struct bna_port *port, enum bna_port_event event)
880{
881 switch (event) {
882 case PORT_E_START:
883 bfa_fsm_set_state(port, bna_port_sm_mtu_init_wait);
884 break;
885
886 case PORT_E_STOP:
887 call_port_stop_cbfn(port, BNA_CB_SUCCESS);
888 break;
889
890 case PORT_E_FAIL:
891 /* No-op */
892 break;
893
894 case PORT_E_PAUSE_CFG:
895 call_port_pause_cbfn(port, BNA_CB_SUCCESS);
896 break;
897
898 case PORT_E_MTU_CFG:
899 call_port_mtu_cbfn(port, BNA_CB_SUCCESS);
900 break;
901
902 case PORT_E_CHLD_STOPPED:
903 /**
904 * This event is received due to LLPort, Tx and Rx objects
905 * failing
906 */
907 /* No-op */
908 break;
909
910 case PORT_E_FWRESP_PAUSE:
911 case PORT_E_FWRESP_MTU:
912 /**
913 * These events are received due to flushing of mbox when
914 * device fails
915 */
916 /* No-op */
917 break;
918
919 default:
920 bfa_sm_fault(event);
921 }
922}
923
924static void
925bna_port_sm_mtu_init_wait_entry(struct bna_port *port)
926{
927 bna_fw_mtu_set(port);
928}
929
930static void
931bna_port_sm_mtu_init_wait(struct bna_port *port, enum bna_port_event event)
932{
933 switch (event) {
934 case PORT_E_STOP:
935 bfa_fsm_set_state(port, bna_port_sm_last_resp_wait);
936 break;
937
938 case PORT_E_FAIL:
939 bfa_fsm_set_state(port, bna_port_sm_stopped);
940 break;
941
942 case PORT_E_PAUSE_CFG:
943 /* No-op */
944 break;
945
946 case PORT_E_MTU_CFG:
947 port->flags |= BNA_PORT_F_MTU_CHANGED;
948 break;
949
950 case PORT_E_FWRESP_MTU:
951 if (port->flags & BNA_PORT_F_MTU_CHANGED) {
952 port->flags &= ~BNA_PORT_F_MTU_CHANGED;
953 bna_fw_mtu_set(port);
954 } else {
955 bfa_fsm_set_state(port, bna_port_sm_pause_init_wait);
956 }
957 break;
958
959 default:
960 bfa_sm_fault(event);
961 }
962}
963
964static void
965bna_port_sm_pause_init_wait_entry(struct bna_port *port)
966{
967 bna_fw_pause_set(port);
968}
969
970static void
971bna_port_sm_pause_init_wait(struct bna_port *port,
972 enum bna_port_event event)
973{
974 switch (event) {
975 case PORT_E_STOP:
976 bfa_fsm_set_state(port, bna_port_sm_last_resp_wait);
977 break;
978
979 case PORT_E_FAIL:
980 bfa_fsm_set_state(port, bna_port_sm_stopped);
981 break;
982
983 case PORT_E_PAUSE_CFG:
984 port->flags |= BNA_PORT_F_PAUSE_CHANGED;
985 break;
986
987 case PORT_E_MTU_CFG:
988 port->flags |= BNA_PORT_F_MTU_CHANGED;
989 break;
990
991 case PORT_E_FWRESP_PAUSE:
992 if (port->flags & BNA_PORT_F_PAUSE_CHANGED) {
993 port->flags &= ~BNA_PORT_F_PAUSE_CHANGED;
994 bna_fw_pause_set(port);
995 } else if (port->flags & BNA_PORT_F_MTU_CHANGED) {
996 port->flags &= ~BNA_PORT_F_MTU_CHANGED;
997 bfa_fsm_set_state(port, bna_port_sm_mtu_init_wait);
998 } else {
999 bfa_fsm_set_state(port, bna_port_sm_started);
1000 bna_port_chld_start(port);
1001 }
1002 break;
1003
1004 default:
1005 bfa_sm_fault(event);
1006 }
1007}
1008
1009static void
1010bna_port_sm_last_resp_wait_entry(struct bna_port *port)
1011{
1012}
1013
1014static void
1015bna_port_sm_last_resp_wait(struct bna_port *port,
1016 enum bna_port_event event)
1017{
1018 switch (event) {
1019 case PORT_E_FAIL:
1020 case PORT_E_FWRESP_PAUSE:
1021 case PORT_E_FWRESP_MTU:
1022 bfa_fsm_set_state(port, bna_port_sm_stopped);
1023 break;
1024
1025 default:
1026 bfa_sm_fault(event);
1027 }
1028}
1029
1030static void
1031bna_port_sm_started_entry(struct bna_port *port)
1032{
1033 /**
1034 * NOTE: Do not call bna_port_chld_start() here, since it will be
1035 * inadvertently called during pause_cfg_wait->started transition
1036 * as well
1037 */
1038 call_port_pause_cbfn(port, BNA_CB_SUCCESS);
1039 call_port_mtu_cbfn(port, BNA_CB_SUCCESS);
1040}
1041
1042static void
1043bna_port_sm_started(struct bna_port *port,
1044 enum bna_port_event event)
1045{
1046 switch (event) {
1047 case PORT_E_STOP:
1048 bfa_fsm_set_state(port, bna_port_sm_chld_stop_wait);
1049 break;
1050
1051 case PORT_E_FAIL:
1052 bfa_fsm_set_state(port, bna_port_sm_stopped);
1053 bna_port_chld_fail(port);
1054 break;
1055
1056 case PORT_E_PAUSE_CFG:
1057 bfa_fsm_set_state(port, bna_port_sm_pause_cfg_wait);
1058 break;
1059
1060 case PORT_E_MTU_CFG:
1061 bfa_fsm_set_state(port, bna_port_sm_rx_stop_wait);
1062 break;
1063
1064 default:
1065 bfa_sm_fault(event);
1066 }
1067}
1068
1069static void
1070bna_port_sm_pause_cfg_wait_entry(struct bna_port *port)
1071{
1072 bna_fw_pause_set(port);
1073}
1074
1075static void
1076bna_port_sm_pause_cfg_wait(struct bna_port *port,
1077 enum bna_port_event event)
1078{
1079 switch (event) {
1080 case PORT_E_FAIL:
1081 bfa_fsm_set_state(port, bna_port_sm_stopped);
1082 bna_port_chld_fail(port);
1083 break;
1084
1085 case PORT_E_FWRESP_PAUSE:
1086 bfa_fsm_set_state(port, bna_port_sm_started);
1087 break;
1088
1089 default:
1090 bfa_sm_fault(event);
1091 }
1092}
1093
1094static void
1095bna_port_sm_rx_stop_wait_entry(struct bna_port *port)
1096{
1097 bna_port_rx_stop(port);
1098}
1099
1100static void
1101bna_port_sm_rx_stop_wait(struct bna_port *port,
1102 enum bna_port_event event)
1103{
1104 switch (event) {
1105 case PORT_E_FAIL:
1106 bfa_fsm_set_state(port, bna_port_sm_stopped);
1107 bna_port_chld_fail(port);
1108 break;
1109
1110 case PORT_E_CHLD_STOPPED:
1111 bfa_fsm_set_state(port, bna_port_sm_mtu_cfg_wait);
1112 break;
1113
1114 default:
1115 bfa_sm_fault(event);
1116 }
1117}
1118
1119static void
1120bna_port_sm_mtu_cfg_wait_entry(struct bna_port *port)
1121{
1122 bna_fw_mtu_set(port);
1123}
1124
1125static void
1126bna_port_sm_mtu_cfg_wait(struct bna_port *port, enum bna_port_event event)
1127{
1128 switch (event) {
1129 case PORT_E_FAIL:
1130 bfa_fsm_set_state(port, bna_port_sm_stopped);
1131 bna_port_chld_fail(port);
1132 break;
1133
1134 case PORT_E_FWRESP_MTU:
1135 bfa_fsm_set_state(port, bna_port_sm_started);
1136 bna_port_rx_start(port);
1137 break;
1138
1139 default:
1140 bfa_sm_fault(event);
1141 }
1142}
1143
1144static void
1145bna_port_sm_chld_stop_wait_entry(struct bna_port *port)
1146{
1147 bna_port_chld_stop(port);
1148}
1149
1150static void
1151bna_port_sm_chld_stop_wait(struct bna_port *port,
1152 enum bna_port_event event)
1153{
1154 switch (event) {
1155 case PORT_E_FAIL:
1156 bfa_fsm_set_state(port, bna_port_sm_stopped);
1157 bna_port_chld_fail(port);
1158 break;
1159
1160 case PORT_E_CHLD_STOPPED:
1161 bfa_fsm_set_state(port, bna_port_sm_stopped);
1162 break;
1163
1164 default:
1165 bfa_sm_fault(event);
1166 }
1167}
1168
1169static void
1170bna_fw_pause_set(struct bna_port *port)
1171{
1172 struct bfi_ll_set_pause_req ll_req;
1173
1174 memset(&ll_req, 0, sizeof(ll_req));
1175 ll_req.mh.msg_class = BFI_MC_LL;
1176 ll_req.mh.msg_id = BFI_LL_H2I_SET_PAUSE_REQ;
1177 ll_req.mh.mtag.h2i.lpu_id = 0;
1178
1179 ll_req.tx_pause = port->pause_config.tx_pause;
1180 ll_req.rx_pause = port->pause_config.rx_pause;
1181
1182 bna_mbox_qe_fill(&port->mbox_qe, &ll_req, sizeof(ll_req),
1183 bna_fw_cb_pause_set, port);
1184
1185 bna_mbox_send(port->bna, &port->mbox_qe);
1186}
1187
1188static void
1189bna_fw_cb_pause_set(void *arg, int status)
1190{
1191 struct bna_port *port = (struct bna_port *)arg;
1192
1193 bfa_q_qe_init(&port->mbox_qe.qe);
1194 bfa_fsm_send_event(port, PORT_E_FWRESP_PAUSE);
1195}
1196
1197void
1198bna_fw_mtu_set(struct bna_port *port)
1199{
1200 struct bfi_ll_mtu_info_req ll_req;
1201
1202 bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_MTU_INFO_REQ, 0);
1203 ll_req.mtu = htons((u16)port->mtu);
1204
1205 bna_mbox_qe_fill(&port->mbox_qe, &ll_req, sizeof(ll_req),
1206 bna_fw_cb_mtu_set, port);
1207 bna_mbox_send(port->bna, &port->mbox_qe);
1208}
1209
1210void
1211bna_fw_cb_mtu_set(void *arg, int status)
1212{
1213 struct bna_port *port = (struct bna_port *)arg;
1214
1215 bfa_q_qe_init(&port->mbox_qe.qe);
1216 bfa_fsm_send_event(port, PORT_E_FWRESP_MTU);
1217}
1218
1219static void
1220bna_port_cb_chld_stopped(void *arg)
1221{
1222 struct bna_port *port = (struct bna_port *)arg;
1223
1224 bfa_fsm_send_event(port, PORT_E_CHLD_STOPPED);
1225}
1226
1227static void
1228bna_port_init(struct bna_port *port, struct bna *bna)
1229{
1230 port->bna = bna;
1231 port->flags = 0;
1232 port->mtu = 0;
1233 port->type = BNA_PORT_T_REGULAR;
1234
1235 port->link_cbfn = bnad_cb_port_link_status;
1236
1237 port->chld_stop_wc.wc_resume = bna_port_cb_chld_stopped;
1238 port->chld_stop_wc.wc_cbarg = port;
1239 port->chld_stop_wc.wc_count = 0;
1240
1241 port->stop_cbfn = NULL;
1242 port->stop_cbarg = NULL;
1243
1244 port->pause_cbfn = NULL;
1245
1246 port->mtu_cbfn = NULL;
1247
1248 bfa_q_qe_init(&port->mbox_qe.qe);
1249
1250 bfa_fsm_set_state(port, bna_port_sm_stopped);
1251
1252 bna_llport_init(&port->llport, bna);
1253}
1254
1255static void
1256bna_port_uninit(struct bna_port *port)
1257{
1258 bna_llport_uninit(&port->llport);
1259
1260 port->flags = 0;
1261
1262 port->bna = NULL;
1263}
1264
1265static int
1266bna_port_state_get(struct bna_port *port)
1267{
1268 return bfa_sm_to_state(port_sm_table, port->fsm);
1269}
1270
1271static void
1272bna_port_start(struct bna_port *port)
1273{
1274 port->flags |= BNA_PORT_F_DEVICE_READY;
1275 if (port->flags & BNA_PORT_F_ENABLED)
1276 bfa_fsm_send_event(port, PORT_E_START);
1277}
1278
1279static void
1280bna_port_stop(struct bna_port *port)
1281{
1282 port->stop_cbfn = bna_device_cb_port_stopped;
1283 port->stop_cbarg = &port->bna->device;
1284
1285 port->flags &= ~BNA_PORT_F_DEVICE_READY;
1286 bfa_fsm_send_event(port, PORT_E_STOP);
1287}
1288
1289static void
1290bna_port_fail(struct bna_port *port)
1291{
1292 port->flags &= ~BNA_PORT_F_DEVICE_READY;
1293 bfa_fsm_send_event(port, PORT_E_FAIL);
1294}
1295
1296void
1297bna_port_cb_tx_stopped(struct bna_port *port, enum bna_cb_status status)
1298{
1299 bfa_wc_down(&port->chld_stop_wc);
1300}
1301
1302void
1303bna_port_cb_rx_stopped(struct bna_port *port, enum bna_cb_status status)
1304{
1305 bfa_wc_down(&port->chld_stop_wc);
1306}
1307
1308int
1309bna_port_mtu_get(struct bna_port *port)
1310{
1311 return port->mtu;
1312}
1313
1314void
1315bna_port_enable(struct bna_port *port)
1316{
1317 if (port->fsm != (bfa_sm_t)bna_port_sm_stopped)
1318 return;
1319
1320 port->flags |= BNA_PORT_F_ENABLED;
1321
1322 if (port->flags & BNA_PORT_F_DEVICE_READY)
1323 bfa_fsm_send_event(port, PORT_E_START);
1324}
1325
1326void
1327bna_port_disable(struct bna_port *port, enum bna_cleanup_type type,
1328 void (*cbfn)(void *, enum bna_cb_status))
1329{
1330 if (type == BNA_SOFT_CLEANUP) {
1331 (*cbfn)(port->bna->bnad, BNA_CB_SUCCESS);
1332 return;
1333 }
1334
1335 port->stop_cbfn = cbfn;
1336 port->stop_cbarg = port->bna->bnad;
1337
1338 port->flags &= ~BNA_PORT_F_ENABLED;
1339
1340 bfa_fsm_send_event(port, PORT_E_STOP);
1341}
1342
1343void
1344bna_port_pause_config(struct bna_port *port,
1345 struct bna_pause_config *pause_config,
1346 void (*cbfn)(struct bnad *, enum bna_cb_status))
1347{
1348 port->pause_config = *pause_config;
1349
1350 port->pause_cbfn = cbfn;
1351
1352 bfa_fsm_send_event(port, PORT_E_PAUSE_CFG);
1353}
1354
1355void
1356bna_port_mtu_set(struct bna_port *port, int mtu,
1357 void (*cbfn)(struct bnad *, enum bna_cb_status))
1358{
1359 port->mtu = mtu;
1360
1361 port->mtu_cbfn = cbfn;
1362
1363 bfa_fsm_send_event(port, PORT_E_MTU_CFG);
1364}
1365
1366void
1367bna_port_mac_get(struct bna_port *port, mac_t *mac)
1368{
1369 *mac = bfa_nw_ioc_get_mac(&port->bna->device.ioc);
1370}
1371
1372/**
1373 * DEVICE
1374 */
1375#define enable_mbox_intr(_device)\
1376do {\
1377 u32 intr_status;\
1378 bna_intr_status_get((_device)->bna, intr_status);\
1379 bnad_cb_device_enable_mbox_intr((_device)->bna->bnad);\
1380 bna_mbox_intr_enable((_device)->bna);\
1381} while (0)
1382
1383#define disable_mbox_intr(_device)\
1384do {\
1385 bna_mbox_intr_disable((_device)->bna);\
1386 bnad_cb_device_disable_mbox_intr((_device)->bna->bnad);\
1387} while (0)
1388
1389static const struct bna_chip_regs_offset reg_offset[] =
1390{{HOST_PAGE_NUM_FN0, HOSTFN0_INT_STATUS,
1391 HOSTFN0_INT_MASK, HOST_MSIX_ERR_INDEX_FN0},
1392{HOST_PAGE_NUM_FN1, HOSTFN1_INT_STATUS,
1393 HOSTFN1_INT_MASK, HOST_MSIX_ERR_INDEX_FN1},
1394{HOST_PAGE_NUM_FN2, HOSTFN2_INT_STATUS,
1395 HOSTFN2_INT_MASK, HOST_MSIX_ERR_INDEX_FN2},
1396{HOST_PAGE_NUM_FN3, HOSTFN3_INT_STATUS,
1397 HOSTFN3_INT_MASK, HOST_MSIX_ERR_INDEX_FN3},
1398};
1399
1400enum bna_device_event {
1401 DEVICE_E_ENABLE = 1,
1402 DEVICE_E_DISABLE = 2,
1403 DEVICE_E_IOC_READY = 3,
1404 DEVICE_E_IOC_FAILED = 4,
1405 DEVICE_E_IOC_DISABLED = 5,
1406 DEVICE_E_IOC_RESET = 6,
1407 DEVICE_E_PORT_STOPPED = 7,
1408};
1409
1410enum bna_device_state {
1411 BNA_DEVICE_STOPPED = 1,
1412 BNA_DEVICE_IOC_READY_WAIT = 2,
1413 BNA_DEVICE_READY = 3,
1414 BNA_DEVICE_PORT_STOP_WAIT = 4,
1415 BNA_DEVICE_IOC_DISABLE_WAIT = 5,
1416 BNA_DEVICE_FAILED = 6
1417};
1418
1419bfa_fsm_state_decl(bna_device, stopped, struct bna_device,
1420 enum bna_device_event);
1421bfa_fsm_state_decl(bna_device, ioc_ready_wait, struct bna_device,
1422 enum bna_device_event);
1423bfa_fsm_state_decl(bna_device, ready, struct bna_device,
1424 enum bna_device_event);
1425bfa_fsm_state_decl(bna_device, port_stop_wait, struct bna_device,
1426 enum bna_device_event);
1427bfa_fsm_state_decl(bna_device, ioc_disable_wait, struct bna_device,
1428 enum bna_device_event);
1429bfa_fsm_state_decl(bna_device, failed, struct bna_device,
1430 enum bna_device_event);
1431
1432static struct bfa_sm_table device_sm_table[] = {
1433 {BFA_SM(bna_device_sm_stopped), BNA_DEVICE_STOPPED},
1434 {BFA_SM(bna_device_sm_ioc_ready_wait), BNA_DEVICE_IOC_READY_WAIT},
1435 {BFA_SM(bna_device_sm_ready), BNA_DEVICE_READY},
1436 {BFA_SM(bna_device_sm_port_stop_wait), BNA_DEVICE_PORT_STOP_WAIT},
1437 {BFA_SM(bna_device_sm_ioc_disable_wait), BNA_DEVICE_IOC_DISABLE_WAIT},
1438 {BFA_SM(bna_device_sm_failed), BNA_DEVICE_FAILED},
1439};
1440
1441static void
1442bna_device_sm_stopped_entry(struct bna_device *device)
1443{
1444 if (device->stop_cbfn)
1445 device->stop_cbfn(device->stop_cbarg, BNA_CB_SUCCESS);
1446
1447 device->stop_cbfn = NULL;
1448 device->stop_cbarg = NULL;
1449}
1450
1451static void
1452bna_device_sm_stopped(struct bna_device *device,
1453 enum bna_device_event event)
1454{
1455 switch (event) {
1456 case DEVICE_E_ENABLE:
1457 if (device->intr_type == BNA_INTR_T_MSIX)
1458 bna_mbox_msix_idx_set(device);
1459 bfa_nw_ioc_enable(&device->ioc);
1460 bfa_fsm_set_state(device, bna_device_sm_ioc_ready_wait);
1461 break;
1462
1463 case DEVICE_E_DISABLE:
1464 bfa_fsm_set_state(device, bna_device_sm_stopped);
1465 break;
1466
1467 case DEVICE_E_IOC_RESET:
1468 enable_mbox_intr(device);
1469 break;
1470
1471 case DEVICE_E_IOC_FAILED:
1472 bfa_fsm_set_state(device, bna_device_sm_failed);
1473 break;
1474
1475 default:
1476 bfa_sm_fault(event);
1477 }
1478}
1479
1480static void
1481bna_device_sm_ioc_ready_wait_entry(struct bna_device *device)
1482{
1483 /**
1484 * Do not call bfa_ioc_enable() here. It must be called in the
1485 * previous state due to failed -> ioc_ready_wait transition.
1486 */
1487}
1488
1489static void
1490bna_device_sm_ioc_ready_wait(struct bna_device *device,
1491 enum bna_device_event event)
1492{
1493 switch (event) {
1494 case DEVICE_E_DISABLE:
1495 if (device->ready_cbfn)
1496 device->ready_cbfn(device->ready_cbarg,
1497 BNA_CB_INTERRUPT);
1498 device->ready_cbfn = NULL;
1499 device->ready_cbarg = NULL;
1500 bfa_fsm_set_state(device, bna_device_sm_ioc_disable_wait);
1501 break;
1502
1503 case DEVICE_E_IOC_READY:
1504 bfa_fsm_set_state(device, bna_device_sm_ready);
1505 break;
1506
1507 case DEVICE_E_IOC_FAILED:
1508 bfa_fsm_set_state(device, bna_device_sm_failed);
1509 break;
1510
1511 case DEVICE_E_IOC_RESET:
1512 enable_mbox_intr(device);
1513 break;
1514
1515 default:
1516 bfa_sm_fault(event);
1517 }
1518}
1519
1520static void
1521bna_device_sm_ready_entry(struct bna_device *device)
1522{
1523 bna_mbox_mod_start(&device->bna->mbox_mod);
1524 bna_port_start(&device->bna->port);
1525
1526 if (device->ready_cbfn)
1527 device->ready_cbfn(device->ready_cbarg,
1528 BNA_CB_SUCCESS);
1529 device->ready_cbfn = NULL;
1530 device->ready_cbarg = NULL;
1531}
1532
1533static void
1534bna_device_sm_ready(struct bna_device *device, enum bna_device_event event)
1535{
1536 switch (event) {
1537 case DEVICE_E_DISABLE:
1538 bfa_fsm_set_state(device, bna_device_sm_port_stop_wait);
1539 break;
1540
1541 case DEVICE_E_IOC_FAILED:
1542 bfa_fsm_set_state(device, bna_device_sm_failed);
1543 break;
1544
1545 default:
1546 bfa_sm_fault(event);
1547 }
1548}
1549
1550static void
1551bna_device_sm_port_stop_wait_entry(struct bna_device *device)
1552{
1553 bna_port_stop(&device->bna->port);
1554}
1555
1556static void
1557bna_device_sm_port_stop_wait(struct bna_device *device,
1558 enum bna_device_event event)
1559{
1560 switch (event) {
1561 case DEVICE_E_PORT_STOPPED:
1562 bna_mbox_mod_stop(&device->bna->mbox_mod);
1563 bfa_fsm_set_state(device, bna_device_sm_ioc_disable_wait);
1564 break;
1565
1566 case DEVICE_E_IOC_FAILED:
1567 disable_mbox_intr(device);
1568 bna_port_fail(&device->bna->port);
1569 break;
1570
1571 default:
1572 bfa_sm_fault(event);
1573 }
1574}
1575
1576static void
1577bna_device_sm_ioc_disable_wait_entry(struct bna_device *device)
1578{
1579 bfa_nw_ioc_disable(&device->ioc);
1580}
1581
1582static void
1583bna_device_sm_ioc_disable_wait(struct bna_device *device,
1584 enum bna_device_event event)
1585{
1586 switch (event) {
1587 case DEVICE_E_IOC_DISABLED:
1588 disable_mbox_intr(device);
1589 bfa_fsm_set_state(device, bna_device_sm_stopped);
1590 break;
1591
1592 default:
1593 bfa_sm_fault(event);
1594 }
1595}
1596
1597static void
1598bna_device_sm_failed_entry(struct bna_device *device)
1599{
1600 disable_mbox_intr(device);
1601 bna_port_fail(&device->bna->port);
1602 bna_mbox_mod_stop(&device->bna->mbox_mod);
1603
1604 if (device->ready_cbfn)
1605 device->ready_cbfn(device->ready_cbarg,
1606 BNA_CB_FAIL);
1607 device->ready_cbfn = NULL;
1608 device->ready_cbarg = NULL;
1609}
1610
1611static void
1612bna_device_sm_failed(struct bna_device *device,
1613 enum bna_device_event event)
1614{
1615 switch (event) {
1616 case DEVICE_E_DISABLE:
1617 bfa_fsm_set_state(device, bna_device_sm_ioc_disable_wait);
1618 break;
1619
1620 case DEVICE_E_IOC_RESET:
1621 enable_mbox_intr(device);
1622 bfa_fsm_set_state(device, bna_device_sm_ioc_ready_wait);
1623 break;
1624
1625 default:
1626 bfa_sm_fault(event);
1627 }
1628}
1629
1630/* IOC callback functions */
1631
1632static void
1633bna_device_cb_iocll_ready(void *dev, enum bfa_status error)
1634{
1635 struct bna_device *device = (struct bna_device *)dev;
1636
1637 if (error)
1638 bfa_fsm_send_event(device, DEVICE_E_IOC_FAILED);
1639 else
1640 bfa_fsm_send_event(device, DEVICE_E_IOC_READY);
1641}
1642
1643static void
1644bna_device_cb_iocll_disabled(void *dev)
1645{
1646 struct bna_device *device = (struct bna_device *)dev;
1647
1648 bfa_fsm_send_event(device, DEVICE_E_IOC_DISABLED);
1649}
1650
1651static void
1652bna_device_cb_iocll_failed(void *dev)
1653{
1654 struct bna_device *device = (struct bna_device *)dev;
1655
1656 bfa_fsm_send_event(device, DEVICE_E_IOC_FAILED);
1657}
1658
1659static void
1660bna_device_cb_iocll_reset(void *dev)
1661{
1662 struct bna_device *device = (struct bna_device *)dev;
1663
1664 bfa_fsm_send_event(device, DEVICE_E_IOC_RESET);
1665}
1666
1667static struct bfa_ioc_cbfn bfa_iocll_cbfn = {
1668 bna_device_cb_iocll_ready,
1669 bna_device_cb_iocll_disabled,
1670 bna_device_cb_iocll_failed,
1671 bna_device_cb_iocll_reset
1672};
1673
1674/* device */
1675static void
1676bna_adv_device_init(struct bna_device *device, struct bna *bna,
1677 struct bna_res_info *res_info)
1678{
1679 u8 *kva;
1680 u64 dma;
1681
1682 device->bna = bna;
1683
1684 kva = res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.mdl[0].kva;
1685
1686 /**
1687 * Attach common modules (Diag, SFP, CEE, Port) and claim respective
1688 * DMA memory.
1689 */
1690 BNA_GET_DMA_ADDR(
1691 &res_info[BNA_RES_MEM_T_COM].res_u.mem_info.mdl[0].dma, dma);
1692 kva = res_info[BNA_RES_MEM_T_COM].res_u.mem_info.mdl[0].kva;
1693
1694 bfa_nw_cee_attach(&bna->cee, &device->ioc, bna);
1695 bfa_nw_cee_mem_claim(&bna->cee, kva, dma);
1696 kva += bfa_nw_cee_meminfo();
1697 dma += bfa_nw_cee_meminfo();
1698
1699}
1700
1701static void
1702bna_device_init(struct bna_device *device, struct bna *bna,
1703 struct bna_res_info *res_info)
1704{
1705 u64 dma;
1706
1707 device->bna = bna;
1708
1709 /**
1710 * Attach IOC and claim:
1711 * 1. DMA memory for IOC attributes
1712 * 2. Kernel memory for FW trace
1713 */
1714 bfa_nw_ioc_attach(&device->ioc, device, &bfa_iocll_cbfn);
1715 bfa_nw_ioc_pci_init(&device->ioc, &bna->pcidev, BFI_MC_LL);
1716
1717 BNA_GET_DMA_ADDR(
1718 &res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.mdl[0].dma, dma);
1719 bfa_nw_ioc_mem_claim(&device->ioc,
1720 res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.mdl[0].kva,
1721 dma);
1722
1723 bna_adv_device_init(device, bna, res_info);
1724 /*
1725 * Initialize mbox_mod only after IOC, so that mbox handler
1726 * registration goes through
1727 */
1728 device->intr_type =
1729 res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.intr_type;
1730 device->vector =
1731 res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.idl[0].vector;
1732 bna_mbox_mod_init(&bna->mbox_mod, bna);
1733
1734 device->ready_cbfn = device->stop_cbfn = NULL;
1735 device->ready_cbarg = device->stop_cbarg = NULL;
1736
1737 bfa_fsm_set_state(device, bna_device_sm_stopped);
1738}
1739
1740static void
1741bna_device_uninit(struct bna_device *device)
1742{
1743 bna_mbox_mod_uninit(&device->bna->mbox_mod);
1744
1745 bfa_nw_ioc_detach(&device->ioc);
1746
1747 device->bna = NULL;
1748}
1749
1750static void
1751bna_device_cb_port_stopped(void *arg, enum bna_cb_status status)
1752{
1753 struct bna_device *device = (struct bna_device *)arg;
1754
1755 bfa_fsm_send_event(device, DEVICE_E_PORT_STOPPED);
1756}
1757
1758static int
1759bna_device_status_get(struct bna_device *device)
1760{
1761 return device->fsm == (bfa_fsm_t)bna_device_sm_ready;
1762}
1763
1764void
1765bna_device_enable(struct bna_device *device)
1766{
1767 if (device->fsm != (bfa_fsm_t)bna_device_sm_stopped) {
1768 bnad_cb_device_enabled(device->bna->bnad, BNA_CB_BUSY);
1769 return;
1770 }
1771
1772 device->ready_cbfn = bnad_cb_device_enabled;
1773 device->ready_cbarg = device->bna->bnad;
1774
1775 bfa_fsm_send_event(device, DEVICE_E_ENABLE);
1776}
1777
1778void
1779bna_device_disable(struct bna_device *device, enum bna_cleanup_type type)
1780{
1781 if (type == BNA_SOFT_CLEANUP) {
1782 bnad_cb_device_disabled(device->bna->bnad, BNA_CB_SUCCESS);
1783 return;
1784 }
1785
1786 device->stop_cbfn = bnad_cb_device_disabled;
1787 device->stop_cbarg = device->bna->bnad;
1788
1789 bfa_fsm_send_event(device, DEVICE_E_DISABLE);
1790}
1791
1792static int
1793bna_device_state_get(struct bna_device *device)
1794{
1795 return bfa_sm_to_state(device_sm_table, device->fsm);
1796}
1797
1798const u32 bna_napi_dim_vector[BNA_LOAD_T_MAX][BNA_BIAS_T_MAX] = {
1799 {12, 12},
1800 {6, 10},
1801 {5, 10},
1802 {4, 8},
1803 {3, 6},
1804 {3, 6},
1805 {2, 4},
1806 {1, 2},
1807};
1808
1809/* utils */
1810
1811static void
1812bna_adv_res_req(struct bna_res_info *res_info)
1813{
1814 /* DMA memory for COMMON_MODULE */
1815 res_info[BNA_RES_MEM_T_COM].res_type = BNA_RES_T_MEM;
1816 res_info[BNA_RES_MEM_T_COM].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
1817 res_info[BNA_RES_MEM_T_COM].res_u.mem_info.num = 1;
1818 res_info[BNA_RES_MEM_T_COM].res_u.mem_info.len = ALIGN(
1819 bfa_nw_cee_meminfo(), PAGE_SIZE);
1820
1821 /* Virtual memory for retreiving fw_trc */
1822 res_info[BNA_RES_MEM_T_FWTRC].res_type = BNA_RES_T_MEM;
1823 res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.mem_type = BNA_MEM_T_KVA;
1824 res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.num = 0;
1825 res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.len = 0;
1826
1827 /* DMA memory for retreiving stats */
1828 res_info[BNA_RES_MEM_T_STATS].res_type = BNA_RES_T_MEM;
1829 res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
1830 res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.num = 1;
1831 res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.len =
1832 ALIGN(BFI_HW_STATS_SIZE, PAGE_SIZE);
1833
1834 /* Virtual memory for soft stats */
1835 res_info[BNA_RES_MEM_T_SWSTATS].res_type = BNA_RES_T_MEM;
1836 res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.mem_type = BNA_MEM_T_KVA;
1837 res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.num = 1;
1838 res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.len =
1839 sizeof(struct bna_sw_stats);
1840}
1841
1842static void
1843bna_sw_stats_get(struct bna *bna, struct bna_sw_stats *sw_stats)
1844{
1845 struct bna_tx *tx;
1846 struct bna_txq *txq;
1847 struct bna_rx *rx;
1848 struct bna_rxp *rxp;
1849 struct list_head *qe;
1850 struct list_head *txq_qe;
1851 struct list_head *rxp_qe;
1852 struct list_head *mac_qe;
1853 int i;
1854
1855 sw_stats->device_state = bna_device_state_get(&bna->device);
1856 sw_stats->port_state = bna_port_state_get(&bna->port);
1857 sw_stats->port_flags = bna->port.flags;
1858 sw_stats->llport_state = bna_llport_state_get(&bna->port.llport);
1859 sw_stats->priority = bna->port.priority;
1860
1861 i = 0;
1862 list_for_each(qe, &bna->tx_mod.tx_active_q) {
1863 tx = (struct bna_tx *)qe;
1864 sw_stats->tx_stats[i].tx_state = bna_tx_state_get(tx);
1865 sw_stats->tx_stats[i].tx_flags = tx->flags;
1866
1867 sw_stats->tx_stats[i].num_txqs = 0;
1868 sw_stats->tx_stats[i].txq_bmap[0] = 0;
1869 sw_stats->tx_stats[i].txq_bmap[1] = 0;
1870 list_for_each(txq_qe, &tx->txq_q) {
1871 txq = (struct bna_txq *)txq_qe;
1872 if (txq->txq_id < 32)
1873 sw_stats->tx_stats[i].txq_bmap[0] |=
1874 ((u32)1 << txq->txq_id);
1875 else
1876 sw_stats->tx_stats[i].txq_bmap[1] |=
1877 ((u32)
1878 1 << (txq->txq_id - 32));
1879 sw_stats->tx_stats[i].num_txqs++;
1880 }
1881
1882 sw_stats->tx_stats[i].txf_id = tx->txf.txf_id;
1883
1884 i++;
1885 }
1886 sw_stats->num_active_tx = i;
1887
1888 i = 0;
1889 list_for_each(qe, &bna->rx_mod.rx_active_q) {
1890 rx = (struct bna_rx *)qe;
1891 sw_stats->rx_stats[i].rx_state = bna_rx_state_get(rx);
1892 sw_stats->rx_stats[i].rx_flags = rx->rx_flags;
1893
1894 sw_stats->rx_stats[i].num_rxps = 0;
1895 sw_stats->rx_stats[i].num_rxqs = 0;
1896 sw_stats->rx_stats[i].rxq_bmap[0] = 0;
1897 sw_stats->rx_stats[i].rxq_bmap[1] = 0;
1898 sw_stats->rx_stats[i].cq_bmap[0] = 0;
1899 sw_stats->rx_stats[i].cq_bmap[1] = 0;
1900 list_for_each(rxp_qe, &rx->rxp_q) {
1901 rxp = (struct bna_rxp *)rxp_qe;
1902
1903 sw_stats->rx_stats[i].num_rxqs += 1;
1904
1905 if (rxp->type == BNA_RXP_SINGLE) {
1906 if (rxp->rxq.single.only->rxq_id < 32) {
1907 sw_stats->rx_stats[i].rxq_bmap[0] |=
1908 ((u32)1 <<
1909 rxp->rxq.single.only->rxq_id);
1910 } else {
1911 sw_stats->rx_stats[i].rxq_bmap[1] |=
1912 ((u32)1 <<
1913 (rxp->rxq.single.only->rxq_id - 32));
1914 }
1915 } else {
1916 if (rxp->rxq.slr.large->rxq_id < 32) {
1917 sw_stats->rx_stats[i].rxq_bmap[0] |=
1918 ((u32)1 <<
1919 rxp->rxq.slr.large->rxq_id);
1920 } else {
1921 sw_stats->rx_stats[i].rxq_bmap[1] |=
1922 ((u32)1 <<
1923 (rxp->rxq.slr.large->rxq_id - 32));
1924 }
1925
1926 if (rxp->rxq.slr.small->rxq_id < 32) {
1927 sw_stats->rx_stats[i].rxq_bmap[0] |=
1928 ((u32)1 <<
1929 rxp->rxq.slr.small->rxq_id);
1930 } else {
1931 sw_stats->rx_stats[i].rxq_bmap[1] |=
1932 ((u32)1 <<
1933 (rxp->rxq.slr.small->rxq_id - 32));
1934 }
1935 sw_stats->rx_stats[i].num_rxqs += 1;
1936 }
1937
1938 if (rxp->cq.cq_id < 32)
1939 sw_stats->rx_stats[i].cq_bmap[0] |=
1940 (1 << rxp->cq.cq_id);
1941 else
1942 sw_stats->rx_stats[i].cq_bmap[1] |=
1943 (1 << (rxp->cq.cq_id - 32));
1944
1945 sw_stats->rx_stats[i].num_rxps++;
1946 }
1947
1948 sw_stats->rx_stats[i].rxf_id = rx->rxf.rxf_id;
1949 sw_stats->rx_stats[i].rxf_state = bna_rxf_state_get(&rx->rxf);
1950 sw_stats->rx_stats[i].rxf_oper_state = rx->rxf.rxf_oper_state;
1951
1952 sw_stats->rx_stats[i].num_active_ucast = 0;
1953 if (rx->rxf.ucast_active_mac)
1954 sw_stats->rx_stats[i].num_active_ucast++;
1955 list_for_each(mac_qe, &rx->rxf.ucast_active_q)
1956 sw_stats->rx_stats[i].num_active_ucast++;
1957
1958 sw_stats->rx_stats[i].num_active_mcast = 0;
1959 list_for_each(mac_qe, &rx->rxf.mcast_active_q)
1960 sw_stats->rx_stats[i].num_active_mcast++;
1961
1962 sw_stats->rx_stats[i].rxmode_active = rx->rxf.rxmode_active;
1963 sw_stats->rx_stats[i].vlan_filter_status =
1964 rx->rxf.vlan_filter_status;
1965 memcpy(sw_stats->rx_stats[i].vlan_filter_table,
1966 rx->rxf.vlan_filter_table,
1967 sizeof(u32) * ((BFI_MAX_VLAN + 1) / 32));
1968
1969 sw_stats->rx_stats[i].rss_status = rx->rxf.rss_status;
1970 sw_stats->rx_stats[i].hds_status = rx->rxf.hds_status;
1971
1972 i++;
1973 }
1974 sw_stats->num_active_rx = i;
1975}
1976
1977static void
1978bna_fw_cb_stats_get(void *arg, int status)
1979{
1980 struct bna *bna = (struct bna *)arg;
1981 u64 *p_stats;
1982 int i, count;
1983 int rxf_count, txf_count;
1984 u64 rxf_bmap, txf_bmap;
1985
1986 bfa_q_qe_init(&bna->mbox_qe.qe);
1987
1988 if (status == 0) {
1989 p_stats = (u64 *)bna->stats.hw_stats;
1990 count = sizeof(struct bfi_ll_stats) / sizeof(u64);
1991 for (i = 0; i < count; i++)
1992 p_stats[i] = cpu_to_be64(p_stats[i]);
1993
1994 rxf_count = 0;
1995 rxf_bmap = (u64)bna->stats.rxf_bmap[0] |
1996 ((u64)bna->stats.rxf_bmap[1] << 32);
1997 for (i = 0; i < BFI_LL_RXF_ID_MAX; i++)
1998 if (rxf_bmap & ((u64)1 << i))
1999 rxf_count++;
2000
2001 txf_count = 0;
2002 txf_bmap = (u64)bna->stats.txf_bmap[0] |
2003 ((u64)bna->stats.txf_bmap[1] << 32);
2004 for (i = 0; i < BFI_LL_TXF_ID_MAX; i++)
2005 if (txf_bmap & ((u64)1 << i))
2006 txf_count++;
2007
2008 p_stats = (u64 *)&bna->stats.hw_stats->rxf_stats[0] +
2009 ((rxf_count * sizeof(struct bfi_ll_stats_rxf) +
2010 txf_count * sizeof(struct bfi_ll_stats_txf))/
2011 sizeof(u64));
2012
2013 /* Populate the TXF stats from the firmware DMAed copy */
2014 for (i = (BFI_LL_TXF_ID_MAX - 1); i >= 0; i--)
2015 if (txf_bmap & ((u64)1 << i)) {
2016 p_stats -= sizeof(struct bfi_ll_stats_txf)/
2017 sizeof(u64);
2018 memcpy(&bna->stats.hw_stats->txf_stats[i],
2019 p_stats,
2020 sizeof(struct bfi_ll_stats_txf));
2021 }
2022
2023 /* Populate the RXF stats from the firmware DMAed copy */
2024 for (i = (BFI_LL_RXF_ID_MAX - 1); i >= 0; i--)
2025 if (rxf_bmap & ((u64)1 << i)) {
2026 p_stats -= sizeof(struct bfi_ll_stats_rxf)/
2027 sizeof(u64);
2028 memcpy(&bna->stats.hw_stats->rxf_stats[i],
2029 p_stats,
2030 sizeof(struct bfi_ll_stats_rxf));
2031 }
2032
2033 bna_sw_stats_get(bna, bna->stats.sw_stats);
2034 bnad_cb_stats_get(bna->bnad, BNA_CB_SUCCESS, &bna->stats);
2035 } else
2036 bnad_cb_stats_get(bna->bnad, BNA_CB_FAIL, &bna->stats);
2037}
2038
2039static void
2040bna_fw_stats_get(struct bna *bna)
2041{
2042 struct bfi_ll_stats_req ll_req;
2043
2044 bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_STATS_GET_REQ, 0);
2045 ll_req.stats_mask = htons(BFI_LL_STATS_ALL);
2046
2047 ll_req.rxf_id_mask[0] = htonl(bna->rx_mod.rxf_bmap[0]);
2048 ll_req.rxf_id_mask[1] = htonl(bna->rx_mod.rxf_bmap[1]);
2049 ll_req.txf_id_mask[0] = htonl(bna->tx_mod.txf_bmap[0]);
2050 ll_req.txf_id_mask[1] = htonl(bna->tx_mod.txf_bmap[1]);
2051
2052 ll_req.host_buffer.a32.addr_hi = bna->hw_stats_dma.msb;
2053 ll_req.host_buffer.a32.addr_lo = bna->hw_stats_dma.lsb;
2054
2055 bna_mbox_qe_fill(&bna->mbox_qe, &ll_req, sizeof(ll_req),
2056 bna_fw_cb_stats_get, bna);
2057 bna_mbox_send(bna, &bna->mbox_qe);
2058
2059 bna->stats.rxf_bmap[0] = bna->rx_mod.rxf_bmap[0];
2060 bna->stats.rxf_bmap[1] = bna->rx_mod.rxf_bmap[1];
2061 bna->stats.txf_bmap[0] = bna->tx_mod.txf_bmap[0];
2062 bna->stats.txf_bmap[1] = bna->tx_mod.txf_bmap[1];
2063}
2064
2065void
2066bna_stats_get(struct bna *bna)
2067{
2068 if (bna_device_status_get(&bna->device))
2069 bna_fw_stats_get(bna);
2070 else
2071 bnad_cb_stats_get(bna->bnad, BNA_CB_FAIL, &bna->stats);
2072}
2073
2074/* IB */
2075static void
2076bna_ib_coalescing_timeo_set(struct bna_ib *ib, u8 coalescing_timeo)
2077{
2078 ib->ib_config.coalescing_timeo = coalescing_timeo;
2079
2080 if (ib->start_count)
2081 ib->door_bell.doorbell_ack = BNA_DOORBELL_IB_INT_ACK(
2082 (u32)ib->ib_config.coalescing_timeo, 0);
2083}
2084
2085/* RxF */
2086void
2087bna_rxf_adv_init(struct bna_rxf *rxf,
2088 struct bna_rx *rx,
2089 struct bna_rx_config *q_config)
2090{
2091 switch (q_config->rxp_type) {
2092 case BNA_RXP_SINGLE:
2093 /* No-op */
2094 break;
2095 case BNA_RXP_SLR:
2096 rxf->ctrl_flags |= BNA_RXF_CF_SM_LG_RXQ;
2097 break;
2098 case BNA_RXP_HDS:
2099 rxf->hds_cfg.hdr_type = q_config->hds_config.hdr_type;
2100 rxf->hds_cfg.header_size =
2101 q_config->hds_config.header_size;
2102 rxf->forced_offset = 0;
2103 break;
2104 default:
2105 break;
2106 }
2107
2108 if (q_config->rss_status == BNA_STATUS_T_ENABLED) {
2109 rxf->ctrl_flags |= BNA_RXF_CF_RSS_ENABLE;
2110 rxf->rss_cfg.hash_type = q_config->rss_config.hash_type;
2111 rxf->rss_cfg.hash_mask = q_config->rss_config.hash_mask;
2112 memcpy(&rxf->rss_cfg.toeplitz_hash_key[0],
2113 &q_config->rss_config.toeplitz_hash_key[0],
2114 sizeof(rxf->rss_cfg.toeplitz_hash_key));
2115 }
2116}
2117
2118static void
2119rxf_fltr_mbox_cmd(struct bna_rxf *rxf, u8 cmd, enum bna_status status)
2120{
2121 struct bfi_ll_rxf_req req;
2122
2123 bfi_h2i_set(req.mh, BFI_MC_LL, cmd, 0);
2124
2125 req.rxf_id = rxf->rxf_id;
2126 req.enable = status;
2127
2128 bna_mbox_qe_fill(&rxf->mbox_qe, &req, sizeof(req),
2129 rxf_cb_cam_fltr_mbox_cmd, rxf);
2130
2131 bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe);
2132}
2133
2134int
2135rxf_process_packet_filter_ucast(struct bna_rxf *rxf)
2136{
2137 struct bna_mac *mac = NULL;
2138 struct list_head *qe;
2139
2140 /* Add additional MAC entries */
2141 if (!list_empty(&rxf->ucast_pending_add_q)) {
2142 bfa_q_deq(&rxf->ucast_pending_add_q, &qe);
2143 bfa_q_qe_init(qe);
2144 mac = (struct bna_mac *)qe;
2145 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_ADD_REQ, mac);
2146 list_add_tail(&mac->qe, &rxf->ucast_active_q);
2147 return 1;
2148 }
2149
2150 /* Delete MAC addresses previousely added */
2151 if (!list_empty(&rxf->ucast_pending_del_q)) {
2152 bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
2153 bfa_q_qe_init(qe);
2154 mac = (struct bna_mac *)qe;
2155 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_DEL_REQ, mac);
2156 bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
2157 return 1;
2158 }
2159
2160 return 0;
2161}
2162
2163int
2164rxf_process_packet_filter_promisc(struct bna_rxf *rxf)
2165{
2166 struct bna *bna = rxf->rx->bna;
2167
2168 /* Enable/disable promiscuous mode */
2169 if (is_promisc_enable(rxf->rxmode_pending,
2170 rxf->rxmode_pending_bitmask)) {
2171 /* move promisc configuration from pending -> active */
2172 promisc_inactive(rxf->rxmode_pending,
2173 rxf->rxmode_pending_bitmask);
2174 rxf->rxmode_active |= BNA_RXMODE_PROMISC;
2175
2176 /* Disable VLAN filter to allow all VLANs */
2177 __rxf_vlan_filter_set(rxf, BNA_STATUS_T_DISABLED);
2178 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
2179 BNA_STATUS_T_ENABLED);
2180 return 1;
2181 } else if (is_promisc_disable(rxf->rxmode_pending,
2182 rxf->rxmode_pending_bitmask)) {
2183 /* move promisc configuration from pending -> active */
2184 promisc_inactive(rxf->rxmode_pending,
2185 rxf->rxmode_pending_bitmask);
2186 rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
2187 bna->rxf_promisc_id = BFI_MAX_RXF;
2188
2189 /* Revert VLAN filter */
2190 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
2191 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
2192 BNA_STATUS_T_DISABLED);
2193 return 1;
2194 }
2195
2196 return 0;
2197}
2198
2199int
2200rxf_process_packet_filter_allmulti(struct bna_rxf *rxf)
2201{
2202 /* Enable/disable allmulti mode */
2203 if (is_allmulti_enable(rxf->rxmode_pending,
2204 rxf->rxmode_pending_bitmask)) {
2205 /* move allmulti configuration from pending -> active */
2206 allmulti_inactive(rxf->rxmode_pending,
2207 rxf->rxmode_pending_bitmask);
2208 rxf->rxmode_active |= BNA_RXMODE_ALLMULTI;
2209
2210 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
2211 BNA_STATUS_T_ENABLED);
2212 return 1;
2213 } else if (is_allmulti_disable(rxf->rxmode_pending,
2214 rxf->rxmode_pending_bitmask)) {
2215 /* move allmulti configuration from pending -> active */
2216 allmulti_inactive(rxf->rxmode_pending,
2217 rxf->rxmode_pending_bitmask);
2218 rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
2219
2220 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
2221 BNA_STATUS_T_DISABLED);
2222 return 1;
2223 }
2224
2225 return 0;
2226}
2227
2228int
2229rxf_clear_packet_filter_ucast(struct bna_rxf *rxf)
2230{
2231 struct bna_mac *mac = NULL;
2232 struct list_head *qe;
2233
2234 /* 1. delete pending ucast entries */
2235 if (!list_empty(&rxf->ucast_pending_del_q)) {
2236 bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
2237 bfa_q_qe_init(qe);
2238 mac = (struct bna_mac *)qe;
2239 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_DEL_REQ, mac);
2240 bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
2241 return 1;
2242 }
2243
2244 /* 2. clear active ucast entries; move them to pending_add_q */
2245 if (!list_empty(&rxf->ucast_active_q)) {
2246 bfa_q_deq(&rxf->ucast_active_q, &qe);
2247 bfa_q_qe_init(qe);
2248 mac = (struct bna_mac *)qe;
2249 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_DEL_REQ, mac);
2250 list_add_tail(&mac->qe, &rxf->ucast_pending_add_q);
2251 return 1;
2252 }
2253
2254 return 0;
2255}
2256
2257int
2258rxf_clear_packet_filter_promisc(struct bna_rxf *rxf)
2259{
2260 struct bna *bna = rxf->rx->bna;
2261
2262 /* 6. Execute pending promisc mode disable command */
2263 if (is_promisc_disable(rxf->rxmode_pending,
2264 rxf->rxmode_pending_bitmask)) {
2265 /* move promisc configuration from pending -> active */
2266 promisc_inactive(rxf->rxmode_pending,
2267 rxf->rxmode_pending_bitmask);
2268 rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
2269 bna->rxf_promisc_id = BFI_MAX_RXF;
2270
2271 /* Revert VLAN filter */
2272 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
2273 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
2274 BNA_STATUS_T_DISABLED);
2275 return 1;
2276 }
2277
2278 /* 7. Clear active promisc mode; move it to pending enable */
2279 if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
2280 /* move promisc configuration from active -> pending */
2281 promisc_enable(rxf->rxmode_pending,
2282 rxf->rxmode_pending_bitmask);
2283 rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
2284
2285 /* Revert VLAN filter */
2286 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
2287 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
2288 BNA_STATUS_T_DISABLED);
2289 return 1;
2290 }
2291
2292 return 0;
2293}
2294
2295int
2296rxf_clear_packet_filter_allmulti(struct bna_rxf *rxf)
2297{
2298 /* 10. Execute pending allmulti mode disable command */
2299 if (is_allmulti_disable(rxf->rxmode_pending,
2300 rxf->rxmode_pending_bitmask)) {
2301 /* move allmulti configuration from pending -> active */
2302 allmulti_inactive(rxf->rxmode_pending,
2303 rxf->rxmode_pending_bitmask);
2304 rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
2305 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
2306 BNA_STATUS_T_DISABLED);
2307 return 1;
2308 }
2309
2310 /* 11. Clear active allmulti mode; move it to pending enable */
2311 if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
2312 /* move allmulti configuration from active -> pending */
2313 allmulti_enable(rxf->rxmode_pending,
2314 rxf->rxmode_pending_bitmask);
2315 rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
2316 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
2317 BNA_STATUS_T_DISABLED);
2318 return 1;
2319 }
2320
2321 return 0;
2322}
2323
2324void
2325rxf_reset_packet_filter_ucast(struct bna_rxf *rxf)
2326{
2327 struct list_head *qe;
2328 struct bna_mac *mac;
2329
2330 /* 1. Move active ucast entries to pending_add_q */
2331 while (!list_empty(&rxf->ucast_active_q)) {
2332 bfa_q_deq(&rxf->ucast_active_q, &qe);
2333 bfa_q_qe_init(qe);
2334 list_add_tail(qe, &rxf->ucast_pending_add_q);
2335 }
2336
2337 /* 2. Throw away delete pending ucast entries */
2338 while (!list_empty(&rxf->ucast_pending_del_q)) {
2339 bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
2340 bfa_q_qe_init(qe);
2341 mac = (struct bna_mac *)qe;
2342 bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
2343 }
2344}
2345
2346void
2347rxf_reset_packet_filter_promisc(struct bna_rxf *rxf)
2348{
2349 struct bna *bna = rxf->rx->bna;
2350
2351 /* 6. Clear pending promisc mode disable */
2352 if (is_promisc_disable(rxf->rxmode_pending,
2353 rxf->rxmode_pending_bitmask)) {
2354 promisc_inactive(rxf->rxmode_pending,
2355 rxf->rxmode_pending_bitmask);
2356 rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
2357 bna->rxf_promisc_id = BFI_MAX_RXF;
2358 }
2359
2360 /* 7. Move promisc mode config from active -> pending */
2361 if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
2362 promisc_enable(rxf->rxmode_pending,
2363 rxf->rxmode_pending_bitmask);
2364 rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
2365 }
2366
2367}
2368
2369void
2370rxf_reset_packet_filter_allmulti(struct bna_rxf *rxf)
2371{
2372 /* 10. Clear pending allmulti mode disable */
2373 if (is_allmulti_disable(rxf->rxmode_pending,
2374 rxf->rxmode_pending_bitmask)) {
2375 allmulti_inactive(rxf->rxmode_pending,
2376 rxf->rxmode_pending_bitmask);
2377 rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
2378 }
2379
2380 /* 11. Move allmulti mode config from active -> pending */
2381 if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
2382 allmulti_enable(rxf->rxmode_pending,
2383 rxf->rxmode_pending_bitmask);
2384 rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
2385 }
2386}
2387
2388/**
2389 * Should only be called by bna_rxf_mode_set.
2390 * Helps deciding if h/w configuration is needed or not.
2391 * Returns:
2392 * 0 = no h/w change
2393 * 1 = need h/w change
2394 */
2395static int
2396rxf_promisc_enable(struct bna_rxf *rxf)
2397{
2398 struct bna *bna = rxf->rx->bna;
2399 int ret = 0;
2400
2401 /* There can not be any pending disable command */
2402
2403 /* Do nothing if pending enable or already enabled */
2404 if (is_promisc_enable(rxf->rxmode_pending,
2405 rxf->rxmode_pending_bitmask) ||
2406 (rxf->rxmode_active & BNA_RXMODE_PROMISC)) {
2407 /* Schedule enable */
2408 } else {
2409 /* Promisc mode should not be active in the system */
2410 promisc_enable(rxf->rxmode_pending,
2411 rxf->rxmode_pending_bitmask);
2412 bna->rxf_promisc_id = rxf->rxf_id;
2413 ret = 1;
2414 }
2415
2416 return ret;
2417}
2418
2419/**
2420 * Should only be called by bna_rxf_mode_set.
2421 * Helps deciding if h/w configuration is needed or not.
2422 * Returns:
2423 * 0 = no h/w change
2424 * 1 = need h/w change
2425 */
2426static int
2427rxf_promisc_disable(struct bna_rxf *rxf)
2428{
2429 struct bna *bna = rxf->rx->bna;
2430 int ret = 0;
2431
2432 /* There can not be any pending disable */
2433
2434 /* Turn off pending enable command , if any */
2435 if (is_promisc_enable(rxf->rxmode_pending,
2436 rxf->rxmode_pending_bitmask)) {
2437 /* Promisc mode should not be active */
2438 /* system promisc state should be pending */
2439 promisc_inactive(rxf->rxmode_pending,
2440 rxf->rxmode_pending_bitmask);
2441 /* Remove the promisc state from the system */
2442 bna->rxf_promisc_id = BFI_MAX_RXF;
2443
2444 /* Schedule disable */
2445 } else if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
2446 /* Promisc mode should be active in the system */
2447 promisc_disable(rxf->rxmode_pending,
2448 rxf->rxmode_pending_bitmask);
2449 ret = 1;
2450
2451 /* Do nothing if already disabled */
2452 } else {
2453 }
2454
2455 return ret;
2456}
2457
2458/**
2459 * Should only be called by bna_rxf_mode_set.
2460 * Helps deciding if h/w configuration is needed or not.
2461 * Returns:
2462 * 0 = no h/w change
2463 * 1 = need h/w change
2464 */
2465static int
2466rxf_allmulti_enable(struct bna_rxf *rxf)
2467{
2468 int ret = 0;
2469
2470 /* There can not be any pending disable command */
2471
2472 /* Do nothing if pending enable or already enabled */
2473 if (is_allmulti_enable(rxf->rxmode_pending,
2474 rxf->rxmode_pending_bitmask) ||
2475 (rxf->rxmode_active & BNA_RXMODE_ALLMULTI)) {
2476 /* Schedule enable */
2477 } else {
2478 allmulti_enable(rxf->rxmode_pending,
2479 rxf->rxmode_pending_bitmask);
2480 ret = 1;
2481 }
2482
2483 return ret;
2484}
2485
2486/**
2487 * Should only be called by bna_rxf_mode_set.
2488 * Helps deciding if h/w configuration is needed or not.
2489 * Returns:
2490 * 0 = no h/w change
2491 * 1 = need h/w change
2492 */
2493static int
2494rxf_allmulti_disable(struct bna_rxf *rxf)
2495{
2496 int ret = 0;
2497
2498 /* There can not be any pending disable */
2499
2500 /* Turn off pending enable command , if any */
2501 if (is_allmulti_enable(rxf->rxmode_pending,
2502 rxf->rxmode_pending_bitmask)) {
2503 /* Allmulti mode should not be active */
2504 allmulti_inactive(rxf->rxmode_pending,
2505 rxf->rxmode_pending_bitmask);
2506
2507 /* Schedule disable */
2508 } else if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
2509 allmulti_disable(rxf->rxmode_pending,
2510 rxf->rxmode_pending_bitmask);
2511 ret = 1;
2512 }
2513
2514 return ret;
2515}
2516
2517/* RxF <- bnad */
2518enum bna_cb_status
2519bna_rx_mode_set(struct bna_rx *rx, enum bna_rxmode new_mode,
2520 enum bna_rxmode bitmask,
2521 void (*cbfn)(struct bnad *, struct bna_rx *,
2522 enum bna_cb_status))
2523{
2524 struct bna_rxf *rxf = &rx->rxf;
2525 int need_hw_config = 0;
2526
2527 /* Process the commands */
2528
2529 if (is_promisc_enable(new_mode, bitmask)) {
2530 /* If promisc mode is already enabled elsewhere in the system */
2531 if ((rx->bna->rxf_promisc_id != BFI_MAX_RXF) &&
2532 (rx->bna->rxf_promisc_id != rxf->rxf_id))
2533 goto err_return;
2534 if (rxf_promisc_enable(rxf))
2535 need_hw_config = 1;
2536 } else if (is_promisc_disable(new_mode, bitmask)) {
2537 if (rxf_promisc_disable(rxf))
2538 need_hw_config = 1;
2539 }
2540
2541 if (is_allmulti_enable(new_mode, bitmask)) {
2542 if (rxf_allmulti_enable(rxf))
2543 need_hw_config = 1;
2544 } else if (is_allmulti_disable(new_mode, bitmask)) {
2545 if (rxf_allmulti_disable(rxf))
2546 need_hw_config = 1;
2547 }
2548
2549 /* Trigger h/w if needed */
2550
2551 if (need_hw_config) {
2552 rxf->cam_fltr_cbfn = cbfn;
2553 rxf->cam_fltr_cbarg = rx->bna->bnad;
2554 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
2555 } else if (cbfn)
2556 (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
2557
2558 return BNA_CB_SUCCESS;
2559
2560err_return:
2561 return BNA_CB_FAIL;
2562}
2563
2564void
2565/* RxF <- bnad */
2566bna_rx_vlanfilter_enable(struct bna_rx *rx)
2567{
2568 struct bna_rxf *rxf = &rx->rxf;
2569
2570 if (rxf->vlan_filter_status == BNA_STATUS_T_DISABLED) {
2571 rxf->rxf_flags |= BNA_RXF_FL_VLAN_CONFIG_PENDING;
2572 rxf->vlan_filter_status = BNA_STATUS_T_ENABLED;
2573 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
2574 }
2575}
2576
2577/* Rx */
2578
2579/* Rx <- bnad */
2580void
2581bna_rx_coalescing_timeo_set(struct bna_rx *rx, int coalescing_timeo)
2582{
2583 struct bna_rxp *rxp;
2584 struct list_head *qe;
2585
2586 list_for_each(qe, &rx->rxp_q) {
2587 rxp = (struct bna_rxp *)qe;
2588 rxp->cq.ccb->rx_coalescing_timeo = coalescing_timeo;
2589 bna_ib_coalescing_timeo_set(rxp->cq.ib, coalescing_timeo);
2590 }
2591}
2592
2593/* Rx <- bnad */
2594void
2595bna_rx_dim_reconfig(struct bna *bna, const u32 vector[][BNA_BIAS_T_MAX])
2596{
2597 int i, j;
2598
2599 for (i = 0; i < BNA_LOAD_T_MAX; i++)
2600 for (j = 0; j < BNA_BIAS_T_MAX; j++)
2601 bna->rx_mod.dim_vector[i][j] = vector[i][j];
2602}
2603
2604/* Rx <- bnad */
2605void
2606bna_rx_dim_update(struct bna_ccb *ccb)
2607{
2608 struct bna *bna = ccb->cq->rx->bna;
2609 u32 load, bias;
2610 u32 pkt_rt, small_rt, large_rt;
2611 u8 coalescing_timeo;
2612
2613 if ((ccb->pkt_rate.small_pkt_cnt == 0) &&
2614 (ccb->pkt_rate.large_pkt_cnt == 0))
2615 return;
2616
2617 /* Arrive at preconfigured coalescing timeo value based on pkt rate */
2618
2619 small_rt = ccb->pkt_rate.small_pkt_cnt;
2620 large_rt = ccb->pkt_rate.large_pkt_cnt;
2621
2622 pkt_rt = small_rt + large_rt;
2623
2624 if (pkt_rt < BNA_PKT_RATE_10K)
2625 load = BNA_LOAD_T_LOW_4;
2626 else if (pkt_rt < BNA_PKT_RATE_20K)
2627 load = BNA_LOAD_T_LOW_3;
2628 else if (pkt_rt < BNA_PKT_RATE_30K)
2629 load = BNA_LOAD_T_LOW_2;
2630 else if (pkt_rt < BNA_PKT_RATE_40K)
2631 load = BNA_LOAD_T_LOW_1;
2632 else if (pkt_rt < BNA_PKT_RATE_50K)
2633 load = BNA_LOAD_T_HIGH_1;
2634 else if (pkt_rt < BNA_PKT_RATE_60K)
2635 load = BNA_LOAD_T_HIGH_2;
2636 else if (pkt_rt < BNA_PKT_RATE_80K)
2637 load = BNA_LOAD_T_HIGH_3;
2638 else
2639 load = BNA_LOAD_T_HIGH_4;
2640
2641 if (small_rt > (large_rt << 1))
2642 bias = 0;
2643 else
2644 bias = 1;
2645
2646 ccb->pkt_rate.small_pkt_cnt = 0;
2647 ccb->pkt_rate.large_pkt_cnt = 0;
2648
2649 coalescing_timeo = bna->rx_mod.dim_vector[load][bias];
2650 ccb->rx_coalescing_timeo = coalescing_timeo;
2651
2652 /* Set it to IB */
2653 bna_ib_coalescing_timeo_set(ccb->cq->ib, coalescing_timeo);
2654}
2655
2656/* Tx */
2657/* TX <- bnad */
2658void
2659bna_tx_coalescing_timeo_set(struct bna_tx *tx, int coalescing_timeo)
2660{
2661 struct bna_txq *txq;
2662 struct list_head *qe;
2663
2664 list_for_each(qe, &tx->txq_q) {
2665 txq = (struct bna_txq *)qe;
2666 bna_ib_coalescing_timeo_set(txq->ib, coalescing_timeo);
2667 }
2668}
2669
2670/*
2671 * Private data
2672 */
2673
2674struct bna_ritseg_pool_cfg {
2675 u32 pool_size;
2676 u32 pool_entry_size;
2677};
2678init_ritseg_pool(ritseg_pool_cfg);
2679
2680/*
2681 * Private functions
2682 */
2683static void
2684bna_ucam_mod_init(struct bna_ucam_mod *ucam_mod, struct bna *bna,
2685 struct bna_res_info *res_info)
2686{
2687 int i;
2688
2689 ucam_mod->ucmac = (struct bna_mac *)
2690 res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.mdl[0].kva;
2691
2692 INIT_LIST_HEAD(&ucam_mod->free_q);
2693 for (i = 0; i < BFI_MAX_UCMAC; i++) {
2694 bfa_q_qe_init(&ucam_mod->ucmac[i].qe);
2695 list_add_tail(&ucam_mod->ucmac[i].qe, &ucam_mod->free_q);
2696 }
2697
2698 ucam_mod->bna = bna;
2699}
2700
2701static void
2702bna_ucam_mod_uninit(struct bna_ucam_mod *ucam_mod)
2703{
2704 struct list_head *qe;
2705 int i = 0;
2706
2707 list_for_each(qe, &ucam_mod->free_q)
2708 i++;
2709
2710 ucam_mod->bna = NULL;
2711}
2712
2713static void
2714bna_mcam_mod_init(struct bna_mcam_mod *mcam_mod, struct bna *bna,
2715 struct bna_res_info *res_info)
2716{
2717 int i;
2718
2719 mcam_mod->mcmac = (struct bna_mac *)
2720 res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.mdl[0].kva;
2721
2722 INIT_LIST_HEAD(&mcam_mod->free_q);
2723 for (i = 0; i < BFI_MAX_MCMAC; i++) {
2724 bfa_q_qe_init(&mcam_mod->mcmac[i].qe);
2725 list_add_tail(&mcam_mod->mcmac[i].qe, &mcam_mod->free_q);
2726 }
2727
2728 mcam_mod->bna = bna;
2729}
2730
2731static void
2732bna_mcam_mod_uninit(struct bna_mcam_mod *mcam_mod)
2733{
2734 struct list_head *qe;
2735 int i = 0;
2736
2737 list_for_each(qe, &mcam_mod->free_q)
2738 i++;
2739
2740 mcam_mod->bna = NULL;
2741}
2742
2743static void
2744bna_rit_mod_init(struct bna_rit_mod *rit_mod,
2745 struct bna_res_info *res_info)
2746{
2747 int i;
2748 int j;
2749 int count;
2750 int offset;
2751
2752 rit_mod->rit = (struct bna_rit_entry *)
2753 res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.mdl[0].kva;
2754 rit_mod->rit_segment = (struct bna_rit_segment *)
2755 res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.mdl[0].kva;
2756
2757 count = 0;
2758 offset = 0;
2759 for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
2760 INIT_LIST_HEAD(&rit_mod->rit_seg_pool[i]);
2761 for (j = 0; j < ritseg_pool_cfg[i].pool_size; j++) {
2762 bfa_q_qe_init(&rit_mod->rit_segment[count].qe);
2763 rit_mod->rit_segment[count].max_rit_size =
2764 ritseg_pool_cfg[i].pool_entry_size;
2765 rit_mod->rit_segment[count].rit_offset = offset;
2766 rit_mod->rit_segment[count].rit =
2767 &rit_mod->rit[offset];
2768 list_add_tail(&rit_mod->rit_segment[count].qe,
2769 &rit_mod->rit_seg_pool[i]);
2770 count++;
2771 offset += ritseg_pool_cfg[i].pool_entry_size;
2772 }
2773 }
2774}
2775
2776/*
2777 * Public functions
2778 */
2779
2780/* Called during probe(), before calling bna_init() */
2781void
2782bna_res_req(struct bna_res_info *res_info)
2783{
2784 bna_adv_res_req(res_info);
2785
2786 /* DMA memory for retrieving IOC attributes */
2787 res_info[BNA_RES_MEM_T_ATTR].res_type = BNA_RES_T_MEM;
2788 res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
2789 res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.num = 1;
2790 res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.len =
2791 ALIGN(bfa_nw_ioc_meminfo(), PAGE_SIZE);
2792
2793 /* DMA memory for index segment of an IB */
2794 res_info[BNA_RES_MEM_T_IBIDX].res_type = BNA_RES_T_MEM;
2795 res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
2796 res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.len =
2797 BFI_IBIDX_SIZE * BFI_IBIDX_MAX_SEGSIZE;
2798 res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.num = BFI_MAX_IB;
2799
2800 /* Virtual memory for IB objects - stored by IB module */
2801 res_info[BNA_RES_MEM_T_IB_ARRAY].res_type = BNA_RES_T_MEM;
2802 res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.mem_type =
2803 BNA_MEM_T_KVA;
2804 res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.num = 1;
2805 res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.len =
2806 BFI_MAX_IB * sizeof(struct bna_ib);
2807
2808 /* Virtual memory for intr objects - stored by IB module */
2809 res_info[BNA_RES_MEM_T_INTR_ARRAY].res_type = BNA_RES_T_MEM;
2810 res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.mem_type =
2811 BNA_MEM_T_KVA;
2812 res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.num = 1;
2813 res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.len =
2814 BFI_MAX_IB * sizeof(struct bna_intr);
2815
2816 /* Virtual memory for idx_seg objects - stored by IB module */
2817 res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_type = BNA_RES_T_MEM;
2818 res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.mem_type =
2819 BNA_MEM_T_KVA;
2820 res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.num = 1;
2821 res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.len =
2822 BFI_IBIDX_TOTAL_SEGS * sizeof(struct bna_ibidx_seg);
2823
2824 /* Virtual memory for Tx objects - stored by Tx module */
2825 res_info[BNA_RES_MEM_T_TX_ARRAY].res_type = BNA_RES_T_MEM;
2826 res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.mem_type =
2827 BNA_MEM_T_KVA;
2828 res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.num = 1;
2829 res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.len =
2830 BFI_MAX_TXQ * sizeof(struct bna_tx);
2831
2832 /* Virtual memory for TxQ - stored by Tx module */
2833 res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_type = BNA_RES_T_MEM;
2834 res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.mem_type =
2835 BNA_MEM_T_KVA;
2836 res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.num = 1;
2837 res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.len =
2838 BFI_MAX_TXQ * sizeof(struct bna_txq);
2839
2840 /* Virtual memory for Rx objects - stored by Rx module */
2841 res_info[BNA_RES_MEM_T_RX_ARRAY].res_type = BNA_RES_T_MEM;
2842 res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.mem_type =
2843 BNA_MEM_T_KVA;
2844 res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.num = 1;
2845 res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.len =
2846 BFI_MAX_RXQ * sizeof(struct bna_rx);
2847
2848 /* Virtual memory for RxPath - stored by Rx module */
2849 res_info[BNA_RES_MEM_T_RXP_ARRAY].res_type = BNA_RES_T_MEM;
2850 res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.mem_type =
2851 BNA_MEM_T_KVA;
2852 res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.num = 1;
2853 res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.len =
2854 BFI_MAX_RXQ * sizeof(struct bna_rxp);
2855
2856 /* Virtual memory for RxQ - stored by Rx module */
2857 res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_type = BNA_RES_T_MEM;
2858 res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.mem_type =
2859 BNA_MEM_T_KVA;
2860 res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.num = 1;
2861 res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.len =
2862 BFI_MAX_RXQ * sizeof(struct bna_rxq);
2863
2864 /* Virtual memory for Unicast MAC address - stored by ucam module */
2865 res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_type = BNA_RES_T_MEM;
2866 res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.mem_type =
2867 BNA_MEM_T_KVA;
2868 res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.num = 1;
2869 res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.len =
2870 BFI_MAX_UCMAC * sizeof(struct bna_mac);
2871
2872 /* Virtual memory for Multicast MAC address - stored by mcam module */
2873 res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_type = BNA_RES_T_MEM;
2874 res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.mem_type =
2875 BNA_MEM_T_KVA;
2876 res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.num = 1;
2877 res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.len =
2878 BFI_MAX_MCMAC * sizeof(struct bna_mac);
2879
2880 /* Virtual memory for RIT entries */
2881 res_info[BNA_RES_MEM_T_RIT_ENTRY].res_type = BNA_RES_T_MEM;
2882 res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.mem_type =
2883 BNA_MEM_T_KVA;
2884 res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.num = 1;
2885 res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.len =
2886 BFI_MAX_RIT_SIZE * sizeof(struct bna_rit_entry);
2887
2888 /* Virtual memory for RIT segment table */
2889 res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_type = BNA_RES_T_MEM;
2890 res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.mem_type =
2891 BNA_MEM_T_KVA;
2892 res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.num = 1;
2893 res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.len =
2894 BFI_RIT_TOTAL_SEGS * sizeof(struct bna_rit_segment);
2895
2896 /* Interrupt resource for mailbox interrupt */
2897 res_info[BNA_RES_INTR_T_MBOX].res_type = BNA_RES_T_INTR;
2898 res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.intr_type =
2899 BNA_INTR_T_MSIX;
2900 res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.num = 1;
2901}
2902
2903/* Called during probe() */
2904void
2905bna_init(struct bna *bna, struct bnad *bnad, struct bfa_pcidev *pcidev,
2906 struct bna_res_info *res_info)
2907{
2908 bna->bnad = bnad;
2909 bna->pcidev = *pcidev;
2910
2911 bna->stats.hw_stats = (struct bfi_ll_stats *)
2912 res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mdl[0].kva;
2913 bna->hw_stats_dma.msb =
2914 res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mdl[0].dma.msb;
2915 bna->hw_stats_dma.lsb =
2916 res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mdl[0].dma.lsb;
2917 bna->stats.sw_stats = (struct bna_sw_stats *)
2918 res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.mdl[0].kva;
2919
2920 bna->regs.page_addr = bna->pcidev.pci_bar_kva +
2921 reg_offset[bna->pcidev.pci_func].page_addr;
2922 bna->regs.fn_int_status = bna->pcidev.pci_bar_kva +
2923 reg_offset[bna->pcidev.pci_func].fn_int_status;
2924 bna->regs.fn_int_mask = bna->pcidev.pci_bar_kva +
2925 reg_offset[bna->pcidev.pci_func].fn_int_mask;
2926
2927 if (bna->pcidev.pci_func < 3)
2928 bna->port_num = 0;
2929 else
2930 bna->port_num = 1;
2931
2932 /* Also initializes diag, cee, sfp, phy_port and mbox_mod */
2933 bna_device_init(&bna->device, bna, res_info);
2934
2935 bna_port_init(&bna->port, bna);
2936
2937 bna_tx_mod_init(&bna->tx_mod, bna, res_info);
2938
2939 bna_rx_mod_init(&bna->rx_mod, bna, res_info);
2940
2941 bna_ib_mod_init(&bna->ib_mod, bna, res_info);
2942
2943 bna_rit_mod_init(&bna->rit_mod, res_info);
2944
2945 bna_ucam_mod_init(&bna->ucam_mod, bna, res_info);
2946
2947 bna_mcam_mod_init(&bna->mcam_mod, bna, res_info);
2948
2949 bna->rxf_promisc_id = BFI_MAX_RXF;
2950
2951 /* Mbox q element for posting stat request to f/w */
2952 bfa_q_qe_init(&bna->mbox_qe.qe);
2953}
2954
2955void
2956bna_uninit(struct bna *bna)
2957{
2958 bna_mcam_mod_uninit(&bna->mcam_mod);
2959
2960 bna_ucam_mod_uninit(&bna->ucam_mod);
2961
2962 bna_ib_mod_uninit(&bna->ib_mod);
2963
2964 bna_rx_mod_uninit(&bna->rx_mod);
2965
2966 bna_tx_mod_uninit(&bna->tx_mod);
2967
2968 bna_port_uninit(&bna->port);
2969
2970 bna_device_uninit(&bna->device);
2971
2972 bna->bnad = NULL;
2973}
2974
2975struct bna_mac *
2976bna_ucam_mod_mac_get(struct bna_ucam_mod *ucam_mod)
2977{
2978 struct list_head *qe;
2979
2980 if (list_empty(&ucam_mod->free_q))
2981 return NULL;
2982
2983 bfa_q_deq(&ucam_mod->free_q, &qe);
2984
2985 return (struct bna_mac *)qe;
2986}
2987
2988void
2989bna_ucam_mod_mac_put(struct bna_ucam_mod *ucam_mod, struct bna_mac *mac)
2990{
2991 list_add_tail(&mac->qe, &ucam_mod->free_q);
2992}
2993
2994struct bna_mac *
2995bna_mcam_mod_mac_get(struct bna_mcam_mod *mcam_mod)
2996{
2997 struct list_head *qe;
2998
2999 if (list_empty(&mcam_mod->free_q))
3000 return NULL;
3001
3002 bfa_q_deq(&mcam_mod->free_q, &qe);
3003
3004 return (struct bna_mac *)qe;
3005}
3006
3007void
3008bna_mcam_mod_mac_put(struct bna_mcam_mod *mcam_mod, struct bna_mac *mac)
3009{
3010 list_add_tail(&mac->qe, &mcam_mod->free_q);
3011}
3012
3013/**
3014 * Note: This should be called in the same locking context as the call to
3015 * bna_rit_mod_seg_get()
3016 */
3017int
3018bna_rit_mod_can_satisfy(struct bna_rit_mod *rit_mod, int seg_size)
3019{
3020 int i;
3021
3022 /* Select the pool for seg_size */
3023 for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
3024 if (seg_size <= ritseg_pool_cfg[i].pool_entry_size)
3025 break;
3026 }
3027
3028 if (i == BFI_RIT_SEG_TOTAL_POOLS)
3029 return 0;
3030
3031 if (list_empty(&rit_mod->rit_seg_pool[i]))
3032 return 0;
3033
3034 return 1;
3035}
3036
3037struct bna_rit_segment *
3038bna_rit_mod_seg_get(struct bna_rit_mod *rit_mod, int seg_size)
3039{
3040 struct bna_rit_segment *seg;
3041 struct list_head *qe;
3042 int i;
3043
3044 /* Select the pool for seg_size */
3045 for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
3046 if (seg_size <= ritseg_pool_cfg[i].pool_entry_size)
3047 break;
3048 }
3049
3050 if (i == BFI_RIT_SEG_TOTAL_POOLS)
3051 return NULL;
3052
3053 if (list_empty(&rit_mod->rit_seg_pool[i]))
3054 return NULL;
3055
3056 bfa_q_deq(&rit_mod->rit_seg_pool[i], &qe);
3057 seg = (struct bna_rit_segment *)qe;
3058 bfa_q_qe_init(&seg->qe);
3059 seg->rit_size = seg_size;
3060
3061 return seg;
3062}
3063
3064void
3065bna_rit_mod_seg_put(struct bna_rit_mod *rit_mod,
3066 struct bna_rit_segment *seg)
3067{
3068 int i;
3069
3070 /* Select the pool for seg->max_rit_size */
3071 for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
3072 if (seg->max_rit_size == ritseg_pool_cfg[i].pool_entry_size)
3073 break;
3074 }
3075
3076 seg->rit_size = 0;
3077 list_add_tail(&seg->qe, &rit_mod->rit_seg_pool[i]);
3078}
diff --git a/drivers/net/ethernet/brocade/bna/bna_hw.h b/drivers/net/ethernet/brocade/bna/bna_hw.h
deleted file mode 100644
index 16a5eed4a03b..000000000000
--- a/drivers/net/ethernet/brocade/bna/bna_hw.h
+++ /dev/null
@@ -1,1492 +0,0 @@
1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18
19/**
20 * File for interrupt macros and functions
21 */
22
23#ifndef __BNA_HW_H__
24#define __BNA_HW_H__
25
26#include "bfi_reg.h"
27
28/**
29 *
30 * SW imposed limits
31 *
32 */
33
34#ifndef BNA_BIOS_BUILD
35
36#define BFI_MAX_TXQ 64
37#define BFI_MAX_RXQ 64
38#define BFI_MAX_RXF 64
39#define BFI_MAX_IB 128
40#define BFI_MAX_RIT_SIZE 256
41#define BFI_RSS_RIT_SIZE 64
42#define BFI_NONRSS_RIT_SIZE 1
43#define BFI_MAX_UCMAC 256
44#define BFI_MAX_MCMAC 512
45#define BFI_IBIDX_SIZE 4
46#define BFI_MAX_VLAN 4095
47
48/**
49 * There are 2 free IB index pools:
50 * pool1: 120 segments of 1 index each
51 * pool8: 1 segment of 8 indexes
52 */
53#define BFI_IBIDX_POOL1_SIZE 116
54#define BFI_IBIDX_POOL1_ENTRY_SIZE 1
55#define BFI_IBIDX_POOL2_SIZE 2
56#define BFI_IBIDX_POOL2_ENTRY_SIZE 2
57#define BFI_IBIDX_POOL8_SIZE 1
58#define BFI_IBIDX_POOL8_ENTRY_SIZE 8
59#define BFI_IBIDX_TOTAL_POOLS 3
60#define BFI_IBIDX_TOTAL_SEGS 119 /* (POOL1 + POOL2 + POOL8)_SIZE */
61#define BFI_IBIDX_MAX_SEGSIZE 8
62#define init_ibidx_pool(name) \
63static struct bna_ibidx_pool name[BFI_IBIDX_TOTAL_POOLS] = \
64{ \
65 { BFI_IBIDX_POOL1_SIZE, BFI_IBIDX_POOL1_ENTRY_SIZE }, \
66 { BFI_IBIDX_POOL2_SIZE, BFI_IBIDX_POOL2_ENTRY_SIZE }, \
67 { BFI_IBIDX_POOL8_SIZE, BFI_IBIDX_POOL8_ENTRY_SIZE } \
68}
69
70/**
71 * There are 2 free RIT segment pools:
72 * Pool1: 192 segments of 1 RIT entry each
73 * Pool2: 1 segment of 64 RIT entry
74 */
75#define BFI_RIT_SEG_POOL1_SIZE 192
76#define BFI_RIT_SEG_POOL1_ENTRY_SIZE 1
77#define BFI_RIT_SEG_POOLRSS_SIZE 1
78#define BFI_RIT_SEG_POOLRSS_ENTRY_SIZE 64
79#define BFI_RIT_SEG_TOTAL_POOLS 2
80#define BFI_RIT_TOTAL_SEGS 193 /* POOL1_SIZE + POOLRSS_SIZE */
81#define init_ritseg_pool(name) \
82static struct bna_ritseg_pool_cfg name[BFI_RIT_SEG_TOTAL_POOLS] = \
83{ \
84 { BFI_RIT_SEG_POOL1_SIZE, BFI_RIT_SEG_POOL1_ENTRY_SIZE }, \
85 { BFI_RIT_SEG_POOLRSS_SIZE, BFI_RIT_SEG_POOLRSS_ENTRY_SIZE } \
86}
87
88#else /* BNA_BIOS_BUILD */
89
90#define BFI_MAX_TXQ 1
91#define BFI_MAX_RXQ 1
92#define BFI_MAX_RXF 1
93#define BFI_MAX_IB 2
94#define BFI_MAX_RIT_SIZE 2
95#define BFI_RSS_RIT_SIZE 64
96#define BFI_NONRSS_RIT_SIZE 1
97#define BFI_MAX_UCMAC 1
98#define BFI_MAX_MCMAC 8
99#define BFI_IBIDX_SIZE 4
100#define BFI_MAX_VLAN 4095
101/* There is one free pool: 2 segments of 1 index each */
102#define BFI_IBIDX_POOL1_SIZE 2
103#define BFI_IBIDX_POOL1_ENTRY_SIZE 1
104#define BFI_IBIDX_TOTAL_POOLS 1
105#define BFI_IBIDX_TOTAL_SEGS 2 /* POOL1_SIZE */
106#define BFI_IBIDX_MAX_SEGSIZE 1
107#define init_ibidx_pool(name) \
108static struct bna_ibidx_pool name[BFI_IBIDX_TOTAL_POOLS] = \
109{ \
110 { BFI_IBIDX_POOL1_SIZE, BFI_IBIDX_POOL1_ENTRY_SIZE } \
111}
112
113#define BFI_RIT_SEG_POOL1_SIZE 1
114#define BFI_RIT_SEG_POOL1_ENTRY_SIZE 1
115#define BFI_RIT_SEG_TOTAL_POOLS 1
116#define BFI_RIT_TOTAL_SEGS 1 /* POOL1_SIZE */
117#define init_ritseg_pool(name) \
118static struct bna_ritseg_pool_cfg name[BFI_RIT_SEG_TOTAL_POOLS] = \
119{ \
120 { BFI_RIT_SEG_POOL1_SIZE, BFI_RIT_SEG_POOL1_ENTRY_SIZE } \
121}
122
123#endif /* BNA_BIOS_BUILD */
124
125#define BFI_RSS_HASH_KEY_LEN 10
126
127#define BFI_COALESCING_TIMER_UNIT 5 /* 5us */
128#define BFI_MAX_COALESCING_TIMEO 0xFF /* in 5us units */
129#define BFI_MAX_INTERPKT_COUNT 0xFF
130#define BFI_MAX_INTERPKT_TIMEO 0xF /* in 0.5us units */
131#define BFI_TX_COALESCING_TIMEO 20 /* 20 * 5 = 100us */
132#define BFI_TX_INTERPKT_COUNT 32
133#define BFI_RX_COALESCING_TIMEO 12 /* 12 * 5 = 60us */
134#define BFI_RX_INTERPKT_COUNT 6 /* Pkt Cnt = 6 */
135#define BFI_RX_INTERPKT_TIMEO 3 /* 3 * 0.5 = 1.5us */
136
137#define BFI_TXQ_WI_SIZE 64 /* bytes */
138#define BFI_RXQ_WI_SIZE 8 /* bytes */
139#define BFI_CQ_WI_SIZE 16 /* bytes */
140#define BFI_TX_MAX_WRR_QUOTA 0xFFF
141
142#define BFI_TX_MAX_VECTORS_PER_WI 4
143#define BFI_TX_MAX_VECTORS_PER_PKT 0xFF
144#define BFI_TX_MAX_DATA_PER_VECTOR 0xFFFF
145#define BFI_TX_MAX_DATA_PER_PKT 0xFFFFFF
146
147/* Small Q buffer size */
148#define BFI_SMALL_RXBUF_SIZE 128
149
150/* Defined separately since BFA_FLASH_DMA_BUF_SZ is in bfa_flash.c */
151#define BFI_FLASH_DMA_BUF_SZ 0x010000 /* 64K DMA */
152#define BFI_HW_STATS_SIZE 0x4000 /* 16K DMA */
153
154/**
155 *
156 * HW register offsets, macros
157 *
158 */
159
160/* DMA Block Register Host Window Start Address */
161#define DMA_BLK_REG_ADDR 0x00013000
162
163/* DMA Block Internal Registers */
164#define DMA_CTRL_REG0 (DMA_BLK_REG_ADDR + 0x000)
165#define DMA_CTRL_REG1 (DMA_BLK_REG_ADDR + 0x004)
166#define DMA_ERR_INT_STATUS (DMA_BLK_REG_ADDR + 0x008)
167#define DMA_ERR_INT_ENABLE (DMA_BLK_REG_ADDR + 0x00c)
168#define DMA_ERR_INT_STATUS_SET (DMA_BLK_REG_ADDR + 0x010)
169
170/* APP Block Register Address Offset from BAR0 */
171#define APP_BLK_REG_ADDR 0x00014000
172
173/* Host Function Interrupt Mask Registers */
174#define HOSTFN0_INT_MASK (APP_BLK_REG_ADDR + 0x004)
175#define HOSTFN1_INT_MASK (APP_BLK_REG_ADDR + 0x104)
176#define HOSTFN2_INT_MASK (APP_BLK_REG_ADDR + 0x304)
177#define HOSTFN3_INT_MASK (APP_BLK_REG_ADDR + 0x404)
178
179/**
180 * Host Function PCIe Error Registers
181 * Duplicates "Correctable" & "Uncorrectable"
182 * registers in PCIe Config space.
183 */
184#define FN0_PCIE_ERR_REG (APP_BLK_REG_ADDR + 0x014)
185#define FN1_PCIE_ERR_REG (APP_BLK_REG_ADDR + 0x114)
186#define FN2_PCIE_ERR_REG (APP_BLK_REG_ADDR + 0x314)
187#define FN3_PCIE_ERR_REG (APP_BLK_REG_ADDR + 0x414)
188
189/* Host Function Error Type Status Registers */
190#define FN0_ERR_TYPE_STATUS_REG (APP_BLK_REG_ADDR + 0x018)
191#define FN1_ERR_TYPE_STATUS_REG (APP_BLK_REG_ADDR + 0x118)
192#define FN2_ERR_TYPE_STATUS_REG (APP_BLK_REG_ADDR + 0x318)
193#define FN3_ERR_TYPE_STATUS_REG (APP_BLK_REG_ADDR + 0x418)
194
195/* Host Function Error Type Mask Registers */
196#define FN0_ERR_TYPE_MSK_STATUS_REG (APP_BLK_REG_ADDR + 0x01c)
197#define FN1_ERR_TYPE_MSK_STATUS_REG (APP_BLK_REG_ADDR + 0x11c)
198#define FN2_ERR_TYPE_MSK_STATUS_REG (APP_BLK_REG_ADDR + 0x31c)
199#define FN3_ERR_TYPE_MSK_STATUS_REG (APP_BLK_REG_ADDR + 0x41c)
200
201/* Catapult Host Semaphore Status Registers (App block) */
202#define HOST_SEM_STS0_REG (APP_BLK_REG_ADDR + 0x630)
203#define HOST_SEM_STS1_REG (APP_BLK_REG_ADDR + 0x634)
204#define HOST_SEM_STS2_REG (APP_BLK_REG_ADDR + 0x638)
205#define HOST_SEM_STS3_REG (APP_BLK_REG_ADDR + 0x63c)
206#define HOST_SEM_STS4_REG (APP_BLK_REG_ADDR + 0x640)
207#define HOST_SEM_STS5_REG (APP_BLK_REG_ADDR + 0x644)
208#define HOST_SEM_STS6_REG (APP_BLK_REG_ADDR + 0x648)
209#define HOST_SEM_STS7_REG (APP_BLK_REG_ADDR + 0x64c)
210
211/* PCIe Misc Register */
212#define PCIE_MISC_REG (APP_BLK_REG_ADDR + 0x200)
213
214/* Temp Sensor Control Registers */
215#define TEMPSENSE_CNTL_REG (APP_BLK_REG_ADDR + 0x250)
216#define TEMPSENSE_STAT_REG (APP_BLK_REG_ADDR + 0x254)
217
218/* APP Block local error registers */
219#define APP_LOCAL_ERR_STAT (APP_BLK_REG_ADDR + 0x258)
220#define APP_LOCAL_ERR_MSK (APP_BLK_REG_ADDR + 0x25c)
221
222/* PCIe Link Error registers */
223#define PCIE_LNK_ERR_STAT (APP_BLK_REG_ADDR + 0x260)
224#define PCIE_LNK_ERR_MSK (APP_BLK_REG_ADDR + 0x264)
225
226/**
227 * FCoE/FIP Ethertype Register
228 * 31:16 -- Chip wide value for FIP type
229 * 15:0 -- Chip wide value for FCoE type
230 */
231#define FCOE_FIP_ETH_TYPE (APP_BLK_REG_ADDR + 0x280)
232
233/**
234 * Reserved Ethertype Register
235 * 31:16 -- Reserved
236 * 15:0 -- Other ethertype
237 */
238#define RESV_ETH_TYPE (APP_BLK_REG_ADDR + 0x284)
239
240/**
241 * Host Command Status Registers
242 * Each set consists of 3 registers :
243 * clear, set, cmd
244 * 16 such register sets in all
245 * See catapult_spec.pdf for detailed functionality
246 * Put each type in a single macro accessed by _num ?
247 */
248#define HOST_CMDSTS0_CLR_REG (APP_BLK_REG_ADDR + 0x500)
249#define HOST_CMDSTS0_SET_REG (APP_BLK_REG_ADDR + 0x504)
250#define HOST_CMDSTS0_REG (APP_BLK_REG_ADDR + 0x508)
251#define HOST_CMDSTS1_CLR_REG (APP_BLK_REG_ADDR + 0x510)
252#define HOST_CMDSTS1_SET_REG (APP_BLK_REG_ADDR + 0x514)
253#define HOST_CMDSTS1_REG (APP_BLK_REG_ADDR + 0x518)
254#define HOST_CMDSTS2_CLR_REG (APP_BLK_REG_ADDR + 0x520)
255#define HOST_CMDSTS2_SET_REG (APP_BLK_REG_ADDR + 0x524)
256#define HOST_CMDSTS2_REG (APP_BLK_REG_ADDR + 0x528)
257#define HOST_CMDSTS3_CLR_REG (APP_BLK_REG_ADDR + 0x530)
258#define HOST_CMDSTS3_SET_REG (APP_BLK_REG_ADDR + 0x534)
259#define HOST_CMDSTS3_REG (APP_BLK_REG_ADDR + 0x538)
260#define HOST_CMDSTS4_CLR_REG (APP_BLK_REG_ADDR + 0x540)
261#define HOST_CMDSTS4_SET_REG (APP_BLK_REG_ADDR + 0x544)
262#define HOST_CMDSTS4_REG (APP_BLK_REG_ADDR + 0x548)
263#define HOST_CMDSTS5_CLR_REG (APP_BLK_REG_ADDR + 0x550)
264#define HOST_CMDSTS5_SET_REG (APP_BLK_REG_ADDR + 0x554)
265#define HOST_CMDSTS5_REG (APP_BLK_REG_ADDR + 0x558)
266#define HOST_CMDSTS6_CLR_REG (APP_BLK_REG_ADDR + 0x560)
267#define HOST_CMDSTS6_SET_REG (APP_BLK_REG_ADDR + 0x564)
268#define HOST_CMDSTS6_REG (APP_BLK_REG_ADDR + 0x568)
269#define HOST_CMDSTS7_CLR_REG (APP_BLK_REG_ADDR + 0x570)
270#define HOST_CMDSTS7_SET_REG (APP_BLK_REG_ADDR + 0x574)
271#define HOST_CMDSTS7_REG (APP_BLK_REG_ADDR + 0x578)
272#define HOST_CMDSTS8_CLR_REG (APP_BLK_REG_ADDR + 0x580)
273#define HOST_CMDSTS8_SET_REG (APP_BLK_REG_ADDR + 0x584)
274#define HOST_CMDSTS8_REG (APP_BLK_REG_ADDR + 0x588)
275#define HOST_CMDSTS9_CLR_REG (APP_BLK_REG_ADDR + 0x590)
276#define HOST_CMDSTS9_SET_REG (APP_BLK_REG_ADDR + 0x594)
277#define HOST_CMDSTS9_REG (APP_BLK_REG_ADDR + 0x598)
278#define HOST_CMDSTS10_CLR_REG (APP_BLK_REG_ADDR + 0x5A0)
279#define HOST_CMDSTS10_SET_REG (APP_BLK_REG_ADDR + 0x5A4)
280#define HOST_CMDSTS10_REG (APP_BLK_REG_ADDR + 0x5A8)
281#define HOST_CMDSTS11_CLR_REG (APP_BLK_REG_ADDR + 0x5B0)
282#define HOST_CMDSTS11_SET_REG (APP_BLK_REG_ADDR + 0x5B4)
283#define HOST_CMDSTS11_REG (APP_BLK_REG_ADDR + 0x5B8)
284#define HOST_CMDSTS12_CLR_REG (APP_BLK_REG_ADDR + 0x5C0)
285#define HOST_CMDSTS12_SET_REG (APP_BLK_REG_ADDR + 0x5C4)
286#define HOST_CMDSTS12_REG (APP_BLK_REG_ADDR + 0x5C8)
287#define HOST_CMDSTS13_CLR_REG (APP_BLK_REG_ADDR + 0x5D0)
288#define HOST_CMDSTS13_SET_REG (APP_BLK_REG_ADDR + 0x5D4)
289#define HOST_CMDSTS13_REG (APP_BLK_REG_ADDR + 0x5D8)
290#define HOST_CMDSTS14_CLR_REG (APP_BLK_REG_ADDR + 0x5E0)
291#define HOST_CMDSTS14_SET_REG (APP_BLK_REG_ADDR + 0x5E4)
292#define HOST_CMDSTS14_REG (APP_BLK_REG_ADDR + 0x5E8)
293#define HOST_CMDSTS15_CLR_REG (APP_BLK_REG_ADDR + 0x5F0)
294#define HOST_CMDSTS15_SET_REG (APP_BLK_REG_ADDR + 0x5F4)
295#define HOST_CMDSTS15_REG (APP_BLK_REG_ADDR + 0x5F8)
296
297/**
298 * LPU0 Block Register Address Offset from BAR0
299 * Range 0x18000 - 0x18033
300 */
301#define LPU0_BLK_REG_ADDR 0x00018000
302
303/**
304 * LPU0 Registers
305 * Should they be directly used from host,
306 * except for diagnostics ?
307 * CTL_REG : Control register
308 * CMD_REG : Triggers exec. of cmd. in
309 * Mailbox memory
310 */
311#define LPU0_MBOX_CTL_REG (LPU0_BLK_REG_ADDR + 0x000)
312#define LPU0_MBOX_CMD_REG (LPU0_BLK_REG_ADDR + 0x004)
313#define LPU0_MBOX_LINK_0REG (LPU0_BLK_REG_ADDR + 0x008)
314#define LPU1_MBOX_LINK_0REG (LPU0_BLK_REG_ADDR + 0x00c)
315#define LPU0_MBOX_STATUS_0REG (LPU0_BLK_REG_ADDR + 0x010)
316#define LPU1_MBOX_STATUS_0REG (LPU0_BLK_REG_ADDR + 0x014)
317#define LPU0_ERR_STATUS_REG (LPU0_BLK_REG_ADDR + 0x018)
318#define LPU0_ERR_SET_REG (LPU0_BLK_REG_ADDR + 0x020)
319
320/**
321 * LPU1 Block Register Address Offset from BAR0
322 * Range 0x18400 - 0x18433
323 */
324#define LPU1_BLK_REG_ADDR 0x00018400
325
326/**
327 * LPU1 Registers
328 * Same as LPU0 registers above
329 */
330#define LPU1_MBOX_CTL_REG (LPU1_BLK_REG_ADDR + 0x000)
331#define LPU1_MBOX_CMD_REG (LPU1_BLK_REG_ADDR + 0x004)
332#define LPU0_MBOX_LINK_1REG (LPU1_BLK_REG_ADDR + 0x008)
333#define LPU1_MBOX_LINK_1REG (LPU1_BLK_REG_ADDR + 0x00c)
334#define LPU0_MBOX_STATUS_1REG (LPU1_BLK_REG_ADDR + 0x010)
335#define LPU1_MBOX_STATUS_1REG (LPU1_BLK_REG_ADDR + 0x014)
336#define LPU1_ERR_STATUS_REG (LPU1_BLK_REG_ADDR + 0x018)
337#define LPU1_ERR_SET_REG (LPU1_BLK_REG_ADDR + 0x020)
338
339/**
340 * PSS Block Register Address Offset from BAR0
341 * Range 0x18800 - 0x188DB
342 */
343#define PSS_BLK_REG_ADDR 0x00018800
344
345/**
346 * PSS Registers
347 * For details, see catapult_spec.pdf
348 * ERR_STATUS_REG : Indicates error in PSS module
349 * RAM_ERR_STATUS_REG : Indicates RAM module that detected error
350 */
351#define ERR_STATUS_SET (PSS_BLK_REG_ADDR + 0x018)
352#define PSS_RAM_ERR_STATUS_REG (PSS_BLK_REG_ADDR + 0x01C)
353
354/**
355 * PSS Semaphore Lock Registers, total 16
356 * First read when unlocked returns 0,
357 * and is set to 1, atomically.
358 * Subsequent reads returns 1.
359 * To clear set the value to 0.
360 * Range : 0x20 to 0x5c
361 */
362#define PSS_SEM_LOCK_REG(_num) \
363 (PSS_BLK_REG_ADDR + 0x020 + ((_num) << 2))
364
365/**
366 * PSS Semaphore Status Registers,
367 * corresponding to the lock registers above
368 */
369#define PSS_SEM_STATUS_REG(_num) \
370 (PSS_BLK_REG_ADDR + 0x060 + ((_num) << 2))
371
372/**
373 * Catapult CPQ Registers
374 * Defines for Mailbox Registers
375 * Used to send mailbox commands to firmware from
376 * host. The data part is written to the MBox
377 * memory, registers are used to indicate that
378 * a commnad is resident in memory.
379 *
380 * Note : LPU0<->LPU1 mailboxes are not listed here
381 */
382#define CPQ_BLK_REG_ADDR 0x00019000
383
384#define HOSTFN0_LPU0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x130)
385#define HOSTFN0_LPU1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x134)
386#define LPU0_HOSTFN0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x138)
387#define LPU1_HOSTFN0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x13C)
388
389#define HOSTFN1_LPU0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x140)
390#define HOSTFN1_LPU1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x144)
391#define LPU0_HOSTFN1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x148)
392#define LPU1_HOSTFN1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x14C)
393
394#define HOSTFN2_LPU0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x170)
395#define HOSTFN2_LPU1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x174)
396#define LPU0_HOSTFN2_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x178)
397#define LPU1_HOSTFN2_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x17C)
398
399#define HOSTFN3_LPU0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x180)
400#define HOSTFN3_LPU1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x184)
401#define LPU0_HOSTFN3_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x188)
402#define LPU1_HOSTFN3_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x18C)
403
404/* Host Function Force Parity Error Registers */
405#define HOSTFN0_LPU_FORCE_PERR (CPQ_BLK_REG_ADDR + 0x120)
406#define HOSTFN1_LPU_FORCE_PERR (CPQ_BLK_REG_ADDR + 0x124)
407#define HOSTFN2_LPU_FORCE_PERR (CPQ_BLK_REG_ADDR + 0x128)
408#define HOSTFN3_LPU_FORCE_PERR (CPQ_BLK_REG_ADDR + 0x12C)
409
410/* LL Port[0|1] Halt Mask Registers */
411#define LL_HALT_MSK_P0 (CPQ_BLK_REG_ADDR + 0x1A0)
412#define LL_HALT_MSK_P1 (CPQ_BLK_REG_ADDR + 0x1B0)
413
414/* LL Port[0|1] Error Mask Registers */
415#define LL_ERR_MSK_P0 (CPQ_BLK_REG_ADDR + 0x1D0)
416#define LL_ERR_MSK_P1 (CPQ_BLK_REG_ADDR + 0x1D4)
417
418/* EMC FLI (Flash Controller) Block Register Address Offset from BAR0 */
419#define FLI_BLK_REG_ADDR 0x0001D000
420
421/* EMC FLI Registers */
422#define FLI_CMD_REG (FLI_BLK_REG_ADDR + 0x000)
423#define FLI_ADDR_REG (FLI_BLK_REG_ADDR + 0x004)
424#define FLI_CTL_REG (FLI_BLK_REG_ADDR + 0x008)
425#define FLI_WRDATA_REG (FLI_BLK_REG_ADDR + 0x00C)
426#define FLI_RDDATA_REG (FLI_BLK_REG_ADDR + 0x010)
427#define FLI_DEV_STATUS_REG (FLI_BLK_REG_ADDR + 0x014)
428#define FLI_SIG_WD_REG (FLI_BLK_REG_ADDR + 0x018)
429
430/**
431 * RO register
432 * 31:16 -- Vendor Id
433 * 15:0 -- Device Id
434 */
435#define FLI_DEV_VENDOR_REG (FLI_BLK_REG_ADDR + 0x01C)
436#define FLI_ERR_STATUS_REG (FLI_BLK_REG_ADDR + 0x020)
437
438/**
439 * RAD (RxAdm) Block Register Address Offset from BAR0
440 * RAD0 Range : 0x20000 - 0x203FF
441 * RAD1 Range : 0x20400 - 0x207FF
442 */
443#define RAD0_BLK_REG_ADDR 0x00020000
444#define RAD1_BLK_REG_ADDR 0x00020400
445
446/* RAD0 Registers */
447#define RAD0_CTL_REG (RAD0_BLK_REG_ADDR + 0x000)
448#define RAD0_PE_PARM_REG (RAD0_BLK_REG_ADDR + 0x004)
449#define RAD0_BCN_REG (RAD0_BLK_REG_ADDR + 0x008)
450
451/* Default function ID register */
452#define RAD0_DEFAULT_REG (RAD0_BLK_REG_ADDR + 0x00C)
453
454/* Default promiscuous ID register */
455#define RAD0_PROMISC_REG (RAD0_BLK_REG_ADDR + 0x010)
456
457#define RAD0_BCNQ_REG (RAD0_BLK_REG_ADDR + 0x014)
458
459/*
460 * This register selects 1 of 8 PM Q's using
461 * VLAN pri, for non-BCN packets without a VLAN tag
462 */
463#define RAD0_DEFAULTQ_REG (RAD0_BLK_REG_ADDR + 0x018)
464
465#define RAD0_ERR_STS (RAD0_BLK_REG_ADDR + 0x01C)
466#define RAD0_SET_ERR_STS (RAD0_BLK_REG_ADDR + 0x020)
467#define RAD0_ERR_INT_EN (RAD0_BLK_REG_ADDR + 0x024)
468#define RAD0_FIRST_ERR (RAD0_BLK_REG_ADDR + 0x028)
469#define RAD0_FORCE_ERR (RAD0_BLK_REG_ADDR + 0x02C)
470
471#define RAD0_IF_RCVD (RAD0_BLK_REG_ADDR + 0x030)
472#define RAD0_IF_RCVD_OCTETS_HIGH (RAD0_BLK_REG_ADDR + 0x034)
473#define RAD0_IF_RCVD_OCTETS_LOW (RAD0_BLK_REG_ADDR + 0x038)
474#define RAD0_IF_RCVD_VLAN (RAD0_BLK_REG_ADDR + 0x03C)
475#define RAD0_IF_RCVD_UCAST (RAD0_BLK_REG_ADDR + 0x040)
476#define RAD0_IF_RCVD_UCAST_OCTETS_HIGH (RAD0_BLK_REG_ADDR + 0x044)
477#define RAD0_IF_RCVD_UCAST_OCTETS_LOW (RAD0_BLK_REG_ADDR + 0x048)
478#define RAD0_IF_RCVD_UCAST_VLAN (RAD0_BLK_REG_ADDR + 0x04C)
479#define RAD0_IF_RCVD_MCAST (RAD0_BLK_REG_ADDR + 0x050)
480#define RAD0_IF_RCVD_MCAST_OCTETS_HIGH (RAD0_BLK_REG_ADDR + 0x054)
481#define RAD0_IF_RCVD_MCAST_OCTETS_LOW (RAD0_BLK_REG_ADDR + 0x058)
482#define RAD0_IF_RCVD_MCAST_VLAN (RAD0_BLK_REG_ADDR + 0x05C)
483#define RAD0_IF_RCVD_BCAST (RAD0_BLK_REG_ADDR + 0x060)
484#define RAD0_IF_RCVD_BCAST_OCTETS_HIGH (RAD0_BLK_REG_ADDR + 0x064)
485#define RAD0_IF_RCVD_BCAST_OCTETS_LOW (RAD0_BLK_REG_ADDR + 0x068)
486#define RAD0_IF_RCVD_BCAST_VLAN (RAD0_BLK_REG_ADDR + 0x06C)
487#define RAD0_DROPPED_FRAMES (RAD0_BLK_REG_ADDR + 0x070)
488
489#define RAD0_MAC_MAN_1H (RAD0_BLK_REG_ADDR + 0x080)
490#define RAD0_MAC_MAN_1L (RAD0_BLK_REG_ADDR + 0x084)
491#define RAD0_MAC_MAN_2H (RAD0_BLK_REG_ADDR + 0x088)
492#define RAD0_MAC_MAN_2L (RAD0_BLK_REG_ADDR + 0x08C)
493#define RAD0_MAC_MAN_3H (RAD0_BLK_REG_ADDR + 0x090)
494#define RAD0_MAC_MAN_3L (RAD0_BLK_REG_ADDR + 0x094)
495#define RAD0_MAC_MAN_4H (RAD0_BLK_REG_ADDR + 0x098)
496#define RAD0_MAC_MAN_4L (RAD0_BLK_REG_ADDR + 0x09C)
497
498#define RAD0_LAST4_IP (RAD0_BLK_REG_ADDR + 0x100)
499
500/* RAD1 Registers */
501#define RAD1_CTL_REG (RAD1_BLK_REG_ADDR + 0x000)
502#define RAD1_PE_PARM_REG (RAD1_BLK_REG_ADDR + 0x004)
503#define RAD1_BCN_REG (RAD1_BLK_REG_ADDR + 0x008)
504
505/* Default function ID register */
506#define RAD1_DEFAULT_REG (RAD1_BLK_REG_ADDR + 0x00C)
507
508/* Promiscuous function ID register */
509#define RAD1_PROMISC_REG (RAD1_BLK_REG_ADDR + 0x010)
510
511#define RAD1_BCNQ_REG (RAD1_BLK_REG_ADDR + 0x014)
512
513/*
514 * This register selects 1 of 8 PM Q's using
515 * VLAN pri, for non-BCN packets without a VLAN tag
516 */
517#define RAD1_DEFAULTQ_REG (RAD1_BLK_REG_ADDR + 0x018)
518
519#define RAD1_ERR_STS (RAD1_BLK_REG_ADDR + 0x01C)
520#define RAD1_SET_ERR_STS (RAD1_BLK_REG_ADDR + 0x020)
521#define RAD1_ERR_INT_EN (RAD1_BLK_REG_ADDR + 0x024)
522
523/**
524 * TXA Block Register Address Offset from BAR0
525 * TXA0 Range : 0x21000 - 0x213FF
526 * TXA1 Range : 0x21400 - 0x217FF
527 */
528#define TXA0_BLK_REG_ADDR 0x00021000
529#define TXA1_BLK_REG_ADDR 0x00021400
530
531/* TXA Registers */
532#define TXA0_CTRL_REG (TXA0_BLK_REG_ADDR + 0x000)
533#define TXA1_CTRL_REG (TXA1_BLK_REG_ADDR + 0x000)
534
535/**
536 * TSO Sequence # Registers (RO)
537 * Total 8 (for 8 queues)
538 * Holds the last seq.# for TSO frames
539 * See catapult_spec.pdf for more details
540 */
541#define TXA0_TSO_TCP_SEQ_REG(_num) \
542 (TXA0_BLK_REG_ADDR + 0x020 + ((_num) << 2))
543
544#define TXA1_TSO_TCP_SEQ_REG(_num) \
545 (TXA1_BLK_REG_ADDR + 0x020 + ((_num) << 2))
546
547/**
548 * TSO IP ID # Registers (RO)
549 * Total 8 (for 8 queues)
550 * Holds the last IP ID for TSO frames
551 * See catapult_spec.pdf for more details
552 */
553#define TXA0_TSO_IP_INFO_REG(_num) \
554 (TXA0_BLK_REG_ADDR + 0x040 + ((_num) << 2))
555
556#define TXA1_TSO_IP_INFO_REG(_num) \
557 (TXA1_BLK_REG_ADDR + 0x040 + ((_num) << 2))
558
559/**
560 * RXA Block Register Address Offset from BAR0
561 * RXA0 Range : 0x21800 - 0x21BFF
562 * RXA1 Range : 0x21C00 - 0x21FFF
563 */
564#define RXA0_BLK_REG_ADDR 0x00021800
565#define RXA1_BLK_REG_ADDR 0x00021C00
566
567/* RXA Registers */
568#define RXA0_CTL_REG (RXA0_BLK_REG_ADDR + 0x040)
569#define RXA1_CTL_REG (RXA1_BLK_REG_ADDR + 0x040)
570
571/**
572 * PPLB Block Register Address Offset from BAR0
573 * PPLB0 Range : 0x22000 - 0x223FF
574 * PPLB1 Range : 0x22400 - 0x227FF
575 */
576#define PLB0_BLK_REG_ADDR 0x00022000
577#define PLB1_BLK_REG_ADDR 0x00022400
578
579/**
580 * PLB Registers
581 * Holds RL timer used time stamps in RLT tagged frames
582 */
583#define PLB0_ECM_TIMER_REG (PLB0_BLK_REG_ADDR + 0x05C)
584#define PLB1_ECM_TIMER_REG (PLB1_BLK_REG_ADDR + 0x05C)
585
586/* Controls the rate-limiter on each of the priority class */
587#define PLB0_RL_CTL (PLB0_BLK_REG_ADDR + 0x060)
588#define PLB1_RL_CTL (PLB1_BLK_REG_ADDR + 0x060)
589
590/**
591 * Max byte register, total 8, 0-7
592 * see catapult_spec.pdf for details
593 */
594#define PLB0_RL_MAX_BC(_num) \
595 (PLB0_BLK_REG_ADDR + 0x064 + ((_num) << 2))
596#define PLB1_RL_MAX_BC(_num) \
597 (PLB1_BLK_REG_ADDR + 0x064 + ((_num) << 2))
598
599/**
600 * RL Time Unit Register for priority 0-7
601 * 4 bits per priority
602 * (2^rl_unit)*1us is the actual time period
603 */
604#define PLB0_RL_TU_PRIO (PLB0_BLK_REG_ADDR + 0x084)
605#define PLB1_RL_TU_PRIO (PLB1_BLK_REG_ADDR + 0x084)
606
607/**
608 * RL byte count register,
609 * bytes transmitted in (rl_unit*1)us time period
610 * 1 per priority, 8 in all, 0-7.
611 */
612#define PLB0_RL_BYTE_CNT(_num) \
613 (PLB0_BLK_REG_ADDR + 0x088 + ((_num) << 2))
614#define PLB1_RL_BYTE_CNT(_num) \
615 (PLB1_BLK_REG_ADDR + 0x088 + ((_num) << 2))
616
617/**
618 * RL Min factor register
619 * 2 bits per priority,
620 * 4 factors possible: 1, 0.5, 0.25, 0
621 * 2'b00 - 0; 2'b01 - 0.25; 2'b10 - 0.5; 2'b11 - 1
622 */
623#define PLB0_RL_MIN_REG (PLB0_BLK_REG_ADDR + 0x0A8)
624#define PLB1_RL_MIN_REG (PLB1_BLK_REG_ADDR + 0x0A8)
625
626/**
627 * RL Max factor register
628 * 2 bits per priority,
629 * 4 factors possible: 1, 0.5, 0.25, 0
630 * 2'b00 - 0; 2'b01 - 0.25; 2'b10 - 0.5; 2'b11 - 1
631 */
632#define PLB0_RL_MAX_REG (PLB0_BLK_REG_ADDR + 0x0AC)
633#define PLB1_RL_MAX_REG (PLB1_BLK_REG_ADDR + 0x0AC)
634
635/* MAC SERDES Address Paging register */
636#define PLB0_EMS_ADD_REG (PLB0_BLK_REG_ADDR + 0xD0)
637#define PLB1_EMS_ADD_REG (PLB1_BLK_REG_ADDR + 0xD0)
638
639/* LL EMS Registers */
640#define LL_EMS0_BLK_REG_ADDR 0x00026800
641#define LL_EMS1_BLK_REG_ADDR 0x00026C00
642
643/**
644 * BPC Block Register Address Offset from BAR0
645 * BPC0 Range : 0x23000 - 0x233FF
646 * BPC1 Range : 0x23400 - 0x237FF
647 */
648#define BPC0_BLK_REG_ADDR 0x00023000
649#define BPC1_BLK_REG_ADDR 0x00023400
650
651/**
652 * PMM Block Register Address Offset from BAR0
653 * PMM0 Range : 0x23800 - 0x23BFF
654 * PMM1 Range : 0x23C00 - 0x23FFF
655 */
656#define PMM0_BLK_REG_ADDR 0x00023800
657#define PMM1_BLK_REG_ADDR 0x00023C00
658
659/**
660 * HQM Block Register Address Offset from BAR0
661 * HQM0 Range : 0x24000 - 0x243FF
662 * HQM1 Range : 0x24400 - 0x247FF
663 */
664#define HQM0_BLK_REG_ADDR 0x00024000
665#define HQM1_BLK_REG_ADDR 0x00024400
666
667/**
668 * HQM Control Register
669 * Controls some aspects of IB
670 * See catapult_spec.pdf for details
671 */
672#define HQM0_CTL_REG (HQM0_BLK_REG_ADDR + 0x000)
673#define HQM1_CTL_REG (HQM1_BLK_REG_ADDR + 0x000)
674
675/**
676 * HQM Stop Q Semaphore Registers.
677 * Only one Queue resource can be stopped at
678 * any given time. This register controls access
679 * to the single stop Q resource.
680 * See catapult_spec.pdf for details
681 */
682#define HQM0_RXQ_STOP_SEM (HQM0_BLK_REG_ADDR + 0x028)
683#define HQM0_TXQ_STOP_SEM (HQM0_BLK_REG_ADDR + 0x02C)
684#define HQM1_RXQ_STOP_SEM (HQM1_BLK_REG_ADDR + 0x028)
685#define HQM1_TXQ_STOP_SEM (HQM1_BLK_REG_ADDR + 0x02C)
686
687/**
688 * LUT Block Register Address Offset from BAR0
689 * LUT0 Range : 0x25800 - 0x25BFF
690 * LUT1 Range : 0x25C00 - 0x25FFF
691 */
692#define LUT0_BLK_REG_ADDR 0x00025800
693#define LUT1_BLK_REG_ADDR 0x00025C00
694
695/**
696 * LUT Registers
697 * See catapult_spec.pdf for details
698 */
699#define LUT0_ERR_STS (LUT0_BLK_REG_ADDR + 0x000)
700#define LUT1_ERR_STS (LUT1_BLK_REG_ADDR + 0x000)
701#define LUT0_SET_ERR_STS (LUT0_BLK_REG_ADDR + 0x004)
702#define LUT1_SET_ERR_STS (LUT1_BLK_REG_ADDR + 0x004)
703
704/**
705 * TRC (Debug/Trace) Register Offset from BAR0
706 * Range : 0x26000 -- 0x263FFF
707 */
708#define TRC_BLK_REG_ADDR 0x00026000
709
710/**
711 * TRC Registers
712 * See catapult_spec.pdf for details of each
713 */
714#define TRC_CTL_REG (TRC_BLK_REG_ADDR + 0x000)
715#define TRC_MODS_REG (TRC_BLK_REG_ADDR + 0x004)
716#define TRC_TRGC_REG (TRC_BLK_REG_ADDR + 0x008)
717#define TRC_CNT1_REG (TRC_BLK_REG_ADDR + 0x010)
718#define TRC_CNT2_REG (TRC_BLK_REG_ADDR + 0x014)
719#define TRC_NXTS_REG (TRC_BLK_REG_ADDR + 0x018)
720#define TRC_DIRR_REG (TRC_BLK_REG_ADDR + 0x01C)
721
722/**
723 * TRC Trigger match filters, total 10
724 * Determines the trigger condition
725 */
726#define TRC_TRGM_REG(_num) \
727 (TRC_BLK_REG_ADDR + 0x040 + ((_num) << 2))
728
729/**
730 * TRC Next State filters, total 10
731 * Determines the next state conditions
732 */
733#define TRC_NXTM_REG(_num) \
734 (TRC_BLK_REG_ADDR + 0x080 + ((_num) << 2))
735
736/**
737 * TRC Store Match filters, total 10
738 * Determines the store conditions
739 */
740#define TRC_STRM_REG(_num) \
741 (TRC_BLK_REG_ADDR + 0x0C0 + ((_num) << 2))
742
743/* DOORBELLS ACCESS */
744
745/**
746 * Catapult doorbells
747 * Each doorbell-queue set has
748 * 1 RxQ, 1 TxQ, 2 IBs in that order
749 * Size of each entry in 32 bytes, even though only 1 word
750 * is used. For Non-VM case each doorbell-q set is
751 * separated by 128 bytes, for VM case it is separated
752 * by 4K bytes
753 * Non VM case Range : 0x38000 - 0x39FFF
754 * VM case Range : 0x100000 - 0x11FFFF
755 * The range applies to both HQMs
756 */
757#define HQM_DOORBELL_BLK_BASE_ADDR 0x00038000
758#define HQM_DOORBELL_VM_BLK_BASE_ADDR 0x00100000
759
760/* MEMORY ACCESS */
761
762/**
763 * Catapult H/W Block Memory Access Address
764 * To the host a memory space of 32K (page) is visible
765 * at a time. The address range is from 0x08000 to 0x0FFFF
766 */
767#define HW_BLK_HOST_MEM_ADDR 0x08000
768
769/**
770 * Catapult LUT Memory Access Page Numbers
771 * Range : LUT0 0xa0-0xa1
772 * LUT1 0xa2-0xa3
773 */
774#define LUT0_MEM_BLK_BASE_PG_NUM 0x000000A0
775#define LUT1_MEM_BLK_BASE_PG_NUM 0x000000A2
776
777/**
778 * Catapult RxFn Database Memory Block Base Offset
779 *
780 * The Rx function database exists in LUT block.
781 * In PCIe space this is accessible as a 256x32
782 * bit block. Each entry in this database is 4
783 * (4 byte) words. Max. entries is 64.
784 * Address of an entry corresponding to a function
785 * = base_addr + (function_no. * 16)
786 */
787#define RX_FNDB_RAM_BASE_OFFSET 0x0000B400
788
789/**
790 * Catapult TxFn Database Memory Block Base Offset Address
791 *
792 * The Tx function database exists in LUT block.
793 * In PCIe space this is accessible as a 64x32
794 * bit block. Each entry in this database is 1
795 * (4 byte) word. Max. entries is 64.
796 * Address of an entry corresponding to a function
797 * = base_addr + (function_no. * 4)
798 */
799#define TX_FNDB_RAM_BASE_OFFSET 0x0000B800
800
801/**
802 * Catapult Unicast CAM Base Offset Address
803 *
804 * Exists in LUT memory space.
805 * Shared by both the LL & FCoE driver.
806 * Size is 256x48 bits; mapped to PCIe space
807 * 512x32 bit blocks. For each address, bits
808 * are written in the order : [47:32] and then
809 * [31:0].
810 */
811#define UCAST_CAM_BASE_OFFSET 0x0000A800
812
813/**
814 * Catapult Unicast RAM Base Offset Address
815 *
816 * Exists in LUT memory space.
817 * Shared by both the LL & FCoE driver.
818 * Size is 256x9 bits.
819 */
820#define UCAST_RAM_BASE_OFFSET 0x0000B000
821
822/**
823 * Catapult Mulicast CAM Base Offset Address
824 *
825 * Exists in LUT memory space.
826 * Shared by both the LL & FCoE driver.
827 * Size is 256x48 bits; mapped to PCIe space
828 * 512x32 bit blocks. For each address, bits
829 * are written in the order : [47:32] and then
830 * [31:0].
831 */
832#define MCAST_CAM_BASE_OFFSET 0x0000A000
833
834/**
835 * Catapult VLAN RAM Base Offset Address
836 *
837 * Exists in LUT memory space.
838 * Size is 4096x66 bits; mapped to PCIe space as
839 * 8192x32 bit blocks.
840 * All the 4K entries are within the address range
841 * 0x0000 to 0x8000, so in the first LUT page.
842 */
843#define VLAN_RAM_BASE_OFFSET 0x00000000
844
845/**
846 * Catapult Tx Stats RAM Base Offset Address
847 *
848 * Exists in LUT memory space.
849 * Size is 1024x33 bits;
850 * Each Tx function has 64 bytes of space
851 */
852#define TX_STATS_RAM_BASE_OFFSET 0x00009000
853
854/**
855 * Catapult Rx Stats RAM Base Offset Address
856 *
857 * Exists in LUT memory space.
858 * Size is 1024x33 bits;
859 * Each Rx function has 64 bytes of space
860 */
861#define RX_STATS_RAM_BASE_OFFSET 0x00008000
862
863/* Catapult RXA Memory Access Page Numbers */
864#define RXA0_MEM_BLK_BASE_PG_NUM 0x0000008C
865#define RXA1_MEM_BLK_BASE_PG_NUM 0x0000008D
866
867/**
868 * Catapult Multicast Vector Table Base Offset Address
869 *
870 * Exists in RxA memory space.
871 * Organized as 512x65 bit block.
872 * However for each entry 16 bytes allocated (power of 2)
873 * Total size 512*16 bytes.
874 * There are two logical divisions, 256 entries each :
875 * a) Entries 0x00 to 0xff (256) -- Approx. MVT
876 * Offset 0x000 to 0xFFF
877 * b) Entries 0x100 to 0x1ff (256) -- Exact MVT
878 * Offsets 0x1000 to 0x1FFF
879 */
880#define MCAST_APPROX_MVT_BASE_OFFSET 0x00000000
881#define MCAST_EXACT_MVT_BASE_OFFSET 0x00001000
882
883/**
884 * Catapult RxQ Translate Table (RIT) Base Offset Address
885 *
886 * Exists in RxA memory space
887 * Total no. of entries 64
888 * Each entry is 1 (4 byte) word.
889 * 31:12 -- Reserved
890 * 11:0 -- Two 6 bit RxQ Ids
891 */
892#define FUNCTION_TO_RXQ_TRANSLATE 0x00002000
893
894/* Catapult RxAdm (RAD) Memory Access Page Numbers */
895#define RAD0_MEM_BLK_BASE_PG_NUM 0x00000086
896#define RAD1_MEM_BLK_BASE_PG_NUM 0x00000087
897
898/**
899 * Catapult RSS Table Base Offset Address
900 *
901 * Exists in RAD memory space.
902 * Each entry is 352 bits, but aligned on
903 * 64 byte (512 bit) boundary. Accessed
904 * 4 byte words, the whole entry can be
905 * broken into 11 word accesses.
906 */
907#define RSS_TABLE_BASE_OFFSET 0x00000800
908
909/**
910 * Catapult CPQ Block Page Number
911 * This value is written to the page number registers
912 * to access the memory associated with the mailboxes.
913 */
914#define CPQ_BLK_PG_NUM 0x00000005
915
916/**
917 * Clarification :
918 * LL functions are 2 & 3; can HostFn0/HostFn1
919 * <-> LPU0/LPU1 memories be used ?
920 */
921/**
922 * Catapult HostFn0/HostFn1 to LPU0/LPU1 Mbox memory
923 * Per catapult_spec.pdf, the offset of the mbox
924 * memory is in the register space at an offset of 0x200
925 */
926#define CPQ_BLK_REG_MBOX_ADDR (CPQ_BLK_REG_ADDR + 0x200)
927
928#define HOSTFN_LPU_MBOX (CPQ_BLK_REG_MBOX_ADDR + 0x000)
929
930/* Catapult LPU0/LPU1 to HostFn0/HostFn1 Mbox memory */
931#define LPU_HOSTFN_MBOX (CPQ_BLK_REG_MBOX_ADDR + 0x080)
932
933/**
934 * Catapult HQM Block Page Number
935 * This is written to the page number register for
936 * the appropriate function to access the memory
937 * associated with HQM
938 */
939#define HQM0_BLK_PG_NUM 0x00000096
940#define HQM1_BLK_PG_NUM 0x00000097
941
942/**
943 * Note that TxQ and RxQ entries are interlaced
944 * the HQM memory, i.e RXQ0, TXQ0, RXQ1, TXQ1.. etc.
945 */
946
947#define HQM_RXTX_Q_RAM_BASE_OFFSET 0x00004000
948
949/**
950 * CQ Memory
951 * Exists in HQM Memory space
952 * Each entry is 16 (4 byte) words of which
953 * only 12 words are used for configuration
954 * Total 64 entries per HQM memory space
955 */
956#define HQM_CQ_RAM_BASE_OFFSET 0x00006000
957
958/**
959 * Interrupt Block (IB) Memory
960 * Exists in HQM Memory space
961 * Each entry is 8 (4 byte) words of which
962 * only 5 words are used for configuration
963 * Total 128 entries per HQM memory space
964 */
965#define HQM_IB_RAM_BASE_OFFSET 0x00001000
966
967/**
968 * Index Table (IT) Memory
969 * Exists in HQM Memory space
970 * Each entry is 1 (4 byte) word which
971 * is used for configuration
972 * Total 128 entries per HQM memory space
973 */
974#define HQM_INDX_TBL_RAM_BASE_OFFSET 0x00002000
975
976/**
977 * PSS Block Memory Page Number
978 * This is written to the appropriate page number
979 * register to access the CPU memory.
980 * Also known as the PSS secondary memory (SMEM).
981 * Range : 0x180 to 0x1CF
982 * See catapult_spec.pdf for details
983 */
984#define PSS_BLK_PG_NUM 0x00000180
985
986/**
987 * Offsets of different instances of PSS SMEM
988 * 2.5M of continuous 1T memory space : 2 blocks
989 * of 1M each (32 pages each, page=32KB) and 4 smaller
990 * blocks of 128K each (4 pages each, page=32KB)
991 * PSS_LMEM_INST0 is used for firmware download
992 */
993#define PSS_LMEM_INST0 0x00000000
994#define PSS_LMEM_INST1 0x00100000
995#define PSS_LMEM_INST2 0x00200000
996#define PSS_LMEM_INST3 0x00220000
997#define PSS_LMEM_INST4 0x00240000
998#define PSS_LMEM_INST5 0x00260000
999
1000#define BNA_PCI_REG_CT_ADDRSZ (0x40000)
1001
1002#define BNA_GET_PAGE_NUM(_base_page, _offset) \
1003 ((_base_page) + ((_offset) >> 15))
1004
1005#define BNA_GET_PAGE_OFFSET(_offset) \
1006 ((_offset) & 0x7fff)
1007
1008#define BNA_GET_MEM_BASE_ADDR(_bar0, _base_offset) \
1009 ((_bar0) + HW_BLK_HOST_MEM_ADDR \
1010 + BNA_GET_PAGE_OFFSET((_base_offset)))
1011
1012#define BNA_GET_VLAN_MEM_ENTRY_ADDR(_bar0, _fn_id, _vlan_id)\
1013 (_bar0 + (HW_BLK_HOST_MEM_ADDR) \
1014 + (BNA_GET_PAGE_OFFSET(VLAN_RAM_BASE_OFFSET)) \
1015 + (((_fn_id) & 0x3f) << 9) \
1016 + (((_vlan_id) & 0xfe0) >> 3))
1017
1018/**
1019 *
1020 * Interrupt related bits, flags and macros
1021 *
1022 */
1023
1024#define __LPU02HOST_MBOX0_STATUS_BITS 0x00100000
1025#define __LPU12HOST_MBOX0_STATUS_BITS 0x00200000
1026#define __LPU02HOST_MBOX1_STATUS_BITS 0x00400000
1027#define __LPU12HOST_MBOX1_STATUS_BITS 0x00800000
1028
1029#define __LPU02HOST_MBOX0_MASK_BITS 0x00100000
1030#define __LPU12HOST_MBOX0_MASK_BITS 0x00200000
1031#define __LPU02HOST_MBOX1_MASK_BITS 0x00400000
1032#define __LPU12HOST_MBOX1_MASK_BITS 0x00800000
1033
1034#define __LPU2HOST_MBOX_MASK_BITS \
1035 (__LPU02HOST_MBOX0_MASK_BITS | __LPU02HOST_MBOX1_MASK_BITS | \
1036 __LPU12HOST_MBOX0_MASK_BITS | __LPU12HOST_MBOX1_MASK_BITS)
1037
1038#define __LPU2HOST_IB_STATUS_BITS 0x0000ffff
1039
1040#define BNA_IS_LPU0_MBOX_INTR(_intr_status) \
1041 ((_intr_status) & (__LPU02HOST_MBOX0_STATUS_BITS | \
1042 __LPU02HOST_MBOX1_STATUS_BITS))
1043
1044#define BNA_IS_LPU1_MBOX_INTR(_intr_status) \
1045 ((_intr_status) & (__LPU12HOST_MBOX0_STATUS_BITS | \
1046 __LPU12HOST_MBOX1_STATUS_BITS))
1047
1048#define BNA_IS_MBOX_INTR(_intr_status) \
1049 ((_intr_status) & \
1050 (__LPU02HOST_MBOX0_STATUS_BITS | \
1051 __LPU02HOST_MBOX1_STATUS_BITS | \
1052 __LPU12HOST_MBOX0_STATUS_BITS | \
1053 __LPU12HOST_MBOX1_STATUS_BITS))
1054
1055#define __EMC_ERROR_STATUS_BITS 0x00010000
1056#define __LPU0_ERROR_STATUS_BITS 0x00020000
1057#define __LPU1_ERROR_STATUS_BITS 0x00040000
1058#define __PSS_ERROR_STATUS_BITS 0x00080000
1059
1060#define __HALT_STATUS_BITS 0x01000000
1061
1062#define __EMC_ERROR_MASK_BITS 0x00010000
1063#define __LPU0_ERROR_MASK_BITS 0x00020000
1064#define __LPU1_ERROR_MASK_BITS 0x00040000
1065#define __PSS_ERROR_MASK_BITS 0x00080000
1066
1067#define __HALT_MASK_BITS 0x01000000
1068
1069#define __ERROR_MASK_BITS \
1070 (__EMC_ERROR_MASK_BITS | __LPU0_ERROR_MASK_BITS | \
1071 __LPU1_ERROR_MASK_BITS | __PSS_ERROR_MASK_BITS | \
1072 __HALT_MASK_BITS)
1073
1074#define BNA_IS_ERR_INTR(_intr_status) \
1075 ((_intr_status) & \
1076 (__EMC_ERROR_STATUS_BITS | \
1077 __LPU0_ERROR_STATUS_BITS | \
1078 __LPU1_ERROR_STATUS_BITS | \
1079 __PSS_ERROR_STATUS_BITS | \
1080 __HALT_STATUS_BITS))
1081
1082#define BNA_IS_MBOX_ERR_INTR(_intr_status) \
1083 (BNA_IS_MBOX_INTR((_intr_status)) | \
1084 BNA_IS_ERR_INTR((_intr_status)))
1085
1086#define BNA_IS_INTX_DATA_INTR(_intr_status) \
1087 ((_intr_status) & __LPU2HOST_IB_STATUS_BITS)
1088
1089#define BNA_INTR_STATUS_MBOX_CLR(_intr_status) \
1090do { \
1091 (_intr_status) &= ~(__LPU02HOST_MBOX0_STATUS_BITS | \
1092 __LPU02HOST_MBOX1_STATUS_BITS | \
1093 __LPU12HOST_MBOX0_STATUS_BITS | \
1094 __LPU12HOST_MBOX1_STATUS_BITS); \
1095} while (0)
1096
1097#define BNA_INTR_STATUS_ERR_CLR(_intr_status) \
1098do { \
1099 (_intr_status) &= ~(__EMC_ERROR_STATUS_BITS | \
1100 __LPU0_ERROR_STATUS_BITS | \
1101 __LPU1_ERROR_STATUS_BITS | \
1102 __PSS_ERROR_STATUS_BITS | \
1103 __HALT_STATUS_BITS); \
1104} while (0)
1105
1106#define bna_intx_disable(_bna, _cur_mask) \
1107{ \
1108 (_cur_mask) = readl((_bna)->regs.fn_int_mask);\
1109 writel(0xffffffff, (_bna)->regs.fn_int_mask);\
1110}
1111
1112#define bna_intx_enable(bna, new_mask) \
1113 writel((new_mask), (bna)->regs.fn_int_mask)
1114
1115#define bna_mbox_intr_disable(bna) \
1116 writel((readl((bna)->regs.fn_int_mask) | \
1117 (__LPU2HOST_MBOX_MASK_BITS | __ERROR_MASK_BITS)), \
1118 (bna)->regs.fn_int_mask)
1119
1120#define bna_mbox_intr_enable(bna) \
1121 writel((readl((bna)->regs.fn_int_mask) & \
1122 ~(__LPU2HOST_MBOX_MASK_BITS | __ERROR_MASK_BITS)), \
1123 (bna)->regs.fn_int_mask)
1124
1125#define bna_intr_status_get(_bna, _status) \
1126{ \
1127 (_status) = readl((_bna)->regs.fn_int_status); \
1128 if ((_status)) { \
1129 writel((_status) & ~(__LPU02HOST_MBOX0_STATUS_BITS |\
1130 __LPU02HOST_MBOX1_STATUS_BITS |\
1131 __LPU12HOST_MBOX0_STATUS_BITS |\
1132 __LPU12HOST_MBOX1_STATUS_BITS), \
1133 (_bna)->regs.fn_int_status);\
1134 } \
1135}
1136
1137#define bna_intr_status_get_no_clr(_bna, _status) \
1138 (_status) = readl((_bna)->regs.fn_int_status)
1139
1140#define bna_intr_mask_get(bna, mask) \
1141 (*mask) = readl((bna)->regs.fn_int_mask)
1142
1143#define bna_intr_ack(bna, intr_bmap) \
1144 writel((intr_bmap), (bna)->regs.fn_int_status)
1145
1146#define bna_ib_intx_disable(bna, ib_id) \
1147 writel(readl((bna)->regs.fn_int_mask) | \
1148 (1 << (ib_id)), \
1149 (bna)->regs.fn_int_mask)
1150
1151#define bna_ib_intx_enable(bna, ib_id) \
1152 writel(readl((bna)->regs.fn_int_mask) & \
1153 ~(1 << (ib_id)), \
1154 (bna)->regs.fn_int_mask)
1155
1156#define bna_mbox_msix_idx_set(_device) \
1157do {\
1158 writel(((_device)->vector & 0x000001FF), \
1159 (_device)->bna->pcidev.pci_bar_kva + \
1160 reg_offset[(_device)->bna->pcidev.pci_func].msix_idx);\
1161} while (0)
1162
1163/**
1164 *
1165 * TxQ, RxQ, CQ related bits, offsets, macros
1166 *
1167 */
1168
1169#define BNA_Q_IDLE_STATE 0x00008001
1170
1171#define BNA_GET_DOORBELL_BASE_ADDR(_bar0) \
1172 ((_bar0) + HQM_DOORBELL_BLK_BASE_ADDR)
1173
1174#define BNA_GET_DOORBELL_ENTRY_OFFSET(_entry) \
1175 ((HQM_DOORBELL_BLK_BASE_ADDR) \
1176 + (_entry << 7))
1177
1178#define BNA_DOORBELL_IB_INT_ACK(_timeout, _events) \
1179 (0x80000000 | ((_timeout) << 16) | (_events))
1180
1181#define BNA_DOORBELL_IB_INT_DISABLE (0x40000000)
1182
1183/* TxQ Entry Opcodes */
1184#define BNA_TXQ_WI_SEND (0x402) /* Single Frame Transmission */
1185#define BNA_TXQ_WI_SEND_LSO (0x403) /* Multi-Frame Transmission */
1186#define BNA_TXQ_WI_EXTENSION (0x104) /* Extension WI */
1187
1188/* TxQ Entry Control Flags */
1189#define BNA_TXQ_WI_CF_FCOE_CRC (1 << 8)
1190#define BNA_TXQ_WI_CF_IPID_MODE (1 << 5)
1191#define BNA_TXQ_WI_CF_INS_PRIO (1 << 4)
1192#define BNA_TXQ_WI_CF_INS_VLAN (1 << 3)
1193#define BNA_TXQ_WI_CF_UDP_CKSUM (1 << 2)
1194#define BNA_TXQ_WI_CF_TCP_CKSUM (1 << 1)
1195#define BNA_TXQ_WI_CF_IP_CKSUM (1 << 0)
1196
1197#define BNA_TXQ_WI_L4_HDR_N_OFFSET(_hdr_size, _offset) \
1198 (((_hdr_size) << 10) | ((_offset) & 0x3FF))
1199
1200/*
1201 * Completion Q defines
1202 */
1203/* CQ Entry Flags */
1204#define BNA_CQ_EF_MAC_ERROR (1 << 0)
1205#define BNA_CQ_EF_FCS_ERROR (1 << 1)
1206#define BNA_CQ_EF_TOO_LONG (1 << 2)
1207#define BNA_CQ_EF_FC_CRC_OK (1 << 3)
1208
1209#define BNA_CQ_EF_RSVD1 (1 << 4)
1210#define BNA_CQ_EF_L4_CKSUM_OK (1 << 5)
1211#define BNA_CQ_EF_L3_CKSUM_OK (1 << 6)
1212#define BNA_CQ_EF_HDS_HEADER (1 << 7)
1213
1214#define BNA_CQ_EF_UDP (1 << 8)
1215#define BNA_CQ_EF_TCP (1 << 9)
1216#define BNA_CQ_EF_IP_OPTIONS (1 << 10)
1217#define BNA_CQ_EF_IPV6 (1 << 11)
1218
1219#define BNA_CQ_EF_IPV4 (1 << 12)
1220#define BNA_CQ_EF_VLAN (1 << 13)
1221#define BNA_CQ_EF_RSS (1 << 14)
1222#define BNA_CQ_EF_RSVD2 (1 << 15)
1223
1224#define BNA_CQ_EF_MCAST_MATCH (1 << 16)
1225#define BNA_CQ_EF_MCAST (1 << 17)
1226#define BNA_CQ_EF_BCAST (1 << 18)
1227#define BNA_CQ_EF_REMOTE (1 << 19)
1228
1229#define BNA_CQ_EF_LOCAL (1 << 20)
1230
1231/**
1232 *
1233 * Data structures
1234 *
1235 */
1236
1237enum txf_flags {
1238 BFI_TXF_CF_ENABLE = 1 << 0,
1239 BFI_TXF_CF_VLAN_FILTER = 1 << 8,
1240 BFI_TXF_CF_VLAN_ADMIT = 1 << 9,
1241 BFI_TXF_CF_VLAN_INSERT = 1 << 10,
1242 BFI_TXF_CF_RSVD1 = 1 << 11,
1243 BFI_TXF_CF_MAC_SA_CHECK = 1 << 12,
1244 BFI_TXF_CF_VLAN_WI_BASED = 1 << 13,
1245 BFI_TXF_CF_VSWITCH_MCAST = 1 << 14,
1246 BFI_TXF_CF_VSWITCH_UCAST = 1 << 15,
1247 BFI_TXF_CF_RSVD2 = 0x7F << 1
1248};
1249
1250enum ib_flags {
1251 BFI_IB_CF_MASTER_ENABLE = (1 << 0),
1252 BFI_IB_CF_MSIX_MODE = (1 << 1),
1253 BFI_IB_CF_COALESCING_MODE = (1 << 2),
1254 BFI_IB_CF_INTER_PKT_ENABLE = (1 << 3),
1255 BFI_IB_CF_INT_ENABLE = (1 << 4),
1256 BFI_IB_CF_INTER_PKT_DMA = (1 << 5),
1257 BFI_IB_CF_ACK_PENDING = (1 << 6),
1258 BFI_IB_CF_RESERVED1 = (1 << 7)
1259};
1260
1261enum rss_hash_type {
1262 BFI_RSS_T_V4_TCP = (1 << 11),
1263 BFI_RSS_T_V4_IP = (1 << 10),
1264 BFI_RSS_T_V6_TCP = (1 << 9),
1265 BFI_RSS_T_V6_IP = (1 << 8)
1266};
1267enum hds_header_type {
1268 BNA_HDS_T_V4_TCP = (1 << 11),
1269 BNA_HDS_T_V4_UDP = (1 << 10),
1270 BNA_HDS_T_V6_TCP = (1 << 9),
1271 BNA_HDS_T_V6_UDP = (1 << 8),
1272 BNA_HDS_FORCED = (1 << 7),
1273};
1274enum rxf_flags {
1275 BNA_RXF_CF_SM_LG_RXQ = (1 << 15),
1276 BNA_RXF_CF_DEFAULT_VLAN = (1 << 14),
1277 BNA_RXF_CF_DEFAULT_FUNCTION_ENABLE = (1 << 13),
1278 BNA_RXF_CF_VLAN_STRIP = (1 << 12),
1279 BNA_RXF_CF_RSS_ENABLE = (1 << 8)
1280};
1281struct bna_chip_regs_offset {
1282 u32 page_addr;
1283 u32 fn_int_status;
1284 u32 fn_int_mask;
1285 u32 msix_idx;
1286};
1287
1288struct bna_chip_regs {
1289 void __iomem *page_addr;
1290 void __iomem *fn_int_status;
1291 void __iomem *fn_int_mask;
1292};
1293
1294struct bna_txq_mem {
1295 u32 pg_tbl_addr_lo;
1296 u32 pg_tbl_addr_hi;
1297 u32 cur_q_entry_lo;
1298 u32 cur_q_entry_hi;
1299 u32 reserved1;
1300 u32 reserved2;
1301 u32 pg_cnt_n_prd_ptr; /* 31:16->total page count */
1302 /* 15:0 ->producer pointer (index?) */
1303 u32 entry_n_pg_size; /* 31:16->entry size */
1304 /* 15:0 ->page size */
1305 u32 int_blk_n_cns_ptr; /* 31:24->Int Blk Id; */
1306 /* 23:16->Int Blk Offset */
1307 /* 15:0 ->consumer pointer(index?) */
1308 u32 cns_ptr2_n_q_state; /* 31:16->cons. ptr 2; 15:0-> Q state */
1309 u32 nxt_qid_n_fid_n_pri; /* 17:10->next */
1310 /* QId;9:3->FID;2:0->Priority */
1311 u32 wvc_n_cquota_n_rquota; /* 31:24->WI Vector Count; */
1312 /* 23:12->Cfg Quota; */
1313 /* 11:0 ->Run Quota */
1314 u32 reserved3[4];
1315};
1316
1317struct bna_rxq_mem {
1318 u32 pg_tbl_addr_lo;
1319 u32 pg_tbl_addr_hi;
1320 u32 cur_q_entry_lo;
1321 u32 cur_q_entry_hi;
1322 u32 reserved1;
1323 u32 reserved2;
1324 u32 pg_cnt_n_prd_ptr; /* 31:16->total page count */
1325 /* 15:0 ->producer pointer (index?) */
1326 u32 entry_n_pg_size; /* 31:16->entry size */
1327 /* 15:0 ->page size */
1328 u32 sg_n_cq_n_cns_ptr; /* 31:28->reserved; 27:24->sg count */
1329 /* 23:16->CQ; */
1330 /* 15:0->consumer pointer(index?) */
1331 u32 buf_sz_n_q_state; /* 31:16->buffer size; 15:0-> Q state */
1332 u32 next_qid; /* 17:10->next QId */
1333 u32 reserved3;
1334 u32 reserved4[4];
1335};
1336
1337struct bna_rxtx_q_mem {
1338 struct bna_rxq_mem rxq;
1339 struct bna_txq_mem txq;
1340};
1341
1342struct bna_cq_mem {
1343 u32 pg_tbl_addr_lo;
1344 u32 pg_tbl_addr_hi;
1345 u32 cur_q_entry_lo;
1346 u32 cur_q_entry_hi;
1347
1348 u32 reserved1;
1349 u32 reserved2;
1350 u32 pg_cnt_n_prd_ptr; /* 31:16->total page count */
1351 /* 15:0 ->producer pointer (index?) */
1352 u32 entry_n_pg_size; /* 31:16->entry size */
1353 /* 15:0 ->page size */
1354 u32 int_blk_n_cns_ptr; /* 31:24->Int Blk Id; */
1355 /* 23:16->Int Blk Offset */
1356 /* 15:0 ->consumer pointer(index?) */
1357 u32 q_state; /* 31:16->reserved; 15:0-> Q state */
1358 u32 reserved3[2];
1359 u32 reserved4[4];
1360};
1361
1362struct bna_ib_blk_mem {
1363 u32 host_addr_lo;
1364 u32 host_addr_hi;
1365 u32 clsc_n_ctrl_n_msix; /* 31:24->coalescing; */
1366 /* 23:16->coalescing cfg; */
1367 /* 15:8 ->control; */
1368 /* 7:0 ->msix; */
1369 u32 ipkt_n_ent_n_idxof;
1370 u32 ipkt_cnt_cfg_n_unacked;
1371
1372 u32 reserved[3];
1373};
1374
1375struct bna_idx_tbl_mem {
1376 u32 idx; /* !< 31:16->res;15:0->idx; */
1377};
1378
1379struct bna_doorbell_qset {
1380 u32 rxq[0x20 >> 2];
1381 u32 txq[0x20 >> 2];
1382 u32 ib0[0x20 >> 2];
1383 u32 ib1[0x20 >> 2];
1384};
1385
1386struct bna_rx_fndb_ram {
1387 u32 rss_prop;
1388 u32 size_routing_props;
1389 u32 rit_hds_mcastq;
1390 u32 control_flags;
1391};
1392
1393struct bna_tx_fndb_ram {
1394 u32 vlan_n_ctrl_flags;
1395};
1396
1397/**
1398 * @brief
1399 * Structure which maps to RxFn Indirection Table (RIT)
1400 * Size : 1 word
1401 * See catapult_spec.pdf, RxA for details
1402 */
1403struct bna_rit_mem {
1404 u32 rxq_ids; /* !< 31:12->res;11:0->two 6 bit RxQ Ids */
1405};
1406
1407/**
1408 * @brief
1409 * Structure which maps to RSS Table entry
1410 * Size : 16 words
1411 * See catapult_spec.pdf, RAD for details
1412 */
1413struct bna_rss_mem {
1414 /*
1415 * 31:12-> res
1416 * 11:8 -> protocol type
1417 * 7:0 -> hash index
1418 */
1419 u32 type_n_hash;
1420 u32 hash_key[10]; /* !< 40 byte Toeplitz hash key */
1421 u32 reserved[5];
1422};
1423
1424/* TxQ Vector (a.k.a. Tx-Buffer Descriptor) */
1425struct bna_dma_addr {
1426 u32 msb;
1427 u32 lsb;
1428};
1429
1430struct bna_txq_wi_vector {
1431 u16 reserved;
1432 u16 length; /* Only 14 LSB are valid */
1433 struct bna_dma_addr host_addr; /* Tx-Buf DMA addr */
1434};
1435
1436typedef u16 bna_txq_wi_opcode_t;
1437
1438typedef u16 bna_txq_wi_ctrl_flag_t;
1439
1440/**
1441 * TxQ Entry Structure
1442 *
1443 * BEWARE: Load values into this structure with correct endianess.
1444 */
1445struct bna_txq_entry {
1446 union {
1447 struct {
1448 u8 reserved;
1449 u8 num_vectors; /* number of vectors present */
1450 bna_txq_wi_opcode_t opcode; /* Either */
1451 /* BNA_TXQ_WI_SEND or */
1452 /* BNA_TXQ_WI_SEND_LSO */
1453 bna_txq_wi_ctrl_flag_t flags; /* OR of all the flags */
1454 u16 l4_hdr_size_n_offset;
1455 u16 vlan_tag;
1456 u16 lso_mss; /* Only 14 LSB are valid */
1457 u32 frame_length; /* Only 24 LSB are valid */
1458 } wi;
1459
1460 struct {
1461 u16 reserved;
1462 bna_txq_wi_opcode_t opcode; /* Must be */
1463 /* BNA_TXQ_WI_EXTENSION */
1464 u32 reserved2[3]; /* Place holder for */
1465 /* removed vector (12 bytes) */
1466 } wi_ext;
1467 } hdr;
1468 struct bna_txq_wi_vector vector[4];
1469};
1470#define wi_hdr hdr.wi
1471#define wi_ext_hdr hdr.wi_ext
1472
1473/* RxQ Entry Structure */
1474struct bna_rxq_entry { /* Rx-Buffer */
1475 struct bna_dma_addr host_addr; /* Rx-Buffer DMA address */
1476};
1477
1478typedef u32 bna_cq_e_flag_t;
1479
1480/* CQ Entry Structure */
1481struct bna_cq_entry {
1482 bna_cq_e_flag_t flags;
1483 u16 vlan_tag;
1484 u16 length;
1485 u32 rss_hash;
1486 u8 valid;
1487 u8 reserved1;
1488 u8 reserved2;
1489 u8 rxq_id;
1490};
1491
1492#endif /* __BNA_HW_H__ */
diff --git a/drivers/net/ethernet/brocade/bna/bna_txrx.c b/drivers/net/ethernet/brocade/bna/bna_txrx.c
deleted file mode 100644
index f0983c832447..000000000000
--- a/drivers/net/ethernet/brocade/bna/bna_txrx.c
+++ /dev/null
@@ -1,4185 +0,0 @@
1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18#include "bna.h"
19#include "bfa_cs.h"
20#include "bfi.h"
21
22/**
23 * IB
24 */
25#define bna_ib_find_free_ibidx(_mask, _pos)\
26do {\
27 (_pos) = 0;\
28 while (((_pos) < (BFI_IBIDX_MAX_SEGSIZE)) &&\
29 ((1 << (_pos)) & (_mask)))\
30 (_pos)++;\
31} while (0)
32
33#define bna_ib_count_ibidx(_mask, _count)\
34do {\
35 int pos = 0;\
36 (_count) = 0;\
37 while (pos < (BFI_IBIDX_MAX_SEGSIZE)) {\
38 if ((1 << pos) & (_mask))\
39 (_count) = pos + 1;\
40 pos++;\
41 } \
42} while (0)
43
44#define bna_ib_select_segpool(_count, _q_idx)\
45do {\
46 int i;\
47 (_q_idx) = -1;\
48 for (i = 0; i < BFI_IBIDX_TOTAL_POOLS; i++) {\
49 if ((_count <= ibidx_pool[i].pool_entry_size)) {\
50 (_q_idx) = i;\
51 break;\
52 } \
53 } \
54} while (0)
55
56struct bna_ibidx_pool {
57 int pool_size;
58 int pool_entry_size;
59};
60init_ibidx_pool(ibidx_pool);
61
62static struct bna_intr *
63bna_intr_get(struct bna_ib_mod *ib_mod, enum bna_intr_type intr_type,
64 int vector)
65{
66 struct bna_intr *intr;
67 struct list_head *qe;
68
69 list_for_each(qe, &ib_mod->intr_active_q) {
70 intr = (struct bna_intr *)qe;
71
72 if ((intr->intr_type == intr_type) &&
73 (intr->vector == vector)) {
74 intr->ref_count++;
75 return intr;
76 }
77 }
78
79 if (list_empty(&ib_mod->intr_free_q))
80 return NULL;
81
82 bfa_q_deq(&ib_mod->intr_free_q, &intr);
83 bfa_q_qe_init(&intr->qe);
84
85 intr->ref_count = 1;
86 intr->intr_type = intr_type;
87 intr->vector = vector;
88
89 list_add_tail(&intr->qe, &ib_mod->intr_active_q);
90
91 return intr;
92}
93
94static void
95bna_intr_put(struct bna_ib_mod *ib_mod,
96 struct bna_intr *intr)
97{
98 intr->ref_count--;
99
100 if (intr->ref_count == 0) {
101 intr->ib = NULL;
102 list_del(&intr->qe);
103 bfa_q_qe_init(&intr->qe);
104 list_add_tail(&intr->qe, &ib_mod->intr_free_q);
105 }
106}
107
108void
109bna_ib_mod_init(struct bna_ib_mod *ib_mod, struct bna *bna,
110 struct bna_res_info *res_info)
111{
112 int i;
113 int j;
114 int count;
115 u8 offset;
116 struct bna_doorbell_qset *qset;
117 unsigned long off;
118
119 ib_mod->bna = bna;
120
121 ib_mod->ib = (struct bna_ib *)
122 res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.mdl[0].kva;
123 ib_mod->intr = (struct bna_intr *)
124 res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.mdl[0].kva;
125 ib_mod->idx_seg = (struct bna_ibidx_seg *)
126 res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.mdl[0].kva;
127
128 INIT_LIST_HEAD(&ib_mod->ib_free_q);
129 INIT_LIST_HEAD(&ib_mod->intr_free_q);
130 INIT_LIST_HEAD(&ib_mod->intr_active_q);
131
132 for (i = 0; i < BFI_IBIDX_TOTAL_POOLS; i++)
133 INIT_LIST_HEAD(&ib_mod->ibidx_seg_pool[i]);
134
135 for (i = 0; i < BFI_MAX_IB; i++) {
136 ib_mod->ib[i].ib_id = i;
137
138 ib_mod->ib[i].ib_seg_host_addr_kva =
139 res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].kva;
140 ib_mod->ib[i].ib_seg_host_addr.lsb =
141 res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.lsb;
142 ib_mod->ib[i].ib_seg_host_addr.msb =
143 res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.msb;
144
145 qset = (struct bna_doorbell_qset *)0;
146 off = (unsigned long)(&qset[i >> 1].ib0[(i & 0x1)
147 * (0x20 >> 2)]);
148 ib_mod->ib[i].door_bell.doorbell_addr = off +
149 BNA_GET_DOORBELL_BASE_ADDR(bna->pcidev.pci_bar_kva);
150
151 bfa_q_qe_init(&ib_mod->ib[i].qe);
152 list_add_tail(&ib_mod->ib[i].qe, &ib_mod->ib_free_q);
153
154 bfa_q_qe_init(&ib_mod->intr[i].qe);
155 list_add_tail(&ib_mod->intr[i].qe, &ib_mod->intr_free_q);
156 }
157
158 count = 0;
159 offset = 0;
160 for (i = 0; i < BFI_IBIDX_TOTAL_POOLS; i++) {
161 for (j = 0; j < ibidx_pool[i].pool_size; j++) {
162 bfa_q_qe_init(&ib_mod->idx_seg[count]);
163 ib_mod->idx_seg[count].ib_seg_size =
164 ibidx_pool[i].pool_entry_size;
165 ib_mod->idx_seg[count].ib_idx_tbl_offset = offset;
166 list_add_tail(&ib_mod->idx_seg[count].qe,
167 &ib_mod->ibidx_seg_pool[i]);
168 count++;
169 offset += ibidx_pool[i].pool_entry_size;
170 }
171 }
172}
173
174void
175bna_ib_mod_uninit(struct bna_ib_mod *ib_mod)
176{
177 int i;
178 int j;
179 struct list_head *qe;
180
181 i = 0;
182 list_for_each(qe, &ib_mod->ib_free_q)
183 i++;
184
185 i = 0;
186 list_for_each(qe, &ib_mod->intr_free_q)
187 i++;
188
189 for (i = 0; i < BFI_IBIDX_TOTAL_POOLS; i++) {
190 j = 0;
191 list_for_each(qe, &ib_mod->ibidx_seg_pool[i])
192 j++;
193 }
194
195 ib_mod->bna = NULL;
196}
197
198static struct bna_ib *
199bna_ib_get(struct bna_ib_mod *ib_mod,
200 enum bna_intr_type intr_type,
201 int vector)
202{
203 struct bna_ib *ib;
204 struct bna_intr *intr;
205
206 if (intr_type == BNA_INTR_T_INTX)
207 vector = (1 << vector);
208
209 intr = bna_intr_get(ib_mod, intr_type, vector);
210 if (intr == NULL)
211 return NULL;
212
213 if (intr->ib) {
214 if (intr->ib->ref_count == BFI_IBIDX_MAX_SEGSIZE) {
215 bna_intr_put(ib_mod, intr);
216 return NULL;
217 }
218 intr->ib->ref_count++;
219 return intr->ib;
220 }
221
222 if (list_empty(&ib_mod->ib_free_q)) {
223 bna_intr_put(ib_mod, intr);
224 return NULL;
225 }
226
227 bfa_q_deq(&ib_mod->ib_free_q, &ib);
228 bfa_q_qe_init(&ib->qe);
229
230 ib->ref_count = 1;
231 ib->start_count = 0;
232 ib->idx_mask = 0;
233
234 ib->intr = intr;
235 ib->idx_seg = NULL;
236 intr->ib = ib;
237
238 ib->bna = ib_mod->bna;
239
240 return ib;
241}
242
243static void
244bna_ib_put(struct bna_ib_mod *ib_mod, struct bna_ib *ib)
245{
246 bna_intr_put(ib_mod, ib->intr);
247
248 ib->ref_count--;
249
250 if (ib->ref_count == 0) {
251 ib->intr = NULL;
252 ib->bna = NULL;
253 list_add_tail(&ib->qe, &ib_mod->ib_free_q);
254 }
255}
256
257/* Returns index offset - starting from 0 */
258static int
259bna_ib_reserve_idx(struct bna_ib *ib)
260{
261 struct bna_ib_mod *ib_mod = &ib->bna->ib_mod;
262 struct bna_ibidx_seg *idx_seg;
263 int idx;
264 int num_idx;
265 int q_idx;
266
267 /* Find the first free index position */
268 bna_ib_find_free_ibidx(ib->idx_mask, idx);
269 if (idx == BFI_IBIDX_MAX_SEGSIZE)
270 return -1;
271
272 /*
273 * Calculate the total number of indexes held by this IB,
274 * including the index newly reserved above.
275 */
276 bna_ib_count_ibidx((ib->idx_mask | (1 << idx)), num_idx);
277
278 /* See if there is a free space in the index segment held by this IB */
279 if (ib->idx_seg && (num_idx <= ib->idx_seg->ib_seg_size)) {
280 ib->idx_mask |= (1 << idx);
281 return idx;
282 }
283
284 if (ib->start_count)
285 return -1;
286
287 /* Allocate a new segment */
288 bna_ib_select_segpool(num_idx, q_idx);
289 while (1) {
290 if (q_idx == BFI_IBIDX_TOTAL_POOLS)
291 return -1;
292 if (!list_empty(&ib_mod->ibidx_seg_pool[q_idx]))
293 break;
294 q_idx++;
295 }
296 bfa_q_deq(&ib_mod->ibidx_seg_pool[q_idx], &idx_seg);
297 bfa_q_qe_init(&idx_seg->qe);
298
299 /* Free the old segment */
300 if (ib->idx_seg) {
301 bna_ib_select_segpool(ib->idx_seg->ib_seg_size, q_idx);
302 list_add_tail(&ib->idx_seg->qe, &ib_mod->ibidx_seg_pool[q_idx]);
303 }
304
305 ib->idx_seg = idx_seg;
306
307 ib->idx_mask |= (1 << idx);
308
309 return idx;
310}
311
312static void
313bna_ib_release_idx(struct bna_ib *ib, int idx)
314{
315 struct bna_ib_mod *ib_mod = &ib->bna->ib_mod;
316 struct bna_ibidx_seg *idx_seg;
317 int num_idx;
318 int cur_q_idx;
319 int new_q_idx;
320
321 ib->idx_mask &= ~(1 << idx);
322
323 if (ib->start_count)
324 return;
325
326 bna_ib_count_ibidx(ib->idx_mask, num_idx);
327
328 /*
329 * Free the segment, if there are no more indexes in the segment
330 * held by this IB
331 */
332 if (!num_idx) {
333 bna_ib_select_segpool(ib->idx_seg->ib_seg_size, cur_q_idx);
334 list_add_tail(&ib->idx_seg->qe,
335 &ib_mod->ibidx_seg_pool[cur_q_idx]);
336 ib->idx_seg = NULL;
337 return;
338 }
339
340 /* See if we can move to a smaller segment */
341 bna_ib_select_segpool(num_idx, new_q_idx);
342 bna_ib_select_segpool(ib->idx_seg->ib_seg_size, cur_q_idx);
343 while (new_q_idx < cur_q_idx) {
344 if (!list_empty(&ib_mod->ibidx_seg_pool[new_q_idx]))
345 break;
346 new_q_idx++;
347 }
348 if (new_q_idx < cur_q_idx) {
349 /* Select the new smaller segment */
350 bfa_q_deq(&ib_mod->ibidx_seg_pool[new_q_idx], &idx_seg);
351 bfa_q_qe_init(&idx_seg->qe);
352 /* Free the old segment */
353 list_add_tail(&ib->idx_seg->qe,
354 &ib_mod->ibidx_seg_pool[cur_q_idx]);
355 ib->idx_seg = idx_seg;
356 }
357}
358
359static int
360bna_ib_config(struct bna_ib *ib, struct bna_ib_config *ib_config)
361{
362 if (ib->start_count)
363 return -1;
364
365 ib->ib_config.coalescing_timeo = ib_config->coalescing_timeo;
366 ib->ib_config.interpkt_timeo = ib_config->interpkt_timeo;
367 ib->ib_config.interpkt_count = ib_config->interpkt_count;
368 ib->ib_config.ctrl_flags = ib_config->ctrl_flags;
369
370 ib->ib_config.ctrl_flags |= BFI_IB_CF_MASTER_ENABLE;
371 if (ib->intr->intr_type == BNA_INTR_T_MSIX)
372 ib->ib_config.ctrl_flags |= BFI_IB_CF_MSIX_MODE;
373
374 return 0;
375}
376
377static void
378bna_ib_start(struct bna_ib *ib)
379{
380 struct bna_ib_blk_mem ib_cfg;
381 struct bna_ib_blk_mem *ib_mem;
382 u32 pg_num;
383 u32 intx_mask;
384 int i;
385 void __iomem *base_addr;
386 unsigned long off;
387
388 ib->start_count++;
389
390 if (ib->start_count > 1)
391 return;
392
393 ib_cfg.host_addr_lo = (u32)(ib->ib_seg_host_addr.lsb);
394 ib_cfg.host_addr_hi = (u32)(ib->ib_seg_host_addr.msb);
395
396 ib_cfg.clsc_n_ctrl_n_msix = (((u32)
397 ib->ib_config.coalescing_timeo << 16) |
398 ((u32)ib->ib_config.ctrl_flags << 8) |
399 (ib->intr->vector));
400 ib_cfg.ipkt_n_ent_n_idxof =
401 ((u32)
402 (ib->ib_config.interpkt_timeo & 0xf) << 16) |
403 ((u32)ib->idx_seg->ib_seg_size << 8) |
404 (ib->idx_seg->ib_idx_tbl_offset);
405 ib_cfg.ipkt_cnt_cfg_n_unacked = ((u32)
406 ib->ib_config.interpkt_count << 24);
407
408 pg_num = BNA_GET_PAGE_NUM(HQM0_BLK_PG_NUM + ib->bna->port_num,
409 HQM_IB_RAM_BASE_OFFSET);
410 writel(pg_num, ib->bna->regs.page_addr);
411
412 base_addr = BNA_GET_MEM_BASE_ADDR(ib->bna->pcidev.pci_bar_kva,
413 HQM_IB_RAM_BASE_OFFSET);
414
415 ib_mem = (struct bna_ib_blk_mem *)0;
416 off = (unsigned long)&ib_mem[ib->ib_id].host_addr_lo;
417 writel(htonl(ib_cfg.host_addr_lo), base_addr + off);
418
419 off = (unsigned long)&ib_mem[ib->ib_id].host_addr_hi;
420 writel(htonl(ib_cfg.host_addr_hi), base_addr + off);
421
422 off = (unsigned long)&ib_mem[ib->ib_id].clsc_n_ctrl_n_msix;
423 writel(ib_cfg.clsc_n_ctrl_n_msix, base_addr + off);
424
425 off = (unsigned long)&ib_mem[ib->ib_id].ipkt_n_ent_n_idxof;
426 writel(ib_cfg.ipkt_n_ent_n_idxof, base_addr + off);
427
428 off = (unsigned long)&ib_mem[ib->ib_id].ipkt_cnt_cfg_n_unacked;
429 writel(ib_cfg.ipkt_cnt_cfg_n_unacked, base_addr + off);
430
431 ib->door_bell.doorbell_ack = BNA_DOORBELL_IB_INT_ACK(
432 (u32)ib->ib_config.coalescing_timeo, 0);
433
434 pg_num = BNA_GET_PAGE_NUM(HQM0_BLK_PG_NUM + ib->bna->port_num,
435 HQM_INDX_TBL_RAM_BASE_OFFSET);
436 writel(pg_num, ib->bna->regs.page_addr);
437
438 base_addr = BNA_GET_MEM_BASE_ADDR(ib->bna->pcidev.pci_bar_kva,
439 HQM_INDX_TBL_RAM_BASE_OFFSET);
440 for (i = 0; i < ib->idx_seg->ib_seg_size; i++) {
441 off = (unsigned long)
442 ((ib->idx_seg->ib_idx_tbl_offset + i) * BFI_IBIDX_SIZE);
443 writel(0, base_addr + off);
444 }
445
446 if (ib->intr->intr_type == BNA_INTR_T_INTX) {
447 bna_intx_disable(ib->bna, intx_mask);
448 intx_mask &= ~(ib->intr->vector);
449 bna_intx_enable(ib->bna, intx_mask);
450 }
451}
452
453static void
454bna_ib_stop(struct bna_ib *ib)
455{
456 u32 intx_mask;
457
458 ib->start_count--;
459
460 if (ib->start_count == 0) {
461 writel(BNA_DOORBELL_IB_INT_DISABLE,
462 ib->door_bell.doorbell_addr);
463 if (ib->intr->intr_type == BNA_INTR_T_INTX) {
464 bna_intx_disable(ib->bna, intx_mask);
465 intx_mask |= (ib->intr->vector);
466 bna_intx_enable(ib->bna, intx_mask);
467 }
468 }
469}
470
471static void
472bna_ib_fail(struct bna_ib *ib)
473{
474 ib->start_count = 0;
475}
476
477/**
478 * RXF
479 */
480static void rxf_enable(struct bna_rxf *rxf);
481static void rxf_disable(struct bna_rxf *rxf);
482static void __rxf_config_set(struct bna_rxf *rxf);
483static void __rxf_rit_set(struct bna_rxf *rxf);
484static void __bna_rxf_stat_clr(struct bna_rxf *rxf);
485static int rxf_process_packet_filter(struct bna_rxf *rxf);
486static int rxf_clear_packet_filter(struct bna_rxf *rxf);
487static void rxf_reset_packet_filter(struct bna_rxf *rxf);
488static void rxf_cb_enabled(void *arg, int status);
489static void rxf_cb_disabled(void *arg, int status);
490static void bna_rxf_cb_stats_cleared(void *arg, int status);
491static void __rxf_enable(struct bna_rxf *rxf);
492static void __rxf_disable(struct bna_rxf *rxf);
493
494bfa_fsm_state_decl(bna_rxf, stopped, struct bna_rxf,
495 enum bna_rxf_event);
496bfa_fsm_state_decl(bna_rxf, start_wait, struct bna_rxf,
497 enum bna_rxf_event);
498bfa_fsm_state_decl(bna_rxf, cam_fltr_mod_wait, struct bna_rxf,
499 enum bna_rxf_event);
500bfa_fsm_state_decl(bna_rxf, started, struct bna_rxf,
501 enum bna_rxf_event);
502bfa_fsm_state_decl(bna_rxf, cam_fltr_clr_wait, struct bna_rxf,
503 enum bna_rxf_event);
504bfa_fsm_state_decl(bna_rxf, stop_wait, struct bna_rxf,
505 enum bna_rxf_event);
506bfa_fsm_state_decl(bna_rxf, pause_wait, struct bna_rxf,
507 enum bna_rxf_event);
508bfa_fsm_state_decl(bna_rxf, resume_wait, struct bna_rxf,
509 enum bna_rxf_event);
510bfa_fsm_state_decl(bna_rxf, stat_clr_wait, struct bna_rxf,
511 enum bna_rxf_event);
512
513static struct bfa_sm_table rxf_sm_table[] = {
514 {BFA_SM(bna_rxf_sm_stopped), BNA_RXF_STOPPED},
515 {BFA_SM(bna_rxf_sm_start_wait), BNA_RXF_START_WAIT},
516 {BFA_SM(bna_rxf_sm_cam_fltr_mod_wait), BNA_RXF_CAM_FLTR_MOD_WAIT},
517 {BFA_SM(bna_rxf_sm_started), BNA_RXF_STARTED},
518 {BFA_SM(bna_rxf_sm_cam_fltr_clr_wait), BNA_RXF_CAM_FLTR_CLR_WAIT},
519 {BFA_SM(bna_rxf_sm_stop_wait), BNA_RXF_STOP_WAIT},
520 {BFA_SM(bna_rxf_sm_pause_wait), BNA_RXF_PAUSE_WAIT},
521 {BFA_SM(bna_rxf_sm_resume_wait), BNA_RXF_RESUME_WAIT},
522 {BFA_SM(bna_rxf_sm_stat_clr_wait), BNA_RXF_STAT_CLR_WAIT}
523};
524
525static void
526bna_rxf_sm_stopped_entry(struct bna_rxf *rxf)
527{
528 call_rxf_stop_cbfn(rxf, BNA_CB_SUCCESS);
529}
530
531static void
532bna_rxf_sm_stopped(struct bna_rxf *rxf, enum bna_rxf_event event)
533{
534 switch (event) {
535 case RXF_E_START:
536 bfa_fsm_set_state(rxf, bna_rxf_sm_start_wait);
537 break;
538
539 case RXF_E_STOP:
540 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
541 break;
542
543 case RXF_E_FAIL:
544 /* No-op */
545 break;
546
547 case RXF_E_CAM_FLTR_MOD:
548 call_rxf_cam_fltr_cbfn(rxf, BNA_CB_SUCCESS);
549 break;
550
551 case RXF_E_STARTED:
552 case RXF_E_STOPPED:
553 case RXF_E_CAM_FLTR_RESP:
554 /**
555 * These events are received due to flushing of mbox
556 * when device fails
557 */
558 /* No-op */
559 break;
560
561 case RXF_E_PAUSE:
562 rxf->rxf_oper_state = BNA_RXF_OPER_STATE_PAUSED;
563 call_rxf_pause_cbfn(rxf, BNA_CB_SUCCESS);
564 break;
565
566 case RXF_E_RESUME:
567 rxf->rxf_oper_state = BNA_RXF_OPER_STATE_RUNNING;
568 call_rxf_resume_cbfn(rxf, BNA_CB_SUCCESS);
569 break;
570
571 default:
572 bfa_sm_fault(event);
573 }
574}
575
576static void
577bna_rxf_sm_start_wait_entry(struct bna_rxf *rxf)
578{
579 __rxf_config_set(rxf);
580 __rxf_rit_set(rxf);
581 rxf_enable(rxf);
582}
583
584static void
585bna_rxf_sm_start_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
586{
587 switch (event) {
588 case RXF_E_STOP:
589 /**
590 * STOP is originated from bnad. When this happens,
591 * it can not be waiting for filter update
592 */
593 call_rxf_start_cbfn(rxf, BNA_CB_INTERRUPT);
594 bfa_fsm_set_state(rxf, bna_rxf_sm_stop_wait);
595 break;
596
597 case RXF_E_FAIL:
598 call_rxf_cam_fltr_cbfn(rxf, BNA_CB_SUCCESS);
599 call_rxf_start_cbfn(rxf, BNA_CB_FAIL);
600 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
601 break;
602
603 case RXF_E_CAM_FLTR_MOD:
604 /* No-op */
605 break;
606
607 case RXF_E_STARTED:
608 /**
609 * Force rxf_process_filter() to go through initial
610 * config
611 */
612 if ((rxf->ucast_active_mac != NULL) &&
613 (rxf->ucast_pending_set == 0))
614 rxf->ucast_pending_set = 1;
615
616 if (rxf->rss_status == BNA_STATUS_T_ENABLED)
617 rxf->rxf_flags |= BNA_RXF_FL_RSS_CONFIG_PENDING;
618
619 rxf->rxf_flags |= BNA_RXF_FL_VLAN_CONFIG_PENDING;
620
621 bfa_fsm_set_state(rxf, bna_rxf_sm_cam_fltr_mod_wait);
622 break;
623
624 case RXF_E_PAUSE:
625 case RXF_E_RESUME:
626 rxf->rxf_flags |= BNA_RXF_FL_OPERSTATE_CHANGED;
627 break;
628
629 default:
630 bfa_sm_fault(event);
631 }
632}
633
634static void
635bna_rxf_sm_cam_fltr_mod_wait_entry(struct bna_rxf *rxf)
636{
637 if (!rxf_process_packet_filter(rxf)) {
638 /* No more pending CAM entries to update */
639 bfa_fsm_set_state(rxf, bna_rxf_sm_started);
640 }
641}
642
643static void
644bna_rxf_sm_cam_fltr_mod_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
645{
646 switch (event) {
647 case RXF_E_STOP:
648 /**
649 * STOP is originated from bnad. When this happens,
650 * it can not be waiting for filter update
651 */
652 call_rxf_start_cbfn(rxf, BNA_CB_INTERRUPT);
653 bfa_fsm_set_state(rxf, bna_rxf_sm_cam_fltr_clr_wait);
654 break;
655
656 case RXF_E_FAIL:
657 rxf_reset_packet_filter(rxf);
658 call_rxf_cam_fltr_cbfn(rxf, BNA_CB_SUCCESS);
659 call_rxf_start_cbfn(rxf, BNA_CB_FAIL);
660 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
661 break;
662
663 case RXF_E_CAM_FLTR_MOD:
664 /* No-op */
665 break;
666
667 case RXF_E_CAM_FLTR_RESP:
668 if (!rxf_process_packet_filter(rxf)) {
669 /* No more pending CAM entries to update */
670 call_rxf_cam_fltr_cbfn(rxf, BNA_CB_SUCCESS);
671 bfa_fsm_set_state(rxf, bna_rxf_sm_started);
672 }
673 break;
674
675 case RXF_E_PAUSE:
676 case RXF_E_RESUME:
677 rxf->rxf_flags |= BNA_RXF_FL_OPERSTATE_CHANGED;
678 break;
679
680 default:
681 bfa_sm_fault(event);
682 }
683}
684
685static void
686bna_rxf_sm_started_entry(struct bna_rxf *rxf)
687{
688 call_rxf_start_cbfn(rxf, BNA_CB_SUCCESS);
689
690 if (rxf->rxf_flags & BNA_RXF_FL_OPERSTATE_CHANGED) {
691 if (rxf->rxf_oper_state == BNA_RXF_OPER_STATE_PAUSED)
692 bfa_fsm_send_event(rxf, RXF_E_PAUSE);
693 else
694 bfa_fsm_send_event(rxf, RXF_E_RESUME);
695 }
696
697}
698
699static void
700bna_rxf_sm_started(struct bna_rxf *rxf, enum bna_rxf_event event)
701{
702 switch (event) {
703 case RXF_E_STOP:
704 bfa_fsm_set_state(rxf, bna_rxf_sm_cam_fltr_clr_wait);
705 /* Hack to get FSM start clearing CAM entries */
706 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_RESP);
707 break;
708
709 case RXF_E_FAIL:
710 rxf_reset_packet_filter(rxf);
711 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
712 break;
713
714 case RXF_E_CAM_FLTR_MOD:
715 bfa_fsm_set_state(rxf, bna_rxf_sm_cam_fltr_mod_wait);
716 break;
717
718 case RXF_E_PAUSE:
719 bfa_fsm_set_state(rxf, bna_rxf_sm_pause_wait);
720 break;
721
722 case RXF_E_RESUME:
723 bfa_fsm_set_state(rxf, bna_rxf_sm_resume_wait);
724 break;
725
726 default:
727 bfa_sm_fault(event);
728 }
729}
730
731static void
732bna_rxf_sm_cam_fltr_clr_wait_entry(struct bna_rxf *rxf)
733{
734 /**
735 * Note: Do not add rxf_clear_packet_filter here.
736 * It will overstep mbox when this transition happens:
737 * cam_fltr_mod_wait -> cam_fltr_clr_wait on RXF_E_STOP event
738 */
739}
740
741static void
742bna_rxf_sm_cam_fltr_clr_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
743{
744 switch (event) {
745 case RXF_E_FAIL:
746 /**
747 * FSM was in the process of stopping, initiated by
748 * bnad. When this happens, no one can be waiting for
749 * start or filter update
750 */
751 rxf_reset_packet_filter(rxf);
752 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
753 break;
754
755 case RXF_E_CAM_FLTR_RESP:
756 if (!rxf_clear_packet_filter(rxf)) {
757 /* No more pending CAM entries to clear */
758 bfa_fsm_set_state(rxf, bna_rxf_sm_stop_wait);
759 rxf_disable(rxf);
760 }
761 break;
762
763 default:
764 bfa_sm_fault(event);
765 }
766}
767
768static void
769bna_rxf_sm_stop_wait_entry(struct bna_rxf *rxf)
770{
771 /**
772 * NOTE: Do not add rxf_disable here.
773 * It will overstep mbox when this transition happens:
774 * start_wait -> stop_wait on RXF_E_STOP event
775 */
776}
777
778static void
779bna_rxf_sm_stop_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
780{
781 switch (event) {
782 case RXF_E_FAIL:
783 /**
784 * FSM was in the process of stopping, initiated by
785 * bnad. When this happens, no one can be waiting for
786 * start or filter update
787 */
788 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
789 break;
790
791 case RXF_E_STARTED:
792 /**
793 * This event is received due to abrupt transition from
794 * bna_rxf_sm_start_wait state on receiving
795 * RXF_E_STOP event
796 */
797 rxf_disable(rxf);
798 break;
799
800 case RXF_E_STOPPED:
801 /**
802 * FSM was in the process of stopping, initiated by
803 * bnad. When this happens, no one can be waiting for
804 * start or filter update
805 */
806 bfa_fsm_set_state(rxf, bna_rxf_sm_stat_clr_wait);
807 break;
808
809 case RXF_E_PAUSE:
810 rxf->rxf_oper_state = BNA_RXF_OPER_STATE_PAUSED;
811 break;
812
813 case RXF_E_RESUME:
814 rxf->rxf_oper_state = BNA_RXF_OPER_STATE_RUNNING;
815 break;
816
817 default:
818 bfa_sm_fault(event);
819 }
820}
821
822static void
823bna_rxf_sm_pause_wait_entry(struct bna_rxf *rxf)
824{
825 rxf->rxf_flags &=
826 ~(BNA_RXF_FL_OPERSTATE_CHANGED | BNA_RXF_FL_RXF_ENABLED);
827 __rxf_disable(rxf);
828}
829
830static void
831bna_rxf_sm_pause_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
832{
833 switch (event) {
834 case RXF_E_FAIL:
835 /**
836 * FSM was in the process of disabling rxf, initiated by
837 * bnad.
838 */
839 call_rxf_pause_cbfn(rxf, BNA_CB_FAIL);
840 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
841 break;
842
843 case RXF_E_STOPPED:
844 rxf->rxf_oper_state = BNA_RXF_OPER_STATE_PAUSED;
845 call_rxf_pause_cbfn(rxf, BNA_CB_SUCCESS);
846 bfa_fsm_set_state(rxf, bna_rxf_sm_started);
847 break;
848
849 /*
850 * Since PAUSE/RESUME can only be sent by bnad, we don't expect
851 * any other event during these states
852 */
853 default:
854 bfa_sm_fault(event);
855 }
856}
857
858static void
859bna_rxf_sm_resume_wait_entry(struct bna_rxf *rxf)
860{
861 rxf->rxf_flags &= ~(BNA_RXF_FL_OPERSTATE_CHANGED);
862 rxf->rxf_flags |= BNA_RXF_FL_RXF_ENABLED;
863 __rxf_enable(rxf);
864}
865
866static void
867bna_rxf_sm_resume_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
868{
869 switch (event) {
870 case RXF_E_FAIL:
871 /**
872 * FSM was in the process of disabling rxf, initiated by
873 * bnad.
874 */
875 call_rxf_resume_cbfn(rxf, BNA_CB_FAIL);
876 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
877 break;
878
879 case RXF_E_STARTED:
880 rxf->rxf_oper_state = BNA_RXF_OPER_STATE_RUNNING;
881 call_rxf_resume_cbfn(rxf, BNA_CB_SUCCESS);
882 bfa_fsm_set_state(rxf, bna_rxf_sm_started);
883 break;
884
885 /*
886 * Since PAUSE/RESUME can only be sent by bnad, we don't expect
887 * any other event during these states
888 */
889 default:
890 bfa_sm_fault(event);
891 }
892}
893
894static void
895bna_rxf_sm_stat_clr_wait_entry(struct bna_rxf *rxf)
896{
897 __bna_rxf_stat_clr(rxf);
898}
899
900static void
901bna_rxf_sm_stat_clr_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
902{
903 switch (event) {
904 case RXF_E_FAIL:
905 case RXF_E_STAT_CLEARED:
906 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
907 break;
908
909 default:
910 bfa_sm_fault(event);
911 }
912}
913
914static void
915__rxf_enable(struct bna_rxf *rxf)
916{
917 struct bfi_ll_rxf_multi_req ll_req;
918 u32 bm[2] = {0, 0};
919
920 if (rxf->rxf_id < 32)
921 bm[0] = 1 << rxf->rxf_id;
922 else
923 bm[1] = 1 << (rxf->rxf_id - 32);
924
925 bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_RX_REQ, 0);
926 ll_req.rxf_id_mask[0] = htonl(bm[0]);
927 ll_req.rxf_id_mask[1] = htonl(bm[1]);
928 ll_req.enable = 1;
929
930 bna_mbox_qe_fill(&rxf->mbox_qe, &ll_req, sizeof(ll_req),
931 rxf_cb_enabled, rxf);
932
933 bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe);
934}
935
936static void
937__rxf_disable(struct bna_rxf *rxf)
938{
939 struct bfi_ll_rxf_multi_req ll_req;
940 u32 bm[2] = {0, 0};
941
942 if (rxf->rxf_id < 32)
943 bm[0] = 1 << rxf->rxf_id;
944 else
945 bm[1] = 1 << (rxf->rxf_id - 32);
946
947 bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_RX_REQ, 0);
948 ll_req.rxf_id_mask[0] = htonl(bm[0]);
949 ll_req.rxf_id_mask[1] = htonl(bm[1]);
950 ll_req.enable = 0;
951
952 bna_mbox_qe_fill(&rxf->mbox_qe, &ll_req, sizeof(ll_req),
953 rxf_cb_disabled, rxf);
954
955 bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe);
956}
957
958static void
959__rxf_config_set(struct bna_rxf *rxf)
960{
961 u32 i;
962 struct bna_rss_mem *rss_mem;
963 struct bna_rx_fndb_ram *rx_fndb_ram;
964 struct bna *bna = rxf->rx->bna;
965 void __iomem *base_addr;
966 unsigned long off;
967
968 base_addr = BNA_GET_MEM_BASE_ADDR(bna->pcidev.pci_bar_kva,
969 RSS_TABLE_BASE_OFFSET);
970
971 rss_mem = (struct bna_rss_mem *)0;
972
973 /* Configure RSS if required */
974 if (rxf->ctrl_flags & BNA_RXF_CF_RSS_ENABLE) {
975 /* configure RSS Table */
976 writel(BNA_GET_PAGE_NUM(RAD0_MEM_BLK_BASE_PG_NUM +
977 bna->port_num, RSS_TABLE_BASE_OFFSET),
978 bna->regs.page_addr);
979
980 /* temporarily disable RSS, while hash value is written */
981 off = (unsigned long)&rss_mem[0].type_n_hash;
982 writel(0, base_addr + off);
983
984 for (i = 0; i < BFI_RSS_HASH_KEY_LEN; i++) {
985 off = (unsigned long)
986 &rss_mem[0].hash_key[(BFI_RSS_HASH_KEY_LEN - 1) - i];
987 writel(htonl(rxf->rss_cfg.toeplitz_hash_key[i]),
988 base_addr + off);
989 }
990
991 off = (unsigned long)&rss_mem[0].type_n_hash;
992 writel(rxf->rss_cfg.hash_type | rxf->rss_cfg.hash_mask,
993 base_addr + off);
994 }
995
996 /* Configure RxF */
997 writel(BNA_GET_PAGE_NUM(
998 LUT0_MEM_BLK_BASE_PG_NUM + (bna->port_num * 2),
999 RX_FNDB_RAM_BASE_OFFSET),
1000 bna->regs.page_addr);
1001
1002 base_addr = BNA_GET_MEM_BASE_ADDR(bna->pcidev.pci_bar_kva,
1003 RX_FNDB_RAM_BASE_OFFSET);
1004
1005 rx_fndb_ram = (struct bna_rx_fndb_ram *)0;
1006
1007 /* We always use RSS table 0 */
1008 off = (unsigned long)&rx_fndb_ram[rxf->rxf_id].rss_prop;
1009 writel(rxf->ctrl_flags & BNA_RXF_CF_RSS_ENABLE,
1010 base_addr + off);
1011
1012 /* small large buffer enable/disable */
1013 off = (unsigned long)&rx_fndb_ram[rxf->rxf_id].size_routing_props;
1014 writel((rxf->ctrl_flags & BNA_RXF_CF_SM_LG_RXQ) | 0x80,
1015 base_addr + off);
1016
1017 /* RIT offset, HDS forced offset, multicast RxQ Id */
1018 off = (unsigned long)&rx_fndb_ram[rxf->rxf_id].rit_hds_mcastq;
1019 writel((rxf->rit_segment->rit_offset << 16) |
1020 (rxf->forced_offset << 8) |
1021 (rxf->hds_cfg.hdr_type & BNA_HDS_FORCED) | rxf->mcast_rxq_id,
1022 base_addr + off);
1023
1024 /*
1025 * default vlan tag, default function enable, strip vlan bytes,
1026 * HDS type, header size
1027 */
1028
1029 off = (unsigned long)&rx_fndb_ram[rxf->rxf_id].control_flags;
1030 writel(((u32)rxf->default_vlan_tag << 16) |
1031 (rxf->ctrl_flags &
1032 (BNA_RXF_CF_DEFAULT_VLAN |
1033 BNA_RXF_CF_DEFAULT_FUNCTION_ENABLE |
1034 BNA_RXF_CF_VLAN_STRIP)) |
1035 (rxf->hds_cfg.hdr_type & ~BNA_HDS_FORCED) |
1036 rxf->hds_cfg.header_size,
1037 base_addr + off);
1038}
1039
1040void
1041__rxf_vlan_filter_set(struct bna_rxf *rxf, enum bna_status status)
1042{
1043 struct bna *bna = rxf->rx->bna;
1044 int i;
1045
1046 writel(BNA_GET_PAGE_NUM(LUT0_MEM_BLK_BASE_PG_NUM +
1047 (bna->port_num * 2), VLAN_RAM_BASE_OFFSET),
1048 bna->regs.page_addr);
1049
1050 if (status == BNA_STATUS_T_ENABLED) {
1051 /* enable VLAN filtering on this function */
1052 for (i = 0; i <= BFI_MAX_VLAN / 32; i++) {
1053 writel(rxf->vlan_filter_table[i],
1054 BNA_GET_VLAN_MEM_ENTRY_ADDR
1055 (bna->pcidev.pci_bar_kva, rxf->rxf_id,
1056 i * 32));
1057 }
1058 } else {
1059 /* disable VLAN filtering on this function */
1060 for (i = 0; i <= BFI_MAX_VLAN / 32; i++) {
1061 writel(0xffffffff,
1062 BNA_GET_VLAN_MEM_ENTRY_ADDR
1063 (bna->pcidev.pci_bar_kva, rxf->rxf_id,
1064 i * 32));
1065 }
1066 }
1067}
1068
1069static void
1070__rxf_rit_set(struct bna_rxf *rxf)
1071{
1072 struct bna *bna = rxf->rx->bna;
1073 struct bna_rit_mem *rit_mem;
1074 int i;
1075 void __iomem *base_addr;
1076 unsigned long off;
1077
1078 base_addr = BNA_GET_MEM_BASE_ADDR(bna->pcidev.pci_bar_kva,
1079 FUNCTION_TO_RXQ_TRANSLATE);
1080
1081 rit_mem = (struct bna_rit_mem *)0;
1082
1083 writel(BNA_GET_PAGE_NUM(RXA0_MEM_BLK_BASE_PG_NUM + bna->port_num,
1084 FUNCTION_TO_RXQ_TRANSLATE),
1085 bna->regs.page_addr);
1086
1087 for (i = 0; i < rxf->rit_segment->rit_size; i++) {
1088 off = (unsigned long)&rit_mem[i + rxf->rit_segment->rit_offset];
1089 writel(rxf->rit_segment->rit[i].large_rxq_id << 6 |
1090 rxf->rit_segment->rit[i].small_rxq_id,
1091 base_addr + off);
1092 }
1093}
1094
1095static void
1096__bna_rxf_stat_clr(struct bna_rxf *rxf)
1097{
1098 struct bfi_ll_stats_req ll_req;
1099 u32 bm[2] = {0, 0};
1100
1101 if (rxf->rxf_id < 32)
1102 bm[0] = 1 << rxf->rxf_id;
1103 else
1104 bm[1] = 1 << (rxf->rxf_id - 32);
1105
1106 bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_STATS_CLEAR_REQ, 0);
1107 ll_req.stats_mask = 0;
1108 ll_req.txf_id_mask[0] = 0;
1109 ll_req.txf_id_mask[1] = 0;
1110
1111 ll_req.rxf_id_mask[0] = htonl(bm[0]);
1112 ll_req.rxf_id_mask[1] = htonl(bm[1]);
1113
1114 bna_mbox_qe_fill(&rxf->mbox_qe, &ll_req, sizeof(ll_req),
1115 bna_rxf_cb_stats_cleared, rxf);
1116 bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe);
1117}
1118
1119static void
1120rxf_enable(struct bna_rxf *rxf)
1121{
1122 if (rxf->rxf_oper_state == BNA_RXF_OPER_STATE_PAUSED)
1123 bfa_fsm_send_event(rxf, RXF_E_STARTED);
1124 else {
1125 rxf->rxf_flags |= BNA_RXF_FL_RXF_ENABLED;
1126 __rxf_enable(rxf);
1127 }
1128}
1129
1130static void
1131rxf_cb_enabled(void *arg, int status)
1132{
1133 struct bna_rxf *rxf = (struct bna_rxf *)arg;
1134
1135 bfa_q_qe_init(&rxf->mbox_qe.qe);
1136 bfa_fsm_send_event(rxf, RXF_E_STARTED);
1137}
1138
1139static void
1140rxf_disable(struct bna_rxf *rxf)
1141{
1142 if (rxf->rxf_oper_state == BNA_RXF_OPER_STATE_PAUSED)
1143 bfa_fsm_send_event(rxf, RXF_E_STOPPED);
1144 else
1145 rxf->rxf_flags &= ~BNA_RXF_FL_RXF_ENABLED;
1146 __rxf_disable(rxf);
1147}
1148
1149static void
1150rxf_cb_disabled(void *arg, int status)
1151{
1152 struct bna_rxf *rxf = (struct bna_rxf *)arg;
1153
1154 bfa_q_qe_init(&rxf->mbox_qe.qe);
1155 bfa_fsm_send_event(rxf, RXF_E_STOPPED);
1156}
1157
1158void
1159rxf_cb_cam_fltr_mbox_cmd(void *arg, int status)
1160{
1161 struct bna_rxf *rxf = (struct bna_rxf *)arg;
1162
1163 bfa_q_qe_init(&rxf->mbox_qe.qe);
1164
1165 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_RESP);
1166}
1167
1168static void
1169bna_rxf_cb_stats_cleared(void *arg, int status)
1170{
1171 struct bna_rxf *rxf = (struct bna_rxf *)arg;
1172
1173 bfa_q_qe_init(&rxf->mbox_qe.qe);
1174 bfa_fsm_send_event(rxf, RXF_E_STAT_CLEARED);
1175}
1176
1177void
1178rxf_cam_mbox_cmd(struct bna_rxf *rxf, u8 cmd,
1179 const struct bna_mac *mac_addr)
1180{
1181 struct bfi_ll_mac_addr_req req;
1182
1183 bfi_h2i_set(req.mh, BFI_MC_LL, cmd, 0);
1184
1185 req.rxf_id = rxf->rxf_id;
1186 memcpy(&req.mac_addr, (void *)&mac_addr->addr, ETH_ALEN);
1187
1188 bna_mbox_qe_fill(&rxf->mbox_qe, &req, sizeof(req),
1189 rxf_cb_cam_fltr_mbox_cmd, rxf);
1190
1191 bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe);
1192}
1193
1194static int
1195rxf_process_packet_filter_mcast(struct bna_rxf *rxf)
1196{
1197 struct bna_mac *mac = NULL;
1198 struct list_head *qe;
1199
1200 /* Add multicast entries */
1201 if (!list_empty(&rxf->mcast_pending_add_q)) {
1202 bfa_q_deq(&rxf->mcast_pending_add_q, &qe);
1203 bfa_q_qe_init(qe);
1204 mac = (struct bna_mac *)qe;
1205 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_ADD_REQ, mac);
1206 list_add_tail(&mac->qe, &rxf->mcast_active_q);
1207 return 1;
1208 }
1209
1210 /* Delete multicast entries previousely added */
1211 if (!list_empty(&rxf->mcast_pending_del_q)) {
1212 bfa_q_deq(&rxf->mcast_pending_del_q, &qe);
1213 bfa_q_qe_init(qe);
1214 mac = (struct bna_mac *)qe;
1215 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_DEL_REQ, mac);
1216 bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
1217 return 1;
1218 }
1219
1220 return 0;
1221}
1222
1223static int
1224rxf_process_packet_filter_vlan(struct bna_rxf *rxf)
1225{
1226 /* Apply the VLAN filter */
1227 if (rxf->rxf_flags & BNA_RXF_FL_VLAN_CONFIG_PENDING) {
1228 rxf->rxf_flags &= ~BNA_RXF_FL_VLAN_CONFIG_PENDING;
1229 if (!(rxf->rxmode_active & BNA_RXMODE_PROMISC))
1230 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
1231 }
1232
1233 /* Apply RSS configuration */
1234 if (rxf->rxf_flags & BNA_RXF_FL_RSS_CONFIG_PENDING) {
1235 rxf->rxf_flags &= ~BNA_RXF_FL_RSS_CONFIG_PENDING;
1236 if (rxf->rss_status == BNA_STATUS_T_DISABLED) {
1237 /* RSS is being disabled */
1238 rxf->ctrl_flags &= ~BNA_RXF_CF_RSS_ENABLE;
1239 __rxf_rit_set(rxf);
1240 __rxf_config_set(rxf);
1241 } else {
1242 /* RSS is being enabled or reconfigured */
1243 rxf->ctrl_flags |= BNA_RXF_CF_RSS_ENABLE;
1244 __rxf_rit_set(rxf);
1245 __rxf_config_set(rxf);
1246 }
1247 }
1248
1249 return 0;
1250}
1251
1252/**
1253 * Processes pending ucast, mcast entry addition/deletion and issues mailbox
1254 * command. Also processes pending filter configuration - promiscuous mode,
1255 * default mode, allmutli mode and issues mailbox command or directly applies
1256 * to h/w
1257 */
1258static int
1259rxf_process_packet_filter(struct bna_rxf *rxf)
1260{
1261 /* Set the default MAC first */
1262 if (rxf->ucast_pending_set > 0) {
1263 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_SET_REQ,
1264 rxf->ucast_active_mac);
1265 rxf->ucast_pending_set--;
1266 return 1;
1267 }
1268
1269 if (rxf_process_packet_filter_ucast(rxf))
1270 return 1;
1271
1272 if (rxf_process_packet_filter_mcast(rxf))
1273 return 1;
1274
1275 if (rxf_process_packet_filter_promisc(rxf))
1276 return 1;
1277
1278 if (rxf_process_packet_filter_allmulti(rxf))
1279 return 1;
1280
1281 if (rxf_process_packet_filter_vlan(rxf))
1282 return 1;
1283
1284 return 0;
1285}
1286
1287static int
1288rxf_clear_packet_filter_mcast(struct bna_rxf *rxf)
1289{
1290 struct bna_mac *mac = NULL;
1291 struct list_head *qe;
1292
1293 /* 3. delete pending mcast entries */
1294 if (!list_empty(&rxf->mcast_pending_del_q)) {
1295 bfa_q_deq(&rxf->mcast_pending_del_q, &qe);
1296 bfa_q_qe_init(qe);
1297 mac = (struct bna_mac *)qe;
1298 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_DEL_REQ, mac);
1299 bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
1300 return 1;
1301 }
1302
1303 /* 4. clear active mcast entries; move them to pending_add_q */
1304 if (!list_empty(&rxf->mcast_active_q)) {
1305 bfa_q_deq(&rxf->mcast_active_q, &qe);
1306 bfa_q_qe_init(qe);
1307 mac = (struct bna_mac *)qe;
1308 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_DEL_REQ, mac);
1309 list_add_tail(&mac->qe, &rxf->mcast_pending_add_q);
1310 return 1;
1311 }
1312
1313 return 0;
1314}
1315
1316/**
1317 * In the rxf stop path, processes pending ucast/mcast delete queue and issues
1318 * the mailbox command. Moves the active ucast/mcast entries to pending add q,
1319 * so that they are added to CAM again in the rxf start path. Moves the current
1320 * filter settings - promiscuous, default, allmutli - to pending filter
1321 * configuration
1322 */
1323static int
1324rxf_clear_packet_filter(struct bna_rxf *rxf)
1325{
1326 if (rxf_clear_packet_filter_ucast(rxf))
1327 return 1;
1328
1329 if (rxf_clear_packet_filter_mcast(rxf))
1330 return 1;
1331
1332 /* 5. clear active default MAC in the CAM */
1333 if (rxf->ucast_pending_set > 0)
1334 rxf->ucast_pending_set = 0;
1335
1336 if (rxf_clear_packet_filter_promisc(rxf))
1337 return 1;
1338
1339 if (rxf_clear_packet_filter_allmulti(rxf))
1340 return 1;
1341
1342 return 0;
1343}
1344
1345static void
1346rxf_reset_packet_filter_mcast(struct bna_rxf *rxf)
1347{
1348 struct list_head *qe;
1349 struct bna_mac *mac;
1350
1351 /* 3. Move active mcast entries to pending_add_q */
1352 while (!list_empty(&rxf->mcast_active_q)) {
1353 bfa_q_deq(&rxf->mcast_active_q, &qe);
1354 bfa_q_qe_init(qe);
1355 list_add_tail(qe, &rxf->mcast_pending_add_q);
1356 }
1357
1358 /* 4. Throw away delete pending mcast entries */
1359 while (!list_empty(&rxf->mcast_pending_del_q)) {
1360 bfa_q_deq(&rxf->mcast_pending_del_q, &qe);
1361 bfa_q_qe_init(qe);
1362 mac = (struct bna_mac *)qe;
1363 bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
1364 }
1365}
1366
1367/**
1368 * In the rxf fail path, throws away the ucast/mcast entries pending for
1369 * deletion, moves all active ucast/mcast entries to pending queue so that
1370 * they are added back to CAM in the rxf start path. Also moves the current
1371 * filter configuration to pending filter configuration.
1372 */
1373static void
1374rxf_reset_packet_filter(struct bna_rxf *rxf)
1375{
1376 rxf_reset_packet_filter_ucast(rxf);
1377
1378 rxf_reset_packet_filter_mcast(rxf);
1379
1380 /* 5. Turn off ucast set flag */
1381 rxf->ucast_pending_set = 0;
1382
1383 rxf_reset_packet_filter_promisc(rxf);
1384
1385 rxf_reset_packet_filter_allmulti(rxf);
1386}
1387
1388static void
1389bna_rxf_init(struct bna_rxf *rxf,
1390 struct bna_rx *rx,
1391 struct bna_rx_config *q_config)
1392{
1393 struct list_head *qe;
1394 struct bna_rxp *rxp;
1395
1396 /* rxf_id is initialized during rx_mod init */
1397 rxf->rx = rx;
1398
1399 INIT_LIST_HEAD(&rxf->ucast_pending_add_q);
1400 INIT_LIST_HEAD(&rxf->ucast_pending_del_q);
1401 rxf->ucast_pending_set = 0;
1402 INIT_LIST_HEAD(&rxf->ucast_active_q);
1403 rxf->ucast_active_mac = NULL;
1404
1405 INIT_LIST_HEAD(&rxf->mcast_pending_add_q);
1406 INIT_LIST_HEAD(&rxf->mcast_pending_del_q);
1407 INIT_LIST_HEAD(&rxf->mcast_active_q);
1408
1409 bfa_q_qe_init(&rxf->mbox_qe.qe);
1410
1411 if (q_config->vlan_strip_status == BNA_STATUS_T_ENABLED)
1412 rxf->ctrl_flags |= BNA_RXF_CF_VLAN_STRIP;
1413
1414 rxf->rxf_oper_state = (q_config->paused) ?
1415 BNA_RXF_OPER_STATE_PAUSED : BNA_RXF_OPER_STATE_RUNNING;
1416
1417 bna_rxf_adv_init(rxf, rx, q_config);
1418
1419 rxf->rit_segment = bna_rit_mod_seg_get(&rxf->rx->bna->rit_mod,
1420 q_config->num_paths);
1421
1422 list_for_each(qe, &rx->rxp_q) {
1423 rxp = (struct bna_rxp *)qe;
1424 if (q_config->rxp_type == BNA_RXP_SINGLE)
1425 rxf->mcast_rxq_id = rxp->rxq.single.only->rxq_id;
1426 else
1427 rxf->mcast_rxq_id = rxp->rxq.slr.large->rxq_id;
1428 break;
1429 }
1430
1431 rxf->vlan_filter_status = BNA_STATUS_T_DISABLED;
1432 memset(rxf->vlan_filter_table, 0,
1433 (sizeof(u32) * ((BFI_MAX_VLAN + 1) / 32)));
1434
1435 /* Set up VLAN 0 for pure priority tagged packets */
1436 rxf->vlan_filter_table[0] |= 1;
1437
1438 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
1439}
1440
1441static void
1442bna_rxf_uninit(struct bna_rxf *rxf)
1443{
1444 struct bna *bna = rxf->rx->bna;
1445 struct bna_mac *mac;
1446
1447 bna_rit_mod_seg_put(&rxf->rx->bna->rit_mod, rxf->rit_segment);
1448 rxf->rit_segment = NULL;
1449
1450 rxf->ucast_pending_set = 0;
1451
1452 while (!list_empty(&rxf->ucast_pending_add_q)) {
1453 bfa_q_deq(&rxf->ucast_pending_add_q, &mac);
1454 bfa_q_qe_init(&mac->qe);
1455 bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
1456 }
1457
1458 if (rxf->ucast_active_mac) {
1459 bfa_q_qe_init(&rxf->ucast_active_mac->qe);
1460 bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod,
1461 rxf->ucast_active_mac);
1462 rxf->ucast_active_mac = NULL;
1463 }
1464
1465 while (!list_empty(&rxf->mcast_pending_add_q)) {
1466 bfa_q_deq(&rxf->mcast_pending_add_q, &mac);
1467 bfa_q_qe_init(&mac->qe);
1468 bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
1469 }
1470
1471 /* Turn off pending promisc mode */
1472 if (is_promisc_enable(rxf->rxmode_pending,
1473 rxf->rxmode_pending_bitmask)) {
1474 /* system promisc state should be pending */
1475 BUG_ON(!(bna->rxf_promisc_id == rxf->rxf_id));
1476 promisc_inactive(rxf->rxmode_pending,
1477 rxf->rxmode_pending_bitmask);
1478 bna->rxf_promisc_id = BFI_MAX_RXF;
1479 }
1480 /* Promisc mode should not be active */
1481 BUG_ON(rxf->rxmode_active & BNA_RXMODE_PROMISC);
1482
1483 /* Turn off pending all-multi mode */
1484 if (is_allmulti_enable(rxf->rxmode_pending,
1485 rxf->rxmode_pending_bitmask)) {
1486 allmulti_inactive(rxf->rxmode_pending,
1487 rxf->rxmode_pending_bitmask);
1488 }
1489 /* Allmulti mode should not be active */
1490 BUG_ON(rxf->rxmode_active & BNA_RXMODE_ALLMULTI);
1491
1492 rxf->rx = NULL;
1493}
1494
1495static void
1496bna_rx_cb_rxf_started(struct bna_rx *rx, enum bna_cb_status status)
1497{
1498 bfa_fsm_send_event(rx, RX_E_RXF_STARTED);
1499 if (rx->rxf.rxf_id < 32)
1500 rx->bna->rx_mod.rxf_bmap[0] |= ((u32)1 << rx->rxf.rxf_id);
1501 else
1502 rx->bna->rx_mod.rxf_bmap[1] |= ((u32)
1503 1 << (rx->rxf.rxf_id - 32));
1504}
1505
1506static void
1507bna_rxf_start(struct bna_rxf *rxf)
1508{
1509 rxf->start_cbfn = bna_rx_cb_rxf_started;
1510 rxf->start_cbarg = rxf->rx;
1511 rxf->rxf_flags &= ~BNA_RXF_FL_FAILED;
1512 bfa_fsm_send_event(rxf, RXF_E_START);
1513}
1514
1515static void
1516bna_rx_cb_rxf_stopped(struct bna_rx *rx, enum bna_cb_status status)
1517{
1518 bfa_fsm_send_event(rx, RX_E_RXF_STOPPED);
1519 if (rx->rxf.rxf_id < 32)
1520 rx->bna->rx_mod.rxf_bmap[0] &= ~(u32)1 << rx->rxf.rxf_id;
1521 else
1522 rx->bna->rx_mod.rxf_bmap[1] &= ~(u32)
1523 1 << (rx->rxf.rxf_id - 32);
1524}
1525
1526static void
1527bna_rxf_stop(struct bna_rxf *rxf)
1528{
1529 rxf->stop_cbfn = bna_rx_cb_rxf_stopped;
1530 rxf->stop_cbarg = rxf->rx;
1531 bfa_fsm_send_event(rxf, RXF_E_STOP);
1532}
1533
1534static void
1535bna_rxf_fail(struct bna_rxf *rxf)
1536{
1537 rxf->rxf_flags |= BNA_RXF_FL_FAILED;
1538 bfa_fsm_send_event(rxf, RXF_E_FAIL);
1539}
1540
1541int
1542bna_rxf_state_get(struct bna_rxf *rxf)
1543{
1544 return bfa_sm_to_state(rxf_sm_table, rxf->fsm);
1545}
1546
1547enum bna_cb_status
1548bna_rx_ucast_set(struct bna_rx *rx, u8 *ucmac,
1549 void (*cbfn)(struct bnad *, struct bna_rx *,
1550 enum bna_cb_status))
1551{
1552 struct bna_rxf *rxf = &rx->rxf;
1553
1554 if (rxf->ucast_active_mac == NULL) {
1555 rxf->ucast_active_mac =
1556 bna_ucam_mod_mac_get(&rxf->rx->bna->ucam_mod);
1557 if (rxf->ucast_active_mac == NULL)
1558 return BNA_CB_UCAST_CAM_FULL;
1559 bfa_q_qe_init(&rxf->ucast_active_mac->qe);
1560 }
1561
1562 memcpy(rxf->ucast_active_mac->addr, ucmac, ETH_ALEN);
1563 rxf->ucast_pending_set++;
1564 rxf->cam_fltr_cbfn = cbfn;
1565 rxf->cam_fltr_cbarg = rx->bna->bnad;
1566
1567 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
1568
1569 return BNA_CB_SUCCESS;
1570}
1571
1572enum bna_cb_status
1573bna_rx_mcast_add(struct bna_rx *rx, u8 *addr,
1574 void (*cbfn)(struct bnad *, struct bna_rx *,
1575 enum bna_cb_status))
1576{
1577 struct bna_rxf *rxf = &rx->rxf;
1578 struct list_head *qe;
1579 struct bna_mac *mac;
1580
1581 /* Check if already added */
1582 list_for_each(qe, &rxf->mcast_active_q) {
1583 mac = (struct bna_mac *)qe;
1584 if (BNA_MAC_IS_EQUAL(mac->addr, addr)) {
1585 if (cbfn)
1586 (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
1587 return BNA_CB_SUCCESS;
1588 }
1589 }
1590
1591 /* Check if pending addition */
1592 list_for_each(qe, &rxf->mcast_pending_add_q) {
1593 mac = (struct bna_mac *)qe;
1594 if (BNA_MAC_IS_EQUAL(mac->addr, addr)) {
1595 if (cbfn)
1596 (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
1597 return BNA_CB_SUCCESS;
1598 }
1599 }
1600
1601 mac = bna_mcam_mod_mac_get(&rxf->rx->bna->mcam_mod);
1602 if (mac == NULL)
1603 return BNA_CB_MCAST_LIST_FULL;
1604 bfa_q_qe_init(&mac->qe);
1605 memcpy(mac->addr, addr, ETH_ALEN);
1606 list_add_tail(&mac->qe, &rxf->mcast_pending_add_q);
1607
1608 rxf->cam_fltr_cbfn = cbfn;
1609 rxf->cam_fltr_cbarg = rx->bna->bnad;
1610
1611 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
1612
1613 return BNA_CB_SUCCESS;
1614}
1615
1616enum bna_cb_status
1617bna_rx_mcast_listset(struct bna_rx *rx, int count, u8 *mclist,
1618 void (*cbfn)(struct bnad *, struct bna_rx *,
1619 enum bna_cb_status))
1620{
1621 struct bna_rxf *rxf = &rx->rxf;
1622 struct list_head list_head;
1623 struct list_head *qe;
1624 u8 *mcaddr;
1625 struct bna_mac *mac;
1626 struct bna_mac *mac1;
1627 int skip;
1628 int delete;
1629 int need_hw_config = 0;
1630 int i;
1631
1632 /* Allocate nodes */
1633 INIT_LIST_HEAD(&list_head);
1634 for (i = 0, mcaddr = mclist; i < count; i++) {
1635 mac = bna_mcam_mod_mac_get(&rxf->rx->bna->mcam_mod);
1636 if (mac == NULL)
1637 goto err_return;
1638 bfa_q_qe_init(&mac->qe);
1639 memcpy(mac->addr, mcaddr, ETH_ALEN);
1640 list_add_tail(&mac->qe, &list_head);
1641
1642 mcaddr += ETH_ALEN;
1643 }
1644
1645 /* Schedule for addition */
1646 while (!list_empty(&list_head)) {
1647 bfa_q_deq(&list_head, &qe);
1648 mac = (struct bna_mac *)qe;
1649 bfa_q_qe_init(&mac->qe);
1650
1651 skip = 0;
1652
1653 /* Skip if already added */
1654 list_for_each(qe, &rxf->mcast_active_q) {
1655 mac1 = (struct bna_mac *)qe;
1656 if (BNA_MAC_IS_EQUAL(mac1->addr, mac->addr)) {
1657 bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod,
1658 mac);
1659 skip = 1;
1660 break;
1661 }
1662 }
1663
1664 if (skip)
1665 continue;
1666
1667 /* Skip if pending addition */
1668 list_for_each(qe, &rxf->mcast_pending_add_q) {
1669 mac1 = (struct bna_mac *)qe;
1670 if (BNA_MAC_IS_EQUAL(mac1->addr, mac->addr)) {
1671 bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod,
1672 mac);
1673 skip = 1;
1674 break;
1675 }
1676 }
1677
1678 if (skip)
1679 continue;
1680
1681 need_hw_config = 1;
1682 list_add_tail(&mac->qe, &rxf->mcast_pending_add_q);
1683 }
1684
1685 /**
1686 * Delete the entries that are in the pending_add_q but not
1687 * in the new list
1688 */
1689 while (!list_empty(&rxf->mcast_pending_add_q)) {
1690 bfa_q_deq(&rxf->mcast_pending_add_q, &qe);
1691 mac = (struct bna_mac *)qe;
1692 bfa_q_qe_init(&mac->qe);
1693 for (i = 0, mcaddr = mclist, delete = 1; i < count; i++) {
1694 if (BNA_MAC_IS_EQUAL(mcaddr, mac->addr)) {
1695 delete = 0;
1696 break;
1697 }
1698 mcaddr += ETH_ALEN;
1699 }
1700 if (delete)
1701 bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
1702 else
1703 list_add_tail(&mac->qe, &list_head);
1704 }
1705 while (!list_empty(&list_head)) {
1706 bfa_q_deq(&list_head, &qe);
1707 mac = (struct bna_mac *)qe;
1708 bfa_q_qe_init(&mac->qe);
1709 list_add_tail(&mac->qe, &rxf->mcast_pending_add_q);
1710 }
1711
1712 /**
1713 * Schedule entries for deletion that are in the active_q but not
1714 * in the new list
1715 */
1716 while (!list_empty(&rxf->mcast_active_q)) {
1717 bfa_q_deq(&rxf->mcast_active_q, &qe);
1718 mac = (struct bna_mac *)qe;
1719 bfa_q_qe_init(&mac->qe);
1720 for (i = 0, mcaddr = mclist, delete = 1; i < count; i++) {
1721 if (BNA_MAC_IS_EQUAL(mcaddr, mac->addr)) {
1722 delete = 0;
1723 break;
1724 }
1725 mcaddr += ETH_ALEN;
1726 }
1727 if (delete) {
1728 list_add_tail(&mac->qe, &rxf->mcast_pending_del_q);
1729 need_hw_config = 1;
1730 } else {
1731 list_add_tail(&mac->qe, &list_head);
1732 }
1733 }
1734 while (!list_empty(&list_head)) {
1735 bfa_q_deq(&list_head, &qe);
1736 mac = (struct bna_mac *)qe;
1737 bfa_q_qe_init(&mac->qe);
1738 list_add_tail(&mac->qe, &rxf->mcast_active_q);
1739 }
1740
1741 if (need_hw_config) {
1742 rxf->cam_fltr_cbfn = cbfn;
1743 rxf->cam_fltr_cbarg = rx->bna->bnad;
1744 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
1745 } else if (cbfn)
1746 (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
1747
1748 return BNA_CB_SUCCESS;
1749
1750err_return:
1751 while (!list_empty(&list_head)) {
1752 bfa_q_deq(&list_head, &qe);
1753 mac = (struct bna_mac *)qe;
1754 bfa_q_qe_init(&mac->qe);
1755 bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
1756 }
1757
1758 return BNA_CB_MCAST_LIST_FULL;
1759}
1760
1761void
1762bna_rx_vlan_add(struct bna_rx *rx, int vlan_id)
1763{
1764 struct bna_rxf *rxf = &rx->rxf;
1765 int index = (vlan_id >> 5);
1766 int bit = (1 << (vlan_id & 0x1F));
1767
1768 rxf->vlan_filter_table[index] |= bit;
1769 if (rxf->vlan_filter_status == BNA_STATUS_T_ENABLED) {
1770 rxf->rxf_flags |= BNA_RXF_FL_VLAN_CONFIG_PENDING;
1771 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
1772 }
1773}
1774
1775void
1776bna_rx_vlan_del(struct bna_rx *rx, int vlan_id)
1777{
1778 struct bna_rxf *rxf = &rx->rxf;
1779 int index = (vlan_id >> 5);
1780 int bit = (1 << (vlan_id & 0x1F));
1781
1782 rxf->vlan_filter_table[index] &= ~bit;
1783 if (rxf->vlan_filter_status == BNA_STATUS_T_ENABLED) {
1784 rxf->rxf_flags |= BNA_RXF_FL_VLAN_CONFIG_PENDING;
1785 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
1786 }
1787}
1788
1789/**
1790 * RX
1791 */
1792#define RXQ_RCB_INIT(q, rxp, qdepth, bna, _id, unmapq_mem) do { \
1793 struct bna_doorbell_qset *_qset; \
1794 unsigned long off; \
1795 (q)->rcb->producer_index = (q)->rcb->consumer_index = 0; \
1796 (q)->rcb->q_depth = (qdepth); \
1797 (q)->rcb->unmap_q = unmapq_mem; \
1798 (q)->rcb->rxq = (q); \
1799 (q)->rcb->cq = &(rxp)->cq; \
1800 (q)->rcb->bnad = (bna)->bnad; \
1801 _qset = (struct bna_doorbell_qset *)0; \
1802 off = (unsigned long)&_qset[(q)->rxq_id].rxq[0]; \
1803 (q)->rcb->q_dbell = off + \
1804 BNA_GET_DOORBELL_BASE_ADDR((bna)->pcidev.pci_bar_kva); \
1805 (q)->rcb->id = _id; \
1806} while (0)
1807
1808#define BNA_GET_RXQS(qcfg) (((qcfg)->rxp_type == BNA_RXP_SINGLE) ? \
1809 (qcfg)->num_paths : ((qcfg)->num_paths * 2))
1810
1811#define SIZE_TO_PAGES(size) (((size) >> PAGE_SHIFT) + ((((size) &\
1812 (PAGE_SIZE - 1)) + (PAGE_SIZE - 1)) >> PAGE_SHIFT))
1813
1814#define call_rx_stop_callback(rx, status) \
1815 if ((rx)->stop_cbfn) { \
1816 (*(rx)->stop_cbfn)((rx)->stop_cbarg, rx, (status)); \
1817 (rx)->stop_cbfn = NULL; \
1818 (rx)->stop_cbarg = NULL; \
1819 }
1820
1821/*
1822 * Since rx_enable is synchronous callback, there is no start_cbfn required.
1823 * Instead, we'll call bnad_rx_post(rxp) so that bnad can post the buffers
1824 * for each rxpath.
1825 */
1826
1827#define call_rx_disable_cbfn(rx, status) \
1828 if ((rx)->disable_cbfn) { \
1829 (*(rx)->disable_cbfn)((rx)->disable_cbarg, \
1830 status); \
1831 (rx)->disable_cbfn = NULL; \
1832 (rx)->disable_cbarg = NULL; \
1833 } \
1834
1835#define rxqs_reqd(type, num_rxqs) \
1836 (((type) == BNA_RXP_SINGLE) ? (num_rxqs) : ((num_rxqs) * 2))
1837
1838#define rx_ib_fail(rx) \
1839do { \
1840 struct bna_rxp *rxp; \
1841 struct list_head *qe; \
1842 list_for_each(qe, &(rx)->rxp_q) { \
1843 rxp = (struct bna_rxp *)qe; \
1844 bna_ib_fail(rxp->cq.ib); \
1845 } \
1846} while (0)
1847
1848static void __bna_multi_rxq_stop(struct bna_rxp *, u32 *);
1849static void __bna_rxq_start(struct bna_rxq *rxq);
1850static void __bna_cq_start(struct bna_cq *cq);
1851static void bna_rit_create(struct bna_rx *rx);
1852static void bna_rx_cb_multi_rxq_stopped(void *arg, int status);
1853static void bna_rx_cb_rxq_stopped_all(void *arg);
1854
1855bfa_fsm_state_decl(bna_rx, stopped,
1856 struct bna_rx, enum bna_rx_event);
1857bfa_fsm_state_decl(bna_rx, rxf_start_wait,
1858 struct bna_rx, enum bna_rx_event);
1859bfa_fsm_state_decl(bna_rx, started,
1860 struct bna_rx, enum bna_rx_event);
1861bfa_fsm_state_decl(bna_rx, rxf_stop_wait,
1862 struct bna_rx, enum bna_rx_event);
1863bfa_fsm_state_decl(bna_rx, rxq_stop_wait,
1864 struct bna_rx, enum bna_rx_event);
1865
1866static const struct bfa_sm_table rx_sm_table[] = {
1867 {BFA_SM(bna_rx_sm_stopped), BNA_RX_STOPPED},
1868 {BFA_SM(bna_rx_sm_rxf_start_wait), BNA_RX_RXF_START_WAIT},
1869 {BFA_SM(bna_rx_sm_started), BNA_RX_STARTED},
1870 {BFA_SM(bna_rx_sm_rxf_stop_wait), BNA_RX_RXF_STOP_WAIT},
1871 {BFA_SM(bna_rx_sm_rxq_stop_wait), BNA_RX_RXQ_STOP_WAIT},
1872};
1873
1874static void bna_rx_sm_stopped_entry(struct bna_rx *rx)
1875{
1876 struct bna_rxp *rxp;
1877 struct list_head *qe_rxp;
1878
1879 list_for_each(qe_rxp, &rx->rxp_q) {
1880 rxp = (struct bna_rxp *)qe_rxp;
1881 rx->rx_cleanup_cbfn(rx->bna->bnad, rxp->cq.ccb);
1882 }
1883
1884 call_rx_stop_callback(rx, BNA_CB_SUCCESS);
1885}
1886
1887static void bna_rx_sm_stopped(struct bna_rx *rx,
1888 enum bna_rx_event event)
1889{
1890 switch (event) {
1891 case RX_E_START:
1892 bfa_fsm_set_state(rx, bna_rx_sm_rxf_start_wait);
1893 break;
1894 case RX_E_STOP:
1895 call_rx_stop_callback(rx, BNA_CB_SUCCESS);
1896 break;
1897 case RX_E_FAIL:
1898 /* no-op */
1899 break;
1900 default:
1901 bfa_sm_fault(event);
1902 break;
1903 }
1904
1905}
1906
1907static void bna_rx_sm_rxf_start_wait_entry(struct bna_rx *rx)
1908{
1909 struct bna_rxp *rxp;
1910 struct list_head *qe_rxp;
1911 struct bna_rxq *q0 = NULL, *q1 = NULL;
1912
1913 /* Setup the RIT */
1914 bna_rit_create(rx);
1915
1916 list_for_each(qe_rxp, &rx->rxp_q) {
1917 rxp = (struct bna_rxp *)qe_rxp;
1918 bna_ib_start(rxp->cq.ib);
1919 GET_RXQS(rxp, q0, q1);
1920 q0->buffer_size = bna_port_mtu_get(&rx->bna->port);
1921 __bna_rxq_start(q0);
1922 rx->rx_post_cbfn(rx->bna->bnad, q0->rcb);
1923 if (q1) {
1924 __bna_rxq_start(q1);
1925 rx->rx_post_cbfn(rx->bna->bnad, q1->rcb);
1926 }
1927 __bna_cq_start(&rxp->cq);
1928 }
1929
1930 bna_rxf_start(&rx->rxf);
1931}
1932
1933static void bna_rx_sm_rxf_start_wait(struct bna_rx *rx,
1934 enum bna_rx_event event)
1935{
1936 switch (event) {
1937 case RX_E_STOP:
1938 bfa_fsm_set_state(rx, bna_rx_sm_rxf_stop_wait);
1939 break;
1940 case RX_E_FAIL:
1941 bfa_fsm_set_state(rx, bna_rx_sm_stopped);
1942 rx_ib_fail(rx);
1943 bna_rxf_fail(&rx->rxf);
1944 break;
1945 case RX_E_RXF_STARTED:
1946 bfa_fsm_set_state(rx, bna_rx_sm_started);
1947 break;
1948 default:
1949 bfa_sm_fault(event);
1950 break;
1951 }
1952}
1953
1954void
1955bna_rx_sm_started_entry(struct bna_rx *rx)
1956{
1957 struct bna_rxp *rxp;
1958 struct list_head *qe_rxp;
1959
1960 /* Start IB */
1961 list_for_each(qe_rxp, &rx->rxp_q) {
1962 rxp = (struct bna_rxp *)qe_rxp;
1963 bna_ib_ack(&rxp->cq.ib->door_bell, 0);
1964 }
1965
1966 bna_llport_rx_started(&rx->bna->port.llport);
1967}
1968
1969void
1970bna_rx_sm_started(struct bna_rx *rx, enum bna_rx_event event)
1971{
1972 switch (event) {
1973 case RX_E_FAIL:
1974 bna_llport_rx_stopped(&rx->bna->port.llport);
1975 bfa_fsm_set_state(rx, bna_rx_sm_stopped);
1976 rx_ib_fail(rx);
1977 bna_rxf_fail(&rx->rxf);
1978 break;
1979 case RX_E_STOP:
1980 bna_llport_rx_stopped(&rx->bna->port.llport);
1981 bfa_fsm_set_state(rx, bna_rx_sm_rxf_stop_wait);
1982 break;
1983 default:
1984 bfa_sm_fault(event);
1985 break;
1986 }
1987}
1988
1989void
1990bna_rx_sm_rxf_stop_wait_entry(struct bna_rx *rx)
1991{
1992 bna_rxf_stop(&rx->rxf);
1993}
1994
1995void
1996bna_rx_sm_rxf_stop_wait(struct bna_rx *rx, enum bna_rx_event event)
1997{
1998 switch (event) {
1999 case RX_E_RXF_STOPPED:
2000 bfa_fsm_set_state(rx, bna_rx_sm_rxq_stop_wait);
2001 break;
2002 case RX_E_RXF_STARTED:
2003 /**
2004 * RxF was in the process of starting up when
2005 * RXF_E_STOP was issued. Ignore this event
2006 */
2007 break;
2008 case RX_E_FAIL:
2009 bfa_fsm_set_state(rx, bna_rx_sm_stopped);
2010 rx_ib_fail(rx);
2011 bna_rxf_fail(&rx->rxf);
2012 break;
2013 default:
2014 bfa_sm_fault(event);
2015 break;
2016 }
2017
2018}
2019
2020void
2021bna_rx_sm_rxq_stop_wait_entry(struct bna_rx *rx)
2022{
2023 struct bna_rxp *rxp = NULL;
2024 struct bna_rxq *q0 = NULL;
2025 struct bna_rxq *q1 = NULL;
2026 struct list_head *qe;
2027 u32 rxq_mask[2] = {0, 0};
2028
2029 /* Only one call to multi-rxq-stop for all RXPs in this RX */
2030 bfa_wc_up(&rx->rxq_stop_wc);
2031 list_for_each(qe, &rx->rxp_q) {
2032 rxp = (struct bna_rxp *)qe;
2033 GET_RXQS(rxp, q0, q1);
2034 if (q0->rxq_id < 32)
2035 rxq_mask[0] |= ((u32)1 << q0->rxq_id);
2036 else
2037 rxq_mask[1] |= ((u32)1 << (q0->rxq_id - 32));
2038 if (q1) {
2039 if (q1->rxq_id < 32)
2040 rxq_mask[0] |= ((u32)1 << q1->rxq_id);
2041 else
2042 rxq_mask[1] |= ((u32)
2043 1 << (q1->rxq_id - 32));
2044 }
2045 }
2046
2047 __bna_multi_rxq_stop(rxp, rxq_mask);
2048}
2049
2050void
2051bna_rx_sm_rxq_stop_wait(struct bna_rx *rx, enum bna_rx_event event)
2052{
2053 struct bna_rxp *rxp = NULL;
2054 struct list_head *qe;
2055
2056 switch (event) {
2057 case RX_E_RXQ_STOPPED:
2058 list_for_each(qe, &rx->rxp_q) {
2059 rxp = (struct bna_rxp *)qe;
2060 bna_ib_stop(rxp->cq.ib);
2061 }
2062 /* Fall through */
2063 case RX_E_FAIL:
2064 bfa_fsm_set_state(rx, bna_rx_sm_stopped);
2065 break;
2066 default:
2067 bfa_sm_fault(event);
2068 break;
2069 }
2070}
2071
2072void
2073__bna_multi_rxq_stop(struct bna_rxp *rxp, u32 * rxq_id_mask)
2074{
2075 struct bfi_ll_q_stop_req ll_req;
2076
2077 bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_RXQ_STOP_REQ, 0);
2078 ll_req.q_id_mask[0] = htonl(rxq_id_mask[0]);
2079 ll_req.q_id_mask[1] = htonl(rxq_id_mask[1]);
2080 bna_mbox_qe_fill(&rxp->mbox_qe, &ll_req, sizeof(ll_req),
2081 bna_rx_cb_multi_rxq_stopped, rxp);
2082 bna_mbox_send(rxp->rx->bna, &rxp->mbox_qe);
2083}
2084
2085void
2086__bna_rxq_start(struct bna_rxq *rxq)
2087{
2088 struct bna_rxtx_q_mem *q_mem;
2089 struct bna_rxq_mem rxq_cfg, *rxq_mem;
2090 struct bna_dma_addr cur_q_addr;
2091 /* struct bna_doorbell_qset *qset; */
2092 struct bna_qpt *qpt;
2093 u32 pg_num;
2094 struct bna *bna = rxq->rx->bna;
2095 void __iomem *base_addr;
2096 unsigned long off;
2097
2098 qpt = &rxq->qpt;
2099 cur_q_addr = *((struct bna_dma_addr *)(qpt->kv_qpt_ptr));
2100
2101 rxq_cfg.pg_tbl_addr_lo = qpt->hw_qpt_ptr.lsb;
2102 rxq_cfg.pg_tbl_addr_hi = qpt->hw_qpt_ptr.msb;
2103 rxq_cfg.cur_q_entry_lo = cur_q_addr.lsb;
2104 rxq_cfg.cur_q_entry_hi = cur_q_addr.msb;
2105
2106 rxq_cfg.pg_cnt_n_prd_ptr = ((u32)qpt->page_count << 16) | 0x0;
2107 rxq_cfg.entry_n_pg_size = ((u32)(BFI_RXQ_WI_SIZE >> 2) << 16) |
2108 (qpt->page_size >> 2);
2109 rxq_cfg.sg_n_cq_n_cns_ptr =
2110 ((u32)(rxq->rxp->cq.cq_id & 0xff) << 16) | 0x0;
2111 rxq_cfg.buf_sz_n_q_state = ((u32)rxq->buffer_size << 16) |
2112 BNA_Q_IDLE_STATE;
2113 rxq_cfg.next_qid = 0x0 | (0x3 << 8);
2114
2115 /* Write the page number register */
2116 pg_num = BNA_GET_PAGE_NUM(HQM0_BLK_PG_NUM + bna->port_num,
2117 HQM_RXTX_Q_RAM_BASE_OFFSET);
2118 writel(pg_num, bna->regs.page_addr);
2119
2120 /* Write to h/w */
2121 base_addr = BNA_GET_MEM_BASE_ADDR(bna->pcidev.pci_bar_kva,
2122 HQM_RXTX_Q_RAM_BASE_OFFSET);
2123
2124 q_mem = (struct bna_rxtx_q_mem *)0;
2125 rxq_mem = &q_mem[rxq->rxq_id].rxq;
2126
2127 off = (unsigned long)&rxq_mem->pg_tbl_addr_lo;
2128 writel(htonl(rxq_cfg.pg_tbl_addr_lo), base_addr + off);
2129
2130 off = (unsigned long)&rxq_mem->pg_tbl_addr_hi;
2131 writel(htonl(rxq_cfg.pg_tbl_addr_hi), base_addr + off);
2132
2133 off = (unsigned long)&rxq_mem->cur_q_entry_lo;
2134 writel(htonl(rxq_cfg.cur_q_entry_lo), base_addr + off);
2135
2136 off = (unsigned long)&rxq_mem->cur_q_entry_hi;
2137 writel(htonl(rxq_cfg.cur_q_entry_hi), base_addr + off);
2138
2139 off = (unsigned long)&rxq_mem->pg_cnt_n_prd_ptr;
2140 writel(rxq_cfg.pg_cnt_n_prd_ptr, base_addr + off);
2141
2142 off = (unsigned long)&rxq_mem->entry_n_pg_size;
2143 writel(rxq_cfg.entry_n_pg_size, base_addr + off);
2144
2145 off = (unsigned long)&rxq_mem->sg_n_cq_n_cns_ptr;
2146 writel(rxq_cfg.sg_n_cq_n_cns_ptr, base_addr + off);
2147
2148 off = (unsigned long)&rxq_mem->buf_sz_n_q_state;
2149 writel(rxq_cfg.buf_sz_n_q_state, base_addr + off);
2150
2151 off = (unsigned long)&rxq_mem->next_qid;
2152 writel(rxq_cfg.next_qid, base_addr + off);
2153
2154 rxq->rcb->producer_index = 0;
2155 rxq->rcb->consumer_index = 0;
2156}
2157
2158void
2159__bna_cq_start(struct bna_cq *cq)
2160{
2161 struct bna_cq_mem cq_cfg, *cq_mem;
2162 const struct bna_qpt *qpt;
2163 struct bna_dma_addr cur_q_addr;
2164 u32 pg_num;
2165 struct bna *bna = cq->rx->bna;
2166 void __iomem *base_addr;
2167 unsigned long off;
2168
2169 qpt = &cq->qpt;
2170 cur_q_addr = *((struct bna_dma_addr *)(qpt->kv_qpt_ptr));
2171
2172 /*
2173 * Fill out structure, to be subsequently written
2174 * to hardware
2175 */
2176 cq_cfg.pg_tbl_addr_lo = qpt->hw_qpt_ptr.lsb;
2177 cq_cfg.pg_tbl_addr_hi = qpt->hw_qpt_ptr.msb;
2178 cq_cfg.cur_q_entry_lo = cur_q_addr.lsb;
2179 cq_cfg.cur_q_entry_hi = cur_q_addr.msb;
2180
2181 cq_cfg.pg_cnt_n_prd_ptr = (qpt->page_count << 16) | 0x0;
2182 cq_cfg.entry_n_pg_size =
2183 ((u32)(BFI_CQ_WI_SIZE >> 2) << 16) | (qpt->page_size >> 2);
2184 cq_cfg.int_blk_n_cns_ptr = ((((u32)cq->ib_seg_offset) << 24) |
2185 ((u32)(cq->ib->ib_id & 0xff) << 16) | 0x0);
2186 cq_cfg.q_state = BNA_Q_IDLE_STATE;
2187
2188 /* Write the page number register */
2189 pg_num = BNA_GET_PAGE_NUM(HQM0_BLK_PG_NUM + bna->port_num,
2190 HQM_CQ_RAM_BASE_OFFSET);
2191
2192 writel(pg_num, bna->regs.page_addr);
2193
2194 /* H/W write */
2195 base_addr = BNA_GET_MEM_BASE_ADDR(bna->pcidev.pci_bar_kva,
2196 HQM_CQ_RAM_BASE_OFFSET);
2197
2198 cq_mem = (struct bna_cq_mem *)0;
2199
2200 off = (unsigned long)&cq_mem[cq->cq_id].pg_tbl_addr_lo;
2201 writel(htonl(cq_cfg.pg_tbl_addr_lo), base_addr + off);
2202
2203 off = (unsigned long)&cq_mem[cq->cq_id].pg_tbl_addr_hi;
2204 writel(htonl(cq_cfg.pg_tbl_addr_hi), base_addr + off);
2205
2206 off = (unsigned long)&cq_mem[cq->cq_id].cur_q_entry_lo;
2207 writel(htonl(cq_cfg.cur_q_entry_lo), base_addr + off);
2208
2209 off = (unsigned long)&cq_mem[cq->cq_id].cur_q_entry_hi;
2210 writel(htonl(cq_cfg.cur_q_entry_hi), base_addr + off);
2211
2212 off = (unsigned long)&cq_mem[cq->cq_id].pg_cnt_n_prd_ptr;
2213 writel(cq_cfg.pg_cnt_n_prd_ptr, base_addr + off);
2214
2215 off = (unsigned long)&cq_mem[cq->cq_id].entry_n_pg_size;
2216 writel(cq_cfg.entry_n_pg_size, base_addr + off);
2217
2218 off = (unsigned long)&cq_mem[cq->cq_id].int_blk_n_cns_ptr;
2219 writel(cq_cfg.int_blk_n_cns_ptr, base_addr + off);
2220
2221 off = (unsigned long)&cq_mem[cq->cq_id].q_state;
2222 writel(cq_cfg.q_state, base_addr + off);
2223
2224 cq->ccb->producer_index = 0;
2225 *(cq->ccb->hw_producer_index) = 0;
2226}
2227
2228void
2229bna_rit_create(struct bna_rx *rx)
2230{
2231 struct list_head *qe_rxp;
2232 struct bna_rxp *rxp;
2233 struct bna_rxq *q0 = NULL;
2234 struct bna_rxq *q1 = NULL;
2235 int offset;
2236
2237 offset = 0;
2238 list_for_each(qe_rxp, &rx->rxp_q) {
2239 rxp = (struct bna_rxp *)qe_rxp;
2240 GET_RXQS(rxp, q0, q1);
2241 rx->rxf.rit_segment->rit[offset].large_rxq_id = q0->rxq_id;
2242 rx->rxf.rit_segment->rit[offset].small_rxq_id =
2243 (q1 ? q1->rxq_id : 0);
2244 offset++;
2245 }
2246}
2247
2248static int
2249_rx_can_satisfy(struct bna_rx_mod *rx_mod,
2250 struct bna_rx_config *rx_cfg)
2251{
2252 if ((rx_mod->rx_free_count == 0) ||
2253 (rx_mod->rxp_free_count == 0) ||
2254 (rx_mod->rxq_free_count == 0))
2255 return 0;
2256
2257 if (rx_cfg->rxp_type == BNA_RXP_SINGLE) {
2258 if ((rx_mod->rxp_free_count < rx_cfg->num_paths) ||
2259 (rx_mod->rxq_free_count < rx_cfg->num_paths))
2260 return 0;
2261 } else {
2262 if ((rx_mod->rxp_free_count < rx_cfg->num_paths) ||
2263 (rx_mod->rxq_free_count < (2 * rx_cfg->num_paths)))
2264 return 0;
2265 }
2266
2267 if (!bna_rit_mod_can_satisfy(&rx_mod->bna->rit_mod, rx_cfg->num_paths))
2268 return 0;
2269
2270 return 1;
2271}
2272
2273static struct bna_rxq *
2274_get_free_rxq(struct bna_rx_mod *rx_mod)
2275{
2276 struct bna_rxq *rxq = NULL;
2277 struct list_head *qe = NULL;
2278
2279 bfa_q_deq(&rx_mod->rxq_free_q, &qe);
2280 if (qe) {
2281 rx_mod->rxq_free_count--;
2282 rxq = (struct bna_rxq *)qe;
2283 }
2284 return rxq;
2285}
2286
2287static void
2288_put_free_rxq(struct bna_rx_mod *rx_mod, struct bna_rxq *rxq)
2289{
2290 bfa_q_qe_init(&rxq->qe);
2291 list_add_tail(&rxq->qe, &rx_mod->rxq_free_q);
2292 rx_mod->rxq_free_count++;
2293}
2294
2295static struct bna_rxp *
2296_get_free_rxp(struct bna_rx_mod *rx_mod)
2297{
2298 struct list_head *qe = NULL;
2299 struct bna_rxp *rxp = NULL;
2300
2301 bfa_q_deq(&rx_mod->rxp_free_q, &qe);
2302 if (qe) {
2303 rx_mod->rxp_free_count--;
2304
2305 rxp = (struct bna_rxp *)qe;
2306 }
2307
2308 return rxp;
2309}
2310
2311static void
2312_put_free_rxp(struct bna_rx_mod *rx_mod, struct bna_rxp *rxp)
2313{
2314 bfa_q_qe_init(&rxp->qe);
2315 list_add_tail(&rxp->qe, &rx_mod->rxp_free_q);
2316 rx_mod->rxp_free_count++;
2317}
2318
2319static struct bna_rx *
2320_get_free_rx(struct bna_rx_mod *rx_mod)
2321{
2322 struct list_head *qe = NULL;
2323 struct bna_rx *rx = NULL;
2324
2325 bfa_q_deq(&rx_mod->rx_free_q, &qe);
2326 if (qe) {
2327 rx_mod->rx_free_count--;
2328
2329 rx = (struct bna_rx *)qe;
2330 bfa_q_qe_init(qe);
2331 list_add_tail(&rx->qe, &rx_mod->rx_active_q);
2332 }
2333
2334 return rx;
2335}
2336
2337static void
2338_put_free_rx(struct bna_rx_mod *rx_mod, struct bna_rx *rx)
2339{
2340 bfa_q_qe_init(&rx->qe);
2341 list_add_tail(&rx->qe, &rx_mod->rx_free_q);
2342 rx_mod->rx_free_count++;
2343}
2344
2345static void
2346_rx_init(struct bna_rx *rx, struct bna *bna)
2347{
2348 rx->bna = bna;
2349 rx->rx_flags = 0;
2350
2351 INIT_LIST_HEAD(&rx->rxp_q);
2352
2353 rx->rxq_stop_wc.wc_resume = bna_rx_cb_rxq_stopped_all;
2354 rx->rxq_stop_wc.wc_cbarg = rx;
2355 rx->rxq_stop_wc.wc_count = 0;
2356
2357 rx->stop_cbfn = NULL;
2358 rx->stop_cbarg = NULL;
2359}
2360
2361static void
2362_rxp_add_rxqs(struct bna_rxp *rxp,
2363 struct bna_rxq *q0,
2364 struct bna_rxq *q1)
2365{
2366 switch (rxp->type) {
2367 case BNA_RXP_SINGLE:
2368 rxp->rxq.single.only = q0;
2369 rxp->rxq.single.reserved = NULL;
2370 break;
2371 case BNA_RXP_SLR:
2372 rxp->rxq.slr.large = q0;
2373 rxp->rxq.slr.small = q1;
2374 break;
2375 case BNA_RXP_HDS:
2376 rxp->rxq.hds.data = q0;
2377 rxp->rxq.hds.hdr = q1;
2378 break;
2379 default:
2380 break;
2381 }
2382}
2383
2384static void
2385_rxq_qpt_init(struct bna_rxq *rxq,
2386 struct bna_rxp *rxp,
2387 u32 page_count,
2388 u32 page_size,
2389 struct bna_mem_descr *qpt_mem,
2390 struct bna_mem_descr *swqpt_mem,
2391 struct bna_mem_descr *page_mem)
2392{
2393 int i;
2394
2395 rxq->qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb;
2396 rxq->qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb;
2397 rxq->qpt.kv_qpt_ptr = qpt_mem->kva;
2398 rxq->qpt.page_count = page_count;
2399 rxq->qpt.page_size = page_size;
2400
2401 rxq->rcb->sw_qpt = (void **) swqpt_mem->kva;
2402
2403 for (i = 0; i < rxq->qpt.page_count; i++) {
2404 rxq->rcb->sw_qpt[i] = page_mem[i].kva;
2405 ((struct bna_dma_addr *)rxq->qpt.kv_qpt_ptr)[i].lsb =
2406 page_mem[i].dma.lsb;
2407 ((struct bna_dma_addr *)rxq->qpt.kv_qpt_ptr)[i].msb =
2408 page_mem[i].dma.msb;
2409
2410 }
2411}
2412
2413static void
2414_rxp_cqpt_setup(struct bna_rxp *rxp,
2415 u32 page_count,
2416 u32 page_size,
2417 struct bna_mem_descr *qpt_mem,
2418 struct bna_mem_descr *swqpt_mem,
2419 struct bna_mem_descr *page_mem)
2420{
2421 int i;
2422
2423 rxp->cq.qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb;
2424 rxp->cq.qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb;
2425 rxp->cq.qpt.kv_qpt_ptr = qpt_mem->kva;
2426 rxp->cq.qpt.page_count = page_count;
2427 rxp->cq.qpt.page_size = page_size;
2428
2429 rxp->cq.ccb->sw_qpt = (void **) swqpt_mem->kva;
2430
2431 for (i = 0; i < rxp->cq.qpt.page_count; i++) {
2432 rxp->cq.ccb->sw_qpt[i] = page_mem[i].kva;
2433
2434 ((struct bna_dma_addr *)rxp->cq.qpt.kv_qpt_ptr)[i].lsb =
2435 page_mem[i].dma.lsb;
2436 ((struct bna_dma_addr *)rxp->cq.qpt.kv_qpt_ptr)[i].msb =
2437 page_mem[i].dma.msb;
2438
2439 }
2440}
2441
2442static void
2443_rx_add_rxp(struct bna_rx *rx, struct bna_rxp *rxp)
2444{
2445 list_add_tail(&rxp->qe, &rx->rxp_q);
2446}
2447
2448static void
2449_init_rxmod_queues(struct bna_rx_mod *rx_mod)
2450{
2451 INIT_LIST_HEAD(&rx_mod->rx_free_q);
2452 INIT_LIST_HEAD(&rx_mod->rxq_free_q);
2453 INIT_LIST_HEAD(&rx_mod->rxp_free_q);
2454 INIT_LIST_HEAD(&rx_mod->rx_active_q);
2455
2456 rx_mod->rx_free_count = 0;
2457 rx_mod->rxq_free_count = 0;
2458 rx_mod->rxp_free_count = 0;
2459}
2460
2461static void
2462_rx_ctor(struct bna_rx *rx, int id)
2463{
2464 bfa_q_qe_init(&rx->qe);
2465 INIT_LIST_HEAD(&rx->rxp_q);
2466 rx->bna = NULL;
2467
2468 rx->rxf.rxf_id = id;
2469
2470 /* FIXME: mbox_qe ctor()?? */
2471 bfa_q_qe_init(&rx->mbox_qe.qe);
2472
2473 rx->stop_cbfn = NULL;
2474 rx->stop_cbarg = NULL;
2475}
2476
2477void
2478bna_rx_cb_multi_rxq_stopped(void *arg, int status)
2479{
2480 struct bna_rxp *rxp = (struct bna_rxp *)arg;
2481
2482 bfa_wc_down(&rxp->rx->rxq_stop_wc);
2483}
2484
2485void
2486bna_rx_cb_rxq_stopped_all(void *arg)
2487{
2488 struct bna_rx *rx = (struct bna_rx *)arg;
2489
2490 bfa_fsm_send_event(rx, RX_E_RXQ_STOPPED);
2491}
2492
2493static void
2494bna_rx_mod_cb_rx_stopped(void *arg, struct bna_rx *rx,
2495 enum bna_cb_status status)
2496{
2497 struct bna_rx_mod *rx_mod = (struct bna_rx_mod *)arg;
2498
2499 bfa_wc_down(&rx_mod->rx_stop_wc);
2500}
2501
2502static void
2503bna_rx_mod_cb_rx_stopped_all(void *arg)
2504{
2505 struct bna_rx_mod *rx_mod = (struct bna_rx_mod *)arg;
2506
2507 if (rx_mod->stop_cbfn)
2508 rx_mod->stop_cbfn(&rx_mod->bna->port, BNA_CB_SUCCESS);
2509 rx_mod->stop_cbfn = NULL;
2510}
2511
2512static void
2513bna_rx_start(struct bna_rx *rx)
2514{
2515 rx->rx_flags |= BNA_RX_F_PORT_ENABLED;
2516 if (rx->rx_flags & BNA_RX_F_ENABLE)
2517 bfa_fsm_send_event(rx, RX_E_START);
2518}
2519
2520static void
2521bna_rx_stop(struct bna_rx *rx)
2522{
2523 rx->rx_flags &= ~BNA_RX_F_PORT_ENABLED;
2524 if (rx->fsm == (bfa_fsm_t) bna_rx_sm_stopped)
2525 bna_rx_mod_cb_rx_stopped(&rx->bna->rx_mod, rx, BNA_CB_SUCCESS);
2526 else {
2527 rx->stop_cbfn = bna_rx_mod_cb_rx_stopped;
2528 rx->stop_cbarg = &rx->bna->rx_mod;
2529 bfa_fsm_send_event(rx, RX_E_STOP);
2530 }
2531}
2532
2533static void
2534bna_rx_fail(struct bna_rx *rx)
2535{
2536 /* Indicate port is not enabled, and failed */
2537 rx->rx_flags &= ~BNA_RX_F_PORT_ENABLED;
2538 rx->rx_flags |= BNA_RX_F_PORT_FAILED;
2539 bfa_fsm_send_event(rx, RX_E_FAIL);
2540}
2541
2542void
2543bna_rx_mod_start(struct bna_rx_mod *rx_mod, enum bna_rx_type type)
2544{
2545 struct bna_rx *rx;
2546 struct list_head *qe;
2547
2548 rx_mod->flags |= BNA_RX_MOD_F_PORT_STARTED;
2549 if (type == BNA_RX_T_LOOPBACK)
2550 rx_mod->flags |= BNA_RX_MOD_F_PORT_LOOPBACK;
2551
2552 list_for_each(qe, &rx_mod->rx_active_q) {
2553 rx = (struct bna_rx *)qe;
2554 if (rx->type == type)
2555 bna_rx_start(rx);
2556 }
2557}
2558
2559void
2560bna_rx_mod_stop(struct bna_rx_mod *rx_mod, enum bna_rx_type type)
2561{
2562 struct bna_rx *rx;
2563 struct list_head *qe;
2564
2565 rx_mod->flags &= ~BNA_RX_MOD_F_PORT_STARTED;
2566 rx_mod->flags &= ~BNA_RX_MOD_F_PORT_LOOPBACK;
2567
2568 rx_mod->stop_cbfn = bna_port_cb_rx_stopped;
2569
2570 /**
2571 * Before calling bna_rx_stop(), increment rx_stop_wc as many times
2572 * as we are going to call bna_rx_stop
2573 */
2574 list_for_each(qe, &rx_mod->rx_active_q) {
2575 rx = (struct bna_rx *)qe;
2576 if (rx->type == type)
2577 bfa_wc_up(&rx_mod->rx_stop_wc);
2578 }
2579
2580 if (rx_mod->rx_stop_wc.wc_count == 0) {
2581 rx_mod->stop_cbfn(&rx_mod->bna->port, BNA_CB_SUCCESS);
2582 rx_mod->stop_cbfn = NULL;
2583 return;
2584 }
2585
2586 list_for_each(qe, &rx_mod->rx_active_q) {
2587 rx = (struct bna_rx *)qe;
2588 if (rx->type == type)
2589 bna_rx_stop(rx);
2590 }
2591}
2592
2593void
2594bna_rx_mod_fail(struct bna_rx_mod *rx_mod)
2595{
2596 struct bna_rx *rx;
2597 struct list_head *qe;
2598
2599 rx_mod->flags &= ~BNA_RX_MOD_F_PORT_STARTED;
2600 rx_mod->flags &= ~BNA_RX_MOD_F_PORT_LOOPBACK;
2601
2602 list_for_each(qe, &rx_mod->rx_active_q) {
2603 rx = (struct bna_rx *)qe;
2604 bna_rx_fail(rx);
2605 }
2606}
2607
2608void bna_rx_mod_init(struct bna_rx_mod *rx_mod, struct bna *bna,
2609 struct bna_res_info *res_info)
2610{
2611 int index;
2612 struct bna_rx *rx_ptr;
2613 struct bna_rxp *rxp_ptr;
2614 struct bna_rxq *rxq_ptr;
2615
2616 rx_mod->bna = bna;
2617 rx_mod->flags = 0;
2618
2619 rx_mod->rx = (struct bna_rx *)
2620 res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.mdl[0].kva;
2621 rx_mod->rxp = (struct bna_rxp *)
2622 res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.mdl[0].kva;
2623 rx_mod->rxq = (struct bna_rxq *)
2624 res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.mdl[0].kva;
2625
2626 /* Initialize the queues */
2627 _init_rxmod_queues(rx_mod);
2628
2629 /* Build RX queues */
2630 for (index = 0; index < BFI_MAX_RXQ; index++) {
2631 rx_ptr = &rx_mod->rx[index];
2632 _rx_ctor(rx_ptr, index);
2633 list_add_tail(&rx_ptr->qe, &rx_mod->rx_free_q);
2634 rx_mod->rx_free_count++;
2635 }
2636
2637 /* build RX-path queue */
2638 for (index = 0; index < BFI_MAX_RXQ; index++) {
2639 rxp_ptr = &rx_mod->rxp[index];
2640 rxp_ptr->cq.cq_id = index;
2641 bfa_q_qe_init(&rxp_ptr->qe);
2642 list_add_tail(&rxp_ptr->qe, &rx_mod->rxp_free_q);
2643 rx_mod->rxp_free_count++;
2644 }
2645
2646 /* build RXQ queue */
2647 for (index = 0; index < BFI_MAX_RXQ; index++) {
2648 rxq_ptr = &rx_mod->rxq[index];
2649 rxq_ptr->rxq_id = index;
2650
2651 bfa_q_qe_init(&rxq_ptr->qe);
2652 list_add_tail(&rxq_ptr->qe, &rx_mod->rxq_free_q);
2653 rx_mod->rxq_free_count++;
2654 }
2655
2656 rx_mod->rx_stop_wc.wc_resume = bna_rx_mod_cb_rx_stopped_all;
2657 rx_mod->rx_stop_wc.wc_cbarg = rx_mod;
2658 rx_mod->rx_stop_wc.wc_count = 0;
2659}
2660
2661void
2662bna_rx_mod_uninit(struct bna_rx_mod *rx_mod)
2663{
2664 struct list_head *qe;
2665 int i;
2666
2667 i = 0;
2668 list_for_each(qe, &rx_mod->rx_free_q)
2669 i++;
2670
2671 i = 0;
2672 list_for_each(qe, &rx_mod->rxp_free_q)
2673 i++;
2674
2675 i = 0;
2676 list_for_each(qe, &rx_mod->rxq_free_q)
2677 i++;
2678
2679 rx_mod->bna = NULL;
2680}
2681
2682int
2683bna_rx_state_get(struct bna_rx *rx)
2684{
2685 return bfa_sm_to_state(rx_sm_table, rx->fsm);
2686}
2687
2688void
2689bna_rx_res_req(struct bna_rx_config *q_cfg, struct bna_res_info *res_info)
2690{
2691 u32 cq_size, hq_size, dq_size;
2692 u32 cpage_count, hpage_count, dpage_count;
2693 struct bna_mem_info *mem_info;
2694 u32 cq_depth;
2695 u32 hq_depth;
2696 u32 dq_depth;
2697
2698 dq_depth = q_cfg->q_depth;
2699 hq_depth = ((q_cfg->rxp_type == BNA_RXP_SINGLE) ? 0 : q_cfg->q_depth);
2700 cq_depth = dq_depth + hq_depth;
2701
2702 BNA_TO_POWER_OF_2_HIGH(cq_depth);
2703 cq_size = cq_depth * BFI_CQ_WI_SIZE;
2704 cq_size = ALIGN(cq_size, PAGE_SIZE);
2705 cpage_count = SIZE_TO_PAGES(cq_size);
2706
2707 BNA_TO_POWER_OF_2_HIGH(dq_depth);
2708 dq_size = dq_depth * BFI_RXQ_WI_SIZE;
2709 dq_size = ALIGN(dq_size, PAGE_SIZE);
2710 dpage_count = SIZE_TO_PAGES(dq_size);
2711
2712 if (BNA_RXP_SINGLE != q_cfg->rxp_type) {
2713 BNA_TO_POWER_OF_2_HIGH(hq_depth);
2714 hq_size = hq_depth * BFI_RXQ_WI_SIZE;
2715 hq_size = ALIGN(hq_size, PAGE_SIZE);
2716 hpage_count = SIZE_TO_PAGES(hq_size);
2717 } else {
2718 hpage_count = 0;
2719 }
2720
2721 /* CCB structures */
2722 res_info[BNA_RX_RES_MEM_T_CCB].res_type = BNA_RES_T_MEM;
2723 mem_info = &res_info[BNA_RX_RES_MEM_T_CCB].res_u.mem_info;
2724 mem_info->mem_type = BNA_MEM_T_KVA;
2725 mem_info->len = sizeof(struct bna_ccb);
2726 mem_info->num = q_cfg->num_paths;
2727
2728 /* RCB structures */
2729 res_info[BNA_RX_RES_MEM_T_RCB].res_type = BNA_RES_T_MEM;
2730 mem_info = &res_info[BNA_RX_RES_MEM_T_RCB].res_u.mem_info;
2731 mem_info->mem_type = BNA_MEM_T_KVA;
2732 mem_info->len = sizeof(struct bna_rcb);
2733 mem_info->num = BNA_GET_RXQS(q_cfg);
2734
2735 /* Completion QPT */
2736 res_info[BNA_RX_RES_MEM_T_CQPT].res_type = BNA_RES_T_MEM;
2737 mem_info = &res_info[BNA_RX_RES_MEM_T_CQPT].res_u.mem_info;
2738 mem_info->mem_type = BNA_MEM_T_DMA;
2739 mem_info->len = cpage_count * sizeof(struct bna_dma_addr);
2740 mem_info->num = q_cfg->num_paths;
2741
2742 /* Completion s/w QPT */
2743 res_info[BNA_RX_RES_MEM_T_CSWQPT].res_type = BNA_RES_T_MEM;
2744 mem_info = &res_info[BNA_RX_RES_MEM_T_CSWQPT].res_u.mem_info;
2745 mem_info->mem_type = BNA_MEM_T_KVA;
2746 mem_info->len = cpage_count * sizeof(void *);
2747 mem_info->num = q_cfg->num_paths;
2748
2749 /* Completion QPT pages */
2750 res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_type = BNA_RES_T_MEM;
2751 mem_info = &res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info;
2752 mem_info->mem_type = BNA_MEM_T_DMA;
2753 mem_info->len = PAGE_SIZE;
2754 mem_info->num = cpage_count * q_cfg->num_paths;
2755
2756 /* Data QPTs */
2757 res_info[BNA_RX_RES_MEM_T_DQPT].res_type = BNA_RES_T_MEM;
2758 mem_info = &res_info[BNA_RX_RES_MEM_T_DQPT].res_u.mem_info;
2759 mem_info->mem_type = BNA_MEM_T_DMA;
2760 mem_info->len = dpage_count * sizeof(struct bna_dma_addr);
2761 mem_info->num = q_cfg->num_paths;
2762
2763 /* Data s/w QPTs */
2764 res_info[BNA_RX_RES_MEM_T_DSWQPT].res_type = BNA_RES_T_MEM;
2765 mem_info = &res_info[BNA_RX_RES_MEM_T_DSWQPT].res_u.mem_info;
2766 mem_info->mem_type = BNA_MEM_T_KVA;
2767 mem_info->len = dpage_count * sizeof(void *);
2768 mem_info->num = q_cfg->num_paths;
2769
2770 /* Data QPT pages */
2771 res_info[BNA_RX_RES_MEM_T_DPAGE].res_type = BNA_RES_T_MEM;
2772 mem_info = &res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info;
2773 mem_info->mem_type = BNA_MEM_T_DMA;
2774 mem_info->len = PAGE_SIZE;
2775 mem_info->num = dpage_count * q_cfg->num_paths;
2776
2777 /* Hdr QPTs */
2778 res_info[BNA_RX_RES_MEM_T_HQPT].res_type = BNA_RES_T_MEM;
2779 mem_info = &res_info[BNA_RX_RES_MEM_T_HQPT].res_u.mem_info;
2780 mem_info->mem_type = BNA_MEM_T_DMA;
2781 mem_info->len = hpage_count * sizeof(struct bna_dma_addr);
2782 mem_info->num = (hpage_count ? q_cfg->num_paths : 0);
2783
2784 /* Hdr s/w QPTs */
2785 res_info[BNA_RX_RES_MEM_T_HSWQPT].res_type = BNA_RES_T_MEM;
2786 mem_info = &res_info[BNA_RX_RES_MEM_T_HSWQPT].res_u.mem_info;
2787 mem_info->mem_type = BNA_MEM_T_KVA;
2788 mem_info->len = hpage_count * sizeof(void *);
2789 mem_info->num = (hpage_count ? q_cfg->num_paths : 0);
2790
2791 /* Hdr QPT pages */
2792 res_info[BNA_RX_RES_MEM_T_HPAGE].res_type = BNA_RES_T_MEM;
2793 mem_info = &res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info;
2794 mem_info->mem_type = BNA_MEM_T_DMA;
2795 mem_info->len = (hpage_count ? PAGE_SIZE : 0);
2796 mem_info->num = (hpage_count ? (hpage_count * q_cfg->num_paths) : 0);
2797
2798 /* RX Interrupts */
2799 res_info[BNA_RX_RES_T_INTR].res_type = BNA_RES_T_INTR;
2800 res_info[BNA_RX_RES_T_INTR].res_u.intr_info.intr_type = BNA_INTR_T_MSIX;
2801 res_info[BNA_RX_RES_T_INTR].res_u.intr_info.num = q_cfg->num_paths;
2802}
2803
2804struct bna_rx *
2805bna_rx_create(struct bna *bna, struct bnad *bnad,
2806 struct bna_rx_config *rx_cfg,
2807 struct bna_rx_event_cbfn *rx_cbfn,
2808 struct bna_res_info *res_info,
2809 void *priv)
2810{
2811 struct bna_rx_mod *rx_mod = &bna->rx_mod;
2812 struct bna_rx *rx;
2813 struct bna_rxp *rxp;
2814 struct bna_rxq *q0;
2815 struct bna_rxq *q1;
2816 struct bna_intr_info *intr_info;
2817 u32 page_count;
2818 struct bna_mem_descr *ccb_mem;
2819 struct bna_mem_descr *rcb_mem;
2820 struct bna_mem_descr *unmapq_mem;
2821 struct bna_mem_descr *cqpt_mem;
2822 struct bna_mem_descr *cswqpt_mem;
2823 struct bna_mem_descr *cpage_mem;
2824 struct bna_mem_descr *hqpt_mem; /* Header/Small Q qpt */
2825 struct bna_mem_descr *dqpt_mem; /* Data/Large Q qpt */
2826 struct bna_mem_descr *hsqpt_mem; /* s/w qpt for hdr */
2827 struct bna_mem_descr *dsqpt_mem; /* s/w qpt for data */
2828 struct bna_mem_descr *hpage_mem; /* hdr page mem */
2829 struct bna_mem_descr *dpage_mem; /* data page mem */
2830 int i, cpage_idx = 0, dpage_idx = 0, hpage_idx = 0;
2831 int dpage_count, hpage_count, rcb_idx;
2832 struct bna_ib_config ibcfg;
2833 /* Fail if we don't have enough RXPs, RXQs */
2834 if (!_rx_can_satisfy(rx_mod, rx_cfg))
2835 return NULL;
2836
2837 /* Initialize resource pointers */
2838 intr_info = &res_info[BNA_RX_RES_T_INTR].res_u.intr_info;
2839 ccb_mem = &res_info[BNA_RX_RES_MEM_T_CCB].res_u.mem_info.mdl[0];
2840 rcb_mem = &res_info[BNA_RX_RES_MEM_T_RCB].res_u.mem_info.mdl[0];
2841 unmapq_mem = &res_info[BNA_RX_RES_MEM_T_UNMAPQ].res_u.mem_info.mdl[0];
2842 cqpt_mem = &res_info[BNA_RX_RES_MEM_T_CQPT].res_u.mem_info.mdl[0];
2843 cswqpt_mem = &res_info[BNA_RX_RES_MEM_T_CSWQPT].res_u.mem_info.mdl[0];
2844 cpage_mem = &res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info.mdl[0];
2845 hqpt_mem = &res_info[BNA_RX_RES_MEM_T_HQPT].res_u.mem_info.mdl[0];
2846 dqpt_mem = &res_info[BNA_RX_RES_MEM_T_DQPT].res_u.mem_info.mdl[0];
2847 hsqpt_mem = &res_info[BNA_RX_RES_MEM_T_HSWQPT].res_u.mem_info.mdl[0];
2848 dsqpt_mem = &res_info[BNA_RX_RES_MEM_T_DSWQPT].res_u.mem_info.mdl[0];
2849 hpage_mem = &res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info.mdl[0];
2850 dpage_mem = &res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info.mdl[0];
2851
2852 /* Compute q depth & page count */
2853 page_count = res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info.num /
2854 rx_cfg->num_paths;
2855
2856 dpage_count = res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info.num /
2857 rx_cfg->num_paths;
2858
2859 hpage_count = res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info.num /
2860 rx_cfg->num_paths;
2861 /* Get RX pointer */
2862 rx = _get_free_rx(rx_mod);
2863 _rx_init(rx, bna);
2864 rx->priv = priv;
2865 rx->type = rx_cfg->rx_type;
2866
2867 rx->rcb_setup_cbfn = rx_cbfn->rcb_setup_cbfn;
2868 rx->rcb_destroy_cbfn = rx_cbfn->rcb_destroy_cbfn;
2869 rx->ccb_setup_cbfn = rx_cbfn->ccb_setup_cbfn;
2870 rx->ccb_destroy_cbfn = rx_cbfn->ccb_destroy_cbfn;
2871 /* Following callbacks are mandatory */
2872 rx->rx_cleanup_cbfn = rx_cbfn->rx_cleanup_cbfn;
2873 rx->rx_post_cbfn = rx_cbfn->rx_post_cbfn;
2874
2875 if (rx->bna->rx_mod.flags & BNA_RX_MOD_F_PORT_STARTED) {
2876 switch (rx->type) {
2877 case BNA_RX_T_REGULAR:
2878 if (!(rx->bna->rx_mod.flags &
2879 BNA_RX_MOD_F_PORT_LOOPBACK))
2880 rx->rx_flags |= BNA_RX_F_PORT_ENABLED;
2881 break;
2882 case BNA_RX_T_LOOPBACK:
2883 if (rx->bna->rx_mod.flags & BNA_RX_MOD_F_PORT_LOOPBACK)
2884 rx->rx_flags |= BNA_RX_F_PORT_ENABLED;
2885 break;
2886 }
2887 }
2888
2889 for (i = 0, rcb_idx = 0; i < rx_cfg->num_paths; i++) {
2890 rxp = _get_free_rxp(rx_mod);
2891 rxp->type = rx_cfg->rxp_type;
2892 rxp->rx = rx;
2893 rxp->cq.rx = rx;
2894
2895 /* Get required RXQs, and queue them to rx-path */
2896 q0 = _get_free_rxq(rx_mod);
2897 if (BNA_RXP_SINGLE == rx_cfg->rxp_type)
2898 q1 = NULL;
2899 else
2900 q1 = _get_free_rxq(rx_mod);
2901
2902 /* Initialize IB */
2903 if (1 == intr_info->num) {
2904 rxp->cq.ib = bna_ib_get(&bna->ib_mod,
2905 intr_info->intr_type,
2906 intr_info->idl[0].vector);
2907 rxp->vector = intr_info->idl[0].vector;
2908 } else {
2909 rxp->cq.ib = bna_ib_get(&bna->ib_mod,
2910 intr_info->intr_type,
2911 intr_info->idl[i].vector);
2912
2913 /* Map the MSI-x vector used for this RXP */
2914 rxp->vector = intr_info->idl[i].vector;
2915 }
2916
2917 rxp->cq.ib_seg_offset = bna_ib_reserve_idx(rxp->cq.ib);
2918
2919 ibcfg.coalescing_timeo = BFI_RX_COALESCING_TIMEO;
2920 ibcfg.interpkt_count = BFI_RX_INTERPKT_COUNT;
2921 ibcfg.interpkt_timeo = BFI_RX_INTERPKT_TIMEO;
2922 ibcfg.ctrl_flags = BFI_IB_CF_INT_ENABLE;
2923
2924 bna_ib_config(rxp->cq.ib, &ibcfg);
2925
2926 /* Link rxqs to rxp */
2927 _rxp_add_rxqs(rxp, q0, q1);
2928
2929 /* Link rxp to rx */
2930 _rx_add_rxp(rx, rxp);
2931
2932 q0->rx = rx;
2933 q0->rxp = rxp;
2934
2935 /* Initialize RCB for the large / data q */
2936 q0->rcb = (struct bna_rcb *) rcb_mem[rcb_idx].kva;
2937 RXQ_RCB_INIT(q0, rxp, rx_cfg->q_depth, bna, 0,
2938 (void *)unmapq_mem[rcb_idx].kva);
2939 rcb_idx++;
2940 (q0)->rx_packets = (q0)->rx_bytes = 0;
2941 (q0)->rx_packets_with_error = (q0)->rxbuf_alloc_failed = 0;
2942
2943 /* Initialize RXQs */
2944 _rxq_qpt_init(q0, rxp, dpage_count, PAGE_SIZE,
2945 &dqpt_mem[i], &dsqpt_mem[i], &dpage_mem[dpage_idx]);
2946 q0->rcb->page_idx = dpage_idx;
2947 q0->rcb->page_count = dpage_count;
2948 dpage_idx += dpage_count;
2949
2950 /* Call bnad to complete rcb setup */
2951 if (rx->rcb_setup_cbfn)
2952 rx->rcb_setup_cbfn(bnad, q0->rcb);
2953
2954 if (q1) {
2955 q1->rx = rx;
2956 q1->rxp = rxp;
2957
2958 q1->rcb = (struct bna_rcb *) rcb_mem[rcb_idx].kva;
2959 RXQ_RCB_INIT(q1, rxp, rx_cfg->q_depth, bna, 1,
2960 (void *)unmapq_mem[rcb_idx].kva);
2961 rcb_idx++;
2962 (q1)->buffer_size = (rx_cfg)->small_buff_size;
2963 (q1)->rx_packets = (q1)->rx_bytes = 0;
2964 (q1)->rx_packets_with_error =
2965 (q1)->rxbuf_alloc_failed = 0;
2966
2967 _rxq_qpt_init(q1, rxp, hpage_count, PAGE_SIZE,
2968 &hqpt_mem[i], &hsqpt_mem[i],
2969 &hpage_mem[hpage_idx]);
2970 q1->rcb->page_idx = hpage_idx;
2971 q1->rcb->page_count = hpage_count;
2972 hpage_idx += hpage_count;
2973
2974 /* Call bnad to complete rcb setup */
2975 if (rx->rcb_setup_cbfn)
2976 rx->rcb_setup_cbfn(bnad, q1->rcb);
2977 }
2978 /* Setup RXP::CQ */
2979 rxp->cq.ccb = (struct bna_ccb *) ccb_mem[i].kva;
2980 _rxp_cqpt_setup(rxp, page_count, PAGE_SIZE,
2981 &cqpt_mem[i], &cswqpt_mem[i], &cpage_mem[cpage_idx]);
2982 rxp->cq.ccb->page_idx = cpage_idx;
2983 rxp->cq.ccb->page_count = page_count;
2984 cpage_idx += page_count;
2985
2986 rxp->cq.ccb->pkt_rate.small_pkt_cnt = 0;
2987 rxp->cq.ccb->pkt_rate.large_pkt_cnt = 0;
2988
2989 rxp->cq.ccb->producer_index = 0;
2990 rxp->cq.ccb->q_depth = rx_cfg->q_depth +
2991 ((rx_cfg->rxp_type == BNA_RXP_SINGLE) ?
2992 0 : rx_cfg->q_depth);
2993 rxp->cq.ccb->i_dbell = &rxp->cq.ib->door_bell;
2994 rxp->cq.ccb->rcb[0] = q0->rcb;
2995 if (q1)
2996 rxp->cq.ccb->rcb[1] = q1->rcb;
2997 rxp->cq.ccb->cq = &rxp->cq;
2998 rxp->cq.ccb->bnad = bna->bnad;
2999 rxp->cq.ccb->hw_producer_index =
3000 ((volatile u32 *)rxp->cq.ib->ib_seg_host_addr_kva +
3001 (rxp->cq.ib_seg_offset * BFI_IBIDX_SIZE));
3002 *(rxp->cq.ccb->hw_producer_index) = 0;
3003 rxp->cq.ccb->intr_type = intr_info->intr_type;
3004 rxp->cq.ccb->intr_vector = (intr_info->num == 1) ?
3005 intr_info->idl[0].vector :
3006 intr_info->idl[i].vector;
3007 rxp->cq.ccb->rx_coalescing_timeo =
3008 rxp->cq.ib->ib_config.coalescing_timeo;
3009 rxp->cq.ccb->id = i;
3010
3011 /* Call bnad to complete CCB setup */
3012 if (rx->ccb_setup_cbfn)
3013 rx->ccb_setup_cbfn(bnad, rxp->cq.ccb);
3014
3015 } /* for each rx-path */
3016
3017 bna_rxf_init(&rx->rxf, rx, rx_cfg);
3018
3019 bfa_fsm_set_state(rx, bna_rx_sm_stopped);
3020
3021 return rx;
3022}
3023
3024void
3025bna_rx_destroy(struct bna_rx *rx)
3026{
3027 struct bna_rx_mod *rx_mod = &rx->bna->rx_mod;
3028 struct bna_ib_mod *ib_mod = &rx->bna->ib_mod;
3029 struct bna_rxq *q0 = NULL;
3030 struct bna_rxq *q1 = NULL;
3031 struct bna_rxp *rxp;
3032 struct list_head *qe;
3033
3034 bna_rxf_uninit(&rx->rxf);
3035
3036 while (!list_empty(&rx->rxp_q)) {
3037 bfa_q_deq(&rx->rxp_q, &rxp);
3038 GET_RXQS(rxp, q0, q1);
3039 /* Callback to bnad for destroying RCB */
3040 if (rx->rcb_destroy_cbfn)
3041 rx->rcb_destroy_cbfn(rx->bna->bnad, q0->rcb);
3042 q0->rcb = NULL;
3043 q0->rxp = NULL;
3044 q0->rx = NULL;
3045 _put_free_rxq(rx_mod, q0);
3046 if (q1) {
3047 /* Callback to bnad for destroying RCB */
3048 if (rx->rcb_destroy_cbfn)
3049 rx->rcb_destroy_cbfn(rx->bna->bnad, q1->rcb);
3050 q1->rcb = NULL;
3051 q1->rxp = NULL;
3052 q1->rx = NULL;
3053 _put_free_rxq(rx_mod, q1);
3054 }
3055 rxp->rxq.slr.large = NULL;
3056 rxp->rxq.slr.small = NULL;
3057 if (rxp->cq.ib) {
3058 if (rxp->cq.ib_seg_offset != 0xff)
3059 bna_ib_release_idx(rxp->cq.ib,
3060 rxp->cq.ib_seg_offset);
3061 bna_ib_put(ib_mod, rxp->cq.ib);
3062 rxp->cq.ib = NULL;
3063 }
3064 /* Callback to bnad for destroying CCB */
3065 if (rx->ccb_destroy_cbfn)
3066 rx->ccb_destroy_cbfn(rx->bna->bnad, rxp->cq.ccb);
3067 rxp->cq.ccb = NULL;
3068 rxp->rx = NULL;
3069 _put_free_rxp(rx_mod, rxp);
3070 }
3071
3072 list_for_each(qe, &rx_mod->rx_active_q) {
3073 if (qe == &rx->qe) {
3074 list_del(&rx->qe);
3075 bfa_q_qe_init(&rx->qe);
3076 break;
3077 }
3078 }
3079
3080 rx->bna = NULL;
3081 rx->priv = NULL;
3082 _put_free_rx(rx_mod, rx);
3083}
3084
3085void
3086bna_rx_enable(struct bna_rx *rx)
3087{
3088 if (rx->fsm != (bfa_sm_t)bna_rx_sm_stopped)
3089 return;
3090
3091 rx->rx_flags |= BNA_RX_F_ENABLE;
3092 if (rx->rx_flags & BNA_RX_F_PORT_ENABLED)
3093 bfa_fsm_send_event(rx, RX_E_START);
3094}
3095
3096void
3097bna_rx_disable(struct bna_rx *rx, enum bna_cleanup_type type,
3098 void (*cbfn)(void *, struct bna_rx *,
3099 enum bna_cb_status))
3100{
3101 if (type == BNA_SOFT_CLEANUP) {
3102 /* h/w should not be accessed. Treat we're stopped */
3103 (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
3104 } else {
3105 rx->stop_cbfn = cbfn;
3106 rx->stop_cbarg = rx->bna->bnad;
3107
3108 rx->rx_flags &= ~BNA_RX_F_ENABLE;
3109
3110 bfa_fsm_send_event(rx, RX_E_STOP);
3111 }
3112}
3113
3114/**
3115 * TX
3116 */
3117#define call_tx_stop_cbfn(tx, status)\
3118do {\
3119 if ((tx)->stop_cbfn)\
3120 (tx)->stop_cbfn((tx)->stop_cbarg, (tx), status);\
3121 (tx)->stop_cbfn = NULL;\
3122 (tx)->stop_cbarg = NULL;\
3123} while (0)
3124
3125#define call_tx_prio_change_cbfn(tx, status)\
3126do {\
3127 if ((tx)->prio_change_cbfn)\
3128 (tx)->prio_change_cbfn((tx)->bna->bnad, (tx), status);\
3129 (tx)->prio_change_cbfn = NULL;\
3130} while (0)
3131
3132static void bna_tx_mod_cb_tx_stopped(void *tx_mod, struct bna_tx *tx,
3133 enum bna_cb_status status);
3134static void bna_tx_cb_txq_stopped(void *arg, int status);
3135static void bna_tx_cb_stats_cleared(void *arg, int status);
3136static void __bna_tx_stop(struct bna_tx *tx);
3137static void __bna_tx_start(struct bna_tx *tx);
3138static void __bna_txf_stat_clr(struct bna_tx *tx);
3139
3140enum bna_tx_event {
3141 TX_E_START = 1,
3142 TX_E_STOP = 2,
3143 TX_E_FAIL = 3,
3144 TX_E_TXQ_STOPPED = 4,
3145 TX_E_PRIO_CHANGE = 5,
3146 TX_E_STAT_CLEARED = 6,
3147};
3148
3149enum bna_tx_state {
3150 BNA_TX_STOPPED = 1,
3151 BNA_TX_STARTED = 2,
3152 BNA_TX_TXQ_STOP_WAIT = 3,
3153 BNA_TX_PRIO_STOP_WAIT = 4,
3154 BNA_TX_STAT_CLR_WAIT = 5,
3155};
3156
3157bfa_fsm_state_decl(bna_tx, stopped, struct bna_tx,
3158 enum bna_tx_event);
3159bfa_fsm_state_decl(bna_tx, started, struct bna_tx,
3160 enum bna_tx_event);
3161bfa_fsm_state_decl(bna_tx, txq_stop_wait, struct bna_tx,
3162 enum bna_tx_event);
3163bfa_fsm_state_decl(bna_tx, prio_stop_wait, struct bna_tx,
3164 enum bna_tx_event);
3165bfa_fsm_state_decl(bna_tx, stat_clr_wait, struct bna_tx,
3166 enum bna_tx_event);
3167
3168static struct bfa_sm_table tx_sm_table[] = {
3169 {BFA_SM(bna_tx_sm_stopped), BNA_TX_STOPPED},
3170 {BFA_SM(bna_tx_sm_started), BNA_TX_STARTED},
3171 {BFA_SM(bna_tx_sm_txq_stop_wait), BNA_TX_TXQ_STOP_WAIT},
3172 {BFA_SM(bna_tx_sm_prio_stop_wait), BNA_TX_PRIO_STOP_WAIT},
3173 {BFA_SM(bna_tx_sm_stat_clr_wait), BNA_TX_STAT_CLR_WAIT},
3174};
3175
3176static void
3177bna_tx_sm_stopped_entry(struct bna_tx *tx)
3178{
3179 struct bna_txq *txq;
3180 struct list_head *qe;
3181
3182 list_for_each(qe, &tx->txq_q) {
3183 txq = (struct bna_txq *)qe;
3184 (tx->tx_cleanup_cbfn)(tx->bna->bnad, txq->tcb);
3185 }
3186
3187 call_tx_stop_cbfn(tx, BNA_CB_SUCCESS);
3188}
3189
3190static void
3191bna_tx_sm_stopped(struct bna_tx *tx, enum bna_tx_event event)
3192{
3193 switch (event) {
3194 case TX_E_START:
3195 bfa_fsm_set_state(tx, bna_tx_sm_started);
3196 break;
3197
3198 case TX_E_STOP:
3199 bfa_fsm_set_state(tx, bna_tx_sm_stopped);
3200 break;
3201
3202 case TX_E_FAIL:
3203 /* No-op */
3204 break;
3205
3206 case TX_E_PRIO_CHANGE:
3207 call_tx_prio_change_cbfn(tx, BNA_CB_SUCCESS);
3208 break;
3209
3210 case TX_E_TXQ_STOPPED:
3211 /**
3212 * This event is received due to flushing of mbox when
3213 * device fails
3214 */
3215 /* No-op */
3216 break;
3217
3218 default:
3219 bfa_sm_fault(event);
3220 }
3221}
3222
3223static void
3224bna_tx_sm_started_entry(struct bna_tx *tx)
3225{
3226 struct bna_txq *txq;
3227 struct list_head *qe;
3228
3229 __bna_tx_start(tx);
3230
3231 /* Start IB */
3232 list_for_each(qe, &tx->txq_q) {
3233 txq = (struct bna_txq *)qe;
3234 bna_ib_ack(&txq->ib->door_bell, 0);
3235 }
3236}
3237
3238static void
3239bna_tx_sm_started(struct bna_tx *tx, enum bna_tx_event event)
3240{
3241 struct bna_txq *txq;
3242 struct list_head *qe;
3243
3244 switch (event) {
3245 case TX_E_STOP:
3246 bfa_fsm_set_state(tx, bna_tx_sm_txq_stop_wait);
3247 __bna_tx_stop(tx);
3248 break;
3249
3250 case TX_E_FAIL:
3251 list_for_each(qe, &tx->txq_q) {
3252 txq = (struct bna_txq *)qe;
3253 bna_ib_fail(txq->ib);
3254 (tx->tx_stall_cbfn)(tx->bna->bnad, txq->tcb);
3255 }
3256 bfa_fsm_set_state(tx, bna_tx_sm_stopped);
3257 break;
3258
3259 case TX_E_PRIO_CHANGE:
3260 bfa_fsm_set_state(tx, bna_tx_sm_prio_stop_wait);
3261 break;
3262
3263 default:
3264 bfa_sm_fault(event);
3265 }
3266}
3267
3268static void
3269bna_tx_sm_txq_stop_wait_entry(struct bna_tx *tx)
3270{
3271}
3272
3273static void
3274bna_tx_sm_txq_stop_wait(struct bna_tx *tx, enum bna_tx_event event)
3275{
3276 struct bna_txq *txq;
3277 struct list_head *qe;
3278
3279 switch (event) {
3280 case TX_E_FAIL:
3281 bfa_fsm_set_state(tx, bna_tx_sm_stopped);
3282 break;
3283
3284 case TX_E_TXQ_STOPPED:
3285 list_for_each(qe, &tx->txq_q) {
3286 txq = (struct bna_txq *)qe;
3287 bna_ib_stop(txq->ib);
3288 }
3289 bfa_fsm_set_state(tx, bna_tx_sm_stat_clr_wait);
3290 break;
3291
3292 case TX_E_PRIO_CHANGE:
3293 /* No-op */
3294 break;
3295
3296 default:
3297 bfa_sm_fault(event);
3298 }
3299}
3300
3301static void
3302bna_tx_sm_prio_stop_wait_entry(struct bna_tx *tx)
3303{
3304 __bna_tx_stop(tx);
3305}
3306
3307static void
3308bna_tx_sm_prio_stop_wait(struct bna_tx *tx, enum bna_tx_event event)
3309{
3310 struct bna_txq *txq;
3311 struct list_head *qe;
3312
3313 switch (event) {
3314 case TX_E_STOP:
3315 bfa_fsm_set_state(tx, bna_tx_sm_txq_stop_wait);
3316 break;
3317
3318 case TX_E_FAIL:
3319 call_tx_prio_change_cbfn(tx, BNA_CB_FAIL);
3320 bfa_fsm_set_state(tx, bna_tx_sm_stopped);
3321 break;
3322
3323 case TX_E_TXQ_STOPPED:
3324 list_for_each(qe, &tx->txq_q) {
3325 txq = (struct bna_txq *)qe;
3326 bna_ib_stop(txq->ib);
3327 (tx->tx_cleanup_cbfn)(tx->bna->bnad, txq->tcb);
3328 }
3329 call_tx_prio_change_cbfn(tx, BNA_CB_SUCCESS);
3330 bfa_fsm_set_state(tx, bna_tx_sm_started);
3331 break;
3332
3333 case TX_E_PRIO_CHANGE:
3334 /* No-op */
3335 break;
3336
3337 default:
3338 bfa_sm_fault(event);
3339 }
3340}
3341
3342static void
3343bna_tx_sm_stat_clr_wait_entry(struct bna_tx *tx)
3344{
3345 __bna_txf_stat_clr(tx);
3346}
3347
3348static void
3349bna_tx_sm_stat_clr_wait(struct bna_tx *tx, enum bna_tx_event event)
3350{
3351 switch (event) {
3352 case TX_E_FAIL:
3353 case TX_E_STAT_CLEARED:
3354 bfa_fsm_set_state(tx, bna_tx_sm_stopped);
3355 break;
3356
3357 default:
3358 bfa_sm_fault(event);
3359 }
3360}
3361
3362static void
3363__bna_txq_start(struct bna_tx *tx, struct bna_txq *txq)
3364{
3365 struct bna_rxtx_q_mem *q_mem;
3366 struct bna_txq_mem txq_cfg;
3367 struct bna_txq_mem *txq_mem;
3368 struct bna_dma_addr cur_q_addr;
3369 u32 pg_num;
3370 void __iomem *base_addr;
3371 unsigned long off;
3372
3373 /* Fill out structure, to be subsequently written to hardware */
3374 txq_cfg.pg_tbl_addr_lo = txq->qpt.hw_qpt_ptr.lsb;
3375 txq_cfg.pg_tbl_addr_hi = txq->qpt.hw_qpt_ptr.msb;
3376 cur_q_addr = *((struct bna_dma_addr *)(txq->qpt.kv_qpt_ptr));
3377 txq_cfg.cur_q_entry_lo = cur_q_addr.lsb;
3378 txq_cfg.cur_q_entry_hi = cur_q_addr.msb;
3379
3380 txq_cfg.pg_cnt_n_prd_ptr = (txq->qpt.page_count << 16) | 0x0;
3381
3382 txq_cfg.entry_n_pg_size = ((u32)(BFI_TXQ_WI_SIZE >> 2) << 16) |
3383 (txq->qpt.page_size >> 2);
3384 txq_cfg.int_blk_n_cns_ptr = ((((u32)txq->ib_seg_offset) << 24) |
3385 ((u32)(txq->ib->ib_id & 0xff) << 16) | 0x0);
3386
3387 txq_cfg.cns_ptr2_n_q_state = BNA_Q_IDLE_STATE;
3388 txq_cfg.nxt_qid_n_fid_n_pri = (((tx->txf.txf_id & 0x3f) << 3) |
3389 (txq->priority & 0x7));
3390 txq_cfg.wvc_n_cquota_n_rquota =
3391 ((((u32)BFI_TX_MAX_WRR_QUOTA & 0xfff) << 12) |
3392 (BFI_TX_MAX_WRR_QUOTA & 0xfff));
3393
3394 /* Setup the page and write to H/W */
3395
3396 pg_num = BNA_GET_PAGE_NUM(HQM0_BLK_PG_NUM + tx->bna->port_num,
3397 HQM_RXTX_Q_RAM_BASE_OFFSET);
3398 writel(pg_num, tx->bna->regs.page_addr);
3399
3400 base_addr = BNA_GET_MEM_BASE_ADDR(tx->bna->pcidev.pci_bar_kva,
3401 HQM_RXTX_Q_RAM_BASE_OFFSET);
3402 q_mem = (struct bna_rxtx_q_mem *)0;
3403 txq_mem = &q_mem[txq->txq_id].txq;
3404
3405 /*
3406 * The following 4 lines, is a hack b'cos the H/W needs to read
3407 * these DMA addresses as little endian
3408 */
3409
3410 off = (unsigned long)&txq_mem->pg_tbl_addr_lo;
3411 writel(htonl(txq_cfg.pg_tbl_addr_lo), base_addr + off);
3412
3413 off = (unsigned long)&txq_mem->pg_tbl_addr_hi;
3414 writel(htonl(txq_cfg.pg_tbl_addr_hi), base_addr + off);
3415
3416 off = (unsigned long)&txq_mem->cur_q_entry_lo;
3417 writel(htonl(txq_cfg.cur_q_entry_lo), base_addr + off);
3418
3419 off = (unsigned long)&txq_mem->cur_q_entry_hi;
3420 writel(htonl(txq_cfg.cur_q_entry_hi), base_addr + off);
3421
3422 off = (unsigned long)&txq_mem->pg_cnt_n_prd_ptr;
3423 writel(txq_cfg.pg_cnt_n_prd_ptr, base_addr + off);
3424
3425 off = (unsigned long)&txq_mem->entry_n_pg_size;
3426 writel(txq_cfg.entry_n_pg_size, base_addr + off);
3427
3428 off = (unsigned long)&txq_mem->int_blk_n_cns_ptr;
3429 writel(txq_cfg.int_blk_n_cns_ptr, base_addr + off);
3430
3431 off = (unsigned long)&txq_mem->cns_ptr2_n_q_state;
3432 writel(txq_cfg.cns_ptr2_n_q_state, base_addr + off);
3433
3434 off = (unsigned long)&txq_mem->nxt_qid_n_fid_n_pri;
3435 writel(txq_cfg.nxt_qid_n_fid_n_pri, base_addr + off);
3436
3437 off = (unsigned long)&txq_mem->wvc_n_cquota_n_rquota;
3438 writel(txq_cfg.wvc_n_cquota_n_rquota, base_addr + off);
3439
3440 txq->tcb->producer_index = 0;
3441 txq->tcb->consumer_index = 0;
3442 *(txq->tcb->hw_consumer_index) = 0;
3443
3444}
3445
3446static void
3447__bna_txq_stop(struct bna_tx *tx, struct bna_txq *txq)
3448{
3449 struct bfi_ll_q_stop_req ll_req;
3450 u32 bit_mask[2] = {0, 0};
3451 if (txq->txq_id < 32)
3452 bit_mask[0] = (u32)1 << txq->txq_id;
3453 else
3454 bit_mask[1] = (u32)1 << (txq->txq_id - 32);
3455
3456 memset(&ll_req, 0, sizeof(ll_req));
3457 ll_req.mh.msg_class = BFI_MC_LL;
3458 ll_req.mh.msg_id = BFI_LL_H2I_TXQ_STOP_REQ;
3459 ll_req.mh.mtag.h2i.lpu_id = 0;
3460 ll_req.q_id_mask[0] = htonl(bit_mask[0]);
3461 ll_req.q_id_mask[1] = htonl(bit_mask[1]);
3462
3463 bna_mbox_qe_fill(&tx->mbox_qe, &ll_req, sizeof(ll_req),
3464 bna_tx_cb_txq_stopped, tx);
3465
3466 bna_mbox_send(tx->bna, &tx->mbox_qe);
3467}
3468
3469static void
3470__bna_txf_start(struct bna_tx *tx)
3471{
3472 struct bna_tx_fndb_ram *tx_fndb;
3473 struct bna_txf *txf = &tx->txf;
3474 void __iomem *base_addr;
3475 unsigned long off;
3476
3477 writel(BNA_GET_PAGE_NUM(LUT0_MEM_BLK_BASE_PG_NUM +
3478 (tx->bna->port_num * 2), TX_FNDB_RAM_BASE_OFFSET),
3479 tx->bna->regs.page_addr);
3480
3481 base_addr = BNA_GET_MEM_BASE_ADDR(tx->bna->pcidev.pci_bar_kva,
3482 TX_FNDB_RAM_BASE_OFFSET);
3483
3484 tx_fndb = (struct bna_tx_fndb_ram *)0;
3485 off = (unsigned long)&tx_fndb[txf->txf_id].vlan_n_ctrl_flags;
3486
3487 writel(((u32)txf->vlan << 16) | txf->ctrl_flags,
3488 base_addr + off);
3489
3490 if (tx->txf.txf_id < 32)
3491 tx->bna->tx_mod.txf_bmap[0] |= ((u32)1 << tx->txf.txf_id);
3492 else
3493 tx->bna->tx_mod.txf_bmap[1] |= ((u32)
3494 1 << (tx->txf.txf_id - 32));
3495}
3496
3497static void
3498__bna_txf_stop(struct bna_tx *tx)
3499{
3500 struct bna_tx_fndb_ram *tx_fndb;
3501 u32 page_num;
3502 u32 ctl_flags;
3503 struct bna_txf *txf = &tx->txf;
3504 void __iomem *base_addr;
3505 unsigned long off;
3506
3507 /* retrieve the running txf_flags & turn off enable bit */
3508 page_num = BNA_GET_PAGE_NUM(LUT0_MEM_BLK_BASE_PG_NUM +
3509 (tx->bna->port_num * 2), TX_FNDB_RAM_BASE_OFFSET);
3510 writel(page_num, tx->bna->regs.page_addr);
3511
3512 base_addr = BNA_GET_MEM_BASE_ADDR(tx->bna->pcidev.pci_bar_kva,
3513 TX_FNDB_RAM_BASE_OFFSET);
3514 tx_fndb = (struct bna_tx_fndb_ram *)0;
3515 off = (unsigned long)&tx_fndb[txf->txf_id].vlan_n_ctrl_flags;
3516
3517 ctl_flags = readl(base_addr + off);
3518 ctl_flags &= ~BFI_TXF_CF_ENABLE;
3519
3520 writel(ctl_flags, base_addr + off);
3521
3522 if (tx->txf.txf_id < 32)
3523 tx->bna->tx_mod.txf_bmap[0] &= ~((u32)1 << tx->txf.txf_id);
3524 else
3525 tx->bna->tx_mod.txf_bmap[0] &= ~((u32)
3526 1 << (tx->txf.txf_id - 32));
3527}
3528
3529static void
3530__bna_txf_stat_clr(struct bna_tx *tx)
3531{
3532 struct bfi_ll_stats_req ll_req;
3533 u32 txf_bmap[2] = {0, 0};
3534 if (tx->txf.txf_id < 32)
3535 txf_bmap[0] = ((u32)1 << tx->txf.txf_id);
3536 else
3537 txf_bmap[1] = ((u32)1 << (tx->txf.txf_id - 32));
3538 bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_STATS_CLEAR_REQ, 0);
3539 ll_req.stats_mask = 0;
3540 ll_req.rxf_id_mask[0] = 0;
3541 ll_req.rxf_id_mask[1] = 0;
3542 ll_req.txf_id_mask[0] = htonl(txf_bmap[0]);
3543 ll_req.txf_id_mask[1] = htonl(txf_bmap[1]);
3544
3545 bna_mbox_qe_fill(&tx->mbox_qe, &ll_req, sizeof(ll_req),
3546 bna_tx_cb_stats_cleared, tx);
3547 bna_mbox_send(tx->bna, &tx->mbox_qe);
3548}
3549
3550static void
3551__bna_tx_start(struct bna_tx *tx)
3552{
3553 struct bna_txq *txq;
3554 struct list_head *qe;
3555
3556 list_for_each(qe, &tx->txq_q) {
3557 txq = (struct bna_txq *)qe;
3558 bna_ib_start(txq->ib);
3559 __bna_txq_start(tx, txq);
3560 }
3561
3562 __bna_txf_start(tx);
3563
3564 list_for_each(qe, &tx->txq_q) {
3565 txq = (struct bna_txq *)qe;
3566 txq->tcb->priority = txq->priority;
3567 (tx->tx_resume_cbfn)(tx->bna->bnad, txq->tcb);
3568 }
3569}
3570
3571static void
3572__bna_tx_stop(struct bna_tx *tx)
3573{
3574 struct bna_txq *txq;
3575 struct list_head *qe;
3576
3577 list_for_each(qe, &tx->txq_q) {
3578 txq = (struct bna_txq *)qe;
3579 (tx->tx_stall_cbfn)(tx->bna->bnad, txq->tcb);
3580 }
3581
3582 __bna_txf_stop(tx);
3583
3584 list_for_each(qe, &tx->txq_q) {
3585 txq = (struct bna_txq *)qe;
3586 bfa_wc_up(&tx->txq_stop_wc);
3587 }
3588
3589 list_for_each(qe, &tx->txq_q) {
3590 txq = (struct bna_txq *)qe;
3591 __bna_txq_stop(tx, txq);
3592 }
3593}
3594
3595static void
3596bna_txq_qpt_setup(struct bna_txq *txq, int page_count, int page_size,
3597 struct bna_mem_descr *qpt_mem,
3598 struct bna_mem_descr *swqpt_mem,
3599 struct bna_mem_descr *page_mem)
3600{
3601 int i;
3602
3603 txq->qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb;
3604 txq->qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb;
3605 txq->qpt.kv_qpt_ptr = qpt_mem->kva;
3606 txq->qpt.page_count = page_count;
3607 txq->qpt.page_size = page_size;
3608
3609 txq->tcb->sw_qpt = (void **) swqpt_mem->kva;
3610
3611 for (i = 0; i < page_count; i++) {
3612 txq->tcb->sw_qpt[i] = page_mem[i].kva;
3613
3614 ((struct bna_dma_addr *)txq->qpt.kv_qpt_ptr)[i].lsb =
3615 page_mem[i].dma.lsb;
3616 ((struct bna_dma_addr *)txq->qpt.kv_qpt_ptr)[i].msb =
3617 page_mem[i].dma.msb;
3618
3619 }
3620}
3621
3622static void
3623bna_tx_free(struct bna_tx *tx)
3624{
3625 struct bna_tx_mod *tx_mod = &tx->bna->tx_mod;
3626 struct bna_txq *txq;
3627 struct bna_ib_mod *ib_mod = &tx->bna->ib_mod;
3628 struct list_head *qe;
3629
3630 while (!list_empty(&tx->txq_q)) {
3631 bfa_q_deq(&tx->txq_q, &txq);
3632 bfa_q_qe_init(&txq->qe);
3633 if (txq->ib) {
3634 if (txq->ib_seg_offset != -1)
3635 bna_ib_release_idx(txq->ib,
3636 txq->ib_seg_offset);
3637 bna_ib_put(ib_mod, txq->ib);
3638 txq->ib = NULL;
3639 }
3640 txq->tcb = NULL;
3641 txq->tx = NULL;
3642 list_add_tail(&txq->qe, &tx_mod->txq_free_q);
3643 }
3644
3645 list_for_each(qe, &tx_mod->tx_active_q) {
3646 if (qe == &tx->qe) {
3647 list_del(&tx->qe);
3648 bfa_q_qe_init(&tx->qe);
3649 break;
3650 }
3651 }
3652
3653 tx->bna = NULL;
3654 tx->priv = NULL;
3655 list_add_tail(&tx->qe, &tx_mod->tx_free_q);
3656}
3657
3658static void
3659bna_tx_cb_txq_stopped(void *arg, int status)
3660{
3661 struct bna_tx *tx = (struct bna_tx *)arg;
3662
3663 bfa_q_qe_init(&tx->mbox_qe.qe);
3664 bfa_wc_down(&tx->txq_stop_wc);
3665}
3666
3667static void
3668bna_tx_cb_txq_stopped_all(void *arg)
3669{
3670 struct bna_tx *tx = (struct bna_tx *)arg;
3671
3672 bfa_fsm_send_event(tx, TX_E_TXQ_STOPPED);
3673}
3674
3675static void
3676bna_tx_cb_stats_cleared(void *arg, int status)
3677{
3678 struct bna_tx *tx = (struct bna_tx *)arg;
3679
3680 bfa_q_qe_init(&tx->mbox_qe.qe);
3681
3682 bfa_fsm_send_event(tx, TX_E_STAT_CLEARED);
3683}
3684
3685static void
3686bna_tx_start(struct bna_tx *tx)
3687{
3688 tx->flags |= BNA_TX_F_PORT_STARTED;
3689 if (tx->flags & BNA_TX_F_ENABLED)
3690 bfa_fsm_send_event(tx, TX_E_START);
3691}
3692
3693static void
3694bna_tx_stop(struct bna_tx *tx)
3695{
3696 tx->stop_cbfn = bna_tx_mod_cb_tx_stopped;
3697 tx->stop_cbarg = &tx->bna->tx_mod;
3698
3699 tx->flags &= ~BNA_TX_F_PORT_STARTED;
3700 bfa_fsm_send_event(tx, TX_E_STOP);
3701}
3702
3703static void
3704bna_tx_fail(struct bna_tx *tx)
3705{
3706 tx->flags &= ~BNA_TX_F_PORT_STARTED;
3707 bfa_fsm_send_event(tx, TX_E_FAIL);
3708}
3709
3710static void
3711bna_tx_prio_changed(struct bna_tx *tx, int prio)
3712{
3713 struct bna_txq *txq;
3714 struct list_head *qe;
3715
3716 list_for_each(qe, &tx->txq_q) {
3717 txq = (struct bna_txq *)qe;
3718 txq->priority = prio;
3719 }
3720
3721 bfa_fsm_send_event(tx, TX_E_PRIO_CHANGE);
3722}
3723
3724static void
3725bna_tx_cee_link_status(struct bna_tx *tx, int cee_link)
3726{
3727 if (cee_link)
3728 tx->flags |= BNA_TX_F_PRIO_LOCK;
3729 else
3730 tx->flags &= ~BNA_TX_F_PRIO_LOCK;
3731}
3732
3733static void
3734bna_tx_mod_cb_tx_stopped(void *arg, struct bna_tx *tx,
3735 enum bna_cb_status status)
3736{
3737 struct bna_tx_mod *tx_mod = (struct bna_tx_mod *)arg;
3738
3739 bfa_wc_down(&tx_mod->tx_stop_wc);
3740}
3741
3742static void
3743bna_tx_mod_cb_tx_stopped_all(void *arg)
3744{
3745 struct bna_tx_mod *tx_mod = (struct bna_tx_mod *)arg;
3746
3747 if (tx_mod->stop_cbfn)
3748 tx_mod->stop_cbfn(&tx_mod->bna->port, BNA_CB_SUCCESS);
3749 tx_mod->stop_cbfn = NULL;
3750}
3751
3752void
3753bna_tx_res_req(int num_txq, int txq_depth, struct bna_res_info *res_info)
3754{
3755 u32 q_size;
3756 u32 page_count;
3757 struct bna_mem_info *mem_info;
3758
3759 res_info[BNA_TX_RES_MEM_T_TCB].res_type = BNA_RES_T_MEM;
3760 mem_info = &res_info[BNA_TX_RES_MEM_T_TCB].res_u.mem_info;
3761 mem_info->mem_type = BNA_MEM_T_KVA;
3762 mem_info->len = sizeof(struct bna_tcb);
3763 mem_info->num = num_txq;
3764
3765 q_size = txq_depth * BFI_TXQ_WI_SIZE;
3766 q_size = ALIGN(q_size, PAGE_SIZE);
3767 page_count = q_size >> PAGE_SHIFT;
3768
3769 res_info[BNA_TX_RES_MEM_T_QPT].res_type = BNA_RES_T_MEM;
3770 mem_info = &res_info[BNA_TX_RES_MEM_T_QPT].res_u.mem_info;
3771 mem_info->mem_type = BNA_MEM_T_DMA;
3772 mem_info->len = page_count * sizeof(struct bna_dma_addr);
3773 mem_info->num = num_txq;
3774
3775 res_info[BNA_TX_RES_MEM_T_SWQPT].res_type = BNA_RES_T_MEM;
3776 mem_info = &res_info[BNA_TX_RES_MEM_T_SWQPT].res_u.mem_info;
3777 mem_info->mem_type = BNA_MEM_T_KVA;
3778 mem_info->len = page_count * sizeof(void *);
3779 mem_info->num = num_txq;
3780
3781 res_info[BNA_TX_RES_MEM_T_PAGE].res_type = BNA_RES_T_MEM;
3782 mem_info = &res_info[BNA_TX_RES_MEM_T_PAGE].res_u.mem_info;
3783 mem_info->mem_type = BNA_MEM_T_DMA;
3784 mem_info->len = PAGE_SIZE;
3785 mem_info->num = num_txq * page_count;
3786
3787 res_info[BNA_TX_RES_INTR_T_TXCMPL].res_type = BNA_RES_T_INTR;
3788 res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info.intr_type =
3789 BNA_INTR_T_MSIX;
3790 res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info.num = num_txq;
3791}
3792
3793struct bna_tx *
3794bna_tx_create(struct bna *bna, struct bnad *bnad,
3795 struct bna_tx_config *tx_cfg,
3796 struct bna_tx_event_cbfn *tx_cbfn,
3797 struct bna_res_info *res_info, void *priv)
3798{
3799 struct bna_intr_info *intr_info;
3800 struct bna_tx_mod *tx_mod = &bna->tx_mod;
3801 struct bna_tx *tx;
3802 struct bna_txq *txq;
3803 struct list_head *qe;
3804 struct bna_ib_mod *ib_mod = &bna->ib_mod;
3805 struct bna_doorbell_qset *qset;
3806 struct bna_ib_config ib_config;
3807 int page_count;
3808 int page_size;
3809 int page_idx;
3810 int i;
3811 unsigned long off;
3812
3813 intr_info = &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info;
3814 page_count = (res_info[BNA_TX_RES_MEM_T_PAGE].res_u.mem_info.num) /
3815 tx_cfg->num_txq;
3816 page_size = res_info[BNA_TX_RES_MEM_T_PAGE].res_u.mem_info.len;
3817
3818 /**
3819 * Get resources
3820 */
3821
3822 if ((intr_info->num != 1) && (intr_info->num != tx_cfg->num_txq))
3823 return NULL;
3824
3825 /* Tx */
3826
3827 if (list_empty(&tx_mod->tx_free_q))
3828 return NULL;
3829 bfa_q_deq(&tx_mod->tx_free_q, &tx);
3830 bfa_q_qe_init(&tx->qe);
3831
3832 /* TxQs */
3833
3834 INIT_LIST_HEAD(&tx->txq_q);
3835 for (i = 0; i < tx_cfg->num_txq; i++) {
3836 if (list_empty(&tx_mod->txq_free_q))
3837 goto err_return;
3838
3839 bfa_q_deq(&tx_mod->txq_free_q, &txq);
3840 bfa_q_qe_init(&txq->qe);
3841 list_add_tail(&txq->qe, &tx->txq_q);
3842 txq->ib = NULL;
3843 txq->ib_seg_offset = -1;
3844 txq->tx = tx;
3845 }
3846
3847 /* IBs */
3848 i = 0;
3849 list_for_each(qe, &tx->txq_q) {
3850 txq = (struct bna_txq *)qe;
3851
3852 if (intr_info->num == 1)
3853 txq->ib = bna_ib_get(ib_mod, intr_info->intr_type,
3854 intr_info->idl[0].vector);
3855 else
3856 txq->ib = bna_ib_get(ib_mod, intr_info->intr_type,
3857 intr_info->idl[i].vector);
3858
3859 if (txq->ib == NULL)
3860 goto err_return;
3861
3862 txq->ib_seg_offset = bna_ib_reserve_idx(txq->ib);
3863 if (txq->ib_seg_offset == -1)
3864 goto err_return;
3865
3866 i++;
3867 }
3868
3869 /*
3870 * Initialize
3871 */
3872
3873 /* Tx */
3874
3875 tx->tcb_setup_cbfn = tx_cbfn->tcb_setup_cbfn;
3876 tx->tcb_destroy_cbfn = tx_cbfn->tcb_destroy_cbfn;
3877 /* Following callbacks are mandatory */
3878 tx->tx_stall_cbfn = tx_cbfn->tx_stall_cbfn;
3879 tx->tx_resume_cbfn = tx_cbfn->tx_resume_cbfn;
3880 tx->tx_cleanup_cbfn = tx_cbfn->tx_cleanup_cbfn;
3881
3882 list_add_tail(&tx->qe, &tx_mod->tx_active_q);
3883 tx->bna = bna;
3884 tx->priv = priv;
3885 tx->txq_stop_wc.wc_resume = bna_tx_cb_txq_stopped_all;
3886 tx->txq_stop_wc.wc_cbarg = tx;
3887 tx->txq_stop_wc.wc_count = 0;
3888
3889 tx->type = tx_cfg->tx_type;
3890
3891 tx->flags = 0;
3892 if (tx->bna->tx_mod.flags & BNA_TX_MOD_F_PORT_STARTED) {
3893 switch (tx->type) {
3894 case BNA_TX_T_REGULAR:
3895 if (!(tx->bna->tx_mod.flags &
3896 BNA_TX_MOD_F_PORT_LOOPBACK))
3897 tx->flags |= BNA_TX_F_PORT_STARTED;
3898 break;
3899 case BNA_TX_T_LOOPBACK:
3900 if (tx->bna->tx_mod.flags & BNA_TX_MOD_F_PORT_LOOPBACK)
3901 tx->flags |= BNA_TX_F_PORT_STARTED;
3902 break;
3903 }
3904 }
3905 if (tx->bna->tx_mod.cee_link)
3906 tx->flags |= BNA_TX_F_PRIO_LOCK;
3907
3908 /* TxQ */
3909
3910 i = 0;
3911 page_idx = 0;
3912 list_for_each(qe, &tx->txq_q) {
3913 txq = (struct bna_txq *)qe;
3914 txq->priority = tx_mod->priority;
3915 txq->tcb = (struct bna_tcb *)
3916 res_info[BNA_TX_RES_MEM_T_TCB].res_u.mem_info.mdl[i].kva;
3917 txq->tx_packets = 0;
3918 txq->tx_bytes = 0;
3919
3920 /* IB */
3921
3922 ib_config.coalescing_timeo = BFI_TX_COALESCING_TIMEO;
3923 ib_config.interpkt_timeo = 0; /* Not used */
3924 ib_config.interpkt_count = BFI_TX_INTERPKT_COUNT;
3925 ib_config.ctrl_flags = (BFI_IB_CF_INTER_PKT_DMA |
3926 BFI_IB_CF_INT_ENABLE |
3927 BFI_IB_CF_COALESCING_MODE);
3928 bna_ib_config(txq->ib, &ib_config);
3929
3930 /* TCB */
3931
3932 txq->tcb->producer_index = 0;
3933 txq->tcb->consumer_index = 0;
3934 txq->tcb->hw_consumer_index = (volatile u32 *)
3935 ((volatile u8 *)txq->ib->ib_seg_host_addr_kva +
3936 (txq->ib_seg_offset * BFI_IBIDX_SIZE));
3937 *(txq->tcb->hw_consumer_index) = 0;
3938 txq->tcb->q_depth = tx_cfg->txq_depth;
3939 txq->tcb->unmap_q = (void *)
3940 res_info[BNA_TX_RES_MEM_T_UNMAPQ].res_u.mem_info.mdl[i].kva;
3941 qset = (struct bna_doorbell_qset *)0;
3942 off = (unsigned long)&qset[txq->txq_id].txq[0];
3943 txq->tcb->q_dbell = off +
3944 BNA_GET_DOORBELL_BASE_ADDR(bna->pcidev.pci_bar_kva);
3945 txq->tcb->i_dbell = &txq->ib->door_bell;
3946 txq->tcb->intr_type = intr_info->intr_type;
3947 txq->tcb->intr_vector = (intr_info->num == 1) ?
3948 intr_info->idl[0].vector :
3949 intr_info->idl[i].vector;
3950 txq->tcb->txq = txq;
3951 txq->tcb->bnad = bnad;
3952 txq->tcb->id = i;
3953
3954 /* QPT, SWQPT, Pages */
3955 bna_txq_qpt_setup(txq, page_count, page_size,
3956 &res_info[BNA_TX_RES_MEM_T_QPT].res_u.mem_info.mdl[i],
3957 &res_info[BNA_TX_RES_MEM_T_SWQPT].res_u.mem_info.mdl[i],
3958 &res_info[BNA_TX_RES_MEM_T_PAGE].
3959 res_u.mem_info.mdl[page_idx]);
3960 txq->tcb->page_idx = page_idx;
3961 txq->tcb->page_count = page_count;
3962 page_idx += page_count;
3963
3964 /* Callback to bnad for setting up TCB */
3965 if (tx->tcb_setup_cbfn)
3966 (tx->tcb_setup_cbfn)(bna->bnad, txq->tcb);
3967
3968 i++;
3969 }
3970
3971 /* TxF */
3972
3973 tx->txf.ctrl_flags = BFI_TXF_CF_ENABLE | BFI_TXF_CF_VLAN_WI_BASED;
3974 tx->txf.vlan = 0;
3975
3976 /* Mbox element */
3977 bfa_q_qe_init(&tx->mbox_qe.qe);
3978
3979 bfa_fsm_set_state(tx, bna_tx_sm_stopped);
3980
3981 return tx;
3982
3983err_return:
3984 bna_tx_free(tx);
3985 return NULL;
3986}
3987
3988void
3989bna_tx_destroy(struct bna_tx *tx)
3990{
3991 /* Callback to bnad for destroying TCB */
3992 if (tx->tcb_destroy_cbfn) {
3993 struct bna_txq *txq;
3994 struct list_head *qe;
3995
3996 list_for_each(qe, &tx->txq_q) {
3997 txq = (struct bna_txq *)qe;
3998 (tx->tcb_destroy_cbfn)(tx->bna->bnad, txq->tcb);
3999 }
4000 }
4001
4002 bna_tx_free(tx);
4003}
4004
4005void
4006bna_tx_enable(struct bna_tx *tx)
4007{
4008 if (tx->fsm != (bfa_sm_t)bna_tx_sm_stopped)
4009 return;
4010
4011 tx->flags |= BNA_TX_F_ENABLED;
4012
4013 if (tx->flags & BNA_TX_F_PORT_STARTED)
4014 bfa_fsm_send_event(tx, TX_E_START);
4015}
4016
4017void
4018bna_tx_disable(struct bna_tx *tx, enum bna_cleanup_type type,
4019 void (*cbfn)(void *, struct bna_tx *, enum bna_cb_status))
4020{
4021 if (type == BNA_SOFT_CLEANUP) {
4022 (*cbfn)(tx->bna->bnad, tx, BNA_CB_SUCCESS);
4023 return;
4024 }
4025
4026 tx->stop_cbfn = cbfn;
4027 tx->stop_cbarg = tx->bna->bnad;
4028
4029 tx->flags &= ~BNA_TX_F_ENABLED;
4030
4031 bfa_fsm_send_event(tx, TX_E_STOP);
4032}
4033
4034int
4035bna_tx_state_get(struct bna_tx *tx)
4036{
4037 return bfa_sm_to_state(tx_sm_table, tx->fsm);
4038}
4039
4040void
4041bna_tx_mod_init(struct bna_tx_mod *tx_mod, struct bna *bna,
4042 struct bna_res_info *res_info)
4043{
4044 int i;
4045
4046 tx_mod->bna = bna;
4047 tx_mod->flags = 0;
4048
4049 tx_mod->tx = (struct bna_tx *)
4050 res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.mdl[0].kva;
4051 tx_mod->txq = (struct bna_txq *)
4052 res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.mdl[0].kva;
4053
4054 INIT_LIST_HEAD(&tx_mod->tx_free_q);
4055 INIT_LIST_HEAD(&tx_mod->tx_active_q);
4056
4057 INIT_LIST_HEAD(&tx_mod->txq_free_q);
4058
4059 for (i = 0; i < BFI_MAX_TXQ; i++) {
4060 tx_mod->tx[i].txf.txf_id = i;
4061 bfa_q_qe_init(&tx_mod->tx[i].qe);
4062 list_add_tail(&tx_mod->tx[i].qe, &tx_mod->tx_free_q);
4063
4064 tx_mod->txq[i].txq_id = i;
4065 bfa_q_qe_init(&tx_mod->txq[i].qe);
4066 list_add_tail(&tx_mod->txq[i].qe, &tx_mod->txq_free_q);
4067 }
4068
4069 tx_mod->tx_stop_wc.wc_resume = bna_tx_mod_cb_tx_stopped_all;
4070 tx_mod->tx_stop_wc.wc_cbarg = tx_mod;
4071 tx_mod->tx_stop_wc.wc_count = 0;
4072}
4073
4074void
4075bna_tx_mod_uninit(struct bna_tx_mod *tx_mod)
4076{
4077 struct list_head *qe;
4078 int i;
4079
4080 i = 0;
4081 list_for_each(qe, &tx_mod->tx_free_q)
4082 i++;
4083
4084 i = 0;
4085 list_for_each(qe, &tx_mod->txq_free_q)
4086 i++;
4087
4088 tx_mod->bna = NULL;
4089}
4090
4091void
4092bna_tx_mod_start(struct bna_tx_mod *tx_mod, enum bna_tx_type type)
4093{
4094 struct bna_tx *tx;
4095 struct list_head *qe;
4096
4097 tx_mod->flags |= BNA_TX_MOD_F_PORT_STARTED;
4098 if (type == BNA_TX_T_LOOPBACK)
4099 tx_mod->flags |= BNA_TX_MOD_F_PORT_LOOPBACK;
4100
4101 list_for_each(qe, &tx_mod->tx_active_q) {
4102 tx = (struct bna_tx *)qe;
4103 if (tx->type == type)
4104 bna_tx_start(tx);
4105 }
4106}
4107
4108void
4109bna_tx_mod_stop(struct bna_tx_mod *tx_mod, enum bna_tx_type type)
4110{
4111 struct bna_tx *tx;
4112 struct list_head *qe;
4113
4114 tx_mod->flags &= ~BNA_TX_MOD_F_PORT_STARTED;
4115 tx_mod->flags &= ~BNA_TX_MOD_F_PORT_LOOPBACK;
4116
4117 tx_mod->stop_cbfn = bna_port_cb_tx_stopped;
4118
4119 /**
4120 * Before calling bna_tx_stop(), increment tx_stop_wc as many times
4121 * as we are going to call bna_tx_stop
4122 */
4123 list_for_each(qe, &tx_mod->tx_active_q) {
4124 tx = (struct bna_tx *)qe;
4125 if (tx->type == type)
4126 bfa_wc_up(&tx_mod->tx_stop_wc);
4127 }
4128
4129 if (tx_mod->tx_stop_wc.wc_count == 0) {
4130 tx_mod->stop_cbfn(&tx_mod->bna->port, BNA_CB_SUCCESS);
4131 tx_mod->stop_cbfn = NULL;
4132 return;
4133 }
4134
4135 list_for_each(qe, &tx_mod->tx_active_q) {
4136 tx = (struct bna_tx *)qe;
4137 if (tx->type == type)
4138 bna_tx_stop(tx);
4139 }
4140}
4141
4142void
4143bna_tx_mod_fail(struct bna_tx_mod *tx_mod)
4144{
4145 struct bna_tx *tx;
4146 struct list_head *qe;
4147
4148 tx_mod->flags &= ~BNA_TX_MOD_F_PORT_STARTED;
4149 tx_mod->flags &= ~BNA_TX_MOD_F_PORT_LOOPBACK;
4150
4151 list_for_each(qe, &tx_mod->tx_active_q) {
4152 tx = (struct bna_tx *)qe;
4153 bna_tx_fail(tx);
4154 }
4155}
4156
4157void
4158bna_tx_mod_prio_changed(struct bna_tx_mod *tx_mod, int prio)
4159{
4160 struct bna_tx *tx;
4161 struct list_head *qe;
4162
4163 if (prio != tx_mod->priority) {
4164 tx_mod->priority = prio;
4165
4166 list_for_each(qe, &tx_mod->tx_active_q) {
4167 tx = (struct bna_tx *)qe;
4168 bna_tx_prio_changed(tx, prio);
4169 }
4170 }
4171}
4172
4173void
4174bna_tx_mod_cee_link_status(struct bna_tx_mod *tx_mod, int cee_link)
4175{
4176 struct bna_tx *tx;
4177 struct list_head *qe;
4178
4179 tx_mod->cee_link = cee_link;
4180
4181 list_for_each(qe, &tx_mod->tx_active_q) {
4182 tx = (struct bna_tx *)qe;
4183 bna_tx_cee_link_status(tx, cee_link);
4184 }
4185}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-03 01:03:27 -0500