diff options
author | Florian Fainelli <florian@openwrt.org> | 2012-04-11 03:18:38 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2012-04-12 16:06:24 -0400 |
commit | 2fa15bbdd8a1ac096819df29db8d69b063752bee (patch) | |
tree | 250b5b9033bf3064f140bcc6b6693fd6d33b03d3 /drivers/net/ethernet | |
parent | 0db0cfcc4ddff3226c8c721760b6a4eaf0e5229a (diff) |
r6040: add a MAC operation timeout define
2048 is the usual value for busy-waiting on a register r/w, define it
as MAC_DEF_TIMEOUT and use it where it is appropriate.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet')
-rw-r--r-- | drivers/net/ethernet/rdc/r6040.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/net/ethernet/rdc/r6040.c b/drivers/net/ethernet/rdc/r6040.c index fa2959689d87..9ffbf6e39b32 100644 --- a/drivers/net/ethernet/rdc/r6040.c +++ b/drivers/net/ethernet/rdc/r6040.c | |||
@@ -137,6 +137,8 @@ | |||
137 | #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */ | 137 | #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */ |
138 | #define MCAST_MAX 3 /* Max number multicast addresses to filter */ | 138 | #define MCAST_MAX 3 /* Max number multicast addresses to filter */ |
139 | 139 | ||
140 | #define MAC_DEF_TIMEOUT 2048 /* Default MAC read/write operation timeout */ | ||
141 | |||
140 | /* Descriptor status */ | 142 | /* Descriptor status */ |
141 | #define DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */ | 143 | #define DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */ |
142 | #define DSC_RX_OK 0x4000 /* RX was successful */ | 144 | #define DSC_RX_OK 0x4000 /* RX was successful */ |
@@ -204,7 +206,7 @@ static char version[] __devinitdata = DRV_NAME | |||
204 | /* Read a word data from PHY Chip */ | 206 | /* Read a word data from PHY Chip */ |
205 | static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg) | 207 | static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg) |
206 | { | 208 | { |
207 | int limit = 2048; | 209 | int limit = MAC_DEF_TIMEOUT; |
208 | u16 cmd; | 210 | u16 cmd; |
209 | 211 | ||
210 | iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO); | 212 | iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO); |
@@ -222,7 +224,7 @@ static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg) | |||
222 | static void r6040_phy_write(void __iomem *ioaddr, | 224 | static void r6040_phy_write(void __iomem *ioaddr, |
223 | int phy_addr, int reg, u16 val) | 225 | int phy_addr, int reg, u16 val) |
224 | { | 226 | { |
225 | int limit = 2048; | 227 | int limit = MAC_DEF_TIMEOUT; |
226 | u16 cmd; | 228 | u16 cmd; |
227 | 229 | ||
228 | iowrite16(val, ioaddr + MMWD); | 230 | iowrite16(val, ioaddr + MMWD); |
@@ -361,7 +363,7 @@ err_exit: | |||
361 | static void r6040_reset_mac(struct r6040_private *lp) | 363 | static void r6040_reset_mac(struct r6040_private *lp) |
362 | { | 364 | { |
363 | void __iomem *ioaddr = lp->base; | 365 | void __iomem *ioaddr = lp->base; |
364 | int limit = 2048; | 366 | int limit = MAC_DEF_TIMEOUT; |
365 | u16 cmd; | 367 | u16 cmd; |
366 | 368 | ||
367 | iowrite16(MAC_RST, ioaddr + MCR1); | 369 | iowrite16(MAC_RST, ioaddr + MCR1); |