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authorJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-05-12 23:21:07 -0400
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-08-10 23:04:03 -0400
commitae150435b59e68de00546330241727f2fec54517 (patch)
tree29a1cb71053306e8a8e0dff1f927d16a9a396917 /drivers/net/ethernet
parentaa43c2158d5ae1dc76cccb08cd57a3ffd32c3825 (diff)
smsc: Move the SMC (SMSC) drivers
Moves the SMC (SMSC) drivers into drivers/net/ethernet/smsc/ and the necessary Kconfig and Makefile changes. Also did some cleanup of NET_VENDOR_SMC Kconfig tag for the 8390 based drivers. CC: Nicolas Pitre <nico@fluxnic.net> CC: Donald Becker <becker@scyld.com> CC: Erik Stahlman <erik@vt.edu> CC: Dustin McIntire <dustin@sensoria.com> CC: Steve Glendinning <steve.glendinning@smsc.com> CC: David Hinds <dahinds@users.sourceforge.net> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ethernet')
-rw-r--r--drivers/net/ethernet/8390/Kconfig21
-rw-r--r--drivers/net/ethernet/Kconfig1
-rw-r--r--drivers/net/ethernet/Makefile1
-rw-r--r--drivers/net/ethernet/smsc/Kconfig131
-rw-r--r--drivers/net/ethernet/smsc/Makefile11
-rw-r--r--drivers/net/ethernet/smsc/epic100.c1609
-rw-r--r--drivers/net/ethernet/smsc/smc911x.c2210
-rw-r--r--drivers/net/ethernet/smsc/smc911x.h924
-rw-r--r--drivers/net/ethernet/smsc/smc9194.c1589
-rw-r--r--drivers/net/ethernet/smsc/smc9194.h241
-rw-r--r--drivers/net/ethernet/smsc/smc91c92_cs.c2070
-rw-r--r--drivers/net/ethernet/smsc/smc91x.c2431
-rw-r--r--drivers/net/ethernet/smsc/smc91x.h1180
-rw-r--r--drivers/net/ethernet/smsc/smsc911x.c2404
-rw-r--r--drivers/net/ethernet/smsc/smsc911x.h404
-rw-r--r--drivers/net/ethernet/smsc/smsc9420.c1763
-rw-r--r--drivers/net/ethernet/smsc/smsc9420.h276
17 files changed, 17249 insertions, 17 deletions
diff --git a/drivers/net/ethernet/8390/Kconfig b/drivers/net/ethernet/8390/Kconfig
index 5cd53f1b84d3..f1b9bddc1550 100644
--- a/drivers/net/ethernet/8390/Kconfig
+++ b/drivers/net/ethernet/8390/Kconfig
@@ -264,22 +264,9 @@ config STNIC
264 264
265 If unsure, say N. 265 If unsure, say N.
266 266
267config NET_VENDOR_SMC
268 bool "Western Digital/SMC cards"
269 depends on (ISA || MCA || EISA || MAC)
270 ---help---
271 If you have a network (Ethernet) card belonging to this class, say Y
272 and read the Ethernet-HOWTO, available from
273 <http://www.tldp.org/docs.html#howto>.
274
275 Note that the answer to this question doesn't directly affect the
276 kernel: saying N will just cause the configurator to skip all
277 the questions about Western Digital cards. If you say Y, you will be
278 asked for your specific card in the following questions.
279
280config ULTRAMCA 267config ULTRAMCA
281 tristate "SMC Ultra MCA support" 268 tristate "SMC Ultra MCA support"
282 depends on NET_VENDOR_SMC && MCA 269 depends on MCA
283 select CRC32 270 select CRC32
284 ---help--- 271 ---help---
285 If you have a network (Ethernet) card of this type and are running 272 If you have a network (Ethernet) card of this type and are running
@@ -291,7 +278,7 @@ config ULTRAMCA
291 278
292config ULTRA 279config ULTRA
293 tristate "SMC Ultra support" 280 tristate "SMC Ultra support"
294 depends on NET_VENDOR_SMC && ISA 281 depends on ISA
295 select CRC32 282 select CRC32
296 ---help--- 283 ---help---
297 If you have a network (Ethernet) card of this type, say Y and read 284 If you have a network (Ethernet) card of this type, say Y and read
@@ -310,7 +297,7 @@ config ULTRA
310 297
311config ULTRA32 298config ULTRA32
312 tristate "SMC Ultra32 EISA support" 299 tristate "SMC Ultra32 EISA support"
313 depends on NET_VENDOR_SMC && EISA 300 depends on EISA
314 select CRC32 301 select CRC32
315 ---help--- 302 ---help---
316 If you have a network (Ethernet) card of this type, say Y and read 303 If you have a network (Ethernet) card of this type, say Y and read
@@ -322,7 +309,7 @@ config ULTRA32
322 309
323config WD80x3 310config WD80x3
324 tristate "WD80*3 support" 311 tristate "WD80*3 support"
325 depends on NET_VENDOR_SMC && ISA 312 depends on ISA
326 select CRC32 313 select CRC32
327 ---help--- 314 ---help---
328 If you have a network (Ethernet) card of this type, say Y and read 315 If you have a network (Ethernet) card of this type, say Y and read
diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
index ab591bb96702..ed5836ccb8d6 100644
--- a/drivers/net/ethernet/Kconfig
+++ b/drivers/net/ethernet/Kconfig
@@ -18,5 +18,6 @@ source "drivers/net/ethernet/broadcom/Kconfig"
18source "drivers/net/ethernet/chelsio/Kconfig" 18source "drivers/net/ethernet/chelsio/Kconfig"
19source "drivers/net/ethernet/intel/Kconfig" 19source "drivers/net/ethernet/intel/Kconfig"
20source "drivers/net/ethernet/qlogic/Kconfig" 20source "drivers/net/ethernet/qlogic/Kconfig"
21source "drivers/net/ethernet/smsc/Kconfig"
21 22
22endif # ETHERNET 23endif # ETHERNET
diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
index d8cf120e3322..983fd2752151 100644
--- a/drivers/net/ethernet/Makefile
+++ b/drivers/net/ethernet/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_NET_VENDOR_BROADCOM) += broadcom/
9obj-$(CONFIG_NET_VENDOR_CHELSIO) += chelsio/ 9obj-$(CONFIG_NET_VENDOR_CHELSIO) += chelsio/
10obj-$(CONFIG_NET_VENDOR_INTEL) += intel/ 10obj-$(CONFIG_NET_VENDOR_INTEL) += intel/
11obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/ 11obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
12obj-$(CONFIG_NET_VENDOR_SMSC) += smsc/
diff --git a/drivers/net/ethernet/smsc/Kconfig b/drivers/net/ethernet/smsc/Kconfig
new file mode 100644
index 000000000000..702efe686c48
--- /dev/null
+++ b/drivers/net/ethernet/smsc/Kconfig
@@ -0,0 +1,131 @@
1#
2# Western Digital/SMC network device configuration
3#
4
5config NET_VENDOR_SMSC
6 bool "SMC (SMSC)/Western Digital devices"
7 depends on ARM || ISA || MAC || ARM || MIPS || M32R || SUPERH || \
8 BLACKFIN || MN10300 || COLDFIRE || PCI || PCMCIA
9 ---help---
10 If you have a network (Ethernet) card belonging to this class, say Y
11 and read the Ethernet-HOWTO, available from
12 <http://www.tldp.org/docs.html#howto>.
13
14 Note that the answer to this question doesn't directly affect the
15 kernel: saying N will just cause the configurator to skip all
16 the questions about SMC/Western Digital cards. If you say Y, you will
17 be asked for your specific card in the following questions.
18
19if NET_VENDOR_SMSC
20
21config SMC9194
22 tristate "SMC 9194 support"
23 depends on (ISA || MAC && BROKEN)
24 select CRC32
25 ---help---
26 This is support for the SMC9xxx based Ethernet cards. Choose this
27 option if you have a DELL laptop with the docking station, or
28 another SMC9192/9194 based chipset. Say Y if you want it compiled
29 into the kernel, and read the file
30 <file:Documentation/networking/smc9.txt> and the Ethernet-HOWTO,
31 available from <http://www.tldp.org/docs.html#howto>.
32
33 To compile this driver as a module, choose M here. The module
34 will be called smc9194.
35
36config SMC91X
37 tristate "SMC 91C9x/91C1xxx support"
38 select CRC32
39 select MII
40 depends on (ARM || M32R || SUPERH || MIPS || BLACKFIN || \
41 MN10300 || COLDFIRE)
42 ---help---
43 This is a driver for SMC's 91x series of Ethernet chipsets,
44 including the SMC91C94 and the SMC91C111. Say Y if you want it
45 compiled into the kernel, and read the file
46 <file:Documentation/networking/smc9.txt> and the Ethernet-HOWTO,
47 available from <http://www.tldp.org/docs.html#howto>.
48
49 This driver is also available as a module ( = code which can be
50 inserted in and removed from the running kernel whenever you want).
51 The module will be called smc91x. If you want to compile it as a
52 module, say M here and read <file:Documentation/kbuild/modules.txt>.
53
54config PCMCIA_SMC91C92
55 tristate "SMC 91Cxx PCMCIA support"
56 depends on PCMCIA
57 select CRC32
58 select MII
59 ---help---
60 Say Y here if you intend to attach an SMC 91Cxx compatible PCMCIA
61 (PC-card) Ethernet or Fast Ethernet card to your computer.
62
63 To compile this driver as a module, choose M here: the module will be
64 called smc91c92_cs. If unsure, say N.
65
66config EPIC100
67 tristate "SMC EtherPower II"
68 depends on PCI
69 select CRC32
70 select MII
71 ---help---
72 This driver is for the SMC EtherPower II 9432 PCI Ethernet NIC,
73 which is based on the SMC83c17x (EPIC/100).
74 More specific information and updates are available from
75 <http://www.scyld.com/network/epic100.html>.
76
77config SMC911X
78 tristate "SMSC LAN911[5678] support"
79 select CRC32
80 select MII
81 depends on (ARM || SUPERH || MN10300)
82 ---help---
83 This is a driver for SMSC's LAN911x series of Ethernet chipsets
84 including the new LAN9115, LAN9116, LAN9117, and LAN9118.
85 Say Y if you want it compiled into the kernel,
86 and read the Ethernet-HOWTO, available from
87 <http://www.tldp.org/docs.html#howto>.
88
89 This driver is also available as a module. The module will be
90 called smc911x. If you want to compile it as a module, say M
91 here and read <file:Documentation/kbuild/modules.txt>
92
93config SMSC911X
94 tristate "SMSC LAN911x/LAN921x families embedded ethernet support"
95 depends on (ARM || SUPERH || BLACKFIN || MIPS || MN10300)
96 select CRC32
97 select MII
98 select PHYLIB
99 ---help---
100 Say Y here if you want support for SMSC LAN911x and LAN921x families
101 of ethernet controllers.
102
103 To compile this driver as a module, choose M here and read
104 <file:Documentation/networking/net-modules.txt>. The module
105 will be called smsc911x.
106
107config SMSC911X_ARCH_HOOKS
108 def_bool n
109 depends on SMSC911X
110 ---help---
111 If the arch enables this, it allows the arch to implement various
112 hooks for more comprehensive interrupt control and also to override
113 the source of the MAC address.
114
115config SMSC9420
116 tristate "SMSC LAN9420 PCI ethernet adapter support"
117 depends on PCI
118 select CRC32
119 select PHYLIB
120 select SMSC_PHY
121 ---help---
122 This is a driver for SMSC's LAN9420 PCI ethernet adapter.
123 Say Y if you want it compiled into the kernel,
124 and read the Ethernet-HOWTO, available from
125 <http://www.tldp.org/docs.html#howto>.
126
127 This driver is also available as a module. The module will be
128 called smsc9420. If you want to compile it as a module, say M
129 here and read <file:Documentation/kbuild/modules.txt>
130
131endif # NET_VENDOR_SMSC
diff --git a/drivers/net/ethernet/smsc/Makefile b/drivers/net/ethernet/smsc/Makefile
new file mode 100644
index 000000000000..f3438dec9d90
--- /dev/null
+++ b/drivers/net/ethernet/smsc/Makefile
@@ -0,0 +1,11 @@
1#
2# Makefile for the SMSC network device drivers.
3#
4
5obj-$(CONFIG_SMC9194) += smc9194.o
6obj-$(CONFIG_SMC91X) += smc91x.o
7obj-$(CONFIG_PCMCIA_SMC91C92) += smc91c92_cs.o
8obj-$(CONFIG_EPIC100) += epic100.o
9obj-$(CONFIG_SMSC9420) += smsc9420.o
10obj-$(CONFIG_SMC911X) += smc911x.o
11obj-$(CONFIG_SMSC911X) += smsc911x.o
diff --git a/drivers/net/ethernet/smsc/epic100.c b/drivers/net/ethernet/smsc/epic100.c
new file mode 100644
index 000000000000..814c187d5f95
--- /dev/null
+++ b/drivers/net/ethernet/smsc/epic100.c
@@ -0,0 +1,1609 @@
1/* epic100.c: A SMC 83c170 EPIC/100 Fast Ethernet driver for Linux. */
2/*
3 Written/copyright 1997-2001 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 This driver is for the SMC83c170/175 "EPIC" series, as used on the
13 SMC EtherPower II 9432 PCI adapter, and several CardBus cards.
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20 Information and updates available at
21 http://www.scyld.com/network/epic100.html
22 [this link no longer provides anything useful -jgarzik]
23
24 ---------------------------------------------------------------------
25
26*/
27
28#define DRV_NAME "epic100"
29#define DRV_VERSION "2.1"
30#define DRV_RELDATE "Sept 11, 2006"
31
32/* The user-configurable values.
33 These may be modified when a driver module is loaded.*/
34
35static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
36
37/* Used to pass the full-duplex flag, etc. */
38#define MAX_UNITS 8 /* More are supported, limit only on options */
39static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
40static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
41
42/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
43 Setting to > 1518 effectively disables this feature. */
44static int rx_copybreak;
45
46/* Operational parameters that are set at compile time. */
47
48/* Keep the ring sizes a power of two for operational efficiency.
49 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
50 Making the Tx ring too large decreases the effectiveness of channel
51 bonding and packet priority.
52 There are no ill effects from too-large receive rings. */
53#define TX_RING_SIZE 256
54#define TX_QUEUE_LEN 240 /* Limit ring entries actually used. */
55#define RX_RING_SIZE 256
56#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct epic_tx_desc)
57#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct epic_rx_desc)
58
59/* Operational parameters that usually are not changed. */
60/* Time in jiffies before concluding the transmitter is hung. */
61#define TX_TIMEOUT (2*HZ)
62
63#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
64
65/* Bytes transferred to chip before transmission starts. */
66/* Initial threshold, increased on underflow, rounded down to 4 byte units. */
67#define TX_FIFO_THRESH 256
68#define RX_FIFO_THRESH 1 /* 0-3, 0==32, 64,96, or 3==128 bytes */
69
70#include <linux/module.h>
71#include <linux/kernel.h>
72#include <linux/string.h>
73#include <linux/timer.h>
74#include <linux/errno.h>
75#include <linux/ioport.h>
76#include <linux/interrupt.h>
77#include <linux/pci.h>
78#include <linux/delay.h>
79#include <linux/netdevice.h>
80#include <linux/etherdevice.h>
81#include <linux/skbuff.h>
82#include <linux/init.h>
83#include <linux/spinlock.h>
84#include <linux/ethtool.h>
85#include <linux/mii.h>
86#include <linux/crc32.h>
87#include <linux/bitops.h>
88#include <asm/io.h>
89#include <asm/uaccess.h>
90#include <asm/byteorder.h>
91
92/* These identify the driver base version and may not be removed. */
93static char version[] __devinitdata =
94DRV_NAME ".c:v1.11 1/7/2001 Written by Donald Becker <becker@scyld.com>\n";
95static char version2[] __devinitdata =
96" (unofficial 2.4.x kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n";
97
98MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
99MODULE_DESCRIPTION("SMC 83c170 EPIC series Ethernet driver");
100MODULE_LICENSE("GPL");
101
102module_param(debug, int, 0);
103module_param(rx_copybreak, int, 0);
104module_param_array(options, int, NULL, 0);
105module_param_array(full_duplex, int, NULL, 0);
106MODULE_PARM_DESC(debug, "EPIC/100 debug level (0-5)");
107MODULE_PARM_DESC(options, "EPIC/100: Bits 0-3: media type, bit 4: full duplex");
108MODULE_PARM_DESC(rx_copybreak, "EPIC/100 copy breakpoint for copy-only-tiny-frames");
109MODULE_PARM_DESC(full_duplex, "EPIC/100 full duplex setting(s) (1)");
110
111/*
112 Theory of Operation
113
114I. Board Compatibility
115
116This device driver is designed for the SMC "EPIC/100", the SMC
117single-chip Ethernet controllers for PCI. This chip is used on
118the SMC EtherPower II boards.
119
120II. Board-specific settings
121
122PCI bus devices are configured by the system at boot time, so no jumpers
123need to be set on the board. The system BIOS will assign the
124PCI INTA signal to a (preferably otherwise unused) system IRQ line.
125Note: Kernel versions earlier than 1.3.73 do not support shared PCI
126interrupt lines.
127
128III. Driver operation
129
130IIIa. Ring buffers
131
132IVb. References
133
134http://www.smsc.com/media/Downloads_Public/discontinued/83c171.pdf
135http://www.smsc.com/media/Downloads_Public/discontinued/83c175.pdf
136http://scyld.com/expert/NWay.html
137http://www.national.com/pf/DP/DP83840A.html
138
139IVc. Errata
140
141*/
142
143
144enum chip_capability_flags { MII_PWRDWN=1, TYPE2_INTR=2, NO_MII=4 };
145
146#define EPIC_TOTAL_SIZE 0x100
147#define USE_IO_OPS 1
148
149typedef enum {
150 SMSC_83C170_0,
151 SMSC_83C170,
152 SMSC_83C175,
153} chip_t;
154
155
156struct epic_chip_info {
157 const char *name;
158 int drv_flags; /* Driver use, intended as capability flags. */
159};
160
161
162/* indexed by chip_t */
163static const struct epic_chip_info pci_id_tbl[] = {
164 { "SMSC EPIC/100 83c170", TYPE2_INTR | NO_MII | MII_PWRDWN },
165 { "SMSC EPIC/100 83c170", TYPE2_INTR },
166 { "SMSC EPIC/C 83c175", TYPE2_INTR | MII_PWRDWN },
167};
168
169
170static DEFINE_PCI_DEVICE_TABLE(epic_pci_tbl) = {
171 { 0x10B8, 0x0005, 0x1092, 0x0AB4, 0, 0, SMSC_83C170_0 },
172 { 0x10B8, 0x0005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMSC_83C170 },
173 { 0x10B8, 0x0006, PCI_ANY_ID, PCI_ANY_ID,
174 PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, SMSC_83C175 },
175 { 0,}
176};
177MODULE_DEVICE_TABLE (pci, epic_pci_tbl);
178
179
180#ifndef USE_IO_OPS
181#undef inb
182#undef inw
183#undef inl
184#undef outb
185#undef outw
186#undef outl
187#define inb readb
188#define inw readw
189#define inl readl
190#define outb writeb
191#define outw writew
192#define outl writel
193#endif
194
195/* Offsets to registers, using the (ugh) SMC names. */
196enum epic_registers {
197 COMMAND=0, INTSTAT=4, INTMASK=8, GENCTL=0x0C, NVCTL=0x10, EECTL=0x14,
198 PCIBurstCnt=0x18,
199 TEST1=0x1C, CRCCNT=0x20, ALICNT=0x24, MPCNT=0x28, /* Rx error counters. */
200 MIICtrl=0x30, MIIData=0x34, MIICfg=0x38,
201 LAN0=64, /* MAC address. */
202 MC0=80, /* Multicast filter table. */
203 RxCtrl=96, TxCtrl=112, TxSTAT=0x74,
204 PRxCDAR=0x84, RxSTAT=0xA4, EarlyRx=0xB0, PTxCDAR=0xC4, TxThresh=0xDC,
205};
206
207/* Interrupt register bits, using my own meaningful names. */
208enum IntrStatus {
209 TxIdle=0x40000, RxIdle=0x20000, IntrSummary=0x010000,
210 PCIBusErr170=0x7000, PCIBusErr175=0x1000, PhyEvent175=0x8000,
211 RxStarted=0x0800, RxEarlyWarn=0x0400, CntFull=0x0200, TxUnderrun=0x0100,
212 TxEmpty=0x0080, TxDone=0x0020, RxError=0x0010,
213 RxOverflow=0x0008, RxFull=0x0004, RxHeader=0x0002, RxDone=0x0001,
214};
215enum CommandBits {
216 StopRx=1, StartRx=2, TxQueued=4, RxQueued=8,
217 StopTxDMA=0x20, StopRxDMA=0x40, RestartTx=0x80,
218};
219
220#define EpicRemoved 0xffffffff /* Chip failed or removed (CardBus) */
221
222#define EpicNapiEvent (TxEmpty | TxDone | \
223 RxDone | RxStarted | RxEarlyWarn | RxOverflow | RxFull)
224#define EpicNormalEvent (0x0000ffff & ~EpicNapiEvent)
225
226static const u16 media2miictl[16] = {
227 0, 0x0C00, 0x0C00, 0x2000, 0x0100, 0x2100, 0, 0,
228 0, 0, 0, 0, 0, 0, 0, 0 };
229
230/*
231 * The EPIC100 Rx and Tx buffer descriptors. Note that these
232 * really ARE host-endian; it's not a misannotation. We tell
233 * the card to byteswap them internally on big-endian hosts -
234 * look for #ifdef __BIG_ENDIAN in epic_open().
235 */
236
237struct epic_tx_desc {
238 u32 txstatus;
239 u32 bufaddr;
240 u32 buflength;
241 u32 next;
242};
243
244struct epic_rx_desc {
245 u32 rxstatus;
246 u32 bufaddr;
247 u32 buflength;
248 u32 next;
249};
250
251enum desc_status_bits {
252 DescOwn=0x8000,
253};
254
255#define PRIV_ALIGN 15 /* Required alignment mask */
256struct epic_private {
257 struct epic_rx_desc *rx_ring;
258 struct epic_tx_desc *tx_ring;
259 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
260 struct sk_buff* tx_skbuff[TX_RING_SIZE];
261 /* The addresses of receive-in-place skbuffs. */
262 struct sk_buff* rx_skbuff[RX_RING_SIZE];
263
264 dma_addr_t tx_ring_dma;
265 dma_addr_t rx_ring_dma;
266
267 /* Ring pointers. */
268 spinlock_t lock; /* Group with Tx control cache line. */
269 spinlock_t napi_lock;
270 struct napi_struct napi;
271 unsigned int reschedule_in_poll;
272 unsigned int cur_tx, dirty_tx;
273
274 unsigned int cur_rx, dirty_rx;
275 u32 irq_mask;
276 unsigned int rx_buf_sz; /* Based on MTU+slack. */
277
278 struct pci_dev *pci_dev; /* PCI bus location. */
279 int chip_id, chip_flags;
280
281 struct timer_list timer; /* Media selection timer. */
282 int tx_threshold;
283 unsigned char mc_filter[8];
284 signed char phys[4]; /* MII device addresses. */
285 u16 advertising; /* NWay media advertisement */
286 int mii_phy_cnt;
287 struct mii_if_info mii;
288 unsigned int tx_full:1; /* The Tx queue is full. */
289 unsigned int default_port:4; /* Last dev->if_port value. */
290};
291
292static int epic_open(struct net_device *dev);
293static int read_eeprom(long ioaddr, int location);
294static int mdio_read(struct net_device *dev, int phy_id, int location);
295static void mdio_write(struct net_device *dev, int phy_id, int loc, int val);
296static void epic_restart(struct net_device *dev);
297static void epic_timer(unsigned long data);
298static void epic_tx_timeout(struct net_device *dev);
299static void epic_init_ring(struct net_device *dev);
300static netdev_tx_t epic_start_xmit(struct sk_buff *skb,
301 struct net_device *dev);
302static int epic_rx(struct net_device *dev, int budget);
303static int epic_poll(struct napi_struct *napi, int budget);
304static irqreturn_t epic_interrupt(int irq, void *dev_instance);
305static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
306static const struct ethtool_ops netdev_ethtool_ops;
307static int epic_close(struct net_device *dev);
308static struct net_device_stats *epic_get_stats(struct net_device *dev);
309static void set_rx_mode(struct net_device *dev);
310
311static const struct net_device_ops epic_netdev_ops = {
312 .ndo_open = epic_open,
313 .ndo_stop = epic_close,
314 .ndo_start_xmit = epic_start_xmit,
315 .ndo_tx_timeout = epic_tx_timeout,
316 .ndo_get_stats = epic_get_stats,
317 .ndo_set_multicast_list = set_rx_mode,
318 .ndo_do_ioctl = netdev_ioctl,
319 .ndo_change_mtu = eth_change_mtu,
320 .ndo_set_mac_address = eth_mac_addr,
321 .ndo_validate_addr = eth_validate_addr,
322};
323
324static int __devinit epic_init_one (struct pci_dev *pdev,
325 const struct pci_device_id *ent)
326{
327 static int card_idx = -1;
328 long ioaddr;
329 int chip_idx = (int) ent->driver_data;
330 int irq;
331 struct net_device *dev;
332 struct epic_private *ep;
333 int i, ret, option = 0, duplex = 0;
334 void *ring_space;
335 dma_addr_t ring_dma;
336
337/* when built into the kernel, we only print version if device is found */
338#ifndef MODULE
339 static int printed_version;
340 if (!printed_version++)
341 printk(KERN_INFO "%s%s", version, version2);
342#endif
343
344 card_idx++;
345
346 ret = pci_enable_device(pdev);
347 if (ret)
348 goto out;
349 irq = pdev->irq;
350
351 if (pci_resource_len(pdev, 0) < EPIC_TOTAL_SIZE) {
352 dev_err(&pdev->dev, "no PCI region space\n");
353 ret = -ENODEV;
354 goto err_out_disable;
355 }
356
357 pci_set_master(pdev);
358
359 ret = pci_request_regions(pdev, DRV_NAME);
360 if (ret < 0)
361 goto err_out_disable;
362
363 ret = -ENOMEM;
364
365 dev = alloc_etherdev(sizeof (*ep));
366 if (!dev) {
367 dev_err(&pdev->dev, "no memory for eth device\n");
368 goto err_out_free_res;
369 }
370 SET_NETDEV_DEV(dev, &pdev->dev);
371
372#ifdef USE_IO_OPS
373 ioaddr = pci_resource_start (pdev, 0);
374#else
375 ioaddr = pci_resource_start (pdev, 1);
376 ioaddr = (long) pci_ioremap_bar(pdev, 1);
377 if (!ioaddr) {
378 dev_err(&pdev->dev, "ioremap failed\n");
379 goto err_out_free_netdev;
380 }
381#endif
382
383 pci_set_drvdata(pdev, dev);
384 ep = netdev_priv(dev);
385 ep->mii.dev = dev;
386 ep->mii.mdio_read = mdio_read;
387 ep->mii.mdio_write = mdio_write;
388 ep->mii.phy_id_mask = 0x1f;
389 ep->mii.reg_num_mask = 0x1f;
390
391 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
392 if (!ring_space)
393 goto err_out_iounmap;
394 ep->tx_ring = ring_space;
395 ep->tx_ring_dma = ring_dma;
396
397 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
398 if (!ring_space)
399 goto err_out_unmap_tx;
400 ep->rx_ring = ring_space;
401 ep->rx_ring_dma = ring_dma;
402
403 if (dev->mem_start) {
404 option = dev->mem_start;
405 duplex = (dev->mem_start & 16) ? 1 : 0;
406 } else if (card_idx >= 0 && card_idx < MAX_UNITS) {
407 if (options[card_idx] >= 0)
408 option = options[card_idx];
409 if (full_duplex[card_idx] >= 0)
410 duplex = full_duplex[card_idx];
411 }
412
413 dev->base_addr = ioaddr;
414 dev->irq = irq;
415
416 spin_lock_init(&ep->lock);
417 spin_lock_init(&ep->napi_lock);
418 ep->reschedule_in_poll = 0;
419
420 /* Bring the chip out of low-power mode. */
421 outl(0x4200, ioaddr + GENCTL);
422 /* Magic?! If we don't set this bit the MII interface won't work. */
423 /* This magic is documented in SMSC app note 7.15 */
424 for (i = 16; i > 0; i--)
425 outl(0x0008, ioaddr + TEST1);
426
427 /* Turn on the MII transceiver. */
428 outl(0x12, ioaddr + MIICfg);
429 if (chip_idx == 1)
430 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
431 outl(0x0200, ioaddr + GENCTL);
432
433 /* Note: the '175 does not have a serial EEPROM. */
434 for (i = 0; i < 3; i++)
435 ((__le16 *)dev->dev_addr)[i] = cpu_to_le16(inw(ioaddr + LAN0 + i*4));
436
437 if (debug > 2) {
438 dev_printk(KERN_DEBUG, &pdev->dev, "EEPROM contents:\n");
439 for (i = 0; i < 64; i++)
440 printk(" %4.4x%s", read_eeprom(ioaddr, i),
441 i % 16 == 15 ? "\n" : "");
442 }
443
444 ep->pci_dev = pdev;
445 ep->chip_id = chip_idx;
446 ep->chip_flags = pci_id_tbl[chip_idx].drv_flags;
447 ep->irq_mask =
448 (ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
449 | CntFull | TxUnderrun | EpicNapiEvent;
450
451 /* Find the connected MII xcvrs.
452 Doing this in open() would allow detecting external xcvrs later, but
453 takes much time and no cards have external MII. */
454 {
455 int phy, phy_idx = 0;
456 for (phy = 1; phy < 32 && phy_idx < sizeof(ep->phys); phy++) {
457 int mii_status = mdio_read(dev, phy, MII_BMSR);
458 if (mii_status != 0xffff && mii_status != 0x0000) {
459 ep->phys[phy_idx++] = phy;
460 dev_info(&pdev->dev,
461 "MII transceiver #%d control "
462 "%4.4x status %4.4x.\n",
463 phy, mdio_read(dev, phy, 0), mii_status);
464 }
465 }
466 ep->mii_phy_cnt = phy_idx;
467 if (phy_idx != 0) {
468 phy = ep->phys[0];
469 ep->mii.advertising = mdio_read(dev, phy, MII_ADVERTISE);
470 dev_info(&pdev->dev,
471 "Autonegotiation advertising %4.4x link "
472 "partner %4.4x.\n",
473 ep->mii.advertising, mdio_read(dev, phy, 5));
474 } else if ( ! (ep->chip_flags & NO_MII)) {
475 dev_warn(&pdev->dev,
476 "***WARNING***: No MII transceiver found!\n");
477 /* Use the known PHY address of the EPII. */
478 ep->phys[0] = 3;
479 }
480 ep->mii.phy_id = ep->phys[0];
481 }
482
483 /* Turn off the MII xcvr (175 only!), leave the chip in low-power mode. */
484 if (ep->chip_flags & MII_PWRDWN)
485 outl(inl(ioaddr + NVCTL) & ~0x483C, ioaddr + NVCTL);
486 outl(0x0008, ioaddr + GENCTL);
487
488 /* The lower four bits are the media type. */
489 if (duplex) {
490 ep->mii.force_media = ep->mii.full_duplex = 1;
491 dev_info(&pdev->dev, "Forced full duplex requested.\n");
492 }
493 dev->if_port = ep->default_port = option;
494
495 /* The Epic-specific entries in the device structure. */
496 dev->netdev_ops = &epic_netdev_ops;
497 dev->ethtool_ops = &netdev_ethtool_ops;
498 dev->watchdog_timeo = TX_TIMEOUT;
499 netif_napi_add(dev, &ep->napi, epic_poll, 64);
500
501 ret = register_netdev(dev);
502 if (ret < 0)
503 goto err_out_unmap_rx;
504
505 printk(KERN_INFO "%s: %s at %#lx, IRQ %d, %pM\n",
506 dev->name, pci_id_tbl[chip_idx].name, ioaddr, dev->irq,
507 dev->dev_addr);
508
509out:
510 return ret;
511
512err_out_unmap_rx:
513 pci_free_consistent(pdev, RX_TOTAL_SIZE, ep->rx_ring, ep->rx_ring_dma);
514err_out_unmap_tx:
515 pci_free_consistent(pdev, TX_TOTAL_SIZE, ep->tx_ring, ep->tx_ring_dma);
516err_out_iounmap:
517#ifndef USE_IO_OPS
518 iounmap(ioaddr);
519err_out_free_netdev:
520#endif
521 free_netdev(dev);
522err_out_free_res:
523 pci_release_regions(pdev);
524err_out_disable:
525 pci_disable_device(pdev);
526 goto out;
527}
528
529/* Serial EEPROM section. */
530
531/* EEPROM_Ctrl bits. */
532#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
533#define EE_CS 0x02 /* EEPROM chip select. */
534#define EE_DATA_WRITE 0x08 /* EEPROM chip data in. */
535#define EE_WRITE_0 0x01
536#define EE_WRITE_1 0x09
537#define EE_DATA_READ 0x10 /* EEPROM chip data out. */
538#define EE_ENB (0x0001 | EE_CS)
539
540/* Delay between EEPROM clock transitions.
541 This serves to flush the operation to the PCI bus.
542 */
543
544#define eeprom_delay() inl(ee_addr)
545
546/* The EEPROM commands include the alway-set leading bit. */
547#define EE_WRITE_CMD (5 << 6)
548#define EE_READ64_CMD (6 << 6)
549#define EE_READ256_CMD (6 << 8)
550#define EE_ERASE_CMD (7 << 6)
551
552static void epic_disable_int(struct net_device *dev, struct epic_private *ep)
553{
554 long ioaddr = dev->base_addr;
555
556 outl(0x00000000, ioaddr + INTMASK);
557}
558
559static inline void __epic_pci_commit(long ioaddr)
560{
561#ifndef USE_IO_OPS
562 inl(ioaddr + INTMASK);
563#endif
564}
565
566static inline void epic_napi_irq_off(struct net_device *dev,
567 struct epic_private *ep)
568{
569 long ioaddr = dev->base_addr;
570
571 outl(ep->irq_mask & ~EpicNapiEvent, ioaddr + INTMASK);
572 __epic_pci_commit(ioaddr);
573}
574
575static inline void epic_napi_irq_on(struct net_device *dev,
576 struct epic_private *ep)
577{
578 long ioaddr = dev->base_addr;
579
580 /* No need to commit possible posted write */
581 outl(ep->irq_mask | EpicNapiEvent, ioaddr + INTMASK);
582}
583
584static int __devinit read_eeprom(long ioaddr, int location)
585{
586 int i;
587 int retval = 0;
588 long ee_addr = ioaddr + EECTL;
589 int read_cmd = location |
590 (inl(ee_addr) & 0x40 ? EE_READ64_CMD : EE_READ256_CMD);
591
592 outl(EE_ENB & ~EE_CS, ee_addr);
593 outl(EE_ENB, ee_addr);
594
595 /* Shift the read command bits out. */
596 for (i = 12; i >= 0; i--) {
597 short dataval = (read_cmd & (1 << i)) ? EE_WRITE_1 : EE_WRITE_0;
598 outl(EE_ENB | dataval, ee_addr);
599 eeprom_delay();
600 outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
601 eeprom_delay();
602 }
603 outl(EE_ENB, ee_addr);
604
605 for (i = 16; i > 0; i--) {
606 outl(EE_ENB | EE_SHIFT_CLK, ee_addr);
607 eeprom_delay();
608 retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
609 outl(EE_ENB, ee_addr);
610 eeprom_delay();
611 }
612
613 /* Terminate the EEPROM access. */
614 outl(EE_ENB & ~EE_CS, ee_addr);
615 return retval;
616}
617
618#define MII_READOP 1
619#define MII_WRITEOP 2
620static int mdio_read(struct net_device *dev, int phy_id, int location)
621{
622 long ioaddr = dev->base_addr;
623 int read_cmd = (phy_id << 9) | (location << 4) | MII_READOP;
624 int i;
625
626 outl(read_cmd, ioaddr + MIICtrl);
627 /* Typical operation takes 25 loops. */
628 for (i = 400; i > 0; i--) {
629 barrier();
630 if ((inl(ioaddr + MIICtrl) & MII_READOP) == 0) {
631 /* Work around read failure bug. */
632 if (phy_id == 1 && location < 6 &&
633 inw(ioaddr + MIIData) == 0xffff) {
634 outl(read_cmd, ioaddr + MIICtrl);
635 continue;
636 }
637 return inw(ioaddr + MIIData);
638 }
639 }
640 return 0xffff;
641}
642
643static void mdio_write(struct net_device *dev, int phy_id, int loc, int value)
644{
645 long ioaddr = dev->base_addr;
646 int i;
647
648 outw(value, ioaddr + MIIData);
649 outl((phy_id << 9) | (loc << 4) | MII_WRITEOP, ioaddr + MIICtrl);
650 for (i = 10000; i > 0; i--) {
651 barrier();
652 if ((inl(ioaddr + MIICtrl) & MII_WRITEOP) == 0)
653 break;
654 }
655}
656
657
658static int epic_open(struct net_device *dev)
659{
660 struct epic_private *ep = netdev_priv(dev);
661 long ioaddr = dev->base_addr;
662 int i;
663 int retval;
664
665 /* Soft reset the chip. */
666 outl(0x4001, ioaddr + GENCTL);
667
668 napi_enable(&ep->napi);
669 if ((retval = request_irq(dev->irq, epic_interrupt, IRQF_SHARED, dev->name, dev))) {
670 napi_disable(&ep->napi);
671 return retval;
672 }
673
674 epic_init_ring(dev);
675
676 outl(0x4000, ioaddr + GENCTL);
677 /* This magic is documented in SMSC app note 7.15 */
678 for (i = 16; i > 0; i--)
679 outl(0x0008, ioaddr + TEST1);
680
681 /* Pull the chip out of low-power mode, enable interrupts, and set for
682 PCI read multiple. The MIIcfg setting and strange write order are
683 required by the details of which bits are reset and the transceiver
684 wiring on the Ositech CardBus card.
685 */
686#if 0
687 outl(dev->if_port == 1 ? 0x13 : 0x12, ioaddr + MIICfg);
688#endif
689 if (ep->chip_flags & MII_PWRDWN)
690 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
691
692 /* Tell the chip to byteswap descriptors on big-endian hosts */
693#ifdef __BIG_ENDIAN
694 outl(0x4432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
695 inl(ioaddr + GENCTL);
696 outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
697#else
698 outl(0x4412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
699 inl(ioaddr + GENCTL);
700 outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
701#endif
702
703 udelay(20); /* Looks like EPII needs that if you want reliable RX init. FIXME: pci posting bug? */
704
705 for (i = 0; i < 3; i++)
706 outl(le16_to_cpu(((__le16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4);
707
708 ep->tx_threshold = TX_FIFO_THRESH;
709 outl(ep->tx_threshold, ioaddr + TxThresh);
710
711 if (media2miictl[dev->if_port & 15]) {
712 if (ep->mii_phy_cnt)
713 mdio_write(dev, ep->phys[0], MII_BMCR, media2miictl[dev->if_port&15]);
714 if (dev->if_port == 1) {
715 if (debug > 1)
716 printk(KERN_INFO "%s: Using the 10base2 transceiver, MII "
717 "status %4.4x.\n",
718 dev->name, mdio_read(dev, ep->phys[0], MII_BMSR));
719 }
720 } else {
721 int mii_lpa = mdio_read(dev, ep->phys[0], MII_LPA);
722 if (mii_lpa != 0xffff) {
723 if ((mii_lpa & LPA_100FULL) || (mii_lpa & 0x01C0) == LPA_10FULL)
724 ep->mii.full_duplex = 1;
725 else if (! (mii_lpa & LPA_LPACK))
726 mdio_write(dev, ep->phys[0], MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART);
727 if (debug > 1)
728 printk(KERN_INFO "%s: Setting %s-duplex based on MII xcvr %d"
729 " register read of %4.4x.\n", dev->name,
730 ep->mii.full_duplex ? "full" : "half",
731 ep->phys[0], mii_lpa);
732 }
733 }
734
735 outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
736 outl(ep->rx_ring_dma, ioaddr + PRxCDAR);
737 outl(ep->tx_ring_dma, ioaddr + PTxCDAR);
738
739 /* Start the chip's Rx process. */
740 set_rx_mode(dev);
741 outl(StartRx | RxQueued, ioaddr + COMMAND);
742
743 netif_start_queue(dev);
744
745 /* Enable interrupts by setting the interrupt mask. */
746 outl((ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
747 | CntFull | TxUnderrun
748 | RxError | RxHeader | EpicNapiEvent, ioaddr + INTMASK);
749
750 if (debug > 1)
751 printk(KERN_DEBUG "%s: epic_open() ioaddr %lx IRQ %d status %4.4x "
752 "%s-duplex.\n",
753 dev->name, ioaddr, dev->irq, (int)inl(ioaddr + GENCTL),
754 ep->mii.full_duplex ? "full" : "half");
755
756 /* Set the timer to switch to check for link beat and perhaps switch
757 to an alternate media type. */
758 init_timer(&ep->timer);
759 ep->timer.expires = jiffies + 3*HZ;
760 ep->timer.data = (unsigned long)dev;
761 ep->timer.function = epic_timer; /* timer handler */
762 add_timer(&ep->timer);
763
764 return 0;
765}
766
767/* Reset the chip to recover from a PCI transaction error.
768 This may occur at interrupt time. */
769static void epic_pause(struct net_device *dev)
770{
771 long ioaddr = dev->base_addr;
772
773 netif_stop_queue (dev);
774
775 /* Disable interrupts by clearing the interrupt mask. */
776 outl(0x00000000, ioaddr + INTMASK);
777 /* Stop the chip's Tx and Rx DMA processes. */
778 outw(StopRx | StopTxDMA | StopRxDMA, ioaddr + COMMAND);
779
780 /* Update the error counts. */
781 if (inw(ioaddr + COMMAND) != 0xffff) {
782 dev->stats.rx_missed_errors += inb(ioaddr + MPCNT);
783 dev->stats.rx_frame_errors += inb(ioaddr + ALICNT);
784 dev->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
785 }
786
787 /* Remove the packets on the Rx queue. */
788 epic_rx(dev, RX_RING_SIZE);
789}
790
791static void epic_restart(struct net_device *dev)
792{
793 long ioaddr = dev->base_addr;
794 struct epic_private *ep = netdev_priv(dev);
795 int i;
796
797 /* Soft reset the chip. */
798 outl(0x4001, ioaddr + GENCTL);
799
800 printk(KERN_DEBUG "%s: Restarting the EPIC chip, Rx %d/%d Tx %d/%d.\n",
801 dev->name, ep->cur_rx, ep->dirty_rx, ep->dirty_tx, ep->cur_tx);
802 udelay(1);
803
804 /* This magic is documented in SMSC app note 7.15 */
805 for (i = 16; i > 0; i--)
806 outl(0x0008, ioaddr + TEST1);
807
808#ifdef __BIG_ENDIAN
809 outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
810#else
811 outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
812#endif
813 outl(dev->if_port == 1 ? 0x13 : 0x12, ioaddr + MIICfg);
814 if (ep->chip_flags & MII_PWRDWN)
815 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
816
817 for (i = 0; i < 3; i++)
818 outl(le16_to_cpu(((__le16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4);
819
820 ep->tx_threshold = TX_FIFO_THRESH;
821 outl(ep->tx_threshold, ioaddr + TxThresh);
822 outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
823 outl(ep->rx_ring_dma + (ep->cur_rx%RX_RING_SIZE)*
824 sizeof(struct epic_rx_desc), ioaddr + PRxCDAR);
825 outl(ep->tx_ring_dma + (ep->dirty_tx%TX_RING_SIZE)*
826 sizeof(struct epic_tx_desc), ioaddr + PTxCDAR);
827
828 /* Start the chip's Rx process. */
829 set_rx_mode(dev);
830 outl(StartRx | RxQueued, ioaddr + COMMAND);
831
832 /* Enable interrupts by setting the interrupt mask. */
833 outl((ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
834 | CntFull | TxUnderrun
835 | RxError | RxHeader | EpicNapiEvent, ioaddr + INTMASK);
836
837 printk(KERN_DEBUG "%s: epic_restart() done, cmd status %4.4x, ctl %4.4x"
838 " interrupt %4.4x.\n",
839 dev->name, (int)inl(ioaddr + COMMAND), (int)inl(ioaddr + GENCTL),
840 (int)inl(ioaddr + INTSTAT));
841}
842
843static void check_media(struct net_device *dev)
844{
845 struct epic_private *ep = netdev_priv(dev);
846 long ioaddr = dev->base_addr;
847 int mii_lpa = ep->mii_phy_cnt ? mdio_read(dev, ep->phys[0], MII_LPA) : 0;
848 int negotiated = mii_lpa & ep->mii.advertising;
849 int duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040;
850
851 if (ep->mii.force_media)
852 return;
853 if (mii_lpa == 0xffff) /* Bogus read */
854 return;
855 if (ep->mii.full_duplex != duplex) {
856 ep->mii.full_duplex = duplex;
857 printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d link"
858 " partner capability of %4.4x.\n", dev->name,
859 ep->mii.full_duplex ? "full" : "half", ep->phys[0], mii_lpa);
860 outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
861 }
862}
863
864static void epic_timer(unsigned long data)
865{
866 struct net_device *dev = (struct net_device *)data;
867 struct epic_private *ep = netdev_priv(dev);
868 long ioaddr = dev->base_addr;
869 int next_tick = 5*HZ;
870
871 if (debug > 3) {
872 printk(KERN_DEBUG "%s: Media monitor tick, Tx status %8.8x.\n",
873 dev->name, (int)inl(ioaddr + TxSTAT));
874 printk(KERN_DEBUG "%s: Other registers are IntMask %4.4x "
875 "IntStatus %4.4x RxStatus %4.4x.\n",
876 dev->name, (int)inl(ioaddr + INTMASK),
877 (int)inl(ioaddr + INTSTAT), (int)inl(ioaddr + RxSTAT));
878 }
879
880 check_media(dev);
881
882 ep->timer.expires = jiffies + next_tick;
883 add_timer(&ep->timer);
884}
885
886static void epic_tx_timeout(struct net_device *dev)
887{
888 struct epic_private *ep = netdev_priv(dev);
889 long ioaddr = dev->base_addr;
890
891 if (debug > 0) {
892 printk(KERN_WARNING "%s: Transmit timeout using MII device, "
893 "Tx status %4.4x.\n",
894 dev->name, (int)inw(ioaddr + TxSTAT));
895 if (debug > 1) {
896 printk(KERN_DEBUG "%s: Tx indices: dirty_tx %d, cur_tx %d.\n",
897 dev->name, ep->dirty_tx, ep->cur_tx);
898 }
899 }
900 if (inw(ioaddr + TxSTAT) & 0x10) { /* Tx FIFO underflow. */
901 dev->stats.tx_fifo_errors++;
902 outl(RestartTx, ioaddr + COMMAND);
903 } else {
904 epic_restart(dev);
905 outl(TxQueued, dev->base_addr + COMMAND);
906 }
907
908 dev->trans_start = jiffies; /* prevent tx timeout */
909 dev->stats.tx_errors++;
910 if (!ep->tx_full)
911 netif_wake_queue(dev);
912}
913
914/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
915static void epic_init_ring(struct net_device *dev)
916{
917 struct epic_private *ep = netdev_priv(dev);
918 int i;
919
920 ep->tx_full = 0;
921 ep->dirty_tx = ep->cur_tx = 0;
922 ep->cur_rx = ep->dirty_rx = 0;
923 ep->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
924
925 /* Initialize all Rx descriptors. */
926 for (i = 0; i < RX_RING_SIZE; i++) {
927 ep->rx_ring[i].rxstatus = 0;
928 ep->rx_ring[i].buflength = ep->rx_buf_sz;
929 ep->rx_ring[i].next = ep->rx_ring_dma +
930 (i+1)*sizeof(struct epic_rx_desc);
931 ep->rx_skbuff[i] = NULL;
932 }
933 /* Mark the last entry as wrapping the ring. */
934 ep->rx_ring[i-1].next = ep->rx_ring_dma;
935
936 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
937 for (i = 0; i < RX_RING_SIZE; i++) {
938 struct sk_buff *skb = dev_alloc_skb(ep->rx_buf_sz + 2);
939 ep->rx_skbuff[i] = skb;
940 if (skb == NULL)
941 break;
942 skb_reserve(skb, 2); /* 16 byte align the IP header. */
943 ep->rx_ring[i].bufaddr = pci_map_single(ep->pci_dev,
944 skb->data, ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
945 ep->rx_ring[i].rxstatus = DescOwn;
946 }
947 ep->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
948
949 /* The Tx buffer descriptor is filled in as needed, but we
950 do need to clear the ownership bit. */
951 for (i = 0; i < TX_RING_SIZE; i++) {
952 ep->tx_skbuff[i] = NULL;
953 ep->tx_ring[i].txstatus = 0x0000;
954 ep->tx_ring[i].next = ep->tx_ring_dma +
955 (i+1)*sizeof(struct epic_tx_desc);
956 }
957 ep->tx_ring[i-1].next = ep->tx_ring_dma;
958}
959
960static netdev_tx_t epic_start_xmit(struct sk_buff *skb, struct net_device *dev)
961{
962 struct epic_private *ep = netdev_priv(dev);
963 int entry, free_count;
964 u32 ctrl_word;
965 unsigned long flags;
966
967 if (skb_padto(skb, ETH_ZLEN))
968 return NETDEV_TX_OK;
969
970 /* Caution: the write order is important here, set the field with the
971 "ownership" bit last. */
972
973 /* Calculate the next Tx descriptor entry. */
974 spin_lock_irqsave(&ep->lock, flags);
975 free_count = ep->cur_tx - ep->dirty_tx;
976 entry = ep->cur_tx % TX_RING_SIZE;
977
978 ep->tx_skbuff[entry] = skb;
979 ep->tx_ring[entry].bufaddr = pci_map_single(ep->pci_dev, skb->data,
980 skb->len, PCI_DMA_TODEVICE);
981 if (free_count < TX_QUEUE_LEN/2) {/* Typical path */
982 ctrl_word = 0x100000; /* No interrupt */
983 } else if (free_count == TX_QUEUE_LEN/2) {
984 ctrl_word = 0x140000; /* Tx-done intr. */
985 } else if (free_count < TX_QUEUE_LEN - 1) {
986 ctrl_word = 0x100000; /* No Tx-done intr. */
987 } else {
988 /* Leave room for an additional entry. */
989 ctrl_word = 0x140000; /* Tx-done intr. */
990 ep->tx_full = 1;
991 }
992 ep->tx_ring[entry].buflength = ctrl_word | skb->len;
993 ep->tx_ring[entry].txstatus =
994 ((skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN) << 16)
995 | DescOwn;
996
997 ep->cur_tx++;
998 if (ep->tx_full)
999 netif_stop_queue(dev);
1000
1001 spin_unlock_irqrestore(&ep->lock, flags);
1002 /* Trigger an immediate transmit demand. */
1003 outl(TxQueued, dev->base_addr + COMMAND);
1004
1005 if (debug > 4)
1006 printk(KERN_DEBUG "%s: Queued Tx packet size %d to slot %d, "
1007 "flag %2.2x Tx status %8.8x.\n",
1008 dev->name, (int)skb->len, entry, ctrl_word,
1009 (int)inl(dev->base_addr + TxSTAT));
1010
1011 return NETDEV_TX_OK;
1012}
1013
1014static void epic_tx_error(struct net_device *dev, struct epic_private *ep,
1015 int status)
1016{
1017 struct net_device_stats *stats = &dev->stats;
1018
1019#ifndef final_version
1020 /* There was an major error, log it. */
1021 if (debug > 1)
1022 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1023 dev->name, status);
1024#endif
1025 stats->tx_errors++;
1026 if (status & 0x1050)
1027 stats->tx_aborted_errors++;
1028 if (status & 0x0008)
1029 stats->tx_carrier_errors++;
1030 if (status & 0x0040)
1031 stats->tx_window_errors++;
1032 if (status & 0x0010)
1033 stats->tx_fifo_errors++;
1034}
1035
1036static void epic_tx(struct net_device *dev, struct epic_private *ep)
1037{
1038 unsigned int dirty_tx, cur_tx;
1039
1040 /*
1041 * Note: if this lock becomes a problem we can narrow the locked
1042 * region at the cost of occasionally grabbing the lock more times.
1043 */
1044 cur_tx = ep->cur_tx;
1045 for (dirty_tx = ep->dirty_tx; cur_tx - dirty_tx > 0; dirty_tx++) {
1046 struct sk_buff *skb;
1047 int entry = dirty_tx % TX_RING_SIZE;
1048 int txstatus = ep->tx_ring[entry].txstatus;
1049
1050 if (txstatus & DescOwn)
1051 break; /* It still hasn't been Txed */
1052
1053 if (likely(txstatus & 0x0001)) {
1054 dev->stats.collisions += (txstatus >> 8) & 15;
1055 dev->stats.tx_packets++;
1056 dev->stats.tx_bytes += ep->tx_skbuff[entry]->len;
1057 } else
1058 epic_tx_error(dev, ep, txstatus);
1059
1060 /* Free the original skb. */
1061 skb = ep->tx_skbuff[entry];
1062 pci_unmap_single(ep->pci_dev, ep->tx_ring[entry].bufaddr,
1063 skb->len, PCI_DMA_TODEVICE);
1064 dev_kfree_skb_irq(skb);
1065 ep->tx_skbuff[entry] = NULL;
1066 }
1067
1068#ifndef final_version
1069 if (cur_tx - dirty_tx > TX_RING_SIZE) {
1070 printk(KERN_WARNING
1071 "%s: Out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1072 dev->name, dirty_tx, cur_tx, ep->tx_full);
1073 dirty_tx += TX_RING_SIZE;
1074 }
1075#endif
1076 ep->dirty_tx = dirty_tx;
1077 if (ep->tx_full && cur_tx - dirty_tx < TX_QUEUE_LEN - 4) {
1078 /* The ring is no longer full, allow new TX entries. */
1079 ep->tx_full = 0;
1080 netif_wake_queue(dev);
1081 }
1082}
1083
1084/* The interrupt handler does all of the Rx thread work and cleans up
1085 after the Tx thread. */
1086static irqreturn_t epic_interrupt(int irq, void *dev_instance)
1087{
1088 struct net_device *dev = dev_instance;
1089 struct epic_private *ep = netdev_priv(dev);
1090 long ioaddr = dev->base_addr;
1091 unsigned int handled = 0;
1092 int status;
1093
1094 status = inl(ioaddr + INTSTAT);
1095 /* Acknowledge all of the current interrupt sources ASAP. */
1096 outl(status & EpicNormalEvent, ioaddr + INTSTAT);
1097
1098 if (debug > 4) {
1099 printk(KERN_DEBUG "%s: Interrupt, status=%#8.8x new "
1100 "intstat=%#8.8x.\n", dev->name, status,
1101 (int)inl(ioaddr + INTSTAT));
1102 }
1103
1104 if ((status & IntrSummary) == 0)
1105 goto out;
1106
1107 handled = 1;
1108
1109 if ((status & EpicNapiEvent) && !ep->reschedule_in_poll) {
1110 spin_lock(&ep->napi_lock);
1111 if (napi_schedule_prep(&ep->napi)) {
1112 epic_napi_irq_off(dev, ep);
1113 __napi_schedule(&ep->napi);
1114 } else
1115 ep->reschedule_in_poll++;
1116 spin_unlock(&ep->napi_lock);
1117 }
1118 status &= ~EpicNapiEvent;
1119
1120 /* Check uncommon events all at once. */
1121 if (status & (CntFull | TxUnderrun | PCIBusErr170 | PCIBusErr175)) {
1122 if (status == EpicRemoved)
1123 goto out;
1124
1125 /* Always update the error counts to avoid overhead later. */
1126 dev->stats.rx_missed_errors += inb(ioaddr + MPCNT);
1127 dev->stats.rx_frame_errors += inb(ioaddr + ALICNT);
1128 dev->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
1129
1130 if (status & TxUnderrun) { /* Tx FIFO underflow. */
1131 dev->stats.tx_fifo_errors++;
1132 outl(ep->tx_threshold += 128, ioaddr + TxThresh);
1133 /* Restart the transmit process. */
1134 outl(RestartTx, ioaddr + COMMAND);
1135 }
1136 if (status & PCIBusErr170) {
1137 printk(KERN_ERR "%s: PCI Bus Error! status %4.4x.\n",
1138 dev->name, status);
1139 epic_pause(dev);
1140 epic_restart(dev);
1141 }
1142 /* Clear all error sources. */
1143 outl(status & 0x7f18, ioaddr + INTSTAT);
1144 }
1145
1146out:
1147 if (debug > 3) {
1148 printk(KERN_DEBUG "%s: exit interrupt, intr_status=%#4.4x.\n",
1149 dev->name, status);
1150 }
1151
1152 return IRQ_RETVAL(handled);
1153}
1154
1155static int epic_rx(struct net_device *dev, int budget)
1156{
1157 struct epic_private *ep = netdev_priv(dev);
1158 int entry = ep->cur_rx % RX_RING_SIZE;
1159 int rx_work_limit = ep->dirty_rx + RX_RING_SIZE - ep->cur_rx;
1160 int work_done = 0;
1161
1162 if (debug > 4)
1163 printk(KERN_DEBUG " In epic_rx(), entry %d %8.8x.\n", entry,
1164 ep->rx_ring[entry].rxstatus);
1165
1166 if (rx_work_limit > budget)
1167 rx_work_limit = budget;
1168
1169 /* If we own the next entry, it's a new packet. Send it up. */
1170 while ((ep->rx_ring[entry].rxstatus & DescOwn) == 0) {
1171 int status = ep->rx_ring[entry].rxstatus;
1172
1173 if (debug > 4)
1174 printk(KERN_DEBUG " epic_rx() status was %8.8x.\n", status);
1175 if (--rx_work_limit < 0)
1176 break;
1177 if (status & 0x2006) {
1178 if (debug > 2)
1179 printk(KERN_DEBUG "%s: epic_rx() error status was %8.8x.\n",
1180 dev->name, status);
1181 if (status & 0x2000) {
1182 printk(KERN_WARNING "%s: Oversized Ethernet frame spanned "
1183 "multiple buffers, status %4.4x!\n", dev->name, status);
1184 dev->stats.rx_length_errors++;
1185 } else if (status & 0x0006)
1186 /* Rx Frame errors are counted in hardware. */
1187 dev->stats.rx_errors++;
1188 } else {
1189 /* Malloc up new buffer, compatible with net-2e. */
1190 /* Omit the four octet CRC from the length. */
1191 short pkt_len = (status >> 16) - 4;
1192 struct sk_buff *skb;
1193
1194 if (pkt_len > PKT_BUF_SZ - 4) {
1195 printk(KERN_ERR "%s: Oversized Ethernet frame, status %x "
1196 "%d bytes.\n",
1197 dev->name, status, pkt_len);
1198 pkt_len = 1514;
1199 }
1200 /* Check if the packet is long enough to accept without copying
1201 to a minimally-sized skbuff. */
1202 if (pkt_len < rx_copybreak &&
1203 (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1204 skb_reserve(skb, 2); /* 16 byte align the IP header */
1205 pci_dma_sync_single_for_cpu(ep->pci_dev,
1206 ep->rx_ring[entry].bufaddr,
1207 ep->rx_buf_sz,
1208 PCI_DMA_FROMDEVICE);
1209 skb_copy_to_linear_data(skb, ep->rx_skbuff[entry]->data, pkt_len);
1210 skb_put(skb, pkt_len);
1211 pci_dma_sync_single_for_device(ep->pci_dev,
1212 ep->rx_ring[entry].bufaddr,
1213 ep->rx_buf_sz,
1214 PCI_DMA_FROMDEVICE);
1215 } else {
1216 pci_unmap_single(ep->pci_dev,
1217 ep->rx_ring[entry].bufaddr,
1218 ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1219 skb_put(skb = ep->rx_skbuff[entry], pkt_len);
1220 ep->rx_skbuff[entry] = NULL;
1221 }
1222 skb->protocol = eth_type_trans(skb, dev);
1223 netif_receive_skb(skb);
1224 dev->stats.rx_packets++;
1225 dev->stats.rx_bytes += pkt_len;
1226 }
1227 work_done++;
1228 entry = (++ep->cur_rx) % RX_RING_SIZE;
1229 }
1230
1231 /* Refill the Rx ring buffers. */
1232 for (; ep->cur_rx - ep->dirty_rx > 0; ep->dirty_rx++) {
1233 entry = ep->dirty_rx % RX_RING_SIZE;
1234 if (ep->rx_skbuff[entry] == NULL) {
1235 struct sk_buff *skb;
1236 skb = ep->rx_skbuff[entry] = dev_alloc_skb(ep->rx_buf_sz + 2);
1237 if (skb == NULL)
1238 break;
1239 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1240 ep->rx_ring[entry].bufaddr = pci_map_single(ep->pci_dev,
1241 skb->data, ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1242 work_done++;
1243 }
1244 /* AV: shouldn't we add a barrier here? */
1245 ep->rx_ring[entry].rxstatus = DescOwn;
1246 }
1247 return work_done;
1248}
1249
1250static void epic_rx_err(struct net_device *dev, struct epic_private *ep)
1251{
1252 long ioaddr = dev->base_addr;
1253 int status;
1254
1255 status = inl(ioaddr + INTSTAT);
1256
1257 if (status == EpicRemoved)
1258 return;
1259 if (status & RxOverflow) /* Missed a Rx frame. */
1260 dev->stats.rx_errors++;
1261 if (status & (RxOverflow | RxFull))
1262 outw(RxQueued, ioaddr + COMMAND);
1263}
1264
1265static int epic_poll(struct napi_struct *napi, int budget)
1266{
1267 struct epic_private *ep = container_of(napi, struct epic_private, napi);
1268 struct net_device *dev = ep->mii.dev;
1269 int work_done = 0;
1270 long ioaddr = dev->base_addr;
1271
1272rx_action:
1273
1274 epic_tx(dev, ep);
1275
1276 work_done += epic_rx(dev, budget);
1277
1278 epic_rx_err(dev, ep);
1279
1280 if (work_done < budget) {
1281 unsigned long flags;
1282 int more;
1283
1284 /* A bit baroque but it avoids a (space hungry) spin_unlock */
1285
1286 spin_lock_irqsave(&ep->napi_lock, flags);
1287
1288 more = ep->reschedule_in_poll;
1289 if (!more) {
1290 __napi_complete(napi);
1291 outl(EpicNapiEvent, ioaddr + INTSTAT);
1292 epic_napi_irq_on(dev, ep);
1293 } else
1294 ep->reschedule_in_poll--;
1295
1296 spin_unlock_irqrestore(&ep->napi_lock, flags);
1297
1298 if (more)
1299 goto rx_action;
1300 }
1301
1302 return work_done;
1303}
1304
1305static int epic_close(struct net_device *dev)
1306{
1307 long ioaddr = dev->base_addr;
1308 struct epic_private *ep = netdev_priv(dev);
1309 struct sk_buff *skb;
1310 int i;
1311
1312 netif_stop_queue(dev);
1313 napi_disable(&ep->napi);
1314
1315 if (debug > 1)
1316 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
1317 dev->name, (int)inl(ioaddr + INTSTAT));
1318
1319 del_timer_sync(&ep->timer);
1320
1321 epic_disable_int(dev, ep);
1322
1323 free_irq(dev->irq, dev);
1324
1325 epic_pause(dev);
1326
1327 /* Free all the skbuffs in the Rx queue. */
1328 for (i = 0; i < RX_RING_SIZE; i++) {
1329 skb = ep->rx_skbuff[i];
1330 ep->rx_skbuff[i] = NULL;
1331 ep->rx_ring[i].rxstatus = 0; /* Not owned by Epic chip. */
1332 ep->rx_ring[i].buflength = 0;
1333 if (skb) {
1334 pci_unmap_single(ep->pci_dev, ep->rx_ring[i].bufaddr,
1335 ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1336 dev_kfree_skb(skb);
1337 }
1338 ep->rx_ring[i].bufaddr = 0xBADF00D0; /* An invalid address. */
1339 }
1340 for (i = 0; i < TX_RING_SIZE; i++) {
1341 skb = ep->tx_skbuff[i];
1342 ep->tx_skbuff[i] = NULL;
1343 if (!skb)
1344 continue;
1345 pci_unmap_single(ep->pci_dev, ep->tx_ring[i].bufaddr,
1346 skb->len, PCI_DMA_TODEVICE);
1347 dev_kfree_skb(skb);
1348 }
1349
1350 /* Green! Leave the chip in low-power mode. */
1351 outl(0x0008, ioaddr + GENCTL);
1352
1353 return 0;
1354}
1355
1356static struct net_device_stats *epic_get_stats(struct net_device *dev)
1357{
1358 long ioaddr = dev->base_addr;
1359
1360 if (netif_running(dev)) {
1361 /* Update the error counts. */
1362 dev->stats.rx_missed_errors += inb(ioaddr + MPCNT);
1363 dev->stats.rx_frame_errors += inb(ioaddr + ALICNT);
1364 dev->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
1365 }
1366
1367 return &dev->stats;
1368}
1369
1370/* Set or clear the multicast filter for this adaptor.
1371 Note that we only use exclusion around actually queueing the
1372 new frame, not around filling ep->setup_frame. This is non-deterministic
1373 when re-entered but still correct. */
1374
1375static void set_rx_mode(struct net_device *dev)
1376{
1377 long ioaddr = dev->base_addr;
1378 struct epic_private *ep = netdev_priv(dev);
1379 unsigned char mc_filter[8]; /* Multicast hash filter */
1380 int i;
1381
1382 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1383 outl(0x002C, ioaddr + RxCtrl);
1384 /* Unconditionally log net taps. */
1385 memset(mc_filter, 0xff, sizeof(mc_filter));
1386 } else if ((!netdev_mc_empty(dev)) || (dev->flags & IFF_ALLMULTI)) {
1387 /* There is apparently a chip bug, so the multicast filter
1388 is never enabled. */
1389 /* Too many to filter perfectly -- accept all multicasts. */
1390 memset(mc_filter, 0xff, sizeof(mc_filter));
1391 outl(0x000C, ioaddr + RxCtrl);
1392 } else if (netdev_mc_empty(dev)) {
1393 outl(0x0004, ioaddr + RxCtrl);
1394 return;
1395 } else { /* Never executed, for now. */
1396 struct netdev_hw_addr *ha;
1397
1398 memset(mc_filter, 0, sizeof(mc_filter));
1399 netdev_for_each_mc_addr(ha, dev) {
1400 unsigned int bit_nr =
1401 ether_crc_le(ETH_ALEN, ha->addr) & 0x3f;
1402 mc_filter[bit_nr >> 3] |= (1 << bit_nr);
1403 }
1404 }
1405 /* ToDo: perhaps we need to stop the Tx and Rx process here? */
1406 if (memcmp(mc_filter, ep->mc_filter, sizeof(mc_filter))) {
1407 for (i = 0; i < 4; i++)
1408 outw(((u16 *)mc_filter)[i], ioaddr + MC0 + i*4);
1409 memcpy(ep->mc_filter, mc_filter, sizeof(mc_filter));
1410 }
1411}
1412
1413static void netdev_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1414{
1415 struct epic_private *np = netdev_priv(dev);
1416
1417 strcpy (info->driver, DRV_NAME);
1418 strcpy (info->version, DRV_VERSION);
1419 strcpy (info->bus_info, pci_name(np->pci_dev));
1420}
1421
1422static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1423{
1424 struct epic_private *np = netdev_priv(dev);
1425 int rc;
1426
1427 spin_lock_irq(&np->lock);
1428 rc = mii_ethtool_gset(&np->mii, cmd);
1429 spin_unlock_irq(&np->lock);
1430
1431 return rc;
1432}
1433
1434static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1435{
1436 struct epic_private *np = netdev_priv(dev);
1437 int rc;
1438
1439 spin_lock_irq(&np->lock);
1440 rc = mii_ethtool_sset(&np->mii, cmd);
1441 spin_unlock_irq(&np->lock);
1442
1443 return rc;
1444}
1445
1446static int netdev_nway_reset(struct net_device *dev)
1447{
1448 struct epic_private *np = netdev_priv(dev);
1449 return mii_nway_restart(&np->mii);
1450}
1451
1452static u32 netdev_get_link(struct net_device *dev)
1453{
1454 struct epic_private *np = netdev_priv(dev);
1455 return mii_link_ok(&np->mii);
1456}
1457
1458static u32 netdev_get_msglevel(struct net_device *dev)
1459{
1460 return debug;
1461}
1462
1463static void netdev_set_msglevel(struct net_device *dev, u32 value)
1464{
1465 debug = value;
1466}
1467
1468static int ethtool_begin(struct net_device *dev)
1469{
1470 unsigned long ioaddr = dev->base_addr;
1471 /* power-up, if interface is down */
1472 if (! netif_running(dev)) {
1473 outl(0x0200, ioaddr + GENCTL);
1474 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
1475 }
1476 return 0;
1477}
1478
1479static void ethtool_complete(struct net_device *dev)
1480{
1481 unsigned long ioaddr = dev->base_addr;
1482 /* power-down, if interface is down */
1483 if (! netif_running(dev)) {
1484 outl(0x0008, ioaddr + GENCTL);
1485 outl((inl(ioaddr + NVCTL) & ~0x483C) | 0x0000, ioaddr + NVCTL);
1486 }
1487}
1488
1489static const struct ethtool_ops netdev_ethtool_ops = {
1490 .get_drvinfo = netdev_get_drvinfo,
1491 .get_settings = netdev_get_settings,
1492 .set_settings = netdev_set_settings,
1493 .nway_reset = netdev_nway_reset,
1494 .get_link = netdev_get_link,
1495 .get_msglevel = netdev_get_msglevel,
1496 .set_msglevel = netdev_set_msglevel,
1497 .begin = ethtool_begin,
1498 .complete = ethtool_complete
1499};
1500
1501static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1502{
1503 struct epic_private *np = netdev_priv(dev);
1504 long ioaddr = dev->base_addr;
1505 struct mii_ioctl_data *data = if_mii(rq);
1506 int rc;
1507
1508 /* power-up, if interface is down */
1509 if (! netif_running(dev)) {
1510 outl(0x0200, ioaddr + GENCTL);
1511 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
1512 }
1513
1514 /* all non-ethtool ioctls (the SIOC[GS]MIIxxx ioctls) */
1515 spin_lock_irq(&np->lock);
1516 rc = generic_mii_ioctl(&np->mii, data, cmd, NULL);
1517 spin_unlock_irq(&np->lock);
1518
1519 /* power-down, if interface is down */
1520 if (! netif_running(dev)) {
1521 outl(0x0008, ioaddr + GENCTL);
1522 outl((inl(ioaddr + NVCTL) & ~0x483C) | 0x0000, ioaddr + NVCTL);
1523 }
1524 return rc;
1525}
1526
1527
1528static void __devexit epic_remove_one (struct pci_dev *pdev)
1529{
1530 struct net_device *dev = pci_get_drvdata(pdev);
1531 struct epic_private *ep = netdev_priv(dev);
1532
1533 pci_free_consistent(pdev, TX_TOTAL_SIZE, ep->tx_ring, ep->tx_ring_dma);
1534 pci_free_consistent(pdev, RX_TOTAL_SIZE, ep->rx_ring, ep->rx_ring_dma);
1535 unregister_netdev(dev);
1536#ifndef USE_IO_OPS
1537 iounmap((void*) dev->base_addr);
1538#endif
1539 pci_release_regions(pdev);
1540 free_netdev(dev);
1541 pci_disable_device(pdev);
1542 pci_set_drvdata(pdev, NULL);
1543 /* pci_power_off(pdev, -1); */
1544}
1545
1546
1547#ifdef CONFIG_PM
1548
1549static int epic_suspend (struct pci_dev *pdev, pm_message_t state)
1550{
1551 struct net_device *dev = pci_get_drvdata(pdev);
1552 long ioaddr = dev->base_addr;
1553
1554 if (!netif_running(dev))
1555 return 0;
1556 epic_pause(dev);
1557 /* Put the chip into low-power mode. */
1558 outl(0x0008, ioaddr + GENCTL);
1559 /* pci_power_off(pdev, -1); */
1560 return 0;
1561}
1562
1563
1564static int epic_resume (struct pci_dev *pdev)
1565{
1566 struct net_device *dev = pci_get_drvdata(pdev);
1567
1568 if (!netif_running(dev))
1569 return 0;
1570 epic_restart(dev);
1571 /* pci_power_on(pdev); */
1572 return 0;
1573}
1574
1575#endif /* CONFIG_PM */
1576
1577
1578static struct pci_driver epic_driver = {
1579 .name = DRV_NAME,
1580 .id_table = epic_pci_tbl,
1581 .probe = epic_init_one,
1582 .remove = __devexit_p(epic_remove_one),
1583#ifdef CONFIG_PM
1584 .suspend = epic_suspend,
1585 .resume = epic_resume,
1586#endif /* CONFIG_PM */
1587};
1588
1589
1590static int __init epic_init (void)
1591{
1592/* when a module, this is printed whether or not devices are found in probe */
1593#ifdef MODULE
1594 printk (KERN_INFO "%s%s",
1595 version, version2);
1596#endif
1597
1598 return pci_register_driver(&epic_driver);
1599}
1600
1601
1602static void __exit epic_cleanup (void)
1603{
1604 pci_unregister_driver (&epic_driver);
1605}
1606
1607
1608module_init(epic_init);
1609module_exit(epic_cleanup);
diff --git a/drivers/net/ethernet/smsc/smc911x.c b/drivers/net/ethernet/smsc/smc911x.c
new file mode 100644
index 000000000000..a91fe1723020
--- /dev/null
+++ b/drivers/net/ethernet/smsc/smc911x.c
@@ -0,0 +1,2210 @@
1/*
2 * smc911x.c
3 * This is a driver for SMSC's LAN911{5,6,7,8} single-chip Ethernet devices.
4 *
5 * Copyright (C) 2005 Sensoria Corp
6 * Derived from the unified SMC91x driver by Nicolas Pitre
7 * and the smsc911x.c reference driver by SMSC
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 * Arguments:
24 * watchdog = TX watchdog timeout
25 * tx_fifo_kb = Size of TX FIFO in KB
26 *
27 * History:
28 * 04/16/05 Dustin McIntire Initial version
29 */
30static const char version[] =
31 "smc911x.c: v1.0 04-16-2005 by Dustin McIntire <dustin@sensoria.com>\n";
32
33/* Debugging options */
34#define ENABLE_SMC_DEBUG_RX 0
35#define ENABLE_SMC_DEBUG_TX 0
36#define ENABLE_SMC_DEBUG_DMA 0
37#define ENABLE_SMC_DEBUG_PKTS 0
38#define ENABLE_SMC_DEBUG_MISC 0
39#define ENABLE_SMC_DEBUG_FUNC 0
40
41#define SMC_DEBUG_RX ((ENABLE_SMC_DEBUG_RX ? 1 : 0) << 0)
42#define SMC_DEBUG_TX ((ENABLE_SMC_DEBUG_TX ? 1 : 0) << 1)
43#define SMC_DEBUG_DMA ((ENABLE_SMC_DEBUG_DMA ? 1 : 0) << 2)
44#define SMC_DEBUG_PKTS ((ENABLE_SMC_DEBUG_PKTS ? 1 : 0) << 3)
45#define SMC_DEBUG_MISC ((ENABLE_SMC_DEBUG_MISC ? 1 : 0) << 4)
46#define SMC_DEBUG_FUNC ((ENABLE_SMC_DEBUG_FUNC ? 1 : 0) << 5)
47
48#ifndef SMC_DEBUG
49#define SMC_DEBUG ( SMC_DEBUG_RX | \
50 SMC_DEBUG_TX | \
51 SMC_DEBUG_DMA | \
52 SMC_DEBUG_PKTS | \
53 SMC_DEBUG_MISC | \
54 SMC_DEBUG_FUNC \
55 )
56#endif
57
58#include <linux/init.h>
59#include <linux/module.h>
60#include <linux/kernel.h>
61#include <linux/sched.h>
62#include <linux/delay.h>
63#include <linux/interrupt.h>
64#include <linux/errno.h>
65#include <linux/ioport.h>
66#include <linux/crc32.h>
67#include <linux/device.h>
68#include <linux/platform_device.h>
69#include <linux/spinlock.h>
70#include <linux/ethtool.h>
71#include <linux/mii.h>
72#include <linux/workqueue.h>
73
74#include <linux/netdevice.h>
75#include <linux/etherdevice.h>
76#include <linux/skbuff.h>
77
78#include <asm/io.h>
79
80#include "smc911x.h"
81
82/*
83 * Transmit timeout, default 5 seconds.
84 */
85static int watchdog = 5000;
86module_param(watchdog, int, 0400);
87MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
88
89static int tx_fifo_kb=8;
90module_param(tx_fifo_kb, int, 0400);
91MODULE_PARM_DESC(tx_fifo_kb,"transmit FIFO size in KB (1<x<15)(default=8)");
92
93MODULE_LICENSE("GPL");
94MODULE_ALIAS("platform:smc911x");
95
96/*
97 * The internal workings of the driver. If you are changing anything
98 * here with the SMC stuff, you should have the datasheet and know
99 * what you are doing.
100 */
101#define CARDNAME "smc911x"
102
103/*
104 * Use power-down feature of the chip
105 */
106#define POWER_DOWN 1
107
108#if SMC_DEBUG > 0
109#define DBG(n, args...) \
110 do { \
111 if (SMC_DEBUG & (n)) \
112 printk(args); \
113 } while (0)
114
115#define PRINTK(args...) printk(args)
116#else
117#define DBG(n, args...) do { } while (0)
118#define PRINTK(args...) printk(KERN_DEBUG args)
119#endif
120
121#if SMC_DEBUG_PKTS > 0
122static void PRINT_PKT(u_char *buf, int length)
123{
124 int i;
125 int remainder;
126 int lines;
127
128 lines = length / 16;
129 remainder = length % 16;
130
131 for (i = 0; i < lines ; i ++) {
132 int cur;
133 for (cur = 0; cur < 8; cur++) {
134 u_char a, b;
135 a = *buf++;
136 b = *buf++;
137 printk("%02x%02x ", a, b);
138 }
139 printk("\n");
140 }
141 for (i = 0; i < remainder/2 ; i++) {
142 u_char a, b;
143 a = *buf++;
144 b = *buf++;
145 printk("%02x%02x ", a, b);
146 }
147 printk("\n");
148}
149#else
150#define PRINT_PKT(x...) do { } while (0)
151#endif
152
153
154/* this enables an interrupt in the interrupt mask register */
155#define SMC_ENABLE_INT(lp, x) do { \
156 unsigned int __mask; \
157 __mask = SMC_GET_INT_EN((lp)); \
158 __mask |= (x); \
159 SMC_SET_INT_EN((lp), __mask); \
160} while (0)
161
162/* this disables an interrupt from the interrupt mask register */
163#define SMC_DISABLE_INT(lp, x) do { \
164 unsigned int __mask; \
165 __mask = SMC_GET_INT_EN((lp)); \
166 __mask &= ~(x); \
167 SMC_SET_INT_EN((lp), __mask); \
168} while (0)
169
170/*
171 * this does a soft reset on the device
172 */
173static void smc911x_reset(struct net_device *dev)
174{
175 struct smc911x_local *lp = netdev_priv(dev);
176 unsigned int reg, timeout=0, resets=1, irq_cfg;
177 unsigned long flags;
178
179 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
180
181 /* Take out of PM setting first */
182 if ((SMC_GET_PMT_CTRL(lp) & PMT_CTRL_READY_) == 0) {
183 /* Write to the bytetest will take out of powerdown */
184 SMC_SET_BYTE_TEST(lp, 0);
185 timeout=10;
186 do {
187 udelay(10);
188 reg = SMC_GET_PMT_CTRL(lp) & PMT_CTRL_READY_;
189 } while (--timeout && !reg);
190 if (timeout == 0) {
191 PRINTK("%s: smc911x_reset timeout waiting for PM restore\n", dev->name);
192 return;
193 }
194 }
195
196 /* Disable all interrupts */
197 spin_lock_irqsave(&lp->lock, flags);
198 SMC_SET_INT_EN(lp, 0);
199 spin_unlock_irqrestore(&lp->lock, flags);
200
201 while (resets--) {
202 SMC_SET_HW_CFG(lp, HW_CFG_SRST_);
203 timeout=10;
204 do {
205 udelay(10);
206 reg = SMC_GET_HW_CFG(lp);
207 /* If chip indicates reset timeout then try again */
208 if (reg & HW_CFG_SRST_TO_) {
209 PRINTK("%s: chip reset timeout, retrying...\n", dev->name);
210 resets++;
211 break;
212 }
213 } while (--timeout && (reg & HW_CFG_SRST_));
214 }
215 if (timeout == 0) {
216 PRINTK("%s: smc911x_reset timeout waiting for reset\n", dev->name);
217 return;
218 }
219
220 /* make sure EEPROM has finished loading before setting GPIO_CFG */
221 timeout=1000;
222 while (--timeout && (SMC_GET_E2P_CMD(lp) & E2P_CMD_EPC_BUSY_))
223 udelay(10);
224
225 if (timeout == 0){
226 PRINTK("%s: smc911x_reset timeout waiting for EEPROM busy\n", dev->name);
227 return;
228 }
229
230 /* Initialize interrupts */
231 SMC_SET_INT_EN(lp, 0);
232 SMC_ACK_INT(lp, -1);
233
234 /* Reset the FIFO level and flow control settings */
235 SMC_SET_HW_CFG(lp, (lp->tx_fifo_kb & 0xF) << 16);
236//TODO: Figure out what appropriate pause time is
237 SMC_SET_FLOW(lp, FLOW_FCPT_ | FLOW_FCEN_);
238 SMC_SET_AFC_CFG(lp, lp->afc_cfg);
239
240
241 /* Set to LED outputs */
242 SMC_SET_GPIO_CFG(lp, 0x70070000);
243
244 /*
245 * Deassert IRQ for 1*10us for edge type interrupts
246 * and drive IRQ pin push-pull
247 */
248 irq_cfg = (1 << 24) | INT_CFG_IRQ_EN_ | INT_CFG_IRQ_TYPE_;
249#ifdef SMC_DYNAMIC_BUS_CONFIG
250 if (lp->cfg.irq_polarity)
251 irq_cfg |= INT_CFG_IRQ_POL_;
252#endif
253 SMC_SET_IRQ_CFG(lp, irq_cfg);
254
255 /* clear anything saved */
256 if (lp->pending_tx_skb != NULL) {
257 dev_kfree_skb (lp->pending_tx_skb);
258 lp->pending_tx_skb = NULL;
259 dev->stats.tx_errors++;
260 dev->stats.tx_aborted_errors++;
261 }
262}
263
264/*
265 * Enable Interrupts, Receive, and Transmit
266 */
267static void smc911x_enable(struct net_device *dev)
268{
269 struct smc911x_local *lp = netdev_priv(dev);
270 unsigned mask, cfg, cr;
271 unsigned long flags;
272
273 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
274
275 spin_lock_irqsave(&lp->lock, flags);
276
277 SMC_SET_MAC_ADDR(lp, dev->dev_addr);
278
279 /* Enable TX */
280 cfg = SMC_GET_HW_CFG(lp);
281 cfg &= HW_CFG_TX_FIF_SZ_ | 0xFFF;
282 cfg |= HW_CFG_SF_;
283 SMC_SET_HW_CFG(lp, cfg);
284 SMC_SET_FIFO_TDA(lp, 0xFF);
285 /* Update TX stats on every 64 packets received or every 1 sec */
286 SMC_SET_FIFO_TSL(lp, 64);
287 SMC_SET_GPT_CFG(lp, GPT_CFG_TIMER_EN_ | 10000);
288
289 SMC_GET_MAC_CR(lp, cr);
290 cr |= MAC_CR_TXEN_ | MAC_CR_HBDIS_;
291 SMC_SET_MAC_CR(lp, cr);
292 SMC_SET_TX_CFG(lp, TX_CFG_TX_ON_);
293
294 /* Add 2 byte padding to start of packets */
295 SMC_SET_RX_CFG(lp, (2<<8) & RX_CFG_RXDOFF_);
296
297 /* Turn on receiver and enable RX */
298 if (cr & MAC_CR_RXEN_)
299 DBG(SMC_DEBUG_RX, "%s: Receiver already enabled\n", dev->name);
300
301 SMC_SET_MAC_CR(lp, cr | MAC_CR_RXEN_);
302
303 /* Interrupt on every received packet */
304 SMC_SET_FIFO_RSA(lp, 0x01);
305 SMC_SET_FIFO_RSL(lp, 0x00);
306
307 /* now, enable interrupts */
308 mask = INT_EN_TDFA_EN_ | INT_EN_TSFL_EN_ | INT_EN_RSFL_EN_ |
309 INT_EN_GPT_INT_EN_ | INT_EN_RXDFH_INT_EN_ | INT_EN_RXE_EN_ |
310 INT_EN_PHY_INT_EN_;
311 if (IS_REV_A(lp->revision))
312 mask|=INT_EN_RDFL_EN_;
313 else {
314 mask|=INT_EN_RDFO_EN_;
315 }
316 SMC_ENABLE_INT(lp, mask);
317
318 spin_unlock_irqrestore(&lp->lock, flags);
319}
320
321/*
322 * this puts the device in an inactive state
323 */
324static void smc911x_shutdown(struct net_device *dev)
325{
326 struct smc911x_local *lp = netdev_priv(dev);
327 unsigned cr;
328 unsigned long flags;
329
330 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", CARDNAME, __func__);
331
332 /* Disable IRQ's */
333 SMC_SET_INT_EN(lp, 0);
334
335 /* Turn of Rx and TX */
336 spin_lock_irqsave(&lp->lock, flags);
337 SMC_GET_MAC_CR(lp, cr);
338 cr &= ~(MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
339 SMC_SET_MAC_CR(lp, cr);
340 SMC_SET_TX_CFG(lp, TX_CFG_STOP_TX_);
341 spin_unlock_irqrestore(&lp->lock, flags);
342}
343
344static inline void smc911x_drop_pkt(struct net_device *dev)
345{
346 struct smc911x_local *lp = netdev_priv(dev);
347 unsigned int fifo_count, timeout, reg;
348
349 DBG(SMC_DEBUG_FUNC | SMC_DEBUG_RX, "%s: --> %s\n", CARDNAME, __func__);
350 fifo_count = SMC_GET_RX_FIFO_INF(lp) & 0xFFFF;
351 if (fifo_count <= 4) {
352 /* Manually dump the packet data */
353 while (fifo_count--)
354 SMC_GET_RX_FIFO(lp);
355 } else {
356 /* Fast forward through the bad packet */
357 SMC_SET_RX_DP_CTRL(lp, RX_DP_CTRL_FFWD_BUSY_);
358 timeout=50;
359 do {
360 udelay(10);
361 reg = SMC_GET_RX_DP_CTRL(lp) & RX_DP_CTRL_FFWD_BUSY_;
362 } while (--timeout && reg);
363 if (timeout == 0) {
364 PRINTK("%s: timeout waiting for RX fast forward\n", dev->name);
365 }
366 }
367}
368
369/*
370 * This is the procedure to handle the receipt of a packet.
371 * It should be called after checking for packet presence in
372 * the RX status FIFO. It must be called with the spin lock
373 * already held.
374 */
375static inline void smc911x_rcv(struct net_device *dev)
376{
377 struct smc911x_local *lp = netdev_priv(dev);
378 unsigned int pkt_len, status;
379 struct sk_buff *skb;
380 unsigned char *data;
381
382 DBG(SMC_DEBUG_FUNC | SMC_DEBUG_RX, "%s: --> %s\n",
383 dev->name, __func__);
384 status = SMC_GET_RX_STS_FIFO(lp);
385 DBG(SMC_DEBUG_RX, "%s: Rx pkt len %d status 0x%08x\n",
386 dev->name, (status & 0x3fff0000) >> 16, status & 0xc000ffff);
387 pkt_len = (status & RX_STS_PKT_LEN_) >> 16;
388 if (status & RX_STS_ES_) {
389 /* Deal with a bad packet */
390 dev->stats.rx_errors++;
391 if (status & RX_STS_CRC_ERR_)
392 dev->stats.rx_crc_errors++;
393 else {
394 if (status & RX_STS_LEN_ERR_)
395 dev->stats.rx_length_errors++;
396 if (status & RX_STS_MCAST_)
397 dev->stats.multicast++;
398 }
399 /* Remove the bad packet data from the RX FIFO */
400 smc911x_drop_pkt(dev);
401 } else {
402 /* Receive a valid packet */
403 /* Alloc a buffer with extra room for DMA alignment */
404 skb=dev_alloc_skb(pkt_len+32);
405 if (unlikely(skb == NULL)) {
406 PRINTK( "%s: Low memory, rcvd packet dropped.\n",
407 dev->name);
408 dev->stats.rx_dropped++;
409 smc911x_drop_pkt(dev);
410 return;
411 }
412 /* Align IP header to 32 bits
413 * Note that the device is configured to add a 2
414 * byte padding to the packet start, so we really
415 * want to write to the orignal data pointer */
416 data = skb->data;
417 skb_reserve(skb, 2);
418 skb_put(skb,pkt_len-4);
419#ifdef SMC_USE_DMA
420 {
421 unsigned int fifo;
422 /* Lower the FIFO threshold if possible */
423 fifo = SMC_GET_FIFO_INT(lp);
424 if (fifo & 0xFF) fifo--;
425 DBG(SMC_DEBUG_RX, "%s: Setting RX stat FIFO threshold to %d\n",
426 dev->name, fifo & 0xff);
427 SMC_SET_FIFO_INT(lp, fifo);
428 /* Setup RX DMA */
429 SMC_SET_RX_CFG(lp, RX_CFG_RX_END_ALGN16_ | ((2<<8) & RX_CFG_RXDOFF_));
430 lp->rxdma_active = 1;
431 lp->current_rx_skb = skb;
432 SMC_PULL_DATA(lp, data, (pkt_len+2+15) & ~15);
433 /* Packet processing deferred to DMA RX interrupt */
434 }
435#else
436 SMC_SET_RX_CFG(lp, RX_CFG_RX_END_ALGN4_ | ((2<<8) & RX_CFG_RXDOFF_));
437 SMC_PULL_DATA(lp, data, pkt_len+2+3);
438
439 DBG(SMC_DEBUG_PKTS, "%s: Received packet\n", dev->name);
440 PRINT_PKT(data, ((pkt_len - 4) <= 64) ? pkt_len - 4 : 64);
441 skb->protocol = eth_type_trans(skb, dev);
442 netif_rx(skb);
443 dev->stats.rx_packets++;
444 dev->stats.rx_bytes += pkt_len-4;
445#endif
446 }
447}
448
449/*
450 * This is called to actually send a packet to the chip.
451 */
452static void smc911x_hardware_send_pkt(struct net_device *dev)
453{
454 struct smc911x_local *lp = netdev_priv(dev);
455 struct sk_buff *skb;
456 unsigned int cmdA, cmdB, len;
457 unsigned char *buf;
458
459 DBG(SMC_DEBUG_FUNC | SMC_DEBUG_TX, "%s: --> %s\n", dev->name, __func__);
460 BUG_ON(lp->pending_tx_skb == NULL);
461
462 skb = lp->pending_tx_skb;
463 lp->pending_tx_skb = NULL;
464
465 /* cmdA {25:24] data alignment [20:16] start offset [10:0] buffer length */
466 /* cmdB {31:16] pkt tag [10:0] length */
467#ifdef SMC_USE_DMA
468 /* 16 byte buffer alignment mode */
469 buf = (char*)((u32)(skb->data) & ~0xF);
470 len = (skb->len + 0xF + ((u32)skb->data & 0xF)) & ~0xF;
471 cmdA = (1<<24) | (((u32)skb->data & 0xF)<<16) |
472 TX_CMD_A_INT_FIRST_SEG_ | TX_CMD_A_INT_LAST_SEG_ |
473 skb->len;
474#else
475 buf = (char*)((u32)skb->data & ~0x3);
476 len = (skb->len + 3 + ((u32)skb->data & 3)) & ~0x3;
477 cmdA = (((u32)skb->data & 0x3) << 16) |
478 TX_CMD_A_INT_FIRST_SEG_ | TX_CMD_A_INT_LAST_SEG_ |
479 skb->len;
480#endif
481 /* tag is packet length so we can use this in stats update later */
482 cmdB = (skb->len << 16) | (skb->len & 0x7FF);
483
484 DBG(SMC_DEBUG_TX, "%s: TX PKT LENGTH 0x%04x (%d) BUF 0x%p CMDA 0x%08x CMDB 0x%08x\n",
485 dev->name, len, len, buf, cmdA, cmdB);
486 SMC_SET_TX_FIFO(lp, cmdA);
487 SMC_SET_TX_FIFO(lp, cmdB);
488
489 DBG(SMC_DEBUG_PKTS, "%s: Transmitted packet\n", dev->name);
490 PRINT_PKT(buf, len <= 64 ? len : 64);
491
492 /* Send pkt via PIO or DMA */
493#ifdef SMC_USE_DMA
494 lp->current_tx_skb = skb;
495 SMC_PUSH_DATA(lp, buf, len);
496 /* DMA complete IRQ will free buffer and set jiffies */
497#else
498 SMC_PUSH_DATA(lp, buf, len);
499 dev->trans_start = jiffies;
500 dev_kfree_skb_irq(skb);
501#endif
502 if (!lp->tx_throttle) {
503 netif_wake_queue(dev);
504 }
505 SMC_ENABLE_INT(lp, INT_EN_TDFA_EN_ | INT_EN_TSFL_EN_);
506}
507
508/*
509 * Since I am not sure if I will have enough room in the chip's ram
510 * to store the packet, I call this routine which either sends it
511 * now, or set the card to generates an interrupt when ready
512 * for the packet.
513 */
514static int smc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
515{
516 struct smc911x_local *lp = netdev_priv(dev);
517 unsigned int free;
518 unsigned long flags;
519
520 DBG(SMC_DEBUG_FUNC | SMC_DEBUG_TX, "%s: --> %s\n",
521 dev->name, __func__);
522
523 spin_lock_irqsave(&lp->lock, flags);
524
525 BUG_ON(lp->pending_tx_skb != NULL);
526
527 free = SMC_GET_TX_FIFO_INF(lp) & TX_FIFO_INF_TDFREE_;
528 DBG(SMC_DEBUG_TX, "%s: TX free space %d\n", dev->name, free);
529
530 /* Turn off the flow when running out of space in FIFO */
531 if (free <= SMC911X_TX_FIFO_LOW_THRESHOLD) {
532 DBG(SMC_DEBUG_TX, "%s: Disabling data flow due to low FIFO space (%d)\n",
533 dev->name, free);
534 /* Reenable when at least 1 packet of size MTU present */
535 SMC_SET_FIFO_TDA(lp, (SMC911X_TX_FIFO_LOW_THRESHOLD)/64);
536 lp->tx_throttle = 1;
537 netif_stop_queue(dev);
538 }
539
540 /* Drop packets when we run out of space in TX FIFO
541 * Account for overhead required for:
542 *
543 * Tx command words 8 bytes
544 * Start offset 15 bytes
545 * End padding 15 bytes
546 */
547 if (unlikely(free < (skb->len + 8 + 15 + 15))) {
548 printk("%s: No Tx free space %d < %d\n",
549 dev->name, free, skb->len);
550 lp->pending_tx_skb = NULL;
551 dev->stats.tx_errors++;
552 dev->stats.tx_dropped++;
553 spin_unlock_irqrestore(&lp->lock, flags);
554 dev_kfree_skb(skb);
555 return NETDEV_TX_OK;
556 }
557
558#ifdef SMC_USE_DMA
559 {
560 /* If the DMA is already running then defer this packet Tx until
561 * the DMA IRQ starts it
562 */
563 if (lp->txdma_active) {
564 DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA, "%s: Tx DMA running, deferring packet\n", dev->name);
565 lp->pending_tx_skb = skb;
566 netif_stop_queue(dev);
567 spin_unlock_irqrestore(&lp->lock, flags);
568 return NETDEV_TX_OK;
569 } else {
570 DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA, "%s: Activating Tx DMA\n", dev->name);
571 lp->txdma_active = 1;
572 }
573 }
574#endif
575 lp->pending_tx_skb = skb;
576 smc911x_hardware_send_pkt(dev);
577 spin_unlock_irqrestore(&lp->lock, flags);
578
579 return NETDEV_TX_OK;
580}
581
582/*
583 * This handles a TX status interrupt, which is only called when:
584 * - a TX error occurred, or
585 * - TX of a packet completed.
586 */
587static void smc911x_tx(struct net_device *dev)
588{
589 struct smc911x_local *lp = netdev_priv(dev);
590 unsigned int tx_status;
591
592 DBG(SMC_DEBUG_FUNC | SMC_DEBUG_TX, "%s: --> %s\n",
593 dev->name, __func__);
594
595 /* Collect the TX status */
596 while (((SMC_GET_TX_FIFO_INF(lp) & TX_FIFO_INF_TSUSED_) >> 16) != 0) {
597 DBG(SMC_DEBUG_TX, "%s: Tx stat FIFO used 0x%04x\n",
598 dev->name,
599 (SMC_GET_TX_FIFO_INF(lp) & TX_FIFO_INF_TSUSED_) >> 16);
600 tx_status = SMC_GET_TX_STS_FIFO(lp);
601 dev->stats.tx_packets++;
602 dev->stats.tx_bytes+=tx_status>>16;
603 DBG(SMC_DEBUG_TX, "%s: Tx FIFO tag 0x%04x status 0x%04x\n",
604 dev->name, (tx_status & 0xffff0000) >> 16,
605 tx_status & 0x0000ffff);
606 /* count Tx errors, but ignore lost carrier errors when in
607 * full-duplex mode */
608 if ((tx_status & TX_STS_ES_) && !(lp->ctl_rfduplx &&
609 !(tx_status & 0x00000306))) {
610 dev->stats.tx_errors++;
611 }
612 if (tx_status & TX_STS_MANY_COLL_) {
613 dev->stats.collisions+=16;
614 dev->stats.tx_aborted_errors++;
615 } else {
616 dev->stats.collisions+=(tx_status & TX_STS_COLL_CNT_) >> 3;
617 }
618 /* carrier error only has meaning for half-duplex communication */
619 if ((tx_status & (TX_STS_LOC_ | TX_STS_NO_CARR_)) &&
620 !lp->ctl_rfduplx) {
621 dev->stats.tx_carrier_errors++;
622 }
623 if (tx_status & TX_STS_LATE_COLL_) {
624 dev->stats.collisions++;
625 dev->stats.tx_aborted_errors++;
626 }
627 }
628}
629
630
631/*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
632/*
633 * Reads a register from the MII Management serial interface
634 */
635
636static int smc911x_phy_read(struct net_device *dev, int phyaddr, int phyreg)
637{
638 struct smc911x_local *lp = netdev_priv(dev);
639 unsigned int phydata;
640
641 SMC_GET_MII(lp, phyreg, phyaddr, phydata);
642
643 DBG(SMC_DEBUG_MISC, "%s: phyaddr=0x%x, phyreg=0x%02x, phydata=0x%04x\n",
644 __func__, phyaddr, phyreg, phydata);
645 return phydata;
646}
647
648
649/*
650 * Writes a register to the MII Management serial interface
651 */
652static void smc911x_phy_write(struct net_device *dev, int phyaddr, int phyreg,
653 int phydata)
654{
655 struct smc911x_local *lp = netdev_priv(dev);
656
657 DBG(SMC_DEBUG_MISC, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
658 __func__, phyaddr, phyreg, phydata);
659
660 SMC_SET_MII(lp, phyreg, phyaddr, phydata);
661}
662
663/*
664 * Finds and reports the PHY address (115 and 117 have external
665 * PHY interface 118 has internal only
666 */
667static void smc911x_phy_detect(struct net_device *dev)
668{
669 struct smc911x_local *lp = netdev_priv(dev);
670 int phyaddr;
671 unsigned int cfg, id1, id2;
672
673 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
674
675 lp->phy_type = 0;
676
677 /*
678 * Scan all 32 PHY addresses if necessary, starting at
679 * PHY#1 to PHY#31, and then PHY#0 last.
680 */
681 switch(lp->version) {
682 case CHIP_9115:
683 case CHIP_9117:
684 case CHIP_9215:
685 case CHIP_9217:
686 cfg = SMC_GET_HW_CFG(lp);
687 if (cfg & HW_CFG_EXT_PHY_DET_) {
688 cfg &= ~HW_CFG_PHY_CLK_SEL_;
689 cfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
690 SMC_SET_HW_CFG(lp, cfg);
691 udelay(10); /* Wait for clocks to stop */
692
693 cfg |= HW_CFG_EXT_PHY_EN_;
694 SMC_SET_HW_CFG(lp, cfg);
695 udelay(10); /* Wait for clocks to stop */
696
697 cfg &= ~HW_CFG_PHY_CLK_SEL_;
698 cfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
699 SMC_SET_HW_CFG(lp, cfg);
700 udelay(10); /* Wait for clocks to stop */
701
702 cfg |= HW_CFG_SMI_SEL_;
703 SMC_SET_HW_CFG(lp, cfg);
704
705 for (phyaddr = 1; phyaddr < 32; ++phyaddr) {
706
707 /* Read the PHY identifiers */
708 SMC_GET_PHY_ID1(lp, phyaddr & 31, id1);
709 SMC_GET_PHY_ID2(lp, phyaddr & 31, id2);
710
711 /* Make sure it is a valid identifier */
712 if (id1 != 0x0000 && id1 != 0xffff &&
713 id1 != 0x8000 && id2 != 0x0000 &&
714 id2 != 0xffff && id2 != 0x8000) {
715 /* Save the PHY's address */
716 lp->mii.phy_id = phyaddr & 31;
717 lp->phy_type = id1 << 16 | id2;
718 break;
719 }
720 }
721 if (phyaddr < 32)
722 /* Found an external PHY */
723 break;
724 }
725 default:
726 /* Internal media only */
727 SMC_GET_PHY_ID1(lp, 1, id1);
728 SMC_GET_PHY_ID2(lp, 1, id2);
729 /* Save the PHY's address */
730 lp->mii.phy_id = 1;
731 lp->phy_type = id1 << 16 | id2;
732 }
733
734 DBG(SMC_DEBUG_MISC, "%s: phy_id1=0x%x, phy_id2=0x%x phyaddr=0x%d\n",
735 dev->name, id1, id2, lp->mii.phy_id);
736}
737
738/*
739 * Sets the PHY to a configuration as determined by the user.
740 * Called with spin_lock held.
741 */
742static int smc911x_phy_fixed(struct net_device *dev)
743{
744 struct smc911x_local *lp = netdev_priv(dev);
745 int phyaddr = lp->mii.phy_id;
746 int bmcr;
747
748 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
749
750 /* Enter Link Disable state */
751 SMC_GET_PHY_BMCR(lp, phyaddr, bmcr);
752 bmcr |= BMCR_PDOWN;
753 SMC_SET_PHY_BMCR(lp, phyaddr, bmcr);
754
755 /*
756 * Set our fixed capabilities
757 * Disable auto-negotiation
758 */
759 bmcr &= ~BMCR_ANENABLE;
760 if (lp->ctl_rfduplx)
761 bmcr |= BMCR_FULLDPLX;
762
763 if (lp->ctl_rspeed == 100)
764 bmcr |= BMCR_SPEED100;
765
766 /* Write our capabilities to the phy control register */
767 SMC_SET_PHY_BMCR(lp, phyaddr, bmcr);
768
769 /* Re-Configure the Receive/Phy Control register */
770 bmcr &= ~BMCR_PDOWN;
771 SMC_SET_PHY_BMCR(lp, phyaddr, bmcr);
772
773 return 1;
774}
775
776/*
777 * smc911x_phy_reset - reset the phy
778 * @dev: net device
779 * @phy: phy address
780 *
781 * Issue a software reset for the specified PHY and
782 * wait up to 100ms for the reset to complete. We should
783 * not access the PHY for 50ms after issuing the reset.
784 *
785 * The time to wait appears to be dependent on the PHY.
786 *
787 */
788static int smc911x_phy_reset(struct net_device *dev, int phy)
789{
790 struct smc911x_local *lp = netdev_priv(dev);
791 int timeout;
792 unsigned long flags;
793 unsigned int reg;
794
795 DBG(SMC_DEBUG_FUNC, "%s: --> %s()\n", dev->name, __func__);
796
797 spin_lock_irqsave(&lp->lock, flags);
798 reg = SMC_GET_PMT_CTRL(lp);
799 reg &= ~0xfffff030;
800 reg |= PMT_CTRL_PHY_RST_;
801 SMC_SET_PMT_CTRL(lp, reg);
802 spin_unlock_irqrestore(&lp->lock, flags);
803 for (timeout = 2; timeout; timeout--) {
804 msleep(50);
805 spin_lock_irqsave(&lp->lock, flags);
806 reg = SMC_GET_PMT_CTRL(lp);
807 spin_unlock_irqrestore(&lp->lock, flags);
808 if (!(reg & PMT_CTRL_PHY_RST_)) {
809 /* extra delay required because the phy may
810 * not be completed with its reset
811 * when PHY_BCR_RESET_ is cleared. 256us
812 * should suffice, but use 500us to be safe
813 */
814 udelay(500);
815 break;
816 }
817 }
818
819 return reg & PMT_CTRL_PHY_RST_;
820}
821
822/*
823 * smc911x_phy_powerdown - powerdown phy
824 * @dev: net device
825 * @phy: phy address
826 *
827 * Power down the specified PHY
828 */
829static void smc911x_phy_powerdown(struct net_device *dev, int phy)
830{
831 struct smc911x_local *lp = netdev_priv(dev);
832 unsigned int bmcr;
833
834 /* Enter Link Disable state */
835 SMC_GET_PHY_BMCR(lp, phy, bmcr);
836 bmcr |= BMCR_PDOWN;
837 SMC_SET_PHY_BMCR(lp, phy, bmcr);
838}
839
840/*
841 * smc911x_phy_check_media - check the media status and adjust BMCR
842 * @dev: net device
843 * @init: set true for initialisation
844 *
845 * Select duplex mode depending on negotiation state. This
846 * also updates our carrier state.
847 */
848static void smc911x_phy_check_media(struct net_device *dev, int init)
849{
850 struct smc911x_local *lp = netdev_priv(dev);
851 int phyaddr = lp->mii.phy_id;
852 unsigned int bmcr, cr;
853
854 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
855
856 if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) {
857 /* duplex state has changed */
858 SMC_GET_PHY_BMCR(lp, phyaddr, bmcr);
859 SMC_GET_MAC_CR(lp, cr);
860 if (lp->mii.full_duplex) {
861 DBG(SMC_DEBUG_MISC, "%s: Configuring for full-duplex mode\n", dev->name);
862 bmcr |= BMCR_FULLDPLX;
863 cr |= MAC_CR_RCVOWN_;
864 } else {
865 DBG(SMC_DEBUG_MISC, "%s: Configuring for half-duplex mode\n", dev->name);
866 bmcr &= ~BMCR_FULLDPLX;
867 cr &= ~MAC_CR_RCVOWN_;
868 }
869 SMC_SET_PHY_BMCR(lp, phyaddr, bmcr);
870 SMC_SET_MAC_CR(lp, cr);
871 }
872}
873
874/*
875 * Configures the specified PHY through the MII management interface
876 * using Autonegotiation.
877 * Calls smc911x_phy_fixed() if the user has requested a certain config.
878 * If RPC ANEG bit is set, the media selection is dependent purely on
879 * the selection by the MII (either in the MII BMCR reg or the result
880 * of autonegotiation.) If the RPC ANEG bit is cleared, the selection
881 * is controlled by the RPC SPEED and RPC DPLX bits.
882 */
883static void smc911x_phy_configure(struct work_struct *work)
884{
885 struct smc911x_local *lp = container_of(work, struct smc911x_local,
886 phy_configure);
887 struct net_device *dev = lp->netdev;
888 int phyaddr = lp->mii.phy_id;
889 int my_phy_caps; /* My PHY capabilities */
890 int my_ad_caps; /* My Advertised capabilities */
891 int status;
892 unsigned long flags;
893
894 DBG(SMC_DEBUG_FUNC, "%s: --> %s()\n", dev->name, __func__);
895
896 /*
897 * We should not be called if phy_type is zero.
898 */
899 if (lp->phy_type == 0)
900 return;
901
902 if (smc911x_phy_reset(dev, phyaddr)) {
903 printk("%s: PHY reset timed out\n", dev->name);
904 return;
905 }
906 spin_lock_irqsave(&lp->lock, flags);
907
908 /*
909 * Enable PHY Interrupts (for register 18)
910 * Interrupts listed here are enabled
911 */
912 SMC_SET_PHY_INT_MASK(lp, phyaddr, PHY_INT_MASK_ENERGY_ON_ |
913 PHY_INT_MASK_ANEG_COMP_ | PHY_INT_MASK_REMOTE_FAULT_ |
914 PHY_INT_MASK_LINK_DOWN_);
915
916 /* If the user requested no auto neg, then go set his request */
917 if (lp->mii.force_media) {
918 smc911x_phy_fixed(dev);
919 goto smc911x_phy_configure_exit;
920 }
921
922 /* Copy our capabilities from MII_BMSR to MII_ADVERTISE */
923 SMC_GET_PHY_BMSR(lp, phyaddr, my_phy_caps);
924 if (!(my_phy_caps & BMSR_ANEGCAPABLE)) {
925 printk(KERN_INFO "Auto negotiation NOT supported\n");
926 smc911x_phy_fixed(dev);
927 goto smc911x_phy_configure_exit;
928 }
929
930 /* CSMA capable w/ both pauses */
931 my_ad_caps = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
932
933 if (my_phy_caps & BMSR_100BASE4)
934 my_ad_caps |= ADVERTISE_100BASE4;
935 if (my_phy_caps & BMSR_100FULL)
936 my_ad_caps |= ADVERTISE_100FULL;
937 if (my_phy_caps & BMSR_100HALF)
938 my_ad_caps |= ADVERTISE_100HALF;
939 if (my_phy_caps & BMSR_10FULL)
940 my_ad_caps |= ADVERTISE_10FULL;
941 if (my_phy_caps & BMSR_10HALF)
942 my_ad_caps |= ADVERTISE_10HALF;
943
944 /* Disable capabilities not selected by our user */
945 if (lp->ctl_rspeed != 100)
946 my_ad_caps &= ~(ADVERTISE_100BASE4|ADVERTISE_100FULL|ADVERTISE_100HALF);
947
948 if (!lp->ctl_rfduplx)
949 my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL);
950
951 /* Update our Auto-Neg Advertisement Register */
952 SMC_SET_PHY_MII_ADV(lp, phyaddr, my_ad_caps);
953 lp->mii.advertising = my_ad_caps;
954
955 /*
956 * Read the register back. Without this, it appears that when
957 * auto-negotiation is restarted, sometimes it isn't ready and
958 * the link does not come up.
959 */
960 udelay(10);
961 SMC_GET_PHY_MII_ADV(lp, phyaddr, status);
962
963 DBG(SMC_DEBUG_MISC, "%s: phy caps=0x%04x\n", dev->name, my_phy_caps);
964 DBG(SMC_DEBUG_MISC, "%s: phy advertised caps=0x%04x\n", dev->name, my_ad_caps);
965
966 /* Restart auto-negotiation process in order to advertise my caps */
967 SMC_SET_PHY_BMCR(lp, phyaddr, BMCR_ANENABLE | BMCR_ANRESTART);
968
969 smc911x_phy_check_media(dev, 1);
970
971smc911x_phy_configure_exit:
972 spin_unlock_irqrestore(&lp->lock, flags);
973}
974
975/*
976 * smc911x_phy_interrupt
977 *
978 * Purpose: Handle interrupts relating to PHY register 18. This is
979 * called from the "hard" interrupt handler under our private spinlock.
980 */
981static void smc911x_phy_interrupt(struct net_device *dev)
982{
983 struct smc911x_local *lp = netdev_priv(dev);
984 int phyaddr = lp->mii.phy_id;
985 int status;
986
987 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
988
989 if (lp->phy_type == 0)
990 return;
991
992 smc911x_phy_check_media(dev, 0);
993 /* read to clear status bits */
994 SMC_GET_PHY_INT_SRC(lp, phyaddr,status);
995 DBG(SMC_DEBUG_MISC, "%s: PHY interrupt status 0x%04x\n",
996 dev->name, status & 0xffff);
997 DBG(SMC_DEBUG_MISC, "%s: AFC_CFG 0x%08x\n",
998 dev->name, SMC_GET_AFC_CFG(lp));
999}
1000
1001/*--- END PHY CONTROL AND CONFIGURATION-------------------------------------*/
1002
1003/*
1004 * This is the main routine of the driver, to handle the device when
1005 * it needs some attention.
1006 */
1007static irqreturn_t smc911x_interrupt(int irq, void *dev_id)
1008{
1009 struct net_device *dev = dev_id;
1010 struct smc911x_local *lp = netdev_priv(dev);
1011 unsigned int status, mask, timeout;
1012 unsigned int rx_overrun=0, cr, pkts;
1013 unsigned long flags;
1014
1015 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
1016
1017 spin_lock_irqsave(&lp->lock, flags);
1018
1019 /* Spurious interrupt check */
1020 if ((SMC_GET_IRQ_CFG(lp) & (INT_CFG_IRQ_INT_ | INT_CFG_IRQ_EN_)) !=
1021 (INT_CFG_IRQ_INT_ | INT_CFG_IRQ_EN_)) {
1022 spin_unlock_irqrestore(&lp->lock, flags);
1023 return IRQ_NONE;
1024 }
1025
1026 mask = SMC_GET_INT_EN(lp);
1027 SMC_SET_INT_EN(lp, 0);
1028
1029 /* set a timeout value, so I don't stay here forever */
1030 timeout = 8;
1031
1032
1033 do {
1034 status = SMC_GET_INT(lp);
1035
1036 DBG(SMC_DEBUG_MISC, "%s: INT 0x%08x MASK 0x%08x OUTSIDE MASK 0x%08x\n",
1037 dev->name, status, mask, status & ~mask);
1038
1039 status &= mask;
1040 if (!status)
1041 break;
1042
1043 /* Handle SW interrupt condition */
1044 if (status & INT_STS_SW_INT_) {
1045 SMC_ACK_INT(lp, INT_STS_SW_INT_);
1046 mask &= ~INT_EN_SW_INT_EN_;
1047 }
1048 /* Handle various error conditions */
1049 if (status & INT_STS_RXE_) {
1050 SMC_ACK_INT(lp, INT_STS_RXE_);
1051 dev->stats.rx_errors++;
1052 }
1053 if (status & INT_STS_RXDFH_INT_) {
1054 SMC_ACK_INT(lp, INT_STS_RXDFH_INT_);
1055 dev->stats.rx_dropped+=SMC_GET_RX_DROP(lp);
1056 }
1057 /* Undocumented interrupt-what is the right thing to do here? */
1058 if (status & INT_STS_RXDF_INT_) {
1059 SMC_ACK_INT(lp, INT_STS_RXDF_INT_);
1060 }
1061
1062 /* Rx Data FIFO exceeds set level */
1063 if (status & INT_STS_RDFL_) {
1064 if (IS_REV_A(lp->revision)) {
1065 rx_overrun=1;
1066 SMC_GET_MAC_CR(lp, cr);
1067 cr &= ~MAC_CR_RXEN_;
1068 SMC_SET_MAC_CR(lp, cr);
1069 DBG(SMC_DEBUG_RX, "%s: RX overrun\n", dev->name);
1070 dev->stats.rx_errors++;
1071 dev->stats.rx_fifo_errors++;
1072 }
1073 SMC_ACK_INT(lp, INT_STS_RDFL_);
1074 }
1075 if (status & INT_STS_RDFO_) {
1076 if (!IS_REV_A(lp->revision)) {
1077 SMC_GET_MAC_CR(lp, cr);
1078 cr &= ~MAC_CR_RXEN_;
1079 SMC_SET_MAC_CR(lp, cr);
1080 rx_overrun=1;
1081 DBG(SMC_DEBUG_RX, "%s: RX overrun\n", dev->name);
1082 dev->stats.rx_errors++;
1083 dev->stats.rx_fifo_errors++;
1084 }
1085 SMC_ACK_INT(lp, INT_STS_RDFO_);
1086 }
1087 /* Handle receive condition */
1088 if ((status & INT_STS_RSFL_) || rx_overrun) {
1089 unsigned int fifo;
1090 DBG(SMC_DEBUG_RX, "%s: RX irq\n", dev->name);
1091 fifo = SMC_GET_RX_FIFO_INF(lp);
1092 pkts = (fifo & RX_FIFO_INF_RXSUSED_) >> 16;
1093 DBG(SMC_DEBUG_RX, "%s: Rx FIFO pkts %d, bytes %d\n",
1094 dev->name, pkts, fifo & 0xFFFF );
1095 if (pkts != 0) {
1096#ifdef SMC_USE_DMA
1097 unsigned int fifo;
1098 if (lp->rxdma_active){
1099 DBG(SMC_DEBUG_RX | SMC_DEBUG_DMA,
1100 "%s: RX DMA active\n", dev->name);
1101 /* The DMA is already running so up the IRQ threshold */
1102 fifo = SMC_GET_FIFO_INT(lp) & ~0xFF;
1103 fifo |= pkts & 0xFF;
1104 DBG(SMC_DEBUG_RX,
1105 "%s: Setting RX stat FIFO threshold to %d\n",
1106 dev->name, fifo & 0xff);
1107 SMC_SET_FIFO_INT(lp, fifo);
1108 } else
1109#endif
1110 smc911x_rcv(dev);
1111 }
1112 SMC_ACK_INT(lp, INT_STS_RSFL_);
1113 }
1114 /* Handle transmit FIFO available */
1115 if (status & INT_STS_TDFA_) {
1116 DBG(SMC_DEBUG_TX, "%s: TX data FIFO space available irq\n", dev->name);
1117 SMC_SET_FIFO_TDA(lp, 0xFF);
1118 lp->tx_throttle = 0;
1119#ifdef SMC_USE_DMA
1120 if (!lp->txdma_active)
1121#endif
1122 netif_wake_queue(dev);
1123 SMC_ACK_INT(lp, INT_STS_TDFA_);
1124 }
1125 /* Handle transmit done condition */
1126#if 1
1127 if (status & (INT_STS_TSFL_ | INT_STS_GPT_INT_)) {
1128 DBG(SMC_DEBUG_TX | SMC_DEBUG_MISC,
1129 "%s: Tx stat FIFO limit (%d) /GPT irq\n",
1130 dev->name, (SMC_GET_FIFO_INT(lp) & 0x00ff0000) >> 16);
1131 smc911x_tx(dev);
1132 SMC_SET_GPT_CFG(lp, GPT_CFG_TIMER_EN_ | 10000);
1133 SMC_ACK_INT(lp, INT_STS_TSFL_);
1134 SMC_ACK_INT(lp, INT_STS_TSFL_ | INT_STS_GPT_INT_);
1135 }
1136#else
1137 if (status & INT_STS_TSFL_) {
1138 DBG(SMC_DEBUG_TX, "%s: TX status FIFO limit (%d) irq\n", dev->name, );
1139 smc911x_tx(dev);
1140 SMC_ACK_INT(lp, INT_STS_TSFL_);
1141 }
1142
1143 if (status & INT_STS_GPT_INT_) {
1144 DBG(SMC_DEBUG_RX, "%s: IRQ_CFG 0x%08x FIFO_INT 0x%08x RX_CFG 0x%08x\n",
1145 dev->name,
1146 SMC_GET_IRQ_CFG(lp),
1147 SMC_GET_FIFO_INT(lp),
1148 SMC_GET_RX_CFG(lp));
1149 DBG(SMC_DEBUG_RX, "%s: Rx Stat FIFO Used 0x%02x "
1150 "Data FIFO Used 0x%04x Stat FIFO 0x%08x\n",
1151 dev->name,
1152 (SMC_GET_RX_FIFO_INF(lp) & 0x00ff0000) >> 16,
1153 SMC_GET_RX_FIFO_INF(lp) & 0xffff,
1154 SMC_GET_RX_STS_FIFO_PEEK(lp));
1155 SMC_SET_GPT_CFG(lp, GPT_CFG_TIMER_EN_ | 10000);
1156 SMC_ACK_INT(lp, INT_STS_GPT_INT_);
1157 }
1158#endif
1159
1160 /* Handle PHY interrupt condition */
1161 if (status & INT_STS_PHY_INT_) {
1162 DBG(SMC_DEBUG_MISC, "%s: PHY irq\n", dev->name);
1163 smc911x_phy_interrupt(dev);
1164 SMC_ACK_INT(lp, INT_STS_PHY_INT_);
1165 }
1166 } while (--timeout);
1167
1168 /* restore mask state */
1169 SMC_SET_INT_EN(lp, mask);
1170
1171 DBG(SMC_DEBUG_MISC, "%s: Interrupt done (%d loops)\n",
1172 dev->name, 8-timeout);
1173
1174 spin_unlock_irqrestore(&lp->lock, flags);
1175
1176 return IRQ_HANDLED;
1177}
1178
1179#ifdef SMC_USE_DMA
1180static void
1181smc911x_tx_dma_irq(int dma, void *data)
1182{
1183 struct net_device *dev = (struct net_device *)data;
1184 struct smc911x_local *lp = netdev_priv(dev);
1185 struct sk_buff *skb = lp->current_tx_skb;
1186 unsigned long flags;
1187
1188 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
1189
1190 DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA, "%s: TX DMA irq handler\n", dev->name);
1191 /* Clear the DMA interrupt sources */
1192 SMC_DMA_ACK_IRQ(dev, dma);
1193 BUG_ON(skb == NULL);
1194 dma_unmap_single(NULL, tx_dmabuf, tx_dmalen, DMA_TO_DEVICE);
1195 dev->trans_start = jiffies;
1196 dev_kfree_skb_irq(skb);
1197 lp->current_tx_skb = NULL;
1198 if (lp->pending_tx_skb != NULL)
1199 smc911x_hardware_send_pkt(dev);
1200 else {
1201 DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA,
1202 "%s: No pending Tx packets. DMA disabled\n", dev->name);
1203 spin_lock_irqsave(&lp->lock, flags);
1204 lp->txdma_active = 0;
1205 if (!lp->tx_throttle) {
1206 netif_wake_queue(dev);
1207 }
1208 spin_unlock_irqrestore(&lp->lock, flags);
1209 }
1210
1211 DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA,
1212 "%s: TX DMA irq completed\n", dev->name);
1213}
1214static void
1215smc911x_rx_dma_irq(int dma, void *data)
1216{
1217 struct net_device *dev = (struct net_device *)data;
1218 unsigned long ioaddr = dev->base_addr;
1219 struct smc911x_local *lp = netdev_priv(dev);
1220 struct sk_buff *skb = lp->current_rx_skb;
1221 unsigned long flags;
1222 unsigned int pkts;
1223
1224 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
1225 DBG(SMC_DEBUG_RX | SMC_DEBUG_DMA, "%s: RX DMA irq handler\n", dev->name);
1226 /* Clear the DMA interrupt sources */
1227 SMC_DMA_ACK_IRQ(dev, dma);
1228 dma_unmap_single(NULL, rx_dmabuf, rx_dmalen, DMA_FROM_DEVICE);
1229 BUG_ON(skb == NULL);
1230 lp->current_rx_skb = NULL;
1231 PRINT_PKT(skb->data, skb->len);
1232 skb->protocol = eth_type_trans(skb, dev);
1233 dev->stats.rx_packets++;
1234 dev->stats.rx_bytes += skb->len;
1235 netif_rx(skb);
1236
1237 spin_lock_irqsave(&lp->lock, flags);
1238 pkts = (SMC_GET_RX_FIFO_INF(lp) & RX_FIFO_INF_RXSUSED_) >> 16;
1239 if (pkts != 0) {
1240 smc911x_rcv(dev);
1241 }else {
1242 lp->rxdma_active = 0;
1243 }
1244 spin_unlock_irqrestore(&lp->lock, flags);
1245 DBG(SMC_DEBUG_RX | SMC_DEBUG_DMA,
1246 "%s: RX DMA irq completed. DMA RX FIFO PKTS %d\n",
1247 dev->name, pkts);
1248}
1249#endif /* SMC_USE_DMA */
1250
1251#ifdef CONFIG_NET_POLL_CONTROLLER
1252/*
1253 * Polling receive - used by netconsole and other diagnostic tools
1254 * to allow network i/o with interrupts disabled.
1255 */
1256static void smc911x_poll_controller(struct net_device *dev)
1257{
1258 disable_irq(dev->irq);
1259 smc911x_interrupt(dev->irq, dev);
1260 enable_irq(dev->irq);
1261}
1262#endif
1263
1264/* Our watchdog timed out. Called by the networking layer */
1265static void smc911x_timeout(struct net_device *dev)
1266{
1267 struct smc911x_local *lp = netdev_priv(dev);
1268 int status, mask;
1269 unsigned long flags;
1270
1271 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
1272
1273 spin_lock_irqsave(&lp->lock, flags);
1274 status = SMC_GET_INT(lp);
1275 mask = SMC_GET_INT_EN(lp);
1276 spin_unlock_irqrestore(&lp->lock, flags);
1277 DBG(SMC_DEBUG_MISC, "%s: INT 0x%02x MASK 0x%02x\n",
1278 dev->name, status, mask);
1279
1280 /* Dump the current TX FIFO contents and restart */
1281 mask = SMC_GET_TX_CFG(lp);
1282 SMC_SET_TX_CFG(lp, mask | TX_CFG_TXS_DUMP_ | TX_CFG_TXD_DUMP_);
1283 /*
1284 * Reconfiguring the PHY doesn't seem like a bad idea here, but
1285 * smc911x_phy_configure() calls msleep() which calls schedule_timeout()
1286 * which calls schedule(). Hence we use a work queue.
1287 */
1288 if (lp->phy_type != 0)
1289 schedule_work(&lp->phy_configure);
1290
1291 /* We can accept TX packets again */
1292 dev->trans_start = jiffies; /* prevent tx timeout */
1293 netif_wake_queue(dev);
1294}
1295
1296/*
1297 * This routine will, depending on the values passed to it,
1298 * either make it accept multicast packets, go into
1299 * promiscuous mode (for TCPDUMP and cousins) or accept
1300 * a select set of multicast packets
1301 */
1302static void smc911x_set_multicast_list(struct net_device *dev)
1303{
1304 struct smc911x_local *lp = netdev_priv(dev);
1305 unsigned int multicast_table[2];
1306 unsigned int mcr, update_multicast = 0;
1307 unsigned long flags;
1308
1309 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
1310
1311 spin_lock_irqsave(&lp->lock, flags);
1312 SMC_GET_MAC_CR(lp, mcr);
1313 spin_unlock_irqrestore(&lp->lock, flags);
1314
1315 if (dev->flags & IFF_PROMISC) {
1316
1317 DBG(SMC_DEBUG_MISC, "%s: RCR_PRMS\n", dev->name);
1318 mcr |= MAC_CR_PRMS_;
1319 }
1320 /*
1321 * Here, I am setting this to accept all multicast packets.
1322 * I don't need to zero the multicast table, because the flag is
1323 * checked before the table is
1324 */
1325 else if (dev->flags & IFF_ALLMULTI || netdev_mc_count(dev) > 16) {
1326 DBG(SMC_DEBUG_MISC, "%s: RCR_ALMUL\n", dev->name);
1327 mcr |= MAC_CR_MCPAS_;
1328 }
1329
1330 /*
1331 * This sets the internal hardware table to filter out unwanted
1332 * multicast packets before they take up memory.
1333 *
1334 * The SMC chip uses a hash table where the high 6 bits of the CRC of
1335 * address are the offset into the table. If that bit is 1, then the
1336 * multicast packet is accepted. Otherwise, it's dropped silently.
1337 *
1338 * To use the 6 bits as an offset into the table, the high 1 bit is
1339 * the number of the 32 bit register, while the low 5 bits are the bit
1340 * within that register.
1341 */
1342 else if (!netdev_mc_empty(dev)) {
1343 struct netdev_hw_addr *ha;
1344
1345 /* Set the Hash perfec mode */
1346 mcr |= MAC_CR_HPFILT_;
1347
1348 /* start with a table of all zeros: reject all */
1349 memset(multicast_table, 0, sizeof(multicast_table));
1350
1351 netdev_for_each_mc_addr(ha, dev) {
1352 u32 position;
1353
1354 /* upper 6 bits are used as hash index */
1355 position = ether_crc(ETH_ALEN, ha->addr)>>26;
1356
1357 multicast_table[position>>5] |= 1 << (position&0x1f);
1358 }
1359
1360 /* be sure I get rid of flags I might have set */
1361 mcr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_);
1362
1363 /* now, the table can be loaded into the chipset */
1364 update_multicast = 1;
1365 } else {
1366 DBG(SMC_DEBUG_MISC, "%s: ~(MAC_CR_PRMS_|MAC_CR_MCPAS_)\n",
1367 dev->name);
1368 mcr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_);
1369
1370 /*
1371 * since I'm disabling all multicast entirely, I need to
1372 * clear the multicast list
1373 */
1374 memset(multicast_table, 0, sizeof(multicast_table));
1375 update_multicast = 1;
1376 }
1377
1378 spin_lock_irqsave(&lp->lock, flags);
1379 SMC_SET_MAC_CR(lp, mcr);
1380 if (update_multicast) {
1381 DBG(SMC_DEBUG_MISC,
1382 "%s: update mcast hash table 0x%08x 0x%08x\n",
1383 dev->name, multicast_table[0], multicast_table[1]);
1384 SMC_SET_HASHL(lp, multicast_table[0]);
1385 SMC_SET_HASHH(lp, multicast_table[1]);
1386 }
1387 spin_unlock_irqrestore(&lp->lock, flags);
1388}
1389
1390
1391/*
1392 * Open and Initialize the board
1393 *
1394 * Set up everything, reset the card, etc..
1395 */
1396static int
1397smc911x_open(struct net_device *dev)
1398{
1399 struct smc911x_local *lp = netdev_priv(dev);
1400
1401 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
1402
1403 /*
1404 * Check that the address is valid. If its not, refuse
1405 * to bring the device up. The user must specify an
1406 * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
1407 */
1408 if (!is_valid_ether_addr(dev->dev_addr)) {
1409 PRINTK("%s: no valid ethernet hw addr\n", __func__);
1410 return -EINVAL;
1411 }
1412
1413 /* reset the hardware */
1414 smc911x_reset(dev);
1415
1416 /* Configure the PHY, initialize the link state */
1417 smc911x_phy_configure(&lp->phy_configure);
1418
1419 /* Turn on Tx + Rx */
1420 smc911x_enable(dev);
1421
1422 netif_start_queue(dev);
1423
1424 return 0;
1425}
1426
1427/*
1428 * smc911x_close
1429 *
1430 * this makes the board clean up everything that it can
1431 * and not talk to the outside world. Caused by
1432 * an 'ifconfig ethX down'
1433 */
1434static int smc911x_close(struct net_device *dev)
1435{
1436 struct smc911x_local *lp = netdev_priv(dev);
1437
1438 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
1439
1440 netif_stop_queue(dev);
1441 netif_carrier_off(dev);
1442
1443 /* clear everything */
1444 smc911x_shutdown(dev);
1445
1446 if (lp->phy_type != 0) {
1447 /* We need to ensure that no calls to
1448 * smc911x_phy_configure are pending.
1449 */
1450 cancel_work_sync(&lp->phy_configure);
1451 smc911x_phy_powerdown(dev, lp->mii.phy_id);
1452 }
1453
1454 if (lp->pending_tx_skb) {
1455 dev_kfree_skb(lp->pending_tx_skb);
1456 lp->pending_tx_skb = NULL;
1457 }
1458
1459 return 0;
1460}
1461
1462/*
1463 * Ethtool support
1464 */
1465static int
1466smc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1467{
1468 struct smc911x_local *lp = netdev_priv(dev);
1469 int ret, status;
1470 unsigned long flags;
1471
1472 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
1473 cmd->maxtxpkt = 1;
1474 cmd->maxrxpkt = 1;
1475
1476 if (lp->phy_type != 0) {
1477 spin_lock_irqsave(&lp->lock, flags);
1478 ret = mii_ethtool_gset(&lp->mii, cmd);
1479 spin_unlock_irqrestore(&lp->lock, flags);
1480 } else {
1481 cmd->supported = SUPPORTED_10baseT_Half |
1482 SUPPORTED_10baseT_Full |
1483 SUPPORTED_TP | SUPPORTED_AUI;
1484
1485 if (lp->ctl_rspeed == 10)
1486 ethtool_cmd_speed_set(cmd, SPEED_10);
1487 else if (lp->ctl_rspeed == 100)
1488 ethtool_cmd_speed_set(cmd, SPEED_100);
1489
1490 cmd->autoneg = AUTONEG_DISABLE;
1491 if (lp->mii.phy_id==1)
1492 cmd->transceiver = XCVR_INTERNAL;
1493 else
1494 cmd->transceiver = XCVR_EXTERNAL;
1495 cmd->port = 0;
1496 SMC_GET_PHY_SPECIAL(lp, lp->mii.phy_id, status);
1497 cmd->duplex =
1498 (status & (PHY_SPECIAL_SPD_10FULL_ | PHY_SPECIAL_SPD_100FULL_)) ?
1499 DUPLEX_FULL : DUPLEX_HALF;
1500 ret = 0;
1501 }
1502
1503 return ret;
1504}
1505
1506static int
1507smc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1508{
1509 struct smc911x_local *lp = netdev_priv(dev);
1510 int ret;
1511 unsigned long flags;
1512
1513 if (lp->phy_type != 0) {
1514 spin_lock_irqsave(&lp->lock, flags);
1515 ret = mii_ethtool_sset(&lp->mii, cmd);
1516 spin_unlock_irqrestore(&lp->lock, flags);
1517 } else {
1518 if (cmd->autoneg != AUTONEG_DISABLE ||
1519 cmd->speed != SPEED_10 ||
1520 (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL) ||
1521 (cmd->port != PORT_TP && cmd->port != PORT_AUI))
1522 return -EINVAL;
1523
1524 lp->ctl_rfduplx = cmd->duplex == DUPLEX_FULL;
1525
1526 ret = 0;
1527 }
1528
1529 return ret;
1530}
1531
1532static void
1533smc911x_ethtool_getdrvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1534{
1535 strncpy(info->driver, CARDNAME, sizeof(info->driver));
1536 strncpy(info->version, version, sizeof(info->version));
1537 strncpy(info->bus_info, dev_name(dev->dev.parent), sizeof(info->bus_info));
1538}
1539
1540static int smc911x_ethtool_nwayreset(struct net_device *dev)
1541{
1542 struct smc911x_local *lp = netdev_priv(dev);
1543 int ret = -EINVAL;
1544 unsigned long flags;
1545
1546 if (lp->phy_type != 0) {
1547 spin_lock_irqsave(&lp->lock, flags);
1548 ret = mii_nway_restart(&lp->mii);
1549 spin_unlock_irqrestore(&lp->lock, flags);
1550 }
1551
1552 return ret;
1553}
1554
1555static u32 smc911x_ethtool_getmsglevel(struct net_device *dev)
1556{
1557 struct smc911x_local *lp = netdev_priv(dev);
1558 return lp->msg_enable;
1559}
1560
1561static void smc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
1562{
1563 struct smc911x_local *lp = netdev_priv(dev);
1564 lp->msg_enable = level;
1565}
1566
1567static int smc911x_ethtool_getregslen(struct net_device *dev)
1568{
1569 /* System regs + MAC regs + PHY regs */
1570 return (((E2P_CMD - ID_REV)/4 + 1) +
1571 (WUCSR - MAC_CR)+1 + 32) * sizeof(u32);
1572}
1573
1574static void smc911x_ethtool_getregs(struct net_device *dev,
1575 struct ethtool_regs* regs, void *buf)
1576{
1577 struct smc911x_local *lp = netdev_priv(dev);
1578 unsigned long flags;
1579 u32 reg,i,j=0;
1580 u32 *data = (u32*)buf;
1581
1582 regs->version = lp->version;
1583 for(i=ID_REV;i<=E2P_CMD;i+=4) {
1584 data[j++] = SMC_inl(lp, i);
1585 }
1586 for(i=MAC_CR;i<=WUCSR;i++) {
1587 spin_lock_irqsave(&lp->lock, flags);
1588 SMC_GET_MAC_CSR(lp, i, reg);
1589 spin_unlock_irqrestore(&lp->lock, flags);
1590 data[j++] = reg;
1591 }
1592 for(i=0;i<=31;i++) {
1593 spin_lock_irqsave(&lp->lock, flags);
1594 SMC_GET_MII(lp, i, lp->mii.phy_id, reg);
1595 spin_unlock_irqrestore(&lp->lock, flags);
1596 data[j++] = reg & 0xFFFF;
1597 }
1598}
1599
1600static int smc911x_ethtool_wait_eeprom_ready(struct net_device *dev)
1601{
1602 struct smc911x_local *lp = netdev_priv(dev);
1603 unsigned int timeout;
1604 int e2p_cmd;
1605
1606 e2p_cmd = SMC_GET_E2P_CMD(lp);
1607 for(timeout=10;(e2p_cmd & E2P_CMD_EPC_BUSY_) && timeout; timeout--) {
1608 if (e2p_cmd & E2P_CMD_EPC_TIMEOUT_) {
1609 PRINTK("%s: %s timeout waiting for EEPROM to respond\n",
1610 dev->name, __func__);
1611 return -EFAULT;
1612 }
1613 mdelay(1);
1614 e2p_cmd = SMC_GET_E2P_CMD(lp);
1615 }
1616 if (timeout == 0) {
1617 PRINTK("%s: %s timeout waiting for EEPROM CMD not busy\n",
1618 dev->name, __func__);
1619 return -ETIMEDOUT;
1620 }
1621 return 0;
1622}
1623
1624static inline int smc911x_ethtool_write_eeprom_cmd(struct net_device *dev,
1625 int cmd, int addr)
1626{
1627 struct smc911x_local *lp = netdev_priv(dev);
1628 int ret;
1629
1630 if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0)
1631 return ret;
1632 SMC_SET_E2P_CMD(lp, E2P_CMD_EPC_BUSY_ |
1633 ((cmd) & (0x7<<28)) |
1634 ((addr) & 0xFF));
1635 return 0;
1636}
1637
1638static inline int smc911x_ethtool_read_eeprom_byte(struct net_device *dev,
1639 u8 *data)
1640{
1641 struct smc911x_local *lp = netdev_priv(dev);
1642 int ret;
1643
1644 if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0)
1645 return ret;
1646 *data = SMC_GET_E2P_DATA(lp);
1647 return 0;
1648}
1649
1650static inline int smc911x_ethtool_write_eeprom_byte(struct net_device *dev,
1651 u8 data)
1652{
1653 struct smc911x_local *lp = netdev_priv(dev);
1654 int ret;
1655
1656 if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0)
1657 return ret;
1658 SMC_SET_E2P_DATA(lp, data);
1659 return 0;
1660}
1661
1662static int smc911x_ethtool_geteeprom(struct net_device *dev,
1663 struct ethtool_eeprom *eeprom, u8 *data)
1664{
1665 u8 eebuf[SMC911X_EEPROM_LEN];
1666 int i, ret;
1667
1668 for(i=0;i<SMC911X_EEPROM_LEN;i++) {
1669 if ((ret=smc911x_ethtool_write_eeprom_cmd(dev, E2P_CMD_EPC_CMD_READ_, i ))!=0)
1670 return ret;
1671 if ((ret=smc911x_ethtool_read_eeprom_byte(dev, &eebuf[i]))!=0)
1672 return ret;
1673 }
1674 memcpy(data, eebuf+eeprom->offset, eeprom->len);
1675 return 0;
1676}
1677
1678static int smc911x_ethtool_seteeprom(struct net_device *dev,
1679 struct ethtool_eeprom *eeprom, u8 *data)
1680{
1681 int i, ret;
1682
1683 /* Enable erase */
1684 if ((ret=smc911x_ethtool_write_eeprom_cmd(dev, E2P_CMD_EPC_CMD_EWEN_, 0 ))!=0)
1685 return ret;
1686 for(i=eeprom->offset;i<(eeprom->offset+eeprom->len);i++) {
1687 /* erase byte */
1688 if ((ret=smc911x_ethtool_write_eeprom_cmd(dev, E2P_CMD_EPC_CMD_ERASE_, i ))!=0)
1689 return ret;
1690 /* write byte */
1691 if ((ret=smc911x_ethtool_write_eeprom_byte(dev, *data))!=0)
1692 return ret;
1693 if ((ret=smc911x_ethtool_write_eeprom_cmd(dev, E2P_CMD_EPC_CMD_WRITE_, i ))!=0)
1694 return ret;
1695 }
1696 return 0;
1697}
1698
1699static int smc911x_ethtool_geteeprom_len(struct net_device *dev)
1700{
1701 return SMC911X_EEPROM_LEN;
1702}
1703
1704static const struct ethtool_ops smc911x_ethtool_ops = {
1705 .get_settings = smc911x_ethtool_getsettings,
1706 .set_settings = smc911x_ethtool_setsettings,
1707 .get_drvinfo = smc911x_ethtool_getdrvinfo,
1708 .get_msglevel = smc911x_ethtool_getmsglevel,
1709 .set_msglevel = smc911x_ethtool_setmsglevel,
1710 .nway_reset = smc911x_ethtool_nwayreset,
1711 .get_link = ethtool_op_get_link,
1712 .get_regs_len = smc911x_ethtool_getregslen,
1713 .get_regs = smc911x_ethtool_getregs,
1714 .get_eeprom_len = smc911x_ethtool_geteeprom_len,
1715 .get_eeprom = smc911x_ethtool_geteeprom,
1716 .set_eeprom = smc911x_ethtool_seteeprom,
1717};
1718
1719/*
1720 * smc911x_findirq
1721 *
1722 * This routine has a simple purpose -- make the SMC chip generate an
1723 * interrupt, so an auto-detect routine can detect it, and find the IRQ,
1724 */
1725static int __devinit smc911x_findirq(struct net_device *dev)
1726{
1727 struct smc911x_local *lp = netdev_priv(dev);
1728 int timeout = 20;
1729 unsigned long cookie;
1730
1731 DBG(SMC_DEBUG_FUNC, "--> %s\n", __func__);
1732
1733 cookie = probe_irq_on();
1734
1735 /*
1736 * Force a SW interrupt
1737 */
1738
1739 SMC_SET_INT_EN(lp, INT_EN_SW_INT_EN_);
1740
1741 /*
1742 * Wait until positive that the interrupt has been generated
1743 */
1744 do {
1745 int int_status;
1746 udelay(10);
1747 int_status = SMC_GET_INT_EN(lp);
1748 if (int_status & INT_EN_SW_INT_EN_)
1749 break; /* got the interrupt */
1750 } while (--timeout);
1751
1752 /*
1753 * there is really nothing that I can do here if timeout fails,
1754 * as autoirq_report will return a 0 anyway, which is what I
1755 * want in this case. Plus, the clean up is needed in both
1756 * cases.
1757 */
1758
1759 /* and disable all interrupts again */
1760 SMC_SET_INT_EN(lp, 0);
1761
1762 /* and return what I found */
1763 return probe_irq_off(cookie);
1764}
1765
1766static const struct net_device_ops smc911x_netdev_ops = {
1767 .ndo_open = smc911x_open,
1768 .ndo_stop = smc911x_close,
1769 .ndo_start_xmit = smc911x_hard_start_xmit,
1770 .ndo_tx_timeout = smc911x_timeout,
1771 .ndo_set_multicast_list = smc911x_set_multicast_list,
1772 .ndo_change_mtu = eth_change_mtu,
1773 .ndo_validate_addr = eth_validate_addr,
1774 .ndo_set_mac_address = eth_mac_addr,
1775#ifdef CONFIG_NET_POLL_CONTROLLER
1776 .ndo_poll_controller = smc911x_poll_controller,
1777#endif
1778};
1779
1780/*
1781 * Function: smc911x_probe(unsigned long ioaddr)
1782 *
1783 * Purpose:
1784 * Tests to see if a given ioaddr points to an SMC911x chip.
1785 * Returns a 0 on success
1786 *
1787 * Algorithm:
1788 * (1) see if the endian word is OK
1789 * (1) see if I recognize the chip ID in the appropriate register
1790 *
1791 * Here I do typical initialization tasks.
1792 *
1793 * o Initialize the structure if needed
1794 * o print out my vanity message if not done so already
1795 * o print out what type of hardware is detected
1796 * o print out the ethernet address
1797 * o find the IRQ
1798 * o set up my private data
1799 * o configure the dev structure with my subroutines
1800 * o actually GRAB the irq.
1801 * o GRAB the region
1802 */
1803static int __devinit smc911x_probe(struct net_device *dev)
1804{
1805 struct smc911x_local *lp = netdev_priv(dev);
1806 int i, retval;
1807 unsigned int val, chip_id, revision;
1808 const char *version_string;
1809 unsigned long irq_flags;
1810
1811 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __func__);
1812
1813 /* First, see if the endian word is recognized */
1814 val = SMC_GET_BYTE_TEST(lp);
1815 DBG(SMC_DEBUG_MISC, "%s: endian probe returned 0x%04x\n", CARDNAME, val);
1816 if (val != 0x87654321) {
1817 printk(KERN_ERR "Invalid chip endian 0x%08x\n",val);
1818 retval = -ENODEV;
1819 goto err_out;
1820 }
1821
1822 /*
1823 * check if the revision register is something that I
1824 * recognize. These might need to be added to later,
1825 * as future revisions could be added.
1826 */
1827 chip_id = SMC_GET_PN(lp);
1828 DBG(SMC_DEBUG_MISC, "%s: id probe returned 0x%04x\n", CARDNAME, chip_id);
1829 for(i=0;chip_ids[i].id != 0; i++) {
1830 if (chip_ids[i].id == chip_id) break;
1831 }
1832 if (!chip_ids[i].id) {
1833 printk(KERN_ERR "Unknown chip ID %04x\n", chip_id);
1834 retval = -ENODEV;
1835 goto err_out;
1836 }
1837 version_string = chip_ids[i].name;
1838
1839 revision = SMC_GET_REV(lp);
1840 DBG(SMC_DEBUG_MISC, "%s: revision = 0x%04x\n", CARDNAME, revision);
1841
1842 /* At this point I'll assume that the chip is an SMC911x. */
1843 DBG(SMC_DEBUG_MISC, "%s: Found a %s\n", CARDNAME, chip_ids[i].name);
1844
1845 /* Validate the TX FIFO size requested */
1846 if ((tx_fifo_kb < 2) || (tx_fifo_kb > 14)) {
1847 printk(KERN_ERR "Invalid TX FIFO size requested %d\n", tx_fifo_kb);
1848 retval = -EINVAL;
1849 goto err_out;
1850 }
1851
1852 /* fill in some of the fields */
1853 lp->version = chip_ids[i].id;
1854 lp->revision = revision;
1855 lp->tx_fifo_kb = tx_fifo_kb;
1856 /* Reverse calculate the RX FIFO size from the TX */
1857 lp->tx_fifo_size=(lp->tx_fifo_kb<<10) - 512;
1858 lp->rx_fifo_size= ((0x4000 - 512 - lp->tx_fifo_size) / 16) * 15;
1859
1860 /* Set the automatic flow control values */
1861 switch(lp->tx_fifo_kb) {
1862 /*
1863 * AFC_HI is about ((Rx Data Fifo Size)*2/3)/64
1864 * AFC_LO is AFC_HI/2
1865 * BACK_DUR is about 5uS*(AFC_LO) rounded down
1866 */
1867 case 2:/* 13440 Rx Data Fifo Size */
1868 lp->afc_cfg=0x008C46AF;break;
1869 case 3:/* 12480 Rx Data Fifo Size */
1870 lp->afc_cfg=0x0082419F;break;
1871 case 4:/* 11520 Rx Data Fifo Size */
1872 lp->afc_cfg=0x00783C9F;break;
1873 case 5:/* 10560 Rx Data Fifo Size */
1874 lp->afc_cfg=0x006E374F;break;
1875 case 6:/* 9600 Rx Data Fifo Size */
1876 lp->afc_cfg=0x0064328F;break;
1877 case 7:/* 8640 Rx Data Fifo Size */
1878 lp->afc_cfg=0x005A2D7F;break;
1879 case 8:/* 7680 Rx Data Fifo Size */
1880 lp->afc_cfg=0x0050287F;break;
1881 case 9:/* 6720 Rx Data Fifo Size */
1882 lp->afc_cfg=0x0046236F;break;
1883 case 10:/* 5760 Rx Data Fifo Size */
1884 lp->afc_cfg=0x003C1E6F;break;
1885 case 11:/* 4800 Rx Data Fifo Size */
1886 lp->afc_cfg=0x0032195F;break;
1887 /*
1888 * AFC_HI is ~1520 bytes less than RX Data Fifo Size
1889 * AFC_LO is AFC_HI/2
1890 * BACK_DUR is about 5uS*(AFC_LO) rounded down
1891 */
1892 case 12:/* 3840 Rx Data Fifo Size */
1893 lp->afc_cfg=0x0024124F;break;
1894 case 13:/* 2880 Rx Data Fifo Size */
1895 lp->afc_cfg=0x0015073F;break;
1896 case 14:/* 1920 Rx Data Fifo Size */
1897 lp->afc_cfg=0x0006032F;break;
1898 default:
1899 PRINTK("%s: ERROR -- no AFC_CFG setting found",
1900 dev->name);
1901 break;
1902 }
1903
1904 DBG(SMC_DEBUG_MISC | SMC_DEBUG_TX | SMC_DEBUG_RX,
1905 "%s: tx_fifo %d rx_fifo %d afc_cfg 0x%08x\n", CARDNAME,
1906 lp->tx_fifo_size, lp->rx_fifo_size, lp->afc_cfg);
1907
1908 spin_lock_init(&lp->lock);
1909
1910 /* Get the MAC address */
1911 SMC_GET_MAC_ADDR(lp, dev->dev_addr);
1912
1913 /* now, reset the chip, and put it into a known state */
1914 smc911x_reset(dev);
1915
1916 /*
1917 * If dev->irq is 0, then the device has to be banged on to see
1918 * what the IRQ is.
1919 *
1920 * Specifying an IRQ is done with the assumption that the user knows
1921 * what (s)he is doing. No checking is done!!!!
1922 */
1923 if (dev->irq < 1) {
1924 int trials;
1925
1926 trials = 3;
1927 while (trials--) {
1928 dev->irq = smc911x_findirq(dev);
1929 if (dev->irq)
1930 break;
1931 /* kick the card and try again */
1932 smc911x_reset(dev);
1933 }
1934 }
1935 if (dev->irq == 0) {
1936 printk("%s: Couldn't autodetect your IRQ. Use irq=xx.\n",
1937 dev->name);
1938 retval = -ENODEV;
1939 goto err_out;
1940 }
1941 dev->irq = irq_canonicalize(dev->irq);
1942
1943 /* Fill in the fields of the device structure with ethernet values. */
1944 ether_setup(dev);
1945
1946 dev->netdev_ops = &smc911x_netdev_ops;
1947 dev->watchdog_timeo = msecs_to_jiffies(watchdog);
1948 dev->ethtool_ops = &smc911x_ethtool_ops;
1949
1950 INIT_WORK(&lp->phy_configure, smc911x_phy_configure);
1951 lp->mii.phy_id_mask = 0x1f;
1952 lp->mii.reg_num_mask = 0x1f;
1953 lp->mii.force_media = 0;
1954 lp->mii.full_duplex = 0;
1955 lp->mii.dev = dev;
1956 lp->mii.mdio_read = smc911x_phy_read;
1957 lp->mii.mdio_write = smc911x_phy_write;
1958
1959 /*
1960 * Locate the phy, if any.
1961 */
1962 smc911x_phy_detect(dev);
1963
1964 /* Set default parameters */
1965 lp->msg_enable = NETIF_MSG_LINK;
1966 lp->ctl_rfduplx = 1;
1967 lp->ctl_rspeed = 100;
1968
1969#ifdef SMC_DYNAMIC_BUS_CONFIG
1970 irq_flags = lp->cfg.irq_flags;
1971#else
1972 irq_flags = IRQF_SHARED | SMC_IRQ_SENSE;
1973#endif
1974
1975 /* Grab the IRQ */
1976 retval = request_irq(dev->irq, smc911x_interrupt,
1977 irq_flags, dev->name, dev);
1978 if (retval)
1979 goto err_out;
1980
1981#ifdef SMC_USE_DMA
1982 lp->rxdma = SMC_DMA_REQUEST(dev, smc911x_rx_dma_irq);
1983 lp->txdma = SMC_DMA_REQUEST(dev, smc911x_tx_dma_irq);
1984 lp->rxdma_active = 0;
1985 lp->txdma_active = 0;
1986 dev->dma = lp->rxdma;
1987#endif
1988
1989 retval = register_netdev(dev);
1990 if (retval == 0) {
1991 /* now, print out the card info, in a short format.. */
1992 printk("%s: %s (rev %d) at %#lx IRQ %d",
1993 dev->name, version_string, lp->revision,
1994 dev->base_addr, dev->irq);
1995
1996#ifdef SMC_USE_DMA
1997 if (lp->rxdma != -1)
1998 printk(" RXDMA %d ", lp->rxdma);
1999
2000 if (lp->txdma != -1)
2001 printk("TXDMA %d", lp->txdma);
2002#endif
2003 printk("\n");
2004 if (!is_valid_ether_addr(dev->dev_addr)) {
2005 printk("%s: Invalid ethernet MAC address. Please "
2006 "set using ifconfig\n", dev->name);
2007 } else {
2008 /* Print the Ethernet address */
2009 printk("%s: Ethernet addr: %pM\n",
2010 dev->name, dev->dev_addr);
2011 }
2012
2013 if (lp->phy_type == 0) {
2014 PRINTK("%s: No PHY found\n", dev->name);
2015 } else if ((lp->phy_type & ~0xff) == LAN911X_INTERNAL_PHY_ID) {
2016 PRINTK("%s: LAN911x Internal PHY\n", dev->name);
2017 } else {
2018 PRINTK("%s: External PHY 0x%08x\n", dev->name, lp->phy_type);
2019 }
2020 }
2021
2022err_out:
2023#ifdef SMC_USE_DMA
2024 if (retval) {
2025 if (lp->rxdma != -1) {
2026 SMC_DMA_FREE(dev, lp->rxdma);
2027 }
2028 if (lp->txdma != -1) {
2029 SMC_DMA_FREE(dev, lp->txdma);
2030 }
2031 }
2032#endif
2033 return retval;
2034}
2035
2036/*
2037 * smc911x_init(void)
2038 *
2039 * Output:
2040 * 0 --> there is a device
2041 * anything else, error
2042 */
2043static int __devinit smc911x_drv_probe(struct platform_device *pdev)
2044{
2045 struct net_device *ndev;
2046 struct resource *res;
2047 struct smc911x_local *lp;
2048 unsigned int *addr;
2049 int ret;
2050
2051 DBG(SMC_DEBUG_FUNC, "--> %s\n", __func__);
2052 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2053 if (!res) {
2054 ret = -ENODEV;
2055 goto out;
2056 }
2057
2058 /*
2059 * Request the regions.
2060 */
2061 if (!request_mem_region(res->start, SMC911X_IO_EXTENT, CARDNAME)) {
2062 ret = -EBUSY;
2063 goto out;
2064 }
2065
2066 ndev = alloc_etherdev(sizeof(struct smc911x_local));
2067 if (!ndev) {
2068 printk("%s: could not allocate device.\n", CARDNAME);
2069 ret = -ENOMEM;
2070 goto release_1;
2071 }
2072 SET_NETDEV_DEV(ndev, &pdev->dev);
2073
2074 ndev->dma = (unsigned char)-1;
2075 ndev->irq = platform_get_irq(pdev, 0);
2076 lp = netdev_priv(ndev);
2077 lp->netdev = ndev;
2078#ifdef SMC_DYNAMIC_BUS_CONFIG
2079 {
2080 struct smc911x_platdata *pd = pdev->dev.platform_data;
2081 if (!pd) {
2082 ret = -EINVAL;
2083 goto release_both;
2084 }
2085 memcpy(&lp->cfg, pd, sizeof(lp->cfg));
2086 }
2087#endif
2088
2089 addr = ioremap(res->start, SMC911X_IO_EXTENT);
2090 if (!addr) {
2091 ret = -ENOMEM;
2092 goto release_both;
2093 }
2094
2095 platform_set_drvdata(pdev, ndev);
2096 lp->base = addr;
2097 ndev->base_addr = res->start;
2098 ret = smc911x_probe(ndev);
2099 if (ret != 0) {
2100 platform_set_drvdata(pdev, NULL);
2101 iounmap(addr);
2102release_both:
2103 free_netdev(ndev);
2104release_1:
2105 release_mem_region(res->start, SMC911X_IO_EXTENT);
2106out:
2107 printk("%s: not found (%d).\n", CARDNAME, ret);
2108 }
2109#ifdef SMC_USE_DMA
2110 else {
2111 lp->physaddr = res->start;
2112 lp->dev = &pdev->dev;
2113 }
2114#endif
2115
2116 return ret;
2117}
2118
2119static int __devexit smc911x_drv_remove(struct platform_device *pdev)
2120{
2121 struct net_device *ndev = platform_get_drvdata(pdev);
2122 struct smc911x_local *lp = netdev_priv(ndev);
2123 struct resource *res;
2124
2125 DBG(SMC_DEBUG_FUNC, "--> %s\n", __func__);
2126 platform_set_drvdata(pdev, NULL);
2127
2128 unregister_netdev(ndev);
2129
2130 free_irq(ndev->irq, ndev);
2131
2132#ifdef SMC_USE_DMA
2133 {
2134 if (lp->rxdma != -1) {
2135 SMC_DMA_FREE(dev, lp->rxdma);
2136 }
2137 if (lp->txdma != -1) {
2138 SMC_DMA_FREE(dev, lp->txdma);
2139 }
2140 }
2141#endif
2142 iounmap(lp->base);
2143 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2144 release_mem_region(res->start, SMC911X_IO_EXTENT);
2145
2146 free_netdev(ndev);
2147 return 0;
2148}
2149
2150static int smc911x_drv_suspend(struct platform_device *dev, pm_message_t state)
2151{
2152 struct net_device *ndev = platform_get_drvdata(dev);
2153 struct smc911x_local *lp = netdev_priv(ndev);
2154
2155 DBG(SMC_DEBUG_FUNC, "--> %s\n", __func__);
2156 if (ndev) {
2157 if (netif_running(ndev)) {
2158 netif_device_detach(ndev);
2159 smc911x_shutdown(ndev);
2160#if POWER_DOWN
2161 /* Set D2 - Energy detect only setting */
2162 SMC_SET_PMT_CTRL(lp, 2<<12);
2163#endif
2164 }
2165 }
2166 return 0;
2167}
2168
2169static int smc911x_drv_resume(struct platform_device *dev)
2170{
2171 struct net_device *ndev = platform_get_drvdata(dev);
2172
2173 DBG(SMC_DEBUG_FUNC, "--> %s\n", __func__);
2174 if (ndev) {
2175 struct smc911x_local *lp = netdev_priv(ndev);
2176
2177 if (netif_running(ndev)) {
2178 smc911x_reset(ndev);
2179 if (lp->phy_type != 0)
2180 smc911x_phy_configure(&lp->phy_configure);
2181 smc911x_enable(ndev);
2182 netif_device_attach(ndev);
2183 }
2184 }
2185 return 0;
2186}
2187
2188static struct platform_driver smc911x_driver = {
2189 .probe = smc911x_drv_probe,
2190 .remove = __devexit_p(smc911x_drv_remove),
2191 .suspend = smc911x_drv_suspend,
2192 .resume = smc911x_drv_resume,
2193 .driver = {
2194 .name = CARDNAME,
2195 .owner = THIS_MODULE,
2196 },
2197};
2198
2199static int __init smc911x_init(void)
2200{
2201 return platform_driver_register(&smc911x_driver);
2202}
2203
2204static void __exit smc911x_cleanup(void)
2205{
2206 platform_driver_unregister(&smc911x_driver);
2207}
2208
2209module_init(smc911x_init);
2210module_exit(smc911x_cleanup);
diff --git a/drivers/net/ethernet/smsc/smc911x.h b/drivers/net/ethernet/smsc/smc911x.h
new file mode 100644
index 000000000000..3269292efecc
--- /dev/null
+++ b/drivers/net/ethernet/smsc/smc911x.h
@@ -0,0 +1,924 @@
1/*------------------------------------------------------------------------
2 . smc911x.h - macros for SMSC's LAN911{5,6,7,8} single-chip Ethernet device.
3 .
4 . Copyright (C) 2005 Sensoria Corp.
5 . Derived from the unified SMC91x driver by Nicolas Pitre
6 .
7 . This program is free software; you can redistribute it and/or modify
8 . it under the terms of the GNU General Public License as published by
9 . the Free Software Foundation; either version 2 of the License, or
10 . (at your option) any later version.
11 .
12 . This program is distributed in the hope that it will be useful,
13 . but WITHOUT ANY WARRANTY; without even the implied warranty of
14 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 . GNU General Public License for more details.
16 .
17 . You should have received a copy of the GNU General Public License
18 . along with this program; if not, write to the Free Software
19 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 .
21 . Information contained in this file was obtained from the LAN9118
22 . manual from SMC. To get a copy, if you really want one, you can find
23 . information under www.smsc.com.
24 .
25 . Authors
26 . Dustin McIntire <dustin@sensoria.com>
27 .
28 ---------------------------------------------------------------------------*/
29#ifndef _SMC911X_H_
30#define _SMC911X_H_
31
32#include <linux/smc911x.h>
33/*
34 * Use the DMA feature on PXA chips
35 */
36#ifdef CONFIG_ARCH_PXA
37 #define SMC_USE_PXA_DMA 1
38 #define SMC_USE_16BIT 0
39 #define SMC_USE_32BIT 1
40 #define SMC_IRQ_SENSE IRQF_TRIGGER_FALLING
41#elif defined(CONFIG_SH_MAGIC_PANEL_R2)
42 #define SMC_USE_16BIT 0
43 #define SMC_USE_32BIT 1
44 #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
45#elif defined(CONFIG_ARCH_OMAP3)
46 #define SMC_USE_16BIT 0
47 #define SMC_USE_32BIT 1
48 #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
49 #define SMC_MEM_RESERVED 1
50#elif defined(CONFIG_ARCH_OMAP2)
51 #define SMC_USE_16BIT 0
52 #define SMC_USE_32BIT 1
53 #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
54 #define SMC_MEM_RESERVED 1
55#else
56/*
57 * Default configuration
58 */
59
60#define SMC_DYNAMIC_BUS_CONFIG
61#endif
62
63#ifdef SMC_USE_PXA_DMA
64#define SMC_USE_DMA
65#endif
66
67/* store this information for the driver.. */
68struct smc911x_local {
69 /*
70 * If I have to wait until the DMA is finished and ready to reload a
71 * packet, I will store the skbuff here. Then, the DMA will send it
72 * out and free it.
73 */
74 struct sk_buff *pending_tx_skb;
75
76 /* version/revision of the SMC911x chip */
77 u16 version;
78 u16 revision;
79
80 /* FIFO sizes */
81 int tx_fifo_kb;
82 int tx_fifo_size;
83 int rx_fifo_size;
84 int afc_cfg;
85
86 /* Contains the current active receive/phy mode */
87 int ctl_rfduplx;
88 int ctl_rspeed;
89
90 u32 msg_enable;
91 u32 phy_type;
92 struct mii_if_info mii;
93
94 /* work queue */
95 struct work_struct phy_configure;
96
97 int tx_throttle;
98 spinlock_t lock;
99
100 struct net_device *netdev;
101
102#ifdef SMC_USE_DMA
103 /* DMA needs the physical address of the chip */
104 u_long physaddr;
105 int rxdma;
106 int txdma;
107 int rxdma_active;
108 int txdma_active;
109 struct sk_buff *current_rx_skb;
110 struct sk_buff *current_tx_skb;
111 struct device *dev;
112#endif
113 void __iomem *base;
114#ifdef SMC_DYNAMIC_BUS_CONFIG
115 struct smc911x_platdata cfg;
116#endif
117};
118
119/*
120 * Define the bus width specific IO macros
121 */
122
123#ifdef SMC_DYNAMIC_BUS_CONFIG
124static inline unsigned int SMC_inl(struct smc911x_local *lp, int reg)
125{
126 void __iomem *ioaddr = lp->base + reg;
127
128 if (lp->cfg.flags & SMC911X_USE_32BIT)
129 return readl(ioaddr);
130
131 if (lp->cfg.flags & SMC911X_USE_16BIT)
132 return readw(ioaddr) | (readw(ioaddr + 2) << 16);
133
134 BUG();
135}
136
137static inline void SMC_outl(unsigned int value, struct smc911x_local *lp,
138 int reg)
139{
140 void __iomem *ioaddr = lp->base + reg;
141
142 if (lp->cfg.flags & SMC911X_USE_32BIT) {
143 writel(value, ioaddr);
144 return;
145 }
146
147 if (lp->cfg.flags & SMC911X_USE_16BIT) {
148 writew(value & 0xffff, ioaddr);
149 writew(value >> 16, ioaddr + 2);
150 return;
151 }
152
153 BUG();
154}
155
156static inline void SMC_insl(struct smc911x_local *lp, int reg,
157 void *addr, unsigned int count)
158{
159 void __iomem *ioaddr = lp->base + reg;
160
161 if (lp->cfg.flags & SMC911X_USE_32BIT) {
162 readsl(ioaddr, addr, count);
163 return;
164 }
165
166 if (lp->cfg.flags & SMC911X_USE_16BIT) {
167 readsw(ioaddr, addr, count * 2);
168 return;
169 }
170
171 BUG();
172}
173
174static inline void SMC_outsl(struct smc911x_local *lp, int reg,
175 void *addr, unsigned int count)
176{
177 void __iomem *ioaddr = lp->base + reg;
178
179 if (lp->cfg.flags & SMC911X_USE_32BIT) {
180 writesl(ioaddr, addr, count);
181 return;
182 }
183
184 if (lp->cfg.flags & SMC911X_USE_16BIT) {
185 writesw(ioaddr, addr, count * 2);
186 return;
187 }
188
189 BUG();
190}
191#else
192#if SMC_USE_16BIT
193#define SMC_inl(lp, r) ((readw((lp)->base + (r)) & 0xFFFF) + (readw((lp)->base + (r) + 2) << 16))
194#define SMC_outl(v, lp, r) \
195 do{ \
196 writew(v & 0xFFFF, (lp)->base + (r)); \
197 writew(v >> 16, (lp)->base + (r) + 2); \
198 } while (0)
199#define SMC_insl(lp, r, p, l) readsw((short*)((lp)->base + (r)), p, l*2)
200#define SMC_outsl(lp, r, p, l) writesw((short*)((lp)->base + (r)), p, l*2)
201
202#elif SMC_USE_32BIT
203#define SMC_inl(lp, r) readl((lp)->base + (r))
204#define SMC_outl(v, lp, r) writel(v, (lp)->base + (r))
205#define SMC_insl(lp, r, p, l) readsl((int*)((lp)->base + (r)), p, l)
206#define SMC_outsl(lp, r, p, l) writesl((int*)((lp)->base + (r)), p, l)
207
208#endif /* SMC_USE_16BIT */
209#endif /* SMC_DYNAMIC_BUS_CONFIG */
210
211
212#ifdef SMC_USE_PXA_DMA
213
214#include <mach/dma.h>
215
216/*
217 * Define the request and free functions
218 * These are unfortunately architecture specific as no generic allocation
219 * mechanism exits
220 */
221#define SMC_DMA_REQUEST(dev, handler) \
222 pxa_request_dma(dev->name, DMA_PRIO_LOW, handler, dev)
223
224#define SMC_DMA_FREE(dev, dma) \
225 pxa_free_dma(dma)
226
227#define SMC_DMA_ACK_IRQ(dev, dma) \
228{ \
229 if (DCSR(dma) & DCSR_BUSERR) { \
230 printk("%s: DMA %d bus error!\n", dev->name, dma); \
231 } \
232 DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; \
233}
234
235/*
236 * Use a DMA for RX and TX packets.
237 */
238#include <linux/dma-mapping.h>
239
240static dma_addr_t rx_dmabuf, tx_dmabuf;
241static int rx_dmalen, tx_dmalen;
242
243#ifdef SMC_insl
244#undef SMC_insl
245#define SMC_insl(lp, r, p, l) \
246 smc_pxa_dma_insl(lp, lp->physaddr, r, lp->rxdma, p, l)
247
248static inline void
249smc_pxa_dma_insl(struct smc911x_local *lp, u_long physaddr,
250 int reg, int dma, u_char *buf, int len)
251{
252 /* 64 bit alignment is required for memory to memory DMA */
253 if ((long)buf & 4) {
254 *((u32 *)buf) = SMC_inl(lp, reg);
255 buf += 4;
256 len--;
257 }
258
259 len *= 4;
260 rx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_FROM_DEVICE);
261 rx_dmalen = len;
262 DCSR(dma) = DCSR_NODESC;
263 DTADR(dma) = rx_dmabuf;
264 DSADR(dma) = physaddr + reg;
265 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
266 DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & rx_dmalen));
267 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
268}
269#endif
270
271#ifdef SMC_outsl
272#undef SMC_outsl
273#define SMC_outsl(lp, r, p, l) \
274 smc_pxa_dma_outsl(lp, lp->physaddr, r, lp->txdma, p, l)
275
276static inline void
277smc_pxa_dma_outsl(struct smc911x_local *lp, u_long physaddr,
278 int reg, int dma, u_char *buf, int len)
279{
280 /* 64 bit alignment is required for memory to memory DMA */
281 if ((long)buf & 4) {
282 SMC_outl(*((u32 *)buf), lp, reg);
283 buf += 4;
284 len--;
285 }
286
287 len *= 4;
288 tx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_TO_DEVICE);
289 tx_dmalen = len;
290 DCSR(dma) = DCSR_NODESC;
291 DSADR(dma) = tx_dmabuf;
292 DTADR(dma) = physaddr + reg;
293 DCMD(dma) = (DCMD_INCSRCADDR | DCMD_BURST32 |
294 DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & tx_dmalen));
295 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
296}
297#endif
298#endif /* SMC_USE_PXA_DMA */
299
300
301/* Chip Parameters and Register Definitions */
302
303#define SMC911X_TX_FIFO_LOW_THRESHOLD (1536*2)
304
305#define SMC911X_IO_EXTENT 0x100
306
307#define SMC911X_EEPROM_LEN 7
308
309/* Below are the register offsets and bit definitions
310 * of the Lan911x memory space
311 */
312#define RX_DATA_FIFO (0x00)
313
314#define TX_DATA_FIFO (0x20)
315#define TX_CMD_A_INT_ON_COMP_ (0x80000000)
316#define TX_CMD_A_INT_BUF_END_ALGN_ (0x03000000)
317#define TX_CMD_A_INT_4_BYTE_ALGN_ (0x00000000)
318#define TX_CMD_A_INT_16_BYTE_ALGN_ (0x01000000)
319#define TX_CMD_A_INT_32_BYTE_ALGN_ (0x02000000)
320#define TX_CMD_A_INT_DATA_OFFSET_ (0x001F0000)
321#define TX_CMD_A_INT_FIRST_SEG_ (0x00002000)
322#define TX_CMD_A_INT_LAST_SEG_ (0x00001000)
323#define TX_CMD_A_BUF_SIZE_ (0x000007FF)
324#define TX_CMD_B_PKT_TAG_ (0xFFFF0000)
325#define TX_CMD_B_ADD_CRC_DISABLE_ (0x00002000)
326#define TX_CMD_B_DISABLE_PADDING_ (0x00001000)
327#define TX_CMD_B_PKT_BYTE_LENGTH_ (0x000007FF)
328
329#define RX_STATUS_FIFO (0x40)
330#define RX_STS_PKT_LEN_ (0x3FFF0000)
331#define RX_STS_ES_ (0x00008000)
332#define RX_STS_BCST_ (0x00002000)
333#define RX_STS_LEN_ERR_ (0x00001000)
334#define RX_STS_RUNT_ERR_ (0x00000800)
335#define RX_STS_MCAST_ (0x00000400)
336#define RX_STS_TOO_LONG_ (0x00000080)
337#define RX_STS_COLL_ (0x00000040)
338#define RX_STS_ETH_TYPE_ (0x00000020)
339#define RX_STS_WDOG_TMT_ (0x00000010)
340#define RX_STS_MII_ERR_ (0x00000008)
341#define RX_STS_DRIBBLING_ (0x00000004)
342#define RX_STS_CRC_ERR_ (0x00000002)
343#define RX_STATUS_FIFO_PEEK (0x44)
344#define TX_STATUS_FIFO (0x48)
345#define TX_STS_TAG_ (0xFFFF0000)
346#define TX_STS_ES_ (0x00008000)
347#define TX_STS_LOC_ (0x00000800)
348#define TX_STS_NO_CARR_ (0x00000400)
349#define TX_STS_LATE_COLL_ (0x00000200)
350#define TX_STS_MANY_COLL_ (0x00000100)
351#define TX_STS_COLL_CNT_ (0x00000078)
352#define TX_STS_MANY_DEFER_ (0x00000004)
353#define TX_STS_UNDERRUN_ (0x00000002)
354#define TX_STS_DEFERRED_ (0x00000001)
355#define TX_STATUS_FIFO_PEEK (0x4C)
356#define ID_REV (0x50)
357#define ID_REV_CHIP_ID_ (0xFFFF0000) /* RO */
358#define ID_REV_REV_ID_ (0x0000FFFF) /* RO */
359
360#define INT_CFG (0x54)
361#define INT_CFG_INT_DEAS_ (0xFF000000) /* R/W */
362#define INT_CFG_INT_DEAS_CLR_ (0x00004000)
363#define INT_CFG_INT_DEAS_STS_ (0x00002000)
364#define INT_CFG_IRQ_INT_ (0x00001000) /* RO */
365#define INT_CFG_IRQ_EN_ (0x00000100) /* R/W */
366#define INT_CFG_IRQ_POL_ (0x00000010) /* R/W Not Affected by SW Reset */
367#define INT_CFG_IRQ_TYPE_ (0x00000001) /* R/W Not Affected by SW Reset */
368
369#define INT_STS (0x58)
370#define INT_STS_SW_INT_ (0x80000000) /* R/WC */
371#define INT_STS_TXSTOP_INT_ (0x02000000) /* R/WC */
372#define INT_STS_RXSTOP_INT_ (0x01000000) /* R/WC */
373#define INT_STS_RXDFH_INT_ (0x00800000) /* R/WC */
374#define INT_STS_RXDF_INT_ (0x00400000) /* R/WC */
375#define INT_STS_TX_IOC_ (0x00200000) /* R/WC */
376#define INT_STS_RXD_INT_ (0x00100000) /* R/WC */
377#define INT_STS_GPT_INT_ (0x00080000) /* R/WC */
378#define INT_STS_PHY_INT_ (0x00040000) /* RO */
379#define INT_STS_PME_INT_ (0x00020000) /* R/WC */
380#define INT_STS_TXSO_ (0x00010000) /* R/WC */
381#define INT_STS_RWT_ (0x00008000) /* R/WC */
382#define INT_STS_RXE_ (0x00004000) /* R/WC */
383#define INT_STS_TXE_ (0x00002000) /* R/WC */
384//#define INT_STS_ERX_ (0x00001000) /* R/WC */
385#define INT_STS_TDFU_ (0x00000800) /* R/WC */
386#define INT_STS_TDFO_ (0x00000400) /* R/WC */
387#define INT_STS_TDFA_ (0x00000200) /* R/WC */
388#define INT_STS_TSFF_ (0x00000100) /* R/WC */
389#define INT_STS_TSFL_ (0x00000080) /* R/WC */
390//#define INT_STS_RXDF_ (0x00000040) /* R/WC */
391#define INT_STS_RDFO_ (0x00000040) /* R/WC */
392#define INT_STS_RDFL_ (0x00000020) /* R/WC */
393#define INT_STS_RSFF_ (0x00000010) /* R/WC */
394#define INT_STS_RSFL_ (0x00000008) /* R/WC */
395#define INT_STS_GPIO2_INT_ (0x00000004) /* R/WC */
396#define INT_STS_GPIO1_INT_ (0x00000002) /* R/WC */
397#define INT_STS_GPIO0_INT_ (0x00000001) /* R/WC */
398
399#define INT_EN (0x5C)
400#define INT_EN_SW_INT_EN_ (0x80000000) /* R/W */
401#define INT_EN_TXSTOP_INT_EN_ (0x02000000) /* R/W */
402#define INT_EN_RXSTOP_INT_EN_ (0x01000000) /* R/W */
403#define INT_EN_RXDFH_INT_EN_ (0x00800000) /* R/W */
404//#define INT_EN_RXDF_INT_EN_ (0x00400000) /* R/W */
405#define INT_EN_TIOC_INT_EN_ (0x00200000) /* R/W */
406#define INT_EN_RXD_INT_EN_ (0x00100000) /* R/W */
407#define INT_EN_GPT_INT_EN_ (0x00080000) /* R/W */
408#define INT_EN_PHY_INT_EN_ (0x00040000) /* R/W */
409#define INT_EN_PME_INT_EN_ (0x00020000) /* R/W */
410#define INT_EN_TXSO_EN_ (0x00010000) /* R/W */
411#define INT_EN_RWT_EN_ (0x00008000) /* R/W */
412#define INT_EN_RXE_EN_ (0x00004000) /* R/W */
413#define INT_EN_TXE_EN_ (0x00002000) /* R/W */
414//#define INT_EN_ERX_EN_ (0x00001000) /* R/W */
415#define INT_EN_TDFU_EN_ (0x00000800) /* R/W */
416#define INT_EN_TDFO_EN_ (0x00000400) /* R/W */
417#define INT_EN_TDFA_EN_ (0x00000200) /* R/W */
418#define INT_EN_TSFF_EN_ (0x00000100) /* R/W */
419#define INT_EN_TSFL_EN_ (0x00000080) /* R/W */
420//#define INT_EN_RXDF_EN_ (0x00000040) /* R/W */
421#define INT_EN_RDFO_EN_ (0x00000040) /* R/W */
422#define INT_EN_RDFL_EN_ (0x00000020) /* R/W */
423#define INT_EN_RSFF_EN_ (0x00000010) /* R/W */
424#define INT_EN_RSFL_EN_ (0x00000008) /* R/W */
425#define INT_EN_GPIO2_INT_ (0x00000004) /* R/W */
426#define INT_EN_GPIO1_INT_ (0x00000002) /* R/W */
427#define INT_EN_GPIO0_INT_ (0x00000001) /* R/W */
428
429#define BYTE_TEST (0x64)
430#define FIFO_INT (0x68)
431#define FIFO_INT_TX_AVAIL_LEVEL_ (0xFF000000) /* R/W */
432#define FIFO_INT_TX_STS_LEVEL_ (0x00FF0000) /* R/W */
433#define FIFO_INT_RX_AVAIL_LEVEL_ (0x0000FF00) /* R/W */
434#define FIFO_INT_RX_STS_LEVEL_ (0x000000FF) /* R/W */
435
436#define RX_CFG (0x6C)
437#define RX_CFG_RX_END_ALGN_ (0xC0000000) /* R/W */
438#define RX_CFG_RX_END_ALGN4_ (0x00000000) /* R/W */
439#define RX_CFG_RX_END_ALGN16_ (0x40000000) /* R/W */
440#define RX_CFG_RX_END_ALGN32_ (0x80000000) /* R/W */
441#define RX_CFG_RX_DMA_CNT_ (0x0FFF0000) /* R/W */
442#define RX_CFG_RX_DUMP_ (0x00008000) /* R/W */
443#define RX_CFG_RXDOFF_ (0x00001F00) /* R/W */
444//#define RX_CFG_RXBAD_ (0x00000001) /* R/W */
445
446#define TX_CFG (0x70)
447//#define TX_CFG_TX_DMA_LVL_ (0xE0000000) /* R/W */
448//#define TX_CFG_TX_DMA_CNT_ (0x0FFF0000) /* R/W Self Clearing */
449#define TX_CFG_TXS_DUMP_ (0x00008000) /* Self Clearing */
450#define TX_CFG_TXD_DUMP_ (0x00004000) /* Self Clearing */
451#define TX_CFG_TXSAO_ (0x00000004) /* R/W */
452#define TX_CFG_TX_ON_ (0x00000002) /* R/W */
453#define TX_CFG_STOP_TX_ (0x00000001) /* Self Clearing */
454
455#define HW_CFG (0x74)
456#define HW_CFG_TTM_ (0x00200000) /* R/W */
457#define HW_CFG_SF_ (0x00100000) /* R/W */
458#define HW_CFG_TX_FIF_SZ_ (0x000F0000) /* R/W */
459#define HW_CFG_TR_ (0x00003000) /* R/W */
460#define HW_CFG_PHY_CLK_SEL_ (0x00000060) /* R/W */
461#define HW_CFG_PHY_CLK_SEL_INT_PHY_ (0x00000000) /* R/W */
462#define HW_CFG_PHY_CLK_SEL_EXT_PHY_ (0x00000020) /* R/W */
463#define HW_CFG_PHY_CLK_SEL_CLK_DIS_ (0x00000040) /* R/W */
464#define HW_CFG_SMI_SEL_ (0x00000010) /* R/W */
465#define HW_CFG_EXT_PHY_DET_ (0x00000008) /* RO */
466#define HW_CFG_EXT_PHY_EN_ (0x00000004) /* R/W */
467#define HW_CFG_32_16_BIT_MODE_ (0x00000004) /* RO */
468#define HW_CFG_SRST_TO_ (0x00000002) /* RO */
469#define HW_CFG_SRST_ (0x00000001) /* Self Clearing */
470
471#define RX_DP_CTRL (0x78)
472#define RX_DP_CTRL_RX_FFWD_ (0x80000000) /* R/W */
473#define RX_DP_CTRL_FFWD_BUSY_ (0x80000000) /* RO */
474
475#define RX_FIFO_INF (0x7C)
476#define RX_FIFO_INF_RXSUSED_ (0x00FF0000) /* RO */
477#define RX_FIFO_INF_RXDUSED_ (0x0000FFFF) /* RO */
478
479#define TX_FIFO_INF (0x80)
480#define TX_FIFO_INF_TSUSED_ (0x00FF0000) /* RO */
481#define TX_FIFO_INF_TDFREE_ (0x0000FFFF) /* RO */
482
483#define PMT_CTRL (0x84)
484#define PMT_CTRL_PM_MODE_ (0x00003000) /* Self Clearing */
485#define PMT_CTRL_PHY_RST_ (0x00000400) /* Self Clearing */
486#define PMT_CTRL_WOL_EN_ (0x00000200) /* R/W */
487#define PMT_CTRL_ED_EN_ (0x00000100) /* R/W */
488#define PMT_CTRL_PME_TYPE_ (0x00000040) /* R/W Not Affected by SW Reset */
489#define PMT_CTRL_WUPS_ (0x00000030) /* R/WC */
490#define PMT_CTRL_WUPS_NOWAKE_ (0x00000000) /* R/WC */
491#define PMT_CTRL_WUPS_ED_ (0x00000010) /* R/WC */
492#define PMT_CTRL_WUPS_WOL_ (0x00000020) /* R/WC */
493#define PMT_CTRL_WUPS_MULTI_ (0x00000030) /* R/WC */
494#define PMT_CTRL_PME_IND_ (0x00000008) /* R/W */
495#define PMT_CTRL_PME_POL_ (0x00000004) /* R/W */
496#define PMT_CTRL_PME_EN_ (0x00000002) /* R/W Not Affected by SW Reset */
497#define PMT_CTRL_READY_ (0x00000001) /* RO */
498
499#define GPIO_CFG (0x88)
500#define GPIO_CFG_LED3_EN_ (0x40000000) /* R/W */
501#define GPIO_CFG_LED2_EN_ (0x20000000) /* R/W */
502#define GPIO_CFG_LED1_EN_ (0x10000000) /* R/W */
503#define GPIO_CFG_GPIO2_INT_POL_ (0x04000000) /* R/W */
504#define GPIO_CFG_GPIO1_INT_POL_ (0x02000000) /* R/W */
505#define GPIO_CFG_GPIO0_INT_POL_ (0x01000000) /* R/W */
506#define GPIO_CFG_EEPR_EN_ (0x00700000) /* R/W */
507#define GPIO_CFG_GPIOBUF2_ (0x00040000) /* R/W */
508#define GPIO_CFG_GPIOBUF1_ (0x00020000) /* R/W */
509#define GPIO_CFG_GPIOBUF0_ (0x00010000) /* R/W */
510#define GPIO_CFG_GPIODIR2_ (0x00000400) /* R/W */
511#define GPIO_CFG_GPIODIR1_ (0x00000200) /* R/W */
512#define GPIO_CFG_GPIODIR0_ (0x00000100) /* R/W */
513#define GPIO_CFG_GPIOD4_ (0x00000010) /* R/W */
514#define GPIO_CFG_GPIOD3_ (0x00000008) /* R/W */
515#define GPIO_CFG_GPIOD2_ (0x00000004) /* R/W */
516#define GPIO_CFG_GPIOD1_ (0x00000002) /* R/W */
517#define GPIO_CFG_GPIOD0_ (0x00000001) /* R/W */
518
519#define GPT_CFG (0x8C)
520#define GPT_CFG_TIMER_EN_ (0x20000000) /* R/W */
521#define GPT_CFG_GPT_LOAD_ (0x0000FFFF) /* R/W */
522
523#define GPT_CNT (0x90)
524#define GPT_CNT_GPT_CNT_ (0x0000FFFF) /* RO */
525
526#define ENDIAN (0x98)
527#define FREE_RUN (0x9C)
528#define RX_DROP (0xA0)
529#define MAC_CSR_CMD (0xA4)
530#define MAC_CSR_CMD_CSR_BUSY_ (0x80000000) /* Self Clearing */
531#define MAC_CSR_CMD_R_NOT_W_ (0x40000000) /* R/W */
532#define MAC_CSR_CMD_CSR_ADDR_ (0x000000FF) /* R/W */
533
534#define MAC_CSR_DATA (0xA8)
535#define AFC_CFG (0xAC)
536#define AFC_CFG_AFC_HI_ (0x00FF0000) /* R/W */
537#define AFC_CFG_AFC_LO_ (0x0000FF00) /* R/W */
538#define AFC_CFG_BACK_DUR_ (0x000000F0) /* R/W */
539#define AFC_CFG_FCMULT_ (0x00000008) /* R/W */
540#define AFC_CFG_FCBRD_ (0x00000004) /* R/W */
541#define AFC_CFG_FCADD_ (0x00000002) /* R/W */
542#define AFC_CFG_FCANY_ (0x00000001) /* R/W */
543
544#define E2P_CMD (0xB0)
545#define E2P_CMD_EPC_BUSY_ (0x80000000) /* Self Clearing */
546#define E2P_CMD_EPC_CMD_ (0x70000000) /* R/W */
547#define E2P_CMD_EPC_CMD_READ_ (0x00000000) /* R/W */
548#define E2P_CMD_EPC_CMD_EWDS_ (0x10000000) /* R/W */
549#define E2P_CMD_EPC_CMD_EWEN_ (0x20000000) /* R/W */
550#define E2P_CMD_EPC_CMD_WRITE_ (0x30000000) /* R/W */
551#define E2P_CMD_EPC_CMD_WRAL_ (0x40000000) /* R/W */
552#define E2P_CMD_EPC_CMD_ERASE_ (0x50000000) /* R/W */
553#define E2P_CMD_EPC_CMD_ERAL_ (0x60000000) /* R/W */
554#define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000) /* R/W */
555#define E2P_CMD_EPC_TIMEOUT_ (0x00000200) /* RO */
556#define E2P_CMD_MAC_ADDR_LOADED_ (0x00000100) /* RO */
557#define E2P_CMD_EPC_ADDR_ (0x000000FF) /* R/W */
558
559#define E2P_DATA (0xB4)
560#define E2P_DATA_EEPROM_DATA_ (0x000000FF) /* R/W */
561/* end of LAN register offsets and bit definitions */
562
563/*
564 ****************************************************************************
565 ****************************************************************************
566 * MAC Control and Status Register (Indirect Address)
567 * Offset (through the MAC_CSR CMD and DATA port)
568 ****************************************************************************
569 ****************************************************************************
570 *
571 */
572#define MAC_CR (0x01) /* R/W */
573
574/* MAC_CR - MAC Control Register */
575#define MAC_CR_RXALL_ (0x80000000)
576// TODO: delete this bit? It is not described in the data sheet.
577#define MAC_CR_HBDIS_ (0x10000000)
578#define MAC_CR_RCVOWN_ (0x00800000)
579#define MAC_CR_LOOPBK_ (0x00200000)
580#define MAC_CR_FDPX_ (0x00100000)
581#define MAC_CR_MCPAS_ (0x00080000)
582#define MAC_CR_PRMS_ (0x00040000)
583#define MAC_CR_INVFILT_ (0x00020000)
584#define MAC_CR_PASSBAD_ (0x00010000)
585#define MAC_CR_HFILT_ (0x00008000)
586#define MAC_CR_HPFILT_ (0x00002000)
587#define MAC_CR_LCOLL_ (0x00001000)
588#define MAC_CR_BCAST_ (0x00000800)
589#define MAC_CR_DISRTY_ (0x00000400)
590#define MAC_CR_PADSTR_ (0x00000100)
591#define MAC_CR_BOLMT_MASK_ (0x000000C0)
592#define MAC_CR_DFCHK_ (0x00000020)
593#define MAC_CR_TXEN_ (0x00000008)
594#define MAC_CR_RXEN_ (0x00000004)
595
596#define ADDRH (0x02) /* R/W mask 0x0000FFFFUL */
597#define ADDRL (0x03) /* R/W mask 0xFFFFFFFFUL */
598#define HASHH (0x04) /* R/W */
599#define HASHL (0x05) /* R/W */
600
601#define MII_ACC (0x06) /* R/W */
602#define MII_ACC_PHY_ADDR_ (0x0000F800)
603#define MII_ACC_MIIRINDA_ (0x000007C0)
604#define MII_ACC_MII_WRITE_ (0x00000002)
605#define MII_ACC_MII_BUSY_ (0x00000001)
606
607#define MII_DATA (0x07) /* R/W mask 0x0000FFFFUL */
608
609#define FLOW (0x08) /* R/W */
610#define FLOW_FCPT_ (0xFFFF0000)
611#define FLOW_FCPASS_ (0x00000004)
612#define FLOW_FCEN_ (0x00000002)
613#define FLOW_FCBSY_ (0x00000001)
614
615#define VLAN1 (0x09) /* R/W mask 0x0000FFFFUL */
616#define VLAN1_VTI1_ (0x0000ffff)
617
618#define VLAN2 (0x0A) /* R/W mask 0x0000FFFFUL */
619#define VLAN2_VTI2_ (0x0000ffff)
620
621#define WUFF (0x0B) /* WO */
622
623#define WUCSR (0x0C) /* R/W */
624#define WUCSR_GUE_ (0x00000200)
625#define WUCSR_WUFR_ (0x00000040)
626#define WUCSR_MPR_ (0x00000020)
627#define WUCSR_WAKE_EN_ (0x00000004)
628#define WUCSR_MPEN_ (0x00000002)
629
630/*
631 ****************************************************************************
632 * Chip Specific MII Defines
633 ****************************************************************************
634 *
635 * Phy register offsets and bit definitions
636 *
637 */
638
639#define PHY_MODE_CTRL_STS ((u32)17) /* Mode Control/Status Register */
640//#define MODE_CTRL_STS_FASTRIP_ ((u16)0x4000)
641#define MODE_CTRL_STS_EDPWRDOWN_ ((u16)0x2000)
642//#define MODE_CTRL_STS_LOWSQEN_ ((u16)0x0800)
643//#define MODE_CTRL_STS_MDPREBP_ ((u16)0x0400)
644//#define MODE_CTRL_STS_FARLOOPBACK_ ((u16)0x0200)
645//#define MODE_CTRL_STS_FASTEST_ ((u16)0x0100)
646//#define MODE_CTRL_STS_REFCLKEN_ ((u16)0x0010)
647//#define MODE_CTRL_STS_PHYADBP_ ((u16)0x0008)
648//#define MODE_CTRL_STS_FORCE_G_LINK_ ((u16)0x0004)
649#define MODE_CTRL_STS_ENERGYON_ ((u16)0x0002)
650
651#define PHY_INT_SRC ((u32)29)
652#define PHY_INT_SRC_ENERGY_ON_ ((u16)0x0080)
653#define PHY_INT_SRC_ANEG_COMP_ ((u16)0x0040)
654#define PHY_INT_SRC_REMOTE_FAULT_ ((u16)0x0020)
655#define PHY_INT_SRC_LINK_DOWN_ ((u16)0x0010)
656#define PHY_INT_SRC_ANEG_LP_ACK_ ((u16)0x0008)
657#define PHY_INT_SRC_PAR_DET_FAULT_ ((u16)0x0004)
658#define PHY_INT_SRC_ANEG_PGRX_ ((u16)0x0002)
659
660#define PHY_INT_MASK ((u32)30)
661#define PHY_INT_MASK_ENERGY_ON_ ((u16)0x0080)
662#define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)
663#define PHY_INT_MASK_REMOTE_FAULT_ ((u16)0x0020)
664#define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)
665#define PHY_INT_MASK_ANEG_LP_ACK_ ((u16)0x0008)
666#define PHY_INT_MASK_PAR_DET_FAULT_ ((u16)0x0004)
667#define PHY_INT_MASK_ANEG_PGRX_ ((u16)0x0002)
668
669#define PHY_SPECIAL ((u32)31)
670#define PHY_SPECIAL_ANEG_DONE_ ((u16)0x1000)
671#define PHY_SPECIAL_RES_ ((u16)0x0040)
672#define PHY_SPECIAL_RES_MASK_ ((u16)0x0FE1)
673#define PHY_SPECIAL_SPD_ ((u16)0x001C)
674#define PHY_SPECIAL_SPD_10HALF_ ((u16)0x0004)
675#define PHY_SPECIAL_SPD_10FULL_ ((u16)0x0014)
676#define PHY_SPECIAL_SPD_100HALF_ ((u16)0x0008)
677#define PHY_SPECIAL_SPD_100FULL_ ((u16)0x0018)
678
679#define LAN911X_INTERNAL_PHY_ID (0x0007C000)
680
681/* Chip ID values */
682#define CHIP_9115 0x0115
683#define CHIP_9116 0x0116
684#define CHIP_9117 0x0117
685#define CHIP_9118 0x0118
686#define CHIP_9211 0x9211
687#define CHIP_9215 0x115A
688#define CHIP_9217 0x117A
689#define CHIP_9218 0x118A
690
691struct chip_id {
692 u16 id;
693 char *name;
694};
695
696static const struct chip_id chip_ids[] = {
697 { CHIP_9115, "LAN9115" },
698 { CHIP_9116, "LAN9116" },
699 { CHIP_9117, "LAN9117" },
700 { CHIP_9118, "LAN9118" },
701 { CHIP_9211, "LAN9211" },
702 { CHIP_9215, "LAN9215" },
703 { CHIP_9217, "LAN9217" },
704 { CHIP_9218, "LAN9218" },
705 { 0, NULL },
706};
707
708#define IS_REV_A(x) ((x & 0xFFFF)==0)
709
710/*
711 * Macros to abstract register access according to the data bus
712 * capabilities. Please use those and not the in/out primitives.
713 */
714/* FIFO read/write macros */
715#define SMC_PUSH_DATA(lp, p, l) SMC_outsl( lp, TX_DATA_FIFO, p, (l) >> 2 )
716#define SMC_PULL_DATA(lp, p, l) SMC_insl ( lp, RX_DATA_FIFO, p, (l) >> 2 )
717#define SMC_SET_TX_FIFO(lp, x) SMC_outl( x, lp, TX_DATA_FIFO )
718#define SMC_GET_RX_FIFO(lp) SMC_inl( lp, RX_DATA_FIFO )
719
720
721/* I/O mapped register read/write macros */
722#define SMC_GET_TX_STS_FIFO(lp) SMC_inl( lp, TX_STATUS_FIFO )
723#define SMC_GET_RX_STS_FIFO(lp) SMC_inl( lp, RX_STATUS_FIFO )
724#define SMC_GET_RX_STS_FIFO_PEEK(lp) SMC_inl( lp, RX_STATUS_FIFO_PEEK )
725#define SMC_GET_PN(lp) (SMC_inl( lp, ID_REV ) >> 16)
726#define SMC_GET_REV(lp) (SMC_inl( lp, ID_REV ) & 0xFFFF)
727#define SMC_GET_IRQ_CFG(lp) SMC_inl( lp, INT_CFG )
728#define SMC_SET_IRQ_CFG(lp, x) SMC_outl( x, lp, INT_CFG )
729#define SMC_GET_INT(lp) SMC_inl( lp, INT_STS )
730#define SMC_ACK_INT(lp, x) SMC_outl( x, lp, INT_STS )
731#define SMC_GET_INT_EN(lp) SMC_inl( lp, INT_EN )
732#define SMC_SET_INT_EN(lp, x) SMC_outl( x, lp, INT_EN )
733#define SMC_GET_BYTE_TEST(lp) SMC_inl( lp, BYTE_TEST )
734#define SMC_SET_BYTE_TEST(lp, x) SMC_outl( x, lp, BYTE_TEST )
735#define SMC_GET_FIFO_INT(lp) SMC_inl( lp, FIFO_INT )
736#define SMC_SET_FIFO_INT(lp, x) SMC_outl( x, lp, FIFO_INT )
737#define SMC_SET_FIFO_TDA(lp, x) \
738 do { \
739 unsigned long __flags; \
740 int __mask; \
741 local_irq_save(__flags); \
742 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<24); \
743 SMC_SET_FIFO_INT( (lp), __mask | (x)<<24 ); \
744 local_irq_restore(__flags); \
745 } while (0)
746#define SMC_SET_FIFO_TSL(lp, x) \
747 do { \
748 unsigned long __flags; \
749 int __mask; \
750 local_irq_save(__flags); \
751 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<16); \
752 SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<16)); \
753 local_irq_restore(__flags); \
754 } while (0)
755#define SMC_SET_FIFO_RSA(lp, x) \
756 do { \
757 unsigned long __flags; \
758 int __mask; \
759 local_irq_save(__flags); \
760 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<8); \
761 SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<8)); \
762 local_irq_restore(__flags); \
763 } while (0)
764#define SMC_SET_FIFO_RSL(lp, x) \
765 do { \
766 unsigned long __flags; \
767 int __mask; \
768 local_irq_save(__flags); \
769 __mask = SMC_GET_FIFO_INT((lp)) & ~0xFF; \
770 SMC_SET_FIFO_INT( (lp),__mask | ((x) & 0xFF)); \
771 local_irq_restore(__flags); \
772 } while (0)
773#define SMC_GET_RX_CFG(lp) SMC_inl( lp, RX_CFG )
774#define SMC_SET_RX_CFG(lp, x) SMC_outl( x, lp, RX_CFG )
775#define SMC_GET_TX_CFG(lp) SMC_inl( lp, TX_CFG )
776#define SMC_SET_TX_CFG(lp, x) SMC_outl( x, lp, TX_CFG )
777#define SMC_GET_HW_CFG(lp) SMC_inl( lp, HW_CFG )
778#define SMC_SET_HW_CFG(lp, x) SMC_outl( x, lp, HW_CFG )
779#define SMC_GET_RX_DP_CTRL(lp) SMC_inl( lp, RX_DP_CTRL )
780#define SMC_SET_RX_DP_CTRL(lp, x) SMC_outl( x, lp, RX_DP_CTRL )
781#define SMC_GET_PMT_CTRL(lp) SMC_inl( lp, PMT_CTRL )
782#define SMC_SET_PMT_CTRL(lp, x) SMC_outl( x, lp, PMT_CTRL )
783#define SMC_GET_GPIO_CFG(lp) SMC_inl( lp, GPIO_CFG )
784#define SMC_SET_GPIO_CFG(lp, x) SMC_outl( x, lp, GPIO_CFG )
785#define SMC_GET_RX_FIFO_INF(lp) SMC_inl( lp, RX_FIFO_INF )
786#define SMC_SET_RX_FIFO_INF(lp, x) SMC_outl( x, lp, RX_FIFO_INF )
787#define SMC_GET_TX_FIFO_INF(lp) SMC_inl( lp, TX_FIFO_INF )
788#define SMC_SET_TX_FIFO_INF(lp, x) SMC_outl( x, lp, TX_FIFO_INF )
789#define SMC_GET_GPT_CFG(lp) SMC_inl( lp, GPT_CFG )
790#define SMC_SET_GPT_CFG(lp, x) SMC_outl( x, lp, GPT_CFG )
791#define SMC_GET_RX_DROP(lp) SMC_inl( lp, RX_DROP )
792#define SMC_SET_RX_DROP(lp, x) SMC_outl( x, lp, RX_DROP )
793#define SMC_GET_MAC_CMD(lp) SMC_inl( lp, MAC_CSR_CMD )
794#define SMC_SET_MAC_CMD(lp, x) SMC_outl( x, lp, MAC_CSR_CMD )
795#define SMC_GET_MAC_DATA(lp) SMC_inl( lp, MAC_CSR_DATA )
796#define SMC_SET_MAC_DATA(lp, x) SMC_outl( x, lp, MAC_CSR_DATA )
797#define SMC_GET_AFC_CFG(lp) SMC_inl( lp, AFC_CFG )
798#define SMC_SET_AFC_CFG(lp, x) SMC_outl( x, lp, AFC_CFG )
799#define SMC_GET_E2P_CMD(lp) SMC_inl( lp, E2P_CMD )
800#define SMC_SET_E2P_CMD(lp, x) SMC_outl( x, lp, E2P_CMD )
801#define SMC_GET_E2P_DATA(lp) SMC_inl( lp, E2P_DATA )
802#define SMC_SET_E2P_DATA(lp, x) SMC_outl( x, lp, E2P_DATA )
803
804/* MAC register read/write macros */
805#define SMC_GET_MAC_CSR(lp,a,v) \
806 do { \
807 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
808 SMC_SET_MAC_CMD((lp),MAC_CSR_CMD_CSR_BUSY_ | \
809 MAC_CSR_CMD_R_NOT_W_ | (a) ); \
810 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
811 v = SMC_GET_MAC_DATA((lp)); \
812 } while (0)
813#define SMC_SET_MAC_CSR(lp,a,v) \
814 do { \
815 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
816 SMC_SET_MAC_DATA((lp), v); \
817 SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_CSR_BUSY_ | (a) ); \
818 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
819 } while (0)
820#define SMC_GET_MAC_CR(lp, x) SMC_GET_MAC_CSR( (lp), MAC_CR, x )
821#define SMC_SET_MAC_CR(lp, x) SMC_SET_MAC_CSR( (lp), MAC_CR, x )
822#define SMC_GET_ADDRH(lp, x) SMC_GET_MAC_CSR( (lp), ADDRH, x )
823#define SMC_SET_ADDRH(lp, x) SMC_SET_MAC_CSR( (lp), ADDRH, x )
824#define SMC_GET_ADDRL(lp, x) SMC_GET_MAC_CSR( (lp), ADDRL, x )
825#define SMC_SET_ADDRL(lp, x) SMC_SET_MAC_CSR( (lp), ADDRL, x )
826#define SMC_GET_HASHH(lp, x) SMC_GET_MAC_CSR( (lp), HASHH, x )
827#define SMC_SET_HASHH(lp, x) SMC_SET_MAC_CSR( (lp), HASHH, x )
828#define SMC_GET_HASHL(lp, x) SMC_GET_MAC_CSR( (lp), HASHL, x )
829#define SMC_SET_HASHL(lp, x) SMC_SET_MAC_CSR( (lp), HASHL, x )
830#define SMC_GET_MII_ACC(lp, x) SMC_GET_MAC_CSR( (lp), MII_ACC, x )
831#define SMC_SET_MII_ACC(lp, x) SMC_SET_MAC_CSR( (lp), MII_ACC, x )
832#define SMC_GET_MII_DATA(lp, x) SMC_GET_MAC_CSR( (lp), MII_DATA, x )
833#define SMC_SET_MII_DATA(lp, x) SMC_SET_MAC_CSR( (lp), MII_DATA, x )
834#define SMC_GET_FLOW(lp, x) SMC_GET_MAC_CSR( (lp), FLOW, x )
835#define SMC_SET_FLOW(lp, x) SMC_SET_MAC_CSR( (lp), FLOW, x )
836#define SMC_GET_VLAN1(lp, x) SMC_GET_MAC_CSR( (lp), VLAN1, x )
837#define SMC_SET_VLAN1(lp, x) SMC_SET_MAC_CSR( (lp), VLAN1, x )
838#define SMC_GET_VLAN2(lp, x) SMC_GET_MAC_CSR( (lp), VLAN2, x )
839#define SMC_SET_VLAN2(lp, x) SMC_SET_MAC_CSR( (lp), VLAN2, x )
840#define SMC_SET_WUFF(lp, x) SMC_SET_MAC_CSR( (lp), WUFF, x )
841#define SMC_GET_WUCSR(lp, x) SMC_GET_MAC_CSR( (lp), WUCSR, x )
842#define SMC_SET_WUCSR(lp, x) SMC_SET_MAC_CSR( (lp), WUCSR, x )
843
844/* PHY register read/write macros */
845#define SMC_GET_MII(lp,a,phy,v) \
846 do { \
847 u32 __v; \
848 do { \
849 SMC_GET_MII_ACC((lp), __v); \
850 } while ( __v & MII_ACC_MII_BUSY_ ); \
851 SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
852 MII_ACC_MII_BUSY_); \
853 do { \
854 SMC_GET_MII_ACC( (lp), __v); \
855 } while ( __v & MII_ACC_MII_BUSY_ ); \
856 SMC_GET_MII_DATA((lp), v); \
857 } while (0)
858#define SMC_SET_MII(lp,a,phy,v) \
859 do { \
860 u32 __v; \
861 do { \
862 SMC_GET_MII_ACC((lp), __v); \
863 } while ( __v & MII_ACC_MII_BUSY_ ); \
864 SMC_SET_MII_DATA((lp), v); \
865 SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
866 MII_ACC_MII_BUSY_ | \
867 MII_ACC_MII_WRITE_ ); \
868 do { \
869 SMC_GET_MII_ACC((lp), __v); \
870 } while ( __v & MII_ACC_MII_BUSY_ ); \
871 } while (0)
872#define SMC_GET_PHY_BMCR(lp,phy,x) SMC_GET_MII( (lp), MII_BMCR, phy, x )
873#define SMC_SET_PHY_BMCR(lp,phy,x) SMC_SET_MII( (lp), MII_BMCR, phy, x )
874#define SMC_GET_PHY_BMSR(lp,phy,x) SMC_GET_MII( (lp), MII_BMSR, phy, x )
875#define SMC_GET_PHY_ID1(lp,phy,x) SMC_GET_MII( (lp), MII_PHYSID1, phy, x )
876#define SMC_GET_PHY_ID2(lp,phy,x) SMC_GET_MII( (lp), MII_PHYSID2, phy, x )
877#define SMC_GET_PHY_MII_ADV(lp,phy,x) SMC_GET_MII( (lp), MII_ADVERTISE, phy, x )
878#define SMC_SET_PHY_MII_ADV(lp,phy,x) SMC_SET_MII( (lp), MII_ADVERTISE, phy, x )
879#define SMC_GET_PHY_MII_LPA(lp,phy,x) SMC_GET_MII( (lp), MII_LPA, phy, x )
880#define SMC_SET_PHY_MII_LPA(lp,phy,x) SMC_SET_MII( (lp), MII_LPA, phy, x )
881#define SMC_GET_PHY_CTRL_STS(lp,phy,x) SMC_GET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
882#define SMC_SET_PHY_CTRL_STS(lp,phy,x) SMC_SET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
883#define SMC_GET_PHY_INT_SRC(lp,phy,x) SMC_GET_MII( (lp), PHY_INT_SRC, phy, x )
884#define SMC_SET_PHY_INT_SRC(lp,phy,x) SMC_SET_MII( (lp), PHY_INT_SRC, phy, x )
885#define SMC_GET_PHY_INT_MASK(lp,phy,x) SMC_GET_MII( (lp), PHY_INT_MASK, phy, x )
886#define SMC_SET_PHY_INT_MASK(lp,phy,x) SMC_SET_MII( (lp), PHY_INT_MASK, phy, x )
887#define SMC_GET_PHY_SPECIAL(lp,phy,x) SMC_GET_MII( (lp), PHY_SPECIAL, phy, x )
888
889
890
891/* Misc read/write macros */
892
893#ifndef SMC_GET_MAC_ADDR
894#define SMC_GET_MAC_ADDR(lp, addr) \
895 do { \
896 unsigned int __v; \
897 \
898 SMC_GET_MAC_CSR((lp), ADDRL, __v); \
899 addr[0] = __v; addr[1] = __v >> 8; \
900 addr[2] = __v >> 16; addr[3] = __v >> 24; \
901 SMC_GET_MAC_CSR((lp), ADDRH, __v); \
902 addr[4] = __v; addr[5] = __v >> 8; \
903 } while (0)
904#endif
905
906#define SMC_SET_MAC_ADDR(lp, addr) \
907 do { \
908 SMC_SET_MAC_CSR((lp), ADDRL, \
909 addr[0] | \
910 (addr[1] << 8) | \
911 (addr[2] << 16) | \
912 (addr[3] << 24)); \
913 SMC_SET_MAC_CSR((lp), ADDRH, addr[4]|(addr[5] << 8));\
914 } while (0)
915
916
917#define SMC_WRITE_EEPROM_CMD(lp, cmd, addr) \
918 do { \
919 while (SMC_GET_E2P_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
920 SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_R_NOT_W_ | a ); \
921 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
922 } while (0)
923
924#endif /* _SMC911X_H_ */
diff --git a/drivers/net/ethernet/smsc/smc9194.c b/drivers/net/ethernet/smsc/smc9194.c
new file mode 100644
index 000000000000..5b65ac4b3cef
--- /dev/null
+++ b/drivers/net/ethernet/smsc/smc9194.c
@@ -0,0 +1,1589 @@
1/*------------------------------------------------------------------------
2 . smc9194.c
3 . This is a driver for SMC's 9000 series of Ethernet cards.
4 .
5 . Copyright (C) 1996 by Erik Stahlman
6 . This software may be used and distributed according to the terms
7 . of the GNU General Public License, incorporated herein by reference.
8 .
9 . "Features" of the SMC chip:
10 . 4608 byte packet memory. ( for the 91C92. Others have more )
11 . EEPROM for configuration
12 . AUI/TP selection ( mine has 10Base2/10BaseT select )
13 .
14 . Arguments:
15 . io = for the base address
16 . irq = for the IRQ
17 . ifport = 0 for autodetect, 1 for TP, 2 for AUI ( or 10base2 )
18 .
19 . author:
20 . Erik Stahlman ( erik@vt.edu )
21 . contributors:
22 . Arnaldo Carvalho de Melo <acme@conectiva.com.br>
23 .
24 . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
25 .
26 . Sources:
27 . o SMC databook
28 . o skeleton.c by Donald Becker ( becker@scyld.com )
29 . o ( a LOT of advice from Becker as well )
30 .
31 . History:
32 . 12/07/95 Erik Stahlman written, got receive/xmit handled
33 . 01/03/96 Erik Stahlman worked out some bugs, actually usable!!! :-)
34 . 01/06/96 Erik Stahlman cleaned up some, better testing, etc
35 . 01/29/96 Erik Stahlman fixed autoirq, added multicast
36 . 02/01/96 Erik Stahlman 1. disabled all interrupts in smc_reset
37 . 2. got rid of post-decrementing bug -- UGH.
38 . 02/13/96 Erik Stahlman Tried to fix autoirq failure. Added more
39 . descriptive error messages.
40 . 02/15/96 Erik Stahlman Fixed typo that caused detection failure
41 . 02/23/96 Erik Stahlman Modified it to fit into kernel tree
42 . Added support to change hardware address
43 . Cleared stats on opens
44 . 02/26/96 Erik Stahlman Trial support for Kernel 1.2.13
45 . Kludge for automatic IRQ detection
46 . 03/04/96 Erik Stahlman Fixed kernel 1.3.70 +
47 . Fixed bug reported by Gardner Buchanan in
48 . smc_enable, with outw instead of outb
49 . 03/06/96 Erik Stahlman Added hardware multicast from Peter Cammaert
50 . 04/14/00 Heiko Pruessing (SMA Regelsysteme) Fixed bug in chip memory
51 . allocation
52 . 08/20/00 Arnaldo Melo fix kfree(skb) in smc_hardware_send_packet
53 . 12/15/00 Christian Jullien fix "Warning: kfree_skb on hard IRQ"
54 . 11/08/01 Matt Domsch Use common crc32 function
55 ----------------------------------------------------------------------------*/
56
57static const char version[] =
58 "smc9194.c:v0.14 12/15/00 by Erik Stahlman (erik@vt.edu)\n";
59
60#include <linux/module.h>
61#include <linux/kernel.h>
62#include <linux/types.h>
63#include <linux/fcntl.h>
64#include <linux/interrupt.h>
65#include <linux/ioport.h>
66#include <linux/in.h>
67#include <linux/string.h>
68#include <linux/init.h>
69#include <linux/crc32.h>
70#include <linux/errno.h>
71#include <linux/netdevice.h>
72#include <linux/etherdevice.h>
73#include <linux/skbuff.h>
74#include <linux/bitops.h>
75
76#include <asm/io.h>
77
78#include "smc9194.h"
79
80#define DRV_NAME "smc9194"
81
82/*------------------------------------------------------------------------
83 .
84 . Configuration options, for the experienced user to change.
85 .
86 -------------------------------------------------------------------------*/
87
88/*
89 . Do you want to use 32 bit xfers? This should work on all chips, as
90 . the chipset is designed to accommodate them.
91*/
92#ifdef __sh__
93#undef USE_32_BIT
94#else
95#define USE_32_BIT 1
96#endif
97
98#if defined(__H8300H__) || defined(__H8300S__)
99#define NO_AUTOPROBE
100#undef insl
101#undef outsl
102#define insl(a,b,l) io_insl_noswap(a,b,l)
103#define outsl(a,b,l) io_outsl_noswap(a,b,l)
104#endif
105
106/*
107 .the SMC9194 can be at any of the following port addresses. To change,
108 .for a slightly different card, you can add it to the array. Keep in
109 .mind that the array must end in zero.
110*/
111
112struct devlist {
113 unsigned int port;
114 unsigned int irq;
115};
116
117#if defined(CONFIG_H8S_EDOSK2674)
118static struct devlist smc_devlist[] __initdata = {
119 {.port = 0xf80000, .irq = 16},
120 {.port = 0, .irq = 0 },
121};
122#else
123static struct devlist smc_devlist[] __initdata = {
124 {.port = 0x200, .irq = 0},
125 {.port = 0x220, .irq = 0},
126 {.port = 0x240, .irq = 0},
127 {.port = 0x260, .irq = 0},
128 {.port = 0x280, .irq = 0},
129 {.port = 0x2A0, .irq = 0},
130 {.port = 0x2C0, .irq = 0},
131 {.port = 0x2E0, .irq = 0},
132 {.port = 0x300, .irq = 0},
133 {.port = 0x320, .irq = 0},
134 {.port = 0x340, .irq = 0},
135 {.port = 0x360, .irq = 0},
136 {.port = 0x380, .irq = 0},
137 {.port = 0x3A0, .irq = 0},
138 {.port = 0x3C0, .irq = 0},
139 {.port = 0x3E0, .irq = 0},
140 {.port = 0, .irq = 0},
141};
142#endif
143/*
144 . Wait time for memory to be free. This probably shouldn't be
145 . tuned that much, as waiting for this means nothing else happens
146 . in the system
147*/
148#define MEMORY_WAIT_TIME 16
149
150/*
151 . DEBUGGING LEVELS
152 .
153 . 0 for normal operation
154 . 1 for slightly more details
155 . >2 for various levels of increasingly useless information
156 . 2 for interrupt tracking, status flags
157 . 3 for packet dumps, etc.
158*/
159#define SMC_DEBUG 0
160
161#if (SMC_DEBUG > 2 )
162#define PRINTK3(x) printk x
163#else
164#define PRINTK3(x)
165#endif
166
167#if SMC_DEBUG > 1
168#define PRINTK2(x) printk x
169#else
170#define PRINTK2(x)
171#endif
172
173#ifdef SMC_DEBUG
174#define PRINTK(x) printk x
175#else
176#define PRINTK(x)
177#endif
178
179
180/*------------------------------------------------------------------------
181 .
182 . The internal workings of the driver. If you are changing anything
183 . here with the SMC stuff, you should have the datasheet and known
184 . what you are doing.
185 .
186 -------------------------------------------------------------------------*/
187#define CARDNAME "SMC9194"
188
189
190/* store this information for the driver.. */
191struct smc_local {
192 /*
193 If I have to wait until memory is available to send
194 a packet, I will store the skbuff here, until I get the
195 desired memory. Then, I'll send it out and free it.
196 */
197 struct sk_buff * saved_skb;
198
199 /*
200 . This keeps track of how many packets that I have
201 . sent out. When an TX_EMPTY interrupt comes, I know
202 . that all of these have been sent.
203 */
204 int packets_waiting;
205};
206
207
208/*-----------------------------------------------------------------
209 .
210 . The driver can be entered at any of the following entry points.
211 .
212 .------------------------------------------------------------------ */
213
214/*
215 . This is called by register_netdev(). It is responsible for
216 . checking the portlist for the SMC9000 series chipset. If it finds
217 . one, then it will initialize the device, find the hardware information,
218 . and sets up the appropriate device parameters.
219 . NOTE: Interrupts are *OFF* when this procedure is called.
220 .
221 . NB:This shouldn't be static since it is referred to externally.
222*/
223struct net_device *smc_init(int unit);
224
225/*
226 . The kernel calls this function when someone wants to use the device,
227 . typically 'ifconfig ethX up'.
228*/
229static int smc_open(struct net_device *dev);
230
231/*
232 . Our watchdog timed out. Called by the networking layer
233*/
234static void smc_timeout(struct net_device *dev);
235
236/*
237 . This is called by the kernel in response to 'ifconfig ethX down'. It
238 . is responsible for cleaning up everything that the open routine
239 . does, and maybe putting the card into a powerdown state.
240*/
241static int smc_close(struct net_device *dev);
242
243/*
244 . Finally, a call to set promiscuous mode ( for TCPDUMP and related
245 . programs ) and multicast modes.
246*/
247static void smc_set_multicast_list(struct net_device *dev);
248
249
250/*---------------------------------------------------------------
251 .
252 . Interrupt level calls..
253 .
254 ----------------------------------------------------------------*/
255
256/*
257 . Handles the actual interrupt
258*/
259static irqreturn_t smc_interrupt(int irq, void *);
260/*
261 . This is a separate procedure to handle the receipt of a packet, to
262 . leave the interrupt code looking slightly cleaner
263*/
264static inline void smc_rcv( struct net_device *dev );
265/*
266 . This handles a TX interrupt, which is only called when an error
267 . relating to a packet is sent.
268*/
269static inline void smc_tx( struct net_device * dev );
270
271/*
272 ------------------------------------------------------------
273 .
274 . Internal routines
275 .
276 ------------------------------------------------------------
277*/
278
279/*
280 . Test if a given location contains a chip, trying to cause as
281 . little damage as possible if it's not a SMC chip.
282*/
283static int smc_probe(struct net_device *dev, int ioaddr);
284
285/*
286 . A rather simple routine to print out a packet for debugging purposes.
287*/
288#if SMC_DEBUG > 2
289static void print_packet( byte *, int );
290#endif
291
292#define tx_done(dev) 1
293
294/* this is called to actually send the packet to the chip */
295static void smc_hardware_send_packet( struct net_device * dev );
296
297/* Since I am not sure if I will have enough room in the chip's ram
298 . to store the packet, I call this routine, which either sends it
299 . now, or generates an interrupt when the card is ready for the
300 . packet */
301static netdev_tx_t smc_wait_to_send_packet( struct sk_buff * skb,
302 struct net_device *dev );
303
304/* this does a soft reset on the device */
305static void smc_reset( int ioaddr );
306
307/* Enable Interrupts, Receive, and Transmit */
308static void smc_enable( int ioaddr );
309
310/* this puts the device in an inactive state */
311static void smc_shutdown( int ioaddr );
312
313/* This routine will find the IRQ of the driver if one is not
314 . specified in the input to the device. */
315static int smc_findirq( int ioaddr );
316
317/*
318 . Function: smc_reset( int ioaddr )
319 . Purpose:
320 . This sets the SMC91xx chip to its normal state, hopefully from whatever
321 . mess that any other DOS driver has put it in.
322 .
323 . Maybe I should reset more registers to defaults in here? SOFTRESET should
324 . do that for me.
325 .
326 . Method:
327 . 1. send a SOFT RESET
328 . 2. wait for it to finish
329 . 3. enable autorelease mode
330 . 4. reset the memory management unit
331 . 5. clear all interrupts
332 .
333*/
334static void smc_reset( int ioaddr )
335{
336 /* This resets the registers mostly to defaults, but doesn't
337 affect EEPROM. That seems unnecessary */
338 SMC_SELECT_BANK( 0 );
339 outw( RCR_SOFTRESET, ioaddr + RCR );
340
341 /* this should pause enough for the chip to be happy */
342 SMC_DELAY( );
343
344 /* Set the transmit and receive configuration registers to
345 default values */
346 outw( RCR_CLEAR, ioaddr + RCR );
347 outw( TCR_CLEAR, ioaddr + TCR );
348
349 /* set the control register to automatically
350 release successfully transmitted packets, to make the best
351 use out of our limited memory */
352 SMC_SELECT_BANK( 1 );
353 outw( inw( ioaddr + CONTROL ) | CTL_AUTO_RELEASE , ioaddr + CONTROL );
354
355 /* Reset the MMU */
356 SMC_SELECT_BANK( 2 );
357 outw( MC_RESET, ioaddr + MMU_CMD );
358
359 /* Note: It doesn't seem that waiting for the MMU busy is needed here,
360 but this is a place where future chipsets _COULD_ break. Be wary
361 of issuing another MMU command right after this */
362
363 outb( 0, ioaddr + INT_MASK );
364}
365
366/*
367 . Function: smc_enable
368 . Purpose: let the chip talk to the outside work
369 . Method:
370 . 1. Enable the transmitter
371 . 2. Enable the receiver
372 . 3. Enable interrupts
373*/
374static void smc_enable( int ioaddr )
375{
376 SMC_SELECT_BANK( 0 );
377 /* see the header file for options in TCR/RCR NORMAL*/
378 outw( TCR_NORMAL, ioaddr + TCR );
379 outw( RCR_NORMAL, ioaddr + RCR );
380
381 /* now, enable interrupts */
382 SMC_SELECT_BANK( 2 );
383 outb( SMC_INTERRUPT_MASK, ioaddr + INT_MASK );
384}
385
386/*
387 . Function: smc_shutdown
388 . Purpose: closes down the SMC91xxx chip.
389 . Method:
390 . 1. zero the interrupt mask
391 . 2. clear the enable receive flag
392 . 3. clear the enable xmit flags
393 .
394 . TODO:
395 . (1) maybe utilize power down mode.
396 . Why not yet? Because while the chip will go into power down mode,
397 . the manual says that it will wake up in response to any I/O requests
398 . in the register space. Empirical results do not show this working.
399*/
400static void smc_shutdown( int ioaddr )
401{
402 /* no more interrupts for me */
403 SMC_SELECT_BANK( 2 );
404 outb( 0, ioaddr + INT_MASK );
405
406 /* and tell the card to stay away from that nasty outside world */
407 SMC_SELECT_BANK( 0 );
408 outb( RCR_CLEAR, ioaddr + RCR );
409 outb( TCR_CLEAR, ioaddr + TCR );
410#if 0
411 /* finally, shut the chip down */
412 SMC_SELECT_BANK( 1 );
413 outw( inw( ioaddr + CONTROL ), CTL_POWERDOWN, ioaddr + CONTROL );
414#endif
415}
416
417
418/*
419 . Function: smc_setmulticast( int ioaddr, struct net_device *dev )
420 . Purpose:
421 . This sets the internal hardware table to filter out unwanted multicast
422 . packets before they take up memory.
423 .
424 . The SMC chip uses a hash table where the high 6 bits of the CRC of
425 . address are the offset into the table. If that bit is 1, then the
426 . multicast packet is accepted. Otherwise, it's dropped silently.
427 .
428 . To use the 6 bits as an offset into the table, the high 3 bits are the
429 . number of the 8 bit register, while the low 3 bits are the bit within
430 . that register.
431 .
432 . This routine is based very heavily on the one provided by Peter Cammaert.
433*/
434
435
436static void smc_setmulticast(int ioaddr, struct net_device *dev)
437{
438 int i;
439 unsigned char multicast_table[ 8 ];
440 struct netdev_hw_addr *ha;
441 /* table for flipping the order of 3 bits */
442 unsigned char invert3[] = { 0, 4, 2, 6, 1, 5, 3, 7 };
443
444 /* start with a table of all zeros: reject all */
445 memset( multicast_table, 0, sizeof( multicast_table ) );
446
447 netdev_for_each_mc_addr(ha, dev) {
448 int position;
449
450 /* only use the low order bits */
451 position = ether_crc_le(6, ha->addr) & 0x3f;
452
453 /* do some messy swapping to put the bit in the right spot */
454 multicast_table[invert3[position&7]] |=
455 (1<<invert3[(position>>3)&7]);
456
457 }
458 /* now, the table can be loaded into the chipset */
459 SMC_SELECT_BANK( 3 );
460
461 for ( i = 0; i < 8 ; i++ ) {
462 outb( multicast_table[i], ioaddr + MULTICAST1 + i );
463 }
464}
465
466/*
467 . Function: smc_wait_to_send_packet( struct sk_buff * skb, struct net_device * )
468 . Purpose:
469 . Attempt to allocate memory for a packet, if chip-memory is not
470 . available, then tell the card to generate an interrupt when it
471 . is available.
472 .
473 . Algorithm:
474 .
475 . o if the saved_skb is not currently null, then drop this packet
476 . on the floor. This should never happen, because of TBUSY.
477 . o if the saved_skb is null, then replace it with the current packet,
478 . o See if I can sending it now.
479 . o (NO): Enable interrupts and let the interrupt handler deal with it.
480 . o (YES):Send it now.
481*/
482static netdev_tx_t smc_wait_to_send_packet(struct sk_buff *skb,
483 struct net_device *dev)
484{
485 struct smc_local *lp = netdev_priv(dev);
486 unsigned int ioaddr = dev->base_addr;
487 word length;
488 unsigned short numPages;
489 word time_out;
490
491 netif_stop_queue(dev);
492 /* Well, I want to send the packet.. but I don't know
493 if I can send it right now... */
494
495 if ( lp->saved_skb) {
496 /* THIS SHOULD NEVER HAPPEN. */
497 dev->stats.tx_aborted_errors++;
498 printk(CARDNAME": Bad Craziness - sent packet while busy.\n" );
499 return NETDEV_TX_BUSY;
500 }
501 lp->saved_skb = skb;
502
503 length = skb->len;
504
505 if (length < ETH_ZLEN) {
506 if (skb_padto(skb, ETH_ZLEN)) {
507 netif_wake_queue(dev);
508 return NETDEV_TX_OK;
509 }
510 length = ETH_ZLEN;
511 }
512
513 /*
514 ** The MMU wants the number of pages to be the number of 256 bytes
515 ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
516 **
517 ** Pkt size for allocating is data length +6 (for additional status words,
518 ** length and ctl!) If odd size last byte is included in this header.
519 */
520 numPages = ((length & 0xfffe) + 6) / 256;
521
522 if (numPages > 7 ) {
523 printk(CARDNAME": Far too big packet error.\n");
524 /* freeing the packet is a good thing here... but should
525 . any packets of this size get down here? */
526 dev_kfree_skb (skb);
527 lp->saved_skb = NULL;
528 /* this IS an error, but, i don't want the skb saved */
529 netif_wake_queue(dev);
530 return NETDEV_TX_OK;
531 }
532 /* either way, a packet is waiting now */
533 lp->packets_waiting++;
534
535 /* now, try to allocate the memory */
536 SMC_SELECT_BANK( 2 );
537 outw( MC_ALLOC | numPages, ioaddr + MMU_CMD );
538 /*
539 . Performance Hack
540 .
541 . wait a short amount of time.. if I can send a packet now, I send
542 . it now. Otherwise, I enable an interrupt and wait for one to be
543 . available.
544 .
545 . I could have handled this a slightly different way, by checking to
546 . see if any memory was available in the FREE MEMORY register. However,
547 . either way, I need to generate an allocation, and the allocation works
548 . no matter what, so I saw no point in checking free memory.
549 */
550 time_out = MEMORY_WAIT_TIME;
551 do {
552 word status;
553
554 status = inb( ioaddr + INTERRUPT );
555 if ( status & IM_ALLOC_INT ) {
556 /* acknowledge the interrupt */
557 outb( IM_ALLOC_INT, ioaddr + INTERRUPT );
558 break;
559 }
560 } while ( -- time_out );
561
562 if ( !time_out ) {
563 /* oh well, wait until the chip finds memory later */
564 SMC_ENABLE_INT( IM_ALLOC_INT );
565 PRINTK2((CARDNAME": memory allocation deferred.\n"));
566 /* it's deferred, but I'll handle it later */
567 return NETDEV_TX_OK;
568 }
569 /* or YES! I can send the packet now.. */
570 smc_hardware_send_packet(dev);
571 netif_wake_queue(dev);
572 return NETDEV_TX_OK;
573}
574
575/*
576 . Function: smc_hardware_send_packet(struct net_device * )
577 . Purpose:
578 . This sends the actual packet to the SMC9xxx chip.
579 .
580 . Algorithm:
581 . First, see if a saved_skb is available.
582 . ( this should NOT be called if there is no 'saved_skb'
583 . Now, find the packet number that the chip allocated
584 . Point the data pointers at it in memory
585 . Set the length word in the chip's memory
586 . Dump the packet to chip memory
587 . Check if a last byte is needed ( odd length packet )
588 . if so, set the control flag right
589 . Tell the card to send it
590 . Enable the transmit interrupt, so I know if it failed
591 . Free the kernel data if I actually sent it.
592*/
593static void smc_hardware_send_packet( struct net_device * dev )
594{
595 struct smc_local *lp = netdev_priv(dev);
596 byte packet_no;
597 struct sk_buff * skb = lp->saved_skb;
598 word length;
599 unsigned int ioaddr;
600 byte * buf;
601
602 ioaddr = dev->base_addr;
603
604 if ( !skb ) {
605 PRINTK((CARDNAME": In XMIT with no packet to send\n"));
606 return;
607 }
608 length = ETH_ZLEN < skb->len ? skb->len : ETH_ZLEN;
609 buf = skb->data;
610
611 /* If I get here, I _know_ there is a packet slot waiting for me */
612 packet_no = inb( ioaddr + PNR_ARR + 1 );
613 if ( packet_no & 0x80 ) {
614 /* or isn't there? BAD CHIP! */
615 printk(KERN_DEBUG CARDNAME": Memory allocation failed.\n");
616 dev_kfree_skb_any(skb);
617 lp->saved_skb = NULL;
618 netif_wake_queue(dev);
619 return;
620 }
621
622 /* we have a packet address, so tell the card to use it */
623 outb( packet_no, ioaddr + PNR_ARR );
624
625 /* point to the beginning of the packet */
626 outw( PTR_AUTOINC , ioaddr + POINTER );
627
628 PRINTK3((CARDNAME": Trying to xmit packet of length %x\n", length ));
629#if SMC_DEBUG > 2
630 print_packet( buf, length );
631#endif
632
633 /* send the packet length ( +6 for status, length and ctl byte )
634 and the status word ( set to zeros ) */
635#ifdef USE_32_BIT
636 outl( (length +6 ) << 16 , ioaddr + DATA_1 );
637#else
638 outw( 0, ioaddr + DATA_1 );
639 /* send the packet length ( +6 for status words, length, and ctl*/
640 outb( (length+6) & 0xFF,ioaddr + DATA_1 );
641 outb( (length+6) >> 8 , ioaddr + DATA_1 );
642#endif
643
644 /* send the actual data
645 . I _think_ it's faster to send the longs first, and then
646 . mop up by sending the last word. It depends heavily
647 . on alignment, at least on the 486. Maybe it would be
648 . a good idea to check which is optimal? But that could take
649 . almost as much time as is saved?
650 */
651#ifdef USE_32_BIT
652 if ( length & 0x2 ) {
653 outsl(ioaddr + DATA_1, buf, length >> 2 );
654#if !defined(__H8300H__) && !defined(__H8300S__)
655 outw( *((word *)(buf + (length & 0xFFFFFFFC))),ioaddr +DATA_1);
656#else
657 ctrl_outw( *((word *)(buf + (length & 0xFFFFFFFC))),ioaddr +DATA_1);
658#endif
659 }
660 else
661 outsl(ioaddr + DATA_1, buf, length >> 2 );
662#else
663 outsw(ioaddr + DATA_1 , buf, (length ) >> 1);
664#endif
665 /* Send the last byte, if there is one. */
666
667 if ( (length & 1) == 0 ) {
668 outw( 0, ioaddr + DATA_1 );
669 } else {
670 outb( buf[length -1 ], ioaddr + DATA_1 );
671 outb( 0x20, ioaddr + DATA_1);
672 }
673
674 /* enable the interrupts */
675 SMC_ENABLE_INT( (IM_TX_INT | IM_TX_EMPTY_INT) );
676
677 /* and let the chipset deal with it */
678 outw( MC_ENQUEUE , ioaddr + MMU_CMD );
679
680 PRINTK2((CARDNAME": Sent packet of length %d\n", length));
681
682 lp->saved_skb = NULL;
683 dev_kfree_skb_any (skb);
684
685 dev->trans_start = jiffies;
686
687 /* we can send another packet */
688 netif_wake_queue(dev);
689}
690
691/*-------------------------------------------------------------------------
692 |
693 | smc_init(int unit)
694 | Input parameters:
695 | dev->base_addr == 0, try to find all possible locations
696 | dev->base_addr == 1, return failure code
697 | dev->base_addr == 2, always allocate space, and return success
698 | dev->base_addr == <anything else> this is the address to check
699 |
700 | Output:
701 | pointer to net_device or ERR_PTR(error)
702 |
703 ---------------------------------------------------------------------------
704*/
705static int io;
706static int irq;
707static int ifport;
708
709struct net_device * __init smc_init(int unit)
710{
711 struct net_device *dev = alloc_etherdev(sizeof(struct smc_local));
712 struct devlist *smcdev = smc_devlist;
713 int err = 0;
714
715 if (!dev)
716 return ERR_PTR(-ENODEV);
717
718 if (unit >= 0) {
719 sprintf(dev->name, "eth%d", unit);
720 netdev_boot_setup_check(dev);
721 io = dev->base_addr;
722 irq = dev->irq;
723 }
724
725 if (io > 0x1ff) { /* Check a single specified location. */
726 err = smc_probe(dev, io);
727 } else if (io != 0) { /* Don't probe at all. */
728 err = -ENXIO;
729 } else {
730 for (;smcdev->port; smcdev++) {
731 if (smc_probe(dev, smcdev->port) == 0)
732 break;
733 }
734 if (!smcdev->port)
735 err = -ENODEV;
736 }
737 if (err)
738 goto out;
739 err = register_netdev(dev);
740 if (err)
741 goto out1;
742 return dev;
743out1:
744 free_irq(dev->irq, dev);
745 release_region(dev->base_addr, SMC_IO_EXTENT);
746out:
747 free_netdev(dev);
748 return ERR_PTR(err);
749}
750
751/*----------------------------------------------------------------------
752 . smc_findirq
753 .
754 . This routine has a simple purpose -- make the SMC chip generate an
755 . interrupt, so an auto-detect routine can detect it, and find the IRQ,
756 ------------------------------------------------------------------------
757*/
758static int __init smc_findirq(int ioaddr)
759{
760#ifndef NO_AUTOPROBE
761 int timeout = 20;
762 unsigned long cookie;
763
764
765 cookie = probe_irq_on();
766
767 /*
768 * What I try to do here is trigger an ALLOC_INT. This is done
769 * by allocating a small chunk of memory, which will give an interrupt
770 * when done.
771 */
772
773
774 SMC_SELECT_BANK(2);
775 /* enable ALLOCation interrupts ONLY */
776 outb( IM_ALLOC_INT, ioaddr + INT_MASK );
777
778 /*
779 . Allocate 512 bytes of memory. Note that the chip was just
780 . reset so all the memory is available
781 */
782 outw( MC_ALLOC | 1, ioaddr + MMU_CMD );
783
784 /*
785 . Wait until positive that the interrupt has been generated
786 */
787 while ( timeout ) {
788 byte int_status;
789
790 int_status = inb( ioaddr + INTERRUPT );
791
792 if ( int_status & IM_ALLOC_INT )
793 break; /* got the interrupt */
794 timeout--;
795 }
796 /* there is really nothing that I can do here if timeout fails,
797 as probe_irq_off will return a 0 anyway, which is what I
798 want in this case. Plus, the clean up is needed in both
799 cases. */
800
801 /* DELAY HERE!
802 On a fast machine, the status might change before the interrupt
803 is given to the processor. This means that the interrupt was
804 never detected, and probe_irq_off fails to report anything.
805 This should fix probe_irq_* problems.
806 */
807 SMC_DELAY();
808 SMC_DELAY();
809
810 /* and disable all interrupts again */
811 outb( 0, ioaddr + INT_MASK );
812
813 /* and return what I found */
814 return probe_irq_off(cookie);
815#else /* NO_AUTOPROBE */
816 struct devlist *smcdev;
817 for (smcdev = smc_devlist; smcdev->port; smcdev++) {
818 if (smcdev->port == ioaddr)
819 return smcdev->irq;
820 }
821 return 0;
822#endif
823}
824
825static const struct net_device_ops smc_netdev_ops = {
826 .ndo_open = smc_open,
827 .ndo_stop = smc_close,
828 .ndo_start_xmit = smc_wait_to_send_packet,
829 .ndo_tx_timeout = smc_timeout,
830 .ndo_set_multicast_list = smc_set_multicast_list,
831 .ndo_change_mtu = eth_change_mtu,
832 .ndo_set_mac_address = eth_mac_addr,
833 .ndo_validate_addr = eth_validate_addr,
834};
835
836/*----------------------------------------------------------------------
837 . Function: smc_probe( int ioaddr )
838 .
839 . Purpose:
840 . Tests to see if a given ioaddr points to an SMC9xxx chip.
841 . Returns a 0 on success
842 .
843 . Algorithm:
844 . (1) see if the high byte of BANK_SELECT is 0x33
845 . (2) compare the ioaddr with the base register's address
846 . (3) see if I recognize the chip ID in the appropriate register
847 .
848 .---------------------------------------------------------------------
849 */
850
851/*---------------------------------------------------------------
852 . Here I do typical initialization tasks.
853 .
854 . o Initialize the structure if needed
855 . o print out my vanity message if not done so already
856 . o print out what type of hardware is detected
857 . o print out the ethernet address
858 . o find the IRQ
859 . o set up my private data
860 . o configure the dev structure with my subroutines
861 . o actually GRAB the irq.
862 . o GRAB the region
863 .-----------------------------------------------------------------
864*/
865static int __init smc_probe(struct net_device *dev, int ioaddr)
866{
867 int i, memory, retval;
868 static unsigned version_printed;
869 unsigned int bank;
870
871 const char *version_string;
872 const char *if_string;
873
874 /* registers */
875 word revision_register;
876 word base_address_register;
877 word configuration_register;
878 word memory_info_register;
879 word memory_cfg_register;
880
881 /* Grab the region so that no one else tries to probe our ioports. */
882 if (!request_region(ioaddr, SMC_IO_EXTENT, DRV_NAME))
883 return -EBUSY;
884
885 dev->irq = irq;
886 dev->if_port = ifport;
887
888 /* First, see if the high byte is 0x33 */
889 bank = inw( ioaddr + BANK_SELECT );
890 if ( (bank & 0xFF00) != 0x3300 ) {
891 retval = -ENODEV;
892 goto err_out;
893 }
894 /* The above MIGHT indicate a device, but I need to write to further
895 test this. */
896 outw( 0x0, ioaddr + BANK_SELECT );
897 bank = inw( ioaddr + BANK_SELECT );
898 if ( (bank & 0xFF00 ) != 0x3300 ) {
899 retval = -ENODEV;
900 goto err_out;
901 }
902#if !defined(CONFIG_H8S_EDOSK2674)
903 /* well, we've already written once, so hopefully another time won't
904 hurt. This time, I need to switch the bank register to bank 1,
905 so I can access the base address register */
906 SMC_SELECT_BANK(1);
907 base_address_register = inw( ioaddr + BASE );
908 if ( ioaddr != ( base_address_register >> 3 & 0x3E0 ) ) {
909 printk(CARDNAME ": IOADDR %x doesn't match configuration (%x). "
910 "Probably not a SMC chip\n",
911 ioaddr, base_address_register >> 3 & 0x3E0 );
912 /* well, the base address register didn't match. Must not have
913 been a SMC chip after all. */
914 retval = -ENODEV;
915 goto err_out;
916 }
917#else
918 (void)base_address_register; /* Warning suppression */
919#endif
920
921
922 /* check if the revision register is something that I recognize.
923 These might need to be added to later, as future revisions
924 could be added. */
925 SMC_SELECT_BANK(3);
926 revision_register = inw( ioaddr + REVISION );
927 if ( !chip_ids[ ( revision_register >> 4 ) & 0xF ] ) {
928 /* I don't recognize this chip, so... */
929 printk(CARDNAME ": IO %x: Unrecognized revision register:"
930 " %x, Contact author.\n", ioaddr, revision_register);
931
932 retval = -ENODEV;
933 goto err_out;
934 }
935
936 /* at this point I'll assume that the chip is an SMC9xxx.
937 It might be prudent to check a listing of MAC addresses
938 against the hardware address, or do some other tests. */
939
940 if (version_printed++ == 0)
941 printk("%s", version);
942
943 /* fill in some of the fields */
944 dev->base_addr = ioaddr;
945
946 /*
947 . Get the MAC address ( bank 1, regs 4 - 9 )
948 */
949 SMC_SELECT_BANK( 1 );
950 for ( i = 0; i < 6; i += 2 ) {
951 word address;
952
953 address = inw( ioaddr + ADDR0 + i );
954 dev->dev_addr[ i + 1] = address >> 8;
955 dev->dev_addr[ i ] = address & 0xFF;
956 }
957
958 /* get the memory information */
959
960 SMC_SELECT_BANK( 0 );
961 memory_info_register = inw( ioaddr + MIR );
962 memory_cfg_register = inw( ioaddr + MCR );
963 memory = ( memory_cfg_register >> 9 ) & 0x7; /* multiplier */
964 memory *= 256 * ( memory_info_register & 0xFF );
965
966 /*
967 Now, I want to find out more about the chip. This is sort of
968 redundant, but it's cleaner to have it in both, rather than having
969 one VERY long probe procedure.
970 */
971 SMC_SELECT_BANK(3);
972 revision_register = inw( ioaddr + REVISION );
973 version_string = chip_ids[ ( revision_register >> 4 ) & 0xF ];
974 if ( !version_string ) {
975 /* I shouldn't get here because this call was done before.... */
976 retval = -ENODEV;
977 goto err_out;
978 }
979
980 /* is it using AUI or 10BaseT ? */
981 if ( dev->if_port == 0 ) {
982 SMC_SELECT_BANK(1);
983 configuration_register = inw( ioaddr + CONFIG );
984 if ( configuration_register & CFG_AUI_SELECT )
985 dev->if_port = 2;
986 else
987 dev->if_port = 1;
988 }
989 if_string = interfaces[ dev->if_port - 1 ];
990
991 /* now, reset the chip, and put it into a known state */
992 smc_reset( ioaddr );
993
994 /*
995 . If dev->irq is 0, then the device has to be banged on to see
996 . what the IRQ is.
997 .
998 . This banging doesn't always detect the IRQ, for unknown reasons.
999 . a workaround is to reset the chip and try again.
1000 .
1001 . Interestingly, the DOS packet driver *SETS* the IRQ on the card to
1002 . be what is requested on the command line. I don't do that, mostly
1003 . because the card that I have uses a non-standard method of accessing
1004 . the IRQs, and because this _should_ work in most configurations.
1005 .
1006 . Specifying an IRQ is done with the assumption that the user knows
1007 . what (s)he is doing. No checking is done!!!!
1008 .
1009 */
1010 if ( dev->irq < 2 ) {
1011 int trials;
1012
1013 trials = 3;
1014 while ( trials-- ) {
1015 dev->irq = smc_findirq( ioaddr );
1016 if ( dev->irq )
1017 break;
1018 /* kick the card and try again */
1019 smc_reset( ioaddr );
1020 }
1021 }
1022 if (dev->irq == 0 ) {
1023 printk(CARDNAME": Couldn't autodetect your IRQ. Use irq=xx.\n");
1024 retval = -ENODEV;
1025 goto err_out;
1026 }
1027
1028 /* now, print out the card info, in a short format.. */
1029
1030 printk("%s: %s(r:%d) at %#3x IRQ:%d INTF:%s MEM:%db ", dev->name,
1031 version_string, revision_register & 0xF, ioaddr, dev->irq,
1032 if_string, memory );
1033 /*
1034 . Print the Ethernet address
1035 */
1036 printk("ADDR: %pM\n", dev->dev_addr);
1037
1038 /* Grab the IRQ */
1039 retval = request_irq(dev->irq, smc_interrupt, 0, DRV_NAME, dev);
1040 if (retval) {
1041 printk("%s: unable to get IRQ %d (irqval=%d).\n", DRV_NAME,
1042 dev->irq, retval);
1043 goto err_out;
1044 }
1045
1046 dev->netdev_ops = &smc_netdev_ops;
1047 dev->watchdog_timeo = HZ/20;
1048
1049 return 0;
1050
1051err_out:
1052 release_region(ioaddr, SMC_IO_EXTENT);
1053 return retval;
1054}
1055
1056#if SMC_DEBUG > 2
1057static void print_packet( byte * buf, int length )
1058{
1059#if 0
1060 int i;
1061 int remainder;
1062 int lines;
1063
1064 printk("Packet of length %d\n", length);
1065 lines = length / 16;
1066 remainder = length % 16;
1067
1068 for ( i = 0; i < lines ; i ++ ) {
1069 int cur;
1070
1071 for ( cur = 0; cur < 8; cur ++ ) {
1072 byte a, b;
1073
1074 a = *(buf ++ );
1075 b = *(buf ++ );
1076 printk("%02x%02x ", a, b );
1077 }
1078 printk("\n");
1079 }
1080 for ( i = 0; i < remainder/2 ; i++ ) {
1081 byte a, b;
1082
1083 a = *(buf ++ );
1084 b = *(buf ++ );
1085 printk("%02x%02x ", a, b );
1086 }
1087 printk("\n");
1088#endif
1089}
1090#endif
1091
1092
1093/*
1094 * Open and Initialize the board
1095 *
1096 * Set up everything, reset the card, etc ..
1097 *
1098 */
1099static int smc_open(struct net_device *dev)
1100{
1101 int ioaddr = dev->base_addr;
1102
1103 int i; /* used to set hw ethernet address */
1104
1105 /* clear out all the junk that was put here before... */
1106 memset(netdev_priv(dev), 0, sizeof(struct smc_local));
1107
1108 /* reset the hardware */
1109
1110 smc_reset( ioaddr );
1111 smc_enable( ioaddr );
1112
1113 /* Select which interface to use */
1114
1115 SMC_SELECT_BANK( 1 );
1116 if ( dev->if_port == 1 ) {
1117 outw( inw( ioaddr + CONFIG ) & ~CFG_AUI_SELECT,
1118 ioaddr + CONFIG );
1119 }
1120 else if ( dev->if_port == 2 ) {
1121 outw( inw( ioaddr + CONFIG ) | CFG_AUI_SELECT,
1122 ioaddr + CONFIG );
1123 }
1124
1125 /*
1126 According to Becker, I have to set the hardware address
1127 at this point, because the (l)user can set it with an
1128 ioctl. Easily done...
1129 */
1130 SMC_SELECT_BANK( 1 );
1131 for ( i = 0; i < 6; i += 2 ) {
1132 word address;
1133
1134 address = dev->dev_addr[ i + 1 ] << 8 ;
1135 address |= dev->dev_addr[ i ];
1136 outw( address, ioaddr + ADDR0 + i );
1137 }
1138
1139 netif_start_queue(dev);
1140 return 0;
1141}
1142
1143/*--------------------------------------------------------
1144 . Called by the kernel to send a packet out into the void
1145 . of the net. This routine is largely based on
1146 . skeleton.c, from Becker.
1147 .--------------------------------------------------------
1148*/
1149
1150static void smc_timeout(struct net_device *dev)
1151{
1152 /* If we get here, some higher level has decided we are broken.
1153 There should really be a "kick me" function call instead. */
1154 printk(KERN_WARNING CARDNAME": transmit timed out, %s?\n",
1155 tx_done(dev) ? "IRQ conflict" :
1156 "network cable problem");
1157 /* "kick" the adaptor */
1158 smc_reset( dev->base_addr );
1159 smc_enable( dev->base_addr );
1160 dev->trans_start = jiffies; /* prevent tx timeout */
1161 /* clear anything saved */
1162 ((struct smc_local *)netdev_priv(dev))->saved_skb = NULL;
1163 netif_wake_queue(dev);
1164}
1165
1166/*-------------------------------------------------------------
1167 .
1168 . smc_rcv - receive a packet from the card
1169 .
1170 . There is ( at least ) a packet waiting to be read from
1171 . chip-memory.
1172 .
1173 . o Read the status
1174 . o If an error, record it
1175 . o otherwise, read in the packet
1176 --------------------------------------------------------------
1177*/
1178static void smc_rcv(struct net_device *dev)
1179{
1180 int ioaddr = dev->base_addr;
1181 int packet_number;
1182 word status;
1183 word packet_length;
1184
1185 /* assume bank 2 */
1186
1187 packet_number = inw( ioaddr + FIFO_PORTS );
1188
1189 if ( packet_number & FP_RXEMPTY ) {
1190 /* we got called , but nothing was on the FIFO */
1191 PRINTK((CARDNAME ": WARNING: smc_rcv with nothing on FIFO.\n"));
1192 /* don't need to restore anything */
1193 return;
1194 }
1195
1196 /* start reading from the start of the packet */
1197 outw( PTR_READ | PTR_RCV | PTR_AUTOINC, ioaddr + POINTER );
1198
1199 /* First two words are status and packet_length */
1200 status = inw( ioaddr + DATA_1 );
1201 packet_length = inw( ioaddr + DATA_1 );
1202
1203 packet_length &= 0x07ff; /* mask off top bits */
1204
1205 PRINTK2(("RCV: STATUS %4x LENGTH %4x\n", status, packet_length ));
1206 /*
1207 . the packet length contains 3 extra words :
1208 . status, length, and an extra word with an odd byte .
1209 */
1210 packet_length -= 6;
1211
1212 if ( !(status & RS_ERRORS ) ){
1213 /* do stuff to make a new packet */
1214 struct sk_buff * skb;
1215 byte * data;
1216
1217 /* read one extra byte */
1218 if ( status & RS_ODDFRAME )
1219 packet_length++;
1220
1221 /* set multicast stats */
1222 if ( status & RS_MULTICAST )
1223 dev->stats.multicast++;
1224
1225 skb = dev_alloc_skb( packet_length + 5);
1226
1227 if ( skb == NULL ) {
1228 printk(KERN_NOTICE CARDNAME ": Low memory, packet dropped.\n");
1229 dev->stats.rx_dropped++;
1230 goto done;
1231 }
1232
1233 /*
1234 ! This should work without alignment, but it could be
1235 ! in the worse case
1236 */
1237
1238 skb_reserve( skb, 2 ); /* 16 bit alignment */
1239
1240 data = skb_put( skb, packet_length);
1241
1242#ifdef USE_32_BIT
1243 /* QUESTION: Like in the TX routine, do I want
1244 to send the DWORDs or the bytes first, or some
1245 mixture. A mixture might improve already slow PIO
1246 performance */
1247 PRINTK3((" Reading %d dwords (and %d bytes)\n",
1248 packet_length >> 2, packet_length & 3 ));
1249 insl(ioaddr + DATA_1 , data, packet_length >> 2 );
1250 /* read the left over bytes */
1251 insb( ioaddr + DATA_1, data + (packet_length & 0xFFFFFC),
1252 packet_length & 0x3 );
1253#else
1254 PRINTK3((" Reading %d words and %d byte(s)\n",
1255 (packet_length >> 1 ), packet_length & 1 ));
1256 insw(ioaddr + DATA_1 , data, packet_length >> 1);
1257 if ( packet_length & 1 ) {
1258 data += packet_length & ~1;
1259 *(data++) = inb( ioaddr + DATA_1 );
1260 }
1261#endif
1262#if SMC_DEBUG > 2
1263 print_packet( data, packet_length );
1264#endif
1265
1266 skb->protocol = eth_type_trans(skb, dev );
1267 netif_rx(skb);
1268 dev->stats.rx_packets++;
1269 dev->stats.rx_bytes += packet_length;
1270 } else {
1271 /* error ... */
1272 dev->stats.rx_errors++;
1273
1274 if ( status & RS_ALGNERR ) dev->stats.rx_frame_errors++;
1275 if ( status & (RS_TOOSHORT | RS_TOOLONG ) )
1276 dev->stats.rx_length_errors++;
1277 if ( status & RS_BADCRC) dev->stats.rx_crc_errors++;
1278 }
1279
1280done:
1281 /* error or good, tell the card to get rid of this packet */
1282 outw( MC_RELEASE, ioaddr + MMU_CMD );
1283}
1284
1285
1286/*************************************************************************
1287 . smc_tx
1288 .
1289 . Purpose: Handle a transmit error message. This will only be called
1290 . when an error, because of the AUTO_RELEASE mode.
1291 .
1292 . Algorithm:
1293 . Save pointer and packet no
1294 . Get the packet no from the top of the queue
1295 . check if it's valid ( if not, is this an error??? )
1296 . read the status word
1297 . record the error
1298 . ( resend? Not really, since we don't want old packets around )
1299 . Restore saved values
1300 ************************************************************************/
1301static void smc_tx( struct net_device * dev )
1302{
1303 int ioaddr = dev->base_addr;
1304 struct smc_local *lp = netdev_priv(dev);
1305 byte saved_packet;
1306 byte packet_no;
1307 word tx_status;
1308
1309
1310 /* assume bank 2 */
1311
1312 saved_packet = inb( ioaddr + PNR_ARR );
1313 packet_no = inw( ioaddr + FIFO_PORTS );
1314 packet_no &= 0x7F;
1315
1316 /* select this as the packet to read from */
1317 outb( packet_no, ioaddr + PNR_ARR );
1318
1319 /* read the first word from this packet */
1320 outw( PTR_AUTOINC | PTR_READ, ioaddr + POINTER );
1321
1322 tx_status = inw( ioaddr + DATA_1 );
1323 PRINTK3((CARDNAME": TX DONE STATUS: %4x\n", tx_status));
1324
1325 dev->stats.tx_errors++;
1326 if ( tx_status & TS_LOSTCAR ) dev->stats.tx_carrier_errors++;
1327 if ( tx_status & TS_LATCOL ) {
1328 printk(KERN_DEBUG CARDNAME
1329 ": Late collision occurred on last xmit.\n");
1330 dev->stats.tx_window_errors++;
1331 }
1332#if 0
1333 if ( tx_status & TS_16COL ) { ... }
1334#endif
1335
1336 if ( tx_status & TS_SUCCESS ) {
1337 printk(CARDNAME": Successful packet caused interrupt\n");
1338 }
1339 /* re-enable transmit */
1340 SMC_SELECT_BANK( 0 );
1341 outw( inw( ioaddr + TCR ) | TCR_ENABLE, ioaddr + TCR );
1342
1343 /* kill the packet */
1344 SMC_SELECT_BANK( 2 );
1345 outw( MC_FREEPKT, ioaddr + MMU_CMD );
1346
1347 /* one less packet waiting for me */
1348 lp->packets_waiting--;
1349
1350 outb( saved_packet, ioaddr + PNR_ARR );
1351}
1352
1353/*--------------------------------------------------------------------
1354 .
1355 . This is the main routine of the driver, to handle the device when
1356 . it needs some attention.
1357 .
1358 . So:
1359 . first, save state of the chipset
1360 . branch off into routines to handle each case, and acknowledge
1361 . each to the interrupt register
1362 . and finally restore state.
1363 .
1364 ---------------------------------------------------------------------*/
1365
1366static irqreturn_t smc_interrupt(int irq, void * dev_id)
1367{
1368 struct net_device *dev = dev_id;
1369 int ioaddr = dev->base_addr;
1370 struct smc_local *lp = netdev_priv(dev);
1371
1372 byte status;
1373 word card_stats;
1374 byte mask;
1375 int timeout;
1376 /* state registers */
1377 word saved_bank;
1378 word saved_pointer;
1379 int handled = 0;
1380
1381
1382 PRINTK3((CARDNAME": SMC interrupt started\n"));
1383
1384 saved_bank = inw( ioaddr + BANK_SELECT );
1385
1386 SMC_SELECT_BANK(2);
1387 saved_pointer = inw( ioaddr + POINTER );
1388
1389 mask = inb( ioaddr + INT_MASK );
1390 /* clear all interrupts */
1391 outb( 0, ioaddr + INT_MASK );
1392
1393
1394 /* set a timeout value, so I don't stay here forever */
1395 timeout = 4;
1396
1397 PRINTK2((KERN_WARNING CARDNAME ": MASK IS %x\n", mask));
1398 do {
1399 /* read the status flag, and mask it */
1400 status = inb( ioaddr + INTERRUPT ) & mask;
1401 if (!status )
1402 break;
1403
1404 handled = 1;
1405
1406 PRINTK3((KERN_WARNING CARDNAME
1407 ": Handling interrupt status %x\n", status));
1408
1409 if (status & IM_RCV_INT) {
1410 /* Got a packet(s). */
1411 PRINTK2((KERN_WARNING CARDNAME
1412 ": Receive Interrupt\n"));
1413 smc_rcv(dev);
1414 } else if (status & IM_TX_INT ) {
1415 PRINTK2((KERN_WARNING CARDNAME
1416 ": TX ERROR handled\n"));
1417 smc_tx(dev);
1418 outb(IM_TX_INT, ioaddr + INTERRUPT );
1419 } else if (status & IM_TX_EMPTY_INT ) {
1420 /* update stats */
1421 SMC_SELECT_BANK( 0 );
1422 card_stats = inw( ioaddr + COUNTER );
1423 /* single collisions */
1424 dev->stats.collisions += card_stats & 0xF;
1425 card_stats >>= 4;
1426 /* multiple collisions */
1427 dev->stats.collisions += card_stats & 0xF;
1428
1429 /* these are for when linux supports these statistics */
1430
1431 SMC_SELECT_BANK( 2 );
1432 PRINTK2((KERN_WARNING CARDNAME
1433 ": TX_BUFFER_EMPTY handled\n"));
1434 outb( IM_TX_EMPTY_INT, ioaddr + INTERRUPT );
1435 mask &= ~IM_TX_EMPTY_INT;
1436 dev->stats.tx_packets += lp->packets_waiting;
1437 lp->packets_waiting = 0;
1438
1439 } else if (status & IM_ALLOC_INT ) {
1440 PRINTK2((KERN_DEBUG CARDNAME
1441 ": Allocation interrupt\n"));
1442 /* clear this interrupt so it doesn't happen again */
1443 mask &= ~IM_ALLOC_INT;
1444
1445 smc_hardware_send_packet( dev );
1446
1447 /* enable xmit interrupts based on this */
1448 mask |= ( IM_TX_EMPTY_INT | IM_TX_INT );
1449
1450 /* and let the card send more packets to me */
1451 netif_wake_queue(dev);
1452
1453 PRINTK2((CARDNAME": Handoff done successfully.\n"));
1454 } else if (status & IM_RX_OVRN_INT ) {
1455 dev->stats.rx_errors++;
1456 dev->stats.rx_fifo_errors++;
1457 outb( IM_RX_OVRN_INT, ioaddr + INTERRUPT );
1458 } else if (status & IM_EPH_INT ) {
1459 PRINTK((CARDNAME ": UNSUPPORTED: EPH INTERRUPT\n"));
1460 } else if (status & IM_ERCV_INT ) {
1461 PRINTK((CARDNAME ": UNSUPPORTED: ERCV INTERRUPT\n"));
1462 outb( IM_ERCV_INT, ioaddr + INTERRUPT );
1463 }
1464 } while ( timeout -- );
1465
1466
1467 /* restore state register */
1468 SMC_SELECT_BANK( 2 );
1469 outb( mask, ioaddr + INT_MASK );
1470
1471 PRINTK3((KERN_WARNING CARDNAME ": MASK is now %x\n", mask));
1472 outw( saved_pointer, ioaddr + POINTER );
1473
1474 SMC_SELECT_BANK( saved_bank );
1475
1476 PRINTK3((CARDNAME ": Interrupt done\n"));
1477 return IRQ_RETVAL(handled);
1478}
1479
1480
1481/*----------------------------------------------------
1482 . smc_close
1483 .
1484 . this makes the board clean up everything that it can
1485 . and not talk to the outside world. Caused by
1486 . an 'ifconfig ethX down'
1487 .
1488 -----------------------------------------------------*/
1489static int smc_close(struct net_device *dev)
1490{
1491 netif_stop_queue(dev);
1492 /* clear everything */
1493 smc_shutdown( dev->base_addr );
1494
1495 /* Update the statistics here. */
1496 return 0;
1497}
1498
1499/*-----------------------------------------------------------
1500 . smc_set_multicast_list
1501 .
1502 . This routine will, depending on the values passed to it,
1503 . either make it accept multicast packets, go into
1504 . promiscuous mode ( for TCPDUMP and cousins ) or accept
1505 . a select set of multicast packets
1506*/
1507static void smc_set_multicast_list(struct net_device *dev)
1508{
1509 short ioaddr = dev->base_addr;
1510
1511 SMC_SELECT_BANK(0);
1512 if ( dev->flags & IFF_PROMISC )
1513 outw( inw(ioaddr + RCR ) | RCR_PROMISC, ioaddr + RCR );
1514
1515/* BUG? I never disable promiscuous mode if multicasting was turned on.
1516 Now, I turn off promiscuous mode, but I don't do anything to multicasting
1517 when promiscuous mode is turned on.
1518*/
1519
1520 /* Here, I am setting this to accept all multicast packets.
1521 I don't need to zero the multicast table, because the flag is
1522 checked before the table is
1523 */
1524 else if (dev->flags & IFF_ALLMULTI)
1525 outw( inw(ioaddr + RCR ) | RCR_ALMUL, ioaddr + RCR );
1526
1527 /* We just get all multicast packets even if we only want them
1528 . from one source. This will be changed at some future
1529 . point. */
1530 else if (!netdev_mc_empty(dev)) {
1531 /* support hardware multicasting */
1532
1533 /* be sure I get rid of flags I might have set */
1534 outw( inw( ioaddr + RCR ) & ~(RCR_PROMISC | RCR_ALMUL),
1535 ioaddr + RCR );
1536 /* NOTE: this has to set the bank, so make sure it is the
1537 last thing called. The bank is set to zero at the top */
1538 smc_setmulticast(ioaddr, dev);
1539 }
1540 else {
1541 outw( inw( ioaddr + RCR ) & ~(RCR_PROMISC | RCR_ALMUL),
1542 ioaddr + RCR );
1543
1544 /*
1545 since I'm disabling all multicast entirely, I need to
1546 clear the multicast list
1547 */
1548 SMC_SELECT_BANK( 3 );
1549 outw( 0, ioaddr + MULTICAST1 );
1550 outw( 0, ioaddr + MULTICAST2 );
1551 outw( 0, ioaddr + MULTICAST3 );
1552 outw( 0, ioaddr + MULTICAST4 );
1553 }
1554}
1555
1556#ifdef MODULE
1557
1558static struct net_device *devSMC9194;
1559MODULE_LICENSE("GPL");
1560
1561module_param(io, int, 0);
1562module_param(irq, int, 0);
1563module_param(ifport, int, 0);
1564MODULE_PARM_DESC(io, "SMC 99194 I/O base address");
1565MODULE_PARM_DESC(irq, "SMC 99194 IRQ number");
1566MODULE_PARM_DESC(ifport, "SMC 99194 interface port (0-default, 1-TP, 2-AUI)");
1567
1568int __init init_module(void)
1569{
1570 if (io == 0)
1571 printk(KERN_WARNING
1572 CARDNAME": You shouldn't use auto-probing with insmod!\n" );
1573
1574 /* copy the parameters from insmod into the device structure */
1575 devSMC9194 = smc_init(-1);
1576 if (IS_ERR(devSMC9194))
1577 return PTR_ERR(devSMC9194);
1578 return 0;
1579}
1580
1581void __exit cleanup_module(void)
1582{
1583 unregister_netdev(devSMC9194);
1584 free_irq(devSMC9194->irq, devSMC9194);
1585 release_region(devSMC9194->base_addr, SMC_IO_EXTENT);
1586 free_netdev(devSMC9194);
1587}
1588
1589#endif /* MODULE */
diff --git a/drivers/net/ethernet/smsc/smc9194.h b/drivers/net/ethernet/smsc/smc9194.h
new file mode 100644
index 000000000000..cf69d0a5a1cb
--- /dev/null
+++ b/drivers/net/ethernet/smsc/smc9194.h
@@ -0,0 +1,241 @@
1/*------------------------------------------------------------------------
2 . smc9194.h
3 . Copyright (C) 1996 by Erik Stahlman
4 .
5 . This software may be used and distributed according to the terms
6 . of the GNU General Public License, incorporated herein by reference.
7 .
8 . This file contains register information and access macros for
9 . the SMC91xxx chipset.
10 .
11 . Information contained in this file was obtained from the SMC91C94
12 . manual from SMC. To get a copy, if you really want one, you can find
13 . information under www.smc.com in the components division.
14 . ( this thanks to advice from Donald Becker ).
15 .
16 . Authors
17 . Erik Stahlman ( erik@vt.edu )
18 .
19 . History
20 . 01/06/96 Erik Stahlman moved definitions here from main .c file
21 . 01/19/96 Erik Stahlman polished this up some, and added better
22 . error handling
23 .
24 ---------------------------------------------------------------------------*/
25#ifndef _SMC9194_H_
26#define _SMC9194_H_
27
28/* I want some simple types */
29
30typedef unsigned char byte;
31typedef unsigned short word;
32typedef unsigned long int dword;
33
34
35/* Because of bank switching, the SMC91xxx uses only 16 I/O ports */
36
37#define SMC_IO_EXTENT 16
38
39
40/*---------------------------------------------------------------
41 .
42 . A description of the SMC registers is probably in order here,
43 . although for details, the SMC datasheet is invaluable.
44 .
45 . Basically, the chip has 4 banks of registers ( 0 to 3 ), which
46 . are accessed by writing a number into the BANK_SELECT register
47 . ( I also use a SMC_SELECT_BANK macro for this ).
48 .
49 . The banks are configured so that for most purposes, bank 2 is all
50 . that is needed for simple run time tasks.
51 -----------------------------------------------------------------------*/
52
53/*
54 . Bank Select Register:
55 .
56 . yyyy yyyy 0000 00xx
57 . xx = bank number
58 . yyyy yyyy = 0x33, for identification purposes.
59*/
60#define BANK_SELECT 14
61
62/* BANK 0 */
63
64#define TCR 0 /* transmit control register */
65#define TCR_ENABLE 0x0001 /* if this is 1, we can transmit */
66#define TCR_FDUPLX 0x0800 /* receive packets sent out */
67#define TCR_STP_SQET 0x1000 /* stop transmitting if Signal quality error */
68#define TCR_MON_CNS 0x0400 /* monitors the carrier status */
69#define TCR_PAD_ENABLE 0x0080 /* pads short packets to 64 bytes */
70
71#define TCR_CLEAR 0 /* do NOTHING */
72/* the normal settings for the TCR register : */
73/* QUESTION: do I want to enable padding of short packets ? */
74#define TCR_NORMAL TCR_ENABLE
75
76
77#define EPH_STATUS 2
78#define ES_LINK_OK 0x4000 /* is the link integrity ok ? */
79
80#define RCR 4
81#define RCR_SOFTRESET 0x8000 /* resets the chip */
82#define RCR_STRIP_CRC 0x200 /* strips CRC */
83#define RCR_ENABLE 0x100 /* IFF this is set, we can receive packets */
84#define RCR_ALMUL 0x4 /* receive all multicast packets */
85#define RCR_PROMISC 0x2 /* enable promiscuous mode */
86
87/* the normal settings for the RCR register : */
88#define RCR_NORMAL (RCR_STRIP_CRC | RCR_ENABLE)
89#define RCR_CLEAR 0x0 /* set it to a base state */
90
91#define COUNTER 6
92#define MIR 8
93#define MCR 10
94/* 12 is reserved */
95
96/* BANK 1 */
97#define CONFIG 0
98#define CFG_AUI_SELECT 0x100
99#define BASE 2
100#define ADDR0 4
101#define ADDR1 6
102#define ADDR2 8
103#define GENERAL 10
104#define CONTROL 12
105#define CTL_POWERDOWN 0x2000
106#define CTL_LE_ENABLE 0x80
107#define CTL_CR_ENABLE 0x40
108#define CTL_TE_ENABLE 0x0020
109#define CTL_AUTO_RELEASE 0x0800
110#define CTL_EPROM_ACCESS 0x0003 /* high if Eprom is being read */
111
112/* BANK 2 */
113#define MMU_CMD 0
114#define MC_BUSY 1 /* only readable bit in the register */
115#define MC_NOP 0
116#define MC_ALLOC 0x20 /* or with number of 256 byte packets */
117#define MC_RESET 0x40
118#define MC_REMOVE 0x60 /* remove the current rx packet */
119#define MC_RELEASE 0x80 /* remove and release the current rx packet */
120#define MC_FREEPKT 0xA0 /* Release packet in PNR register */
121#define MC_ENQUEUE 0xC0 /* Enqueue the packet for transmit */
122
123#define PNR_ARR 2
124#define FIFO_PORTS 4
125
126#define FP_RXEMPTY 0x8000
127#define FP_TXEMPTY 0x80
128
129#define POINTER 6
130#define PTR_READ 0x2000
131#define PTR_RCV 0x8000
132#define PTR_AUTOINC 0x4000
133#define PTR_AUTO_INC 0x0040
134
135#define DATA_1 8
136#define DATA_2 10
137#define INTERRUPT 12
138
139#define INT_MASK 13
140#define IM_RCV_INT 0x1
141#define IM_TX_INT 0x2
142#define IM_TX_EMPTY_INT 0x4
143#define IM_ALLOC_INT 0x8
144#define IM_RX_OVRN_INT 0x10
145#define IM_EPH_INT 0x20
146#define IM_ERCV_INT 0x40 /* not on SMC9192 */
147
148/* BANK 3 */
149#define MULTICAST1 0
150#define MULTICAST2 2
151#define MULTICAST3 4
152#define MULTICAST4 6
153#define MGMT 8
154#define REVISION 10 /* ( hi: chip id low: rev # ) */
155
156
157/* this is NOT on SMC9192 */
158#define ERCV 12
159
160#define CHIP_9190 3
161#define CHIP_9194 4
162#define CHIP_9195 5
163#define CHIP_91100 7
164
165static const char * chip_ids[ 15 ] = {
166 NULL, NULL, NULL,
167 /* 3 */ "SMC91C90/91C92",
168 /* 4 */ "SMC91C94",
169 /* 5 */ "SMC91C95",
170 NULL,
171 /* 7 */ "SMC91C100",
172 /* 8 */ "SMC91C100FD",
173 NULL, NULL, NULL,
174 NULL, NULL, NULL};
175
176/*
177 . Transmit status bits
178*/
179#define TS_SUCCESS 0x0001
180#define TS_LOSTCAR 0x0400
181#define TS_LATCOL 0x0200
182#define TS_16COL 0x0010
183
184/*
185 . Receive status bits
186*/
187#define RS_ALGNERR 0x8000
188#define RS_BADCRC 0x2000
189#define RS_ODDFRAME 0x1000
190#define RS_TOOLONG 0x0800
191#define RS_TOOSHORT 0x0400
192#define RS_MULTICAST 0x0001
193#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
194
195static const char * interfaces[ 2 ] = { "TP", "AUI" };
196
197/*-------------------------------------------------------------------------
198 . I define some macros to make it easier to do somewhat common
199 . or slightly complicated, repeated tasks.
200 --------------------------------------------------------------------------*/
201
202/* select a register bank, 0 to 3 */
203
204#define SMC_SELECT_BANK(x) { outw( x, ioaddr + BANK_SELECT ); }
205
206/* define a small delay for the reset */
207#define SMC_DELAY() { inw( ioaddr + RCR );\
208 inw( ioaddr + RCR );\
209 inw( ioaddr + RCR ); }
210
211/* this enables an interrupt in the interrupt mask register */
212#define SMC_ENABLE_INT(x) {\
213 unsigned char mask;\
214 SMC_SELECT_BANK(2);\
215 mask = inb( ioaddr + INT_MASK );\
216 mask |= (x);\
217 outb( mask, ioaddr + INT_MASK ); \
218}
219
220/* this disables an interrupt from the interrupt mask register */
221
222#define SMC_DISABLE_INT(x) {\
223 unsigned char mask;\
224 SMC_SELECT_BANK(2);\
225 mask = inb( ioaddr + INT_MASK );\
226 mask &= ~(x);\
227 outb( mask, ioaddr + INT_MASK ); \
228}
229
230/*----------------------------------------------------------------------
231 . Define the interrupts that I want to receive from the card
232 .
233 . I want:
234 . IM_EPH_INT, for nasty errors
235 . IM_RCV_INT, for happy received packets
236 . IM_RX_OVRN_INT, because I have to kick the receiver
237 --------------------------------------------------------------------------*/
238#define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT)
239
240#endif /* _SMC_9194_H_ */
241
diff --git a/drivers/net/ethernet/smsc/smc91c92_cs.c b/drivers/net/ethernet/smsc/smc91c92_cs.c
new file mode 100644
index 000000000000..cffbc0373fa9
--- /dev/null
+++ b/drivers/net/ethernet/smsc/smc91c92_cs.c
@@ -0,0 +1,2070 @@
1/*======================================================================
2
3 A PCMCIA ethernet driver for SMC91c92-based cards.
4
5 This driver supports Megahertz PCMCIA ethernet cards; and
6 Megahertz, Motorola, Ositech, and Psion Dacom ethernet/modem
7 multifunction cards.
8
9 Copyright (C) 1999 David A. Hinds -- dahinds@users.sourceforge.net
10
11 smc91c92_cs.c 1.122 2002/10/25 06:26:39
12
13 This driver contains code written by Donald Becker
14 (becker@scyld.com), Rowan Hughes (x-csrdh@jcu.edu.au),
15 David Hinds (dahinds@users.sourceforge.net), and Erik Stahlman
16 (erik@vt.edu). Donald wrote the SMC 91c92 code using parts of
17 Erik's SMC 91c94 driver. Rowan wrote a similar driver, and I've
18 incorporated some parts of his driver here. I (Dave) wrote most
19 of the PCMCIA glue code, and the Ositech support code. Kelly
20 Stephens (kstephen@holli.com) added support for the Motorola
21 Mariner, with help from Allen Brost.
22
23 This software may be used and distributed according to the terms of
24 the GNU General Public License, incorporated herein by reference.
25
26======================================================================*/
27
28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/init.h>
33#include <linux/slab.h>
34#include <linux/string.h>
35#include <linux/timer.h>
36#include <linux/interrupt.h>
37#include <linux/delay.h>
38#include <linux/crc32.h>
39#include <linux/netdevice.h>
40#include <linux/etherdevice.h>
41#include <linux/skbuff.h>
42#include <linux/if_arp.h>
43#include <linux/ioport.h>
44#include <linux/ethtool.h>
45#include <linux/mii.h>
46#include <linux/jiffies.h>
47#include <linux/firmware.h>
48
49#include <pcmcia/cistpl.h>
50#include <pcmcia/cisreg.h>
51#include <pcmcia/ciscode.h>
52#include <pcmcia/ds.h>
53#include <pcmcia/ss.h>
54
55#include <asm/io.h>
56#include <asm/system.h>
57#include <asm/uaccess.h>
58
59/*====================================================================*/
60
61static const char *if_names[] = { "auto", "10baseT", "10base2"};
62
63/* Firmware name */
64#define FIRMWARE_NAME "ositech/Xilinx7OD.bin"
65
66/* Module parameters */
67
68MODULE_DESCRIPTION("SMC 91c92 series PCMCIA ethernet driver");
69MODULE_LICENSE("GPL");
70MODULE_FIRMWARE(FIRMWARE_NAME);
71
72#define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
73
74/*
75 Transceiver/media type.
76 0 = auto
77 1 = 10baseT (and autoselect if #define AUTOSELECT),
78 2 = AUI/10base2,
79*/
80INT_MODULE_PARM(if_port, 0);
81
82
83#define DRV_NAME "smc91c92_cs"
84#define DRV_VERSION "1.123"
85
86/*====================================================================*/
87
88/* Operational parameter that usually are not changed. */
89
90/* Time in jiffies before concluding Tx hung */
91#define TX_TIMEOUT ((400*HZ)/1000)
92
93/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
94#define INTR_WORK 4
95
96/* Times to check the check the chip before concluding that it doesn't
97 currently have room for another Tx packet. */
98#define MEMORY_WAIT_TIME 8
99
100struct smc_private {
101 struct pcmcia_device *p_dev;
102 spinlock_t lock;
103 u_short manfid;
104 u_short cardid;
105
106 struct sk_buff *saved_skb;
107 int packets_waiting;
108 void __iomem *base;
109 u_short cfg;
110 struct timer_list media;
111 int watchdog, tx_err;
112 u_short media_status;
113 u_short fast_poll;
114 u_short link_status;
115 struct mii_if_info mii_if;
116 int duplex;
117 int rx_ovrn;
118};
119
120/* Special definitions for Megahertz multifunction cards */
121#define MEGAHERTZ_ISR 0x0380
122
123/* Special function registers for Motorola Mariner */
124#define MOT_LAN 0x0000
125#define MOT_UART 0x0020
126#define MOT_EEPROM 0x20
127
128#define MOT_NORMAL \
129(COR_LEVEL_REQ | COR_FUNC_ENA | COR_ADDR_DECODE | COR_IREQ_ENA)
130
131/* Special function registers for Ositech cards */
132#define OSITECH_AUI_CTL 0x0c
133#define OSITECH_PWRDOWN 0x0d
134#define OSITECH_RESET 0x0e
135#define OSITECH_ISR 0x0f
136#define OSITECH_AUI_PWR 0x0c
137#define OSITECH_RESET_ISR 0x0e
138
139#define OSI_AUI_PWR 0x40
140#define OSI_LAN_PWRDOWN 0x02
141#define OSI_MODEM_PWRDOWN 0x01
142#define OSI_LAN_RESET 0x02
143#define OSI_MODEM_RESET 0x01
144
145/* Symbolic constants for the SMC91c9* series chips, from Erik Stahlman. */
146#define BANK_SELECT 14 /* Window select register. */
147#define SMC_SELECT_BANK(x) { outw(x, ioaddr + BANK_SELECT); }
148
149/* Bank 0 registers. */
150#define TCR 0 /* transmit control register */
151#define TCR_CLEAR 0 /* do NOTHING */
152#define TCR_ENABLE 0x0001 /* if this is 1, we can transmit */
153#define TCR_PAD_EN 0x0080 /* pads short packets to 64 bytes */
154#define TCR_MONCSN 0x0400 /* Monitor Carrier. */
155#define TCR_FDUPLX 0x0800 /* Full duplex mode. */
156#define TCR_NORMAL TCR_ENABLE | TCR_PAD_EN
157
158#define EPH 2 /* Ethernet Protocol Handler report. */
159#define EPH_TX_SUC 0x0001
160#define EPH_SNGLCOL 0x0002
161#define EPH_MULCOL 0x0004
162#define EPH_LTX_MULT 0x0008
163#define EPH_16COL 0x0010
164#define EPH_SQET 0x0020
165#define EPH_LTX_BRD 0x0040
166#define EPH_TX_DEFR 0x0080
167#define EPH_LAT_COL 0x0200
168#define EPH_LOST_CAR 0x0400
169#define EPH_EXC_DEF 0x0800
170#define EPH_CTR_ROL 0x1000
171#define EPH_RX_OVRN 0x2000
172#define EPH_LINK_OK 0x4000
173#define EPH_TX_UNRN 0x8000
174#define MEMINFO 8 /* Memory Information Register */
175#define MEMCFG 10 /* Memory Configuration Register */
176
177/* Bank 1 registers. */
178#define CONFIG 0
179#define CFG_MII_SELECT 0x8000 /* 91C100 only */
180#define CFG_NO_WAIT 0x1000
181#define CFG_FULL_STEP 0x0400
182#define CFG_SET_SQLCH 0x0200
183#define CFG_AUI_SELECT 0x0100
184#define CFG_16BIT 0x0080
185#define CFG_DIS_LINK 0x0040
186#define CFG_STATIC 0x0030
187#define CFG_IRQ_SEL_1 0x0004
188#define CFG_IRQ_SEL_0 0x0002
189#define BASE_ADDR 2
190#define ADDR0 4
191#define GENERAL 10
192#define CONTROL 12
193#define CTL_STORE 0x0001
194#define CTL_RELOAD 0x0002
195#define CTL_EE_SELECT 0x0004
196#define CTL_TE_ENABLE 0x0020
197#define CTL_CR_ENABLE 0x0040
198#define CTL_LE_ENABLE 0x0080
199#define CTL_AUTO_RELEASE 0x0800
200#define CTL_POWERDOWN 0x2000
201
202/* Bank 2 registers. */
203#define MMU_CMD 0
204#define MC_ALLOC 0x20 /* or with number of 256 byte packets */
205#define MC_RESET 0x40
206#define MC_RELEASE 0x80 /* remove and release the current rx packet */
207#define MC_FREEPKT 0xA0 /* Release packet in PNR register */
208#define MC_ENQUEUE 0xC0 /* Enqueue the packet for transmit */
209#define PNR_ARR 2
210#define FIFO_PORTS 4
211#define FP_RXEMPTY 0x8000
212#define POINTER 6
213#define PTR_AUTO_INC 0x0040
214#define PTR_READ 0x2000
215#define PTR_AUTOINC 0x4000
216#define PTR_RCV 0x8000
217#define DATA_1 8
218#define INTERRUPT 12
219#define IM_RCV_INT 0x1
220#define IM_TX_INT 0x2
221#define IM_TX_EMPTY_INT 0x4
222#define IM_ALLOC_INT 0x8
223#define IM_RX_OVRN_INT 0x10
224#define IM_EPH_INT 0x20
225
226#define RCR 4
227enum RxCfg { RxAllMulti = 0x0004, RxPromisc = 0x0002,
228 RxEnable = 0x0100, RxStripCRC = 0x0200};
229#define RCR_SOFTRESET 0x8000 /* resets the chip */
230#define RCR_STRIP_CRC 0x200 /* strips CRC */
231#define RCR_ENABLE 0x100 /* IFF this is set, we can receive packets */
232#define RCR_ALMUL 0x4 /* receive all multicast packets */
233#define RCR_PROMISC 0x2 /* enable promiscuous mode */
234
235/* the normal settings for the RCR register : */
236#define RCR_NORMAL (RCR_STRIP_CRC | RCR_ENABLE)
237#define RCR_CLEAR 0x0 /* set it to a base state */
238#define COUNTER 6
239
240/* BANK 3 -- not the same values as in smc9194! */
241#define MULTICAST0 0
242#define MULTICAST2 2
243#define MULTICAST4 4
244#define MULTICAST6 6
245#define MGMT 8
246#define REVISION 0x0a
247
248/* Transmit status bits. */
249#define TS_SUCCESS 0x0001
250#define TS_16COL 0x0010
251#define TS_LATCOL 0x0200
252#define TS_LOSTCAR 0x0400
253
254/* Receive status bits. */
255#define RS_ALGNERR 0x8000
256#define RS_BADCRC 0x2000
257#define RS_ODDFRAME 0x1000
258#define RS_TOOLONG 0x0800
259#define RS_TOOSHORT 0x0400
260#define RS_MULTICAST 0x0001
261#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
262
263#define set_bits(v, p) outw(inw(p)|(v), (p))
264#define mask_bits(v, p) outw(inw(p)&(v), (p))
265
266/*====================================================================*/
267
268static void smc91c92_detach(struct pcmcia_device *p_dev);
269static int smc91c92_config(struct pcmcia_device *link);
270static void smc91c92_release(struct pcmcia_device *link);
271
272static int smc_open(struct net_device *dev);
273static int smc_close(struct net_device *dev);
274static int smc_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
275static void smc_tx_timeout(struct net_device *dev);
276static netdev_tx_t smc_start_xmit(struct sk_buff *skb,
277 struct net_device *dev);
278static irqreturn_t smc_interrupt(int irq, void *dev_id);
279static void smc_rx(struct net_device *dev);
280static void set_rx_mode(struct net_device *dev);
281static int s9k_config(struct net_device *dev, struct ifmap *map);
282static void smc_set_xcvr(struct net_device *dev, int if_port);
283static void smc_reset(struct net_device *dev);
284static void media_check(u_long arg);
285static void mdio_sync(unsigned int addr);
286static int mdio_read(struct net_device *dev, int phy_id, int loc);
287static void mdio_write(struct net_device *dev, int phy_id, int loc, int value);
288static int smc_link_ok(struct net_device *dev);
289static const struct ethtool_ops ethtool_ops;
290
291static const struct net_device_ops smc_netdev_ops = {
292 .ndo_open = smc_open,
293 .ndo_stop = smc_close,
294 .ndo_start_xmit = smc_start_xmit,
295 .ndo_tx_timeout = smc_tx_timeout,
296 .ndo_set_config = s9k_config,
297 .ndo_set_multicast_list = set_rx_mode,
298 .ndo_do_ioctl = smc_ioctl,
299 .ndo_change_mtu = eth_change_mtu,
300 .ndo_set_mac_address = eth_mac_addr,
301 .ndo_validate_addr = eth_validate_addr,
302};
303
304static int smc91c92_probe(struct pcmcia_device *link)
305{
306 struct smc_private *smc;
307 struct net_device *dev;
308
309 dev_dbg(&link->dev, "smc91c92_attach()\n");
310
311 /* Create new ethernet device */
312 dev = alloc_etherdev(sizeof(struct smc_private));
313 if (!dev)
314 return -ENOMEM;
315 smc = netdev_priv(dev);
316 smc->p_dev = link;
317 link->priv = dev;
318
319 spin_lock_init(&smc->lock);
320
321 /* The SMC91c92-specific entries in the device structure. */
322 dev->netdev_ops = &smc_netdev_ops;
323 SET_ETHTOOL_OPS(dev, &ethtool_ops);
324 dev->watchdog_timeo = TX_TIMEOUT;
325
326 smc->mii_if.dev = dev;
327 smc->mii_if.mdio_read = mdio_read;
328 smc->mii_if.mdio_write = mdio_write;
329 smc->mii_if.phy_id_mask = 0x1f;
330 smc->mii_if.reg_num_mask = 0x1f;
331
332 return smc91c92_config(link);
333} /* smc91c92_attach */
334
335static void smc91c92_detach(struct pcmcia_device *link)
336{
337 struct net_device *dev = link->priv;
338
339 dev_dbg(&link->dev, "smc91c92_detach\n");
340
341 unregister_netdev(dev);
342
343 smc91c92_release(link);
344
345 free_netdev(dev);
346} /* smc91c92_detach */
347
348/*====================================================================*/
349
350static int cvt_ascii_address(struct net_device *dev, char *s)
351{
352 int i, j, da, c;
353
354 if (strlen(s) != 12)
355 return -1;
356 for (i = 0; i < 6; i++) {
357 da = 0;
358 for (j = 0; j < 2; j++) {
359 c = *s++;
360 da <<= 4;
361 da += ((c >= '0') && (c <= '9')) ?
362 (c - '0') : ((c & 0x0f) + 9);
363 }
364 dev->dev_addr[i] = da;
365 }
366 return 0;
367}
368
369/*====================================================================
370
371 Configuration stuff for Megahertz cards
372
373 mhz_3288_power() is used to power up a 3288's ethernet chip.
374 mhz_mfc_config() handles socket setup for multifunction (1144
375 and 3288) cards. mhz_setup() gets a card's hardware ethernet
376 address.
377
378======================================================================*/
379
380static int mhz_3288_power(struct pcmcia_device *link)
381{
382 struct net_device *dev = link->priv;
383 struct smc_private *smc = netdev_priv(dev);
384 u_char tmp;
385
386 /* Read the ISR twice... */
387 readb(smc->base+MEGAHERTZ_ISR);
388 udelay(5);
389 readb(smc->base+MEGAHERTZ_ISR);
390
391 /* Pause 200ms... */
392 mdelay(200);
393
394 /* Now read and write the COR... */
395 tmp = readb(smc->base + link->config_base + CISREG_COR);
396 udelay(5);
397 writeb(tmp, smc->base + link->config_base + CISREG_COR);
398
399 return 0;
400}
401
402static int mhz_mfc_config_check(struct pcmcia_device *p_dev, void *priv_data)
403{
404 int k;
405 p_dev->io_lines = 16;
406 p_dev->resource[1]->start = p_dev->resource[0]->start;
407 p_dev->resource[1]->end = 8;
408 p_dev->resource[1]->flags &= ~IO_DATA_PATH_WIDTH;
409 p_dev->resource[1]->flags |= IO_DATA_PATH_WIDTH_8;
410 p_dev->resource[0]->end = 16;
411 p_dev->resource[0]->flags &= ~IO_DATA_PATH_WIDTH;
412 p_dev->resource[0]->flags |= IO_DATA_PATH_WIDTH_AUTO;
413 for (k = 0; k < 0x400; k += 0x10) {
414 if (k & 0x80)
415 continue;
416 p_dev->resource[0]->start = k ^ 0x300;
417 if (!pcmcia_request_io(p_dev))
418 return 0;
419 }
420 return -ENODEV;
421}
422
423static int mhz_mfc_config(struct pcmcia_device *link)
424{
425 struct net_device *dev = link->priv;
426 struct smc_private *smc = netdev_priv(dev);
427 unsigned int offset;
428 int i;
429
430 link->config_flags |= CONF_ENABLE_SPKR | CONF_ENABLE_IRQ |
431 CONF_AUTO_SET_IO;
432
433 /* The Megahertz combo cards have modem-like CIS entries, so
434 we have to explicitly try a bunch of port combinations. */
435 if (pcmcia_loop_config(link, mhz_mfc_config_check, NULL))
436 return -ENODEV;
437
438 dev->base_addr = link->resource[0]->start;
439
440 /* Allocate a memory window, for accessing the ISR */
441 link->resource[2]->flags = WIN_DATA_WIDTH_8|WIN_MEMORY_TYPE_AM|WIN_ENABLE;
442 link->resource[2]->start = link->resource[2]->end = 0;
443 i = pcmcia_request_window(link, link->resource[2], 0);
444 if (i != 0)
445 return -ENODEV;
446
447 smc->base = ioremap(link->resource[2]->start,
448 resource_size(link->resource[2]));
449 offset = (smc->manfid == MANFID_MOTOROLA) ? link->config_base : 0;
450 i = pcmcia_map_mem_page(link, link->resource[2], offset);
451 if ((i == 0) &&
452 (smc->manfid == MANFID_MEGAHERTZ) &&
453 (smc->cardid == PRODID_MEGAHERTZ_EM3288))
454 mhz_3288_power(link);
455
456 return 0;
457}
458
459static int pcmcia_get_versmac(struct pcmcia_device *p_dev,
460 tuple_t *tuple,
461 void *priv)
462{
463 struct net_device *dev = priv;
464 cisparse_t parse;
465 u8 *buf;
466
467 if (pcmcia_parse_tuple(tuple, &parse))
468 return -EINVAL;
469
470 buf = parse.version_1.str + parse.version_1.ofs[3];
471
472 if ((parse.version_1.ns > 3) && (cvt_ascii_address(dev, buf) == 0))
473 return 0;
474
475 return -EINVAL;
476};
477
478static int mhz_setup(struct pcmcia_device *link)
479{
480 struct net_device *dev = link->priv;
481 size_t len;
482 u8 *buf;
483 int rc;
484
485 /* Read the station address from the CIS. It is stored as the last
486 (fourth) string in the Version 1 Version/ID tuple. */
487 if ((link->prod_id[3]) &&
488 (cvt_ascii_address(dev, link->prod_id[3]) == 0))
489 return 0;
490
491 /* Workarounds for broken cards start here. */
492 /* Ugh -- the EM1144 card has two VERS_1 tuples!?! */
493 if (!pcmcia_loop_tuple(link, CISTPL_VERS_1, pcmcia_get_versmac, dev))
494 return 0;
495
496 /* Another possibility: for the EM3288, in a special tuple */
497 rc = -1;
498 len = pcmcia_get_tuple(link, 0x81, &buf);
499 if (buf && len >= 13) {
500 buf[12] = '\0';
501 if (cvt_ascii_address(dev, buf) == 0)
502 rc = 0;
503 }
504 kfree(buf);
505
506 return rc;
507};
508
509/*======================================================================
510
511 Configuration stuff for the Motorola Mariner
512
513 mot_config() writes directly to the Mariner configuration
514 registers because the CIS is just bogus.
515
516======================================================================*/
517
518static void mot_config(struct pcmcia_device *link)
519{
520 struct net_device *dev = link->priv;
521 struct smc_private *smc = netdev_priv(dev);
522 unsigned int ioaddr = dev->base_addr;
523 unsigned int iouart = link->resource[1]->start;
524
525 /* Set UART base address and force map with COR bit 1 */
526 writeb(iouart & 0xff, smc->base + MOT_UART + CISREG_IOBASE_0);
527 writeb((iouart >> 8) & 0xff, smc->base + MOT_UART + CISREG_IOBASE_1);
528 writeb(MOT_NORMAL, smc->base + MOT_UART + CISREG_COR);
529
530 /* Set SMC base address and force map with COR bit 1 */
531 writeb(ioaddr & 0xff, smc->base + MOT_LAN + CISREG_IOBASE_0);
532 writeb((ioaddr >> 8) & 0xff, smc->base + MOT_LAN + CISREG_IOBASE_1);
533 writeb(MOT_NORMAL, smc->base + MOT_LAN + CISREG_COR);
534
535 /* Wait for things to settle down */
536 mdelay(100);
537}
538
539static int mot_setup(struct pcmcia_device *link)
540{
541 struct net_device *dev = link->priv;
542 unsigned int ioaddr = dev->base_addr;
543 int i, wait, loop;
544 u_int addr;
545
546 /* Read Ethernet address from Serial EEPROM */
547
548 for (i = 0; i < 3; i++) {
549 SMC_SELECT_BANK(2);
550 outw(MOT_EEPROM + i, ioaddr + POINTER);
551 SMC_SELECT_BANK(1);
552 outw((CTL_RELOAD | CTL_EE_SELECT), ioaddr + CONTROL);
553
554 for (loop = wait = 0; loop < 200; loop++) {
555 udelay(10);
556 wait = ((CTL_RELOAD | CTL_STORE) & inw(ioaddr + CONTROL));
557 if (wait == 0) break;
558 }
559
560 if (wait)
561 return -1;
562
563 addr = inw(ioaddr + GENERAL);
564 dev->dev_addr[2*i] = addr & 0xff;
565 dev->dev_addr[2*i+1] = (addr >> 8) & 0xff;
566 }
567
568 return 0;
569}
570
571/*====================================================================*/
572
573static int smc_configcheck(struct pcmcia_device *p_dev, void *priv_data)
574{
575 p_dev->resource[0]->end = 16;
576 p_dev->resource[0]->flags &= ~IO_DATA_PATH_WIDTH;
577 p_dev->resource[0]->flags |= IO_DATA_PATH_WIDTH_AUTO;
578
579 return pcmcia_request_io(p_dev);
580}
581
582static int smc_config(struct pcmcia_device *link)
583{
584 struct net_device *dev = link->priv;
585 int i;
586
587 link->config_flags |= CONF_ENABLE_IRQ | CONF_AUTO_SET_IO;
588
589 i = pcmcia_loop_config(link, smc_configcheck, NULL);
590 if (!i)
591 dev->base_addr = link->resource[0]->start;
592
593 return i;
594}
595
596
597static int smc_setup(struct pcmcia_device *link)
598{
599 struct net_device *dev = link->priv;
600
601 /* Check for a LAN function extension tuple */
602 if (!pcmcia_get_mac_from_cis(link, dev))
603 return 0;
604
605 /* Try the third string in the Version 1 Version/ID tuple. */
606 if (link->prod_id[2]) {
607 if (cvt_ascii_address(dev, link->prod_id[2]) == 0)
608 return 0;
609 }
610 return -1;
611}
612
613/*====================================================================*/
614
615static int osi_config(struct pcmcia_device *link)
616{
617 struct net_device *dev = link->priv;
618 static const unsigned int com[4] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
619 int i, j;
620
621 link->config_flags |= CONF_ENABLE_SPKR | CONF_ENABLE_IRQ;
622 link->resource[0]->end = 64;
623 link->resource[1]->flags |= IO_DATA_PATH_WIDTH_8;
624 link->resource[1]->end = 8;
625
626 /* Enable Hard Decode, LAN, Modem */
627 link->io_lines = 16;
628 link->config_index = 0x23;
629
630 for (i = j = 0; j < 4; j++) {
631 link->resource[1]->start = com[j];
632 i = pcmcia_request_io(link);
633 if (i == 0)
634 break;
635 }
636 if (i != 0) {
637 /* Fallback: turn off hard decode */
638 link->config_index = 0x03;
639 link->resource[1]->end = 0;
640 i = pcmcia_request_io(link);
641 }
642 dev->base_addr = link->resource[0]->start + 0x10;
643 return i;
644}
645
646static int osi_load_firmware(struct pcmcia_device *link)
647{
648 const struct firmware *fw;
649 int i, err;
650
651 err = request_firmware(&fw, FIRMWARE_NAME, &link->dev);
652 if (err) {
653 pr_err("Failed to load firmware \"%s\"\n", FIRMWARE_NAME);
654 return err;
655 }
656
657 /* Download the Seven of Diamonds firmware */
658 for (i = 0; i < fw->size; i++) {
659 outb(fw->data[i], link->resource[0]->start + 2);
660 udelay(50);
661 }
662 release_firmware(fw);
663 return err;
664}
665
666static int pcmcia_osi_mac(struct pcmcia_device *p_dev,
667 tuple_t *tuple,
668 void *priv)
669{
670 struct net_device *dev = priv;
671 int i;
672
673 if (tuple->TupleDataLen < 8)
674 return -EINVAL;
675 if (tuple->TupleData[0] != 0x04)
676 return -EINVAL;
677 for (i = 0; i < 6; i++)
678 dev->dev_addr[i] = tuple->TupleData[i+2];
679 return 0;
680};
681
682
683static int osi_setup(struct pcmcia_device *link, u_short manfid, u_short cardid)
684{
685 struct net_device *dev = link->priv;
686 int rc;
687
688 /* Read the station address from tuple 0x90, subtuple 0x04 */
689 if (pcmcia_loop_tuple(link, 0x90, pcmcia_osi_mac, dev))
690 return -1;
691
692 if (((manfid == MANFID_OSITECH) &&
693 (cardid == PRODID_OSITECH_SEVEN)) ||
694 ((manfid == MANFID_PSION) &&
695 (cardid == PRODID_PSION_NET100))) {
696 rc = osi_load_firmware(link);
697 if (rc)
698 return rc;
699 } else if (manfid == MANFID_OSITECH) {
700 /* Make sure both functions are powered up */
701 set_bits(0x300, link->resource[0]->start + OSITECH_AUI_PWR);
702 /* Now, turn on the interrupt for both card functions */
703 set_bits(0x300, link->resource[0]->start + OSITECH_RESET_ISR);
704 dev_dbg(&link->dev, "AUI/PWR: %4.4x RESET/ISR: %4.4x\n",
705 inw(link->resource[0]->start + OSITECH_AUI_PWR),
706 inw(link->resource[0]->start + OSITECH_RESET_ISR));
707 }
708 return 0;
709}
710
711static int smc91c92_suspend(struct pcmcia_device *link)
712{
713 struct net_device *dev = link->priv;
714
715 if (link->open)
716 netif_device_detach(dev);
717
718 return 0;
719}
720
721static int smc91c92_resume(struct pcmcia_device *link)
722{
723 struct net_device *dev = link->priv;
724 struct smc_private *smc = netdev_priv(dev);
725 int i;
726
727 if ((smc->manfid == MANFID_MEGAHERTZ) &&
728 (smc->cardid == PRODID_MEGAHERTZ_EM3288))
729 mhz_3288_power(link);
730 if (smc->manfid == MANFID_MOTOROLA)
731 mot_config(link);
732 if ((smc->manfid == MANFID_OSITECH) &&
733 (smc->cardid != PRODID_OSITECH_SEVEN)) {
734 /* Power up the card and enable interrupts */
735 set_bits(0x0300, dev->base_addr-0x10+OSITECH_AUI_PWR);
736 set_bits(0x0300, dev->base_addr-0x10+OSITECH_RESET_ISR);
737 }
738 if (((smc->manfid == MANFID_OSITECH) &&
739 (smc->cardid == PRODID_OSITECH_SEVEN)) ||
740 ((smc->manfid == MANFID_PSION) &&
741 (smc->cardid == PRODID_PSION_NET100))) {
742 i = osi_load_firmware(link);
743 if (i) {
744 pr_err("smc91c92_cs: Failed to load firmware\n");
745 return i;
746 }
747 }
748 if (link->open) {
749 smc_reset(dev);
750 netif_device_attach(dev);
751 }
752
753 return 0;
754}
755
756
757/*======================================================================
758
759 This verifies that the chip is some SMC91cXX variant, and returns
760 the revision code if successful. Otherwise, it returns -ENODEV.
761
762======================================================================*/
763
764static int check_sig(struct pcmcia_device *link)
765{
766 struct net_device *dev = link->priv;
767 unsigned int ioaddr = dev->base_addr;
768 int width;
769 u_short s;
770
771 SMC_SELECT_BANK(1);
772 if (inw(ioaddr + BANK_SELECT) >> 8 != 0x33) {
773 /* Try powering up the chip */
774 outw(0, ioaddr + CONTROL);
775 mdelay(55);
776 }
777
778 /* Try setting bus width */
779 width = (link->resource[0]->flags == IO_DATA_PATH_WIDTH_AUTO);
780 s = inb(ioaddr + CONFIG);
781 if (width)
782 s |= CFG_16BIT;
783 else
784 s &= ~CFG_16BIT;
785 outb(s, ioaddr + CONFIG);
786
787 /* Check Base Address Register to make sure bus width is OK */
788 s = inw(ioaddr + BASE_ADDR);
789 if ((inw(ioaddr + BANK_SELECT) >> 8 == 0x33) &&
790 ((s >> 8) != (s & 0xff))) {
791 SMC_SELECT_BANK(3);
792 s = inw(ioaddr + REVISION);
793 return s & 0xff;
794 }
795
796 if (width) {
797 pr_info("using 8-bit IO window\n");
798
799 smc91c92_suspend(link);
800 pcmcia_fixup_iowidth(link);
801 smc91c92_resume(link);
802 return check_sig(link);
803 }
804 return -ENODEV;
805}
806
807static int smc91c92_config(struct pcmcia_device *link)
808{
809 struct net_device *dev = link->priv;
810 struct smc_private *smc = netdev_priv(dev);
811 char *name;
812 int i, rev, j = 0;
813 unsigned int ioaddr;
814 u_long mir;
815
816 dev_dbg(&link->dev, "smc91c92_config\n");
817
818 smc->manfid = link->manf_id;
819 smc->cardid = link->card_id;
820
821 if ((smc->manfid == MANFID_OSITECH) &&
822 (smc->cardid != PRODID_OSITECH_SEVEN)) {
823 i = osi_config(link);
824 } else if ((smc->manfid == MANFID_MOTOROLA) ||
825 ((smc->manfid == MANFID_MEGAHERTZ) &&
826 ((smc->cardid == PRODID_MEGAHERTZ_VARIOUS) ||
827 (smc->cardid == PRODID_MEGAHERTZ_EM3288)))) {
828 i = mhz_mfc_config(link);
829 } else {
830 i = smc_config(link);
831 }
832 if (i)
833 goto config_failed;
834
835 i = pcmcia_request_irq(link, smc_interrupt);
836 if (i)
837 goto config_failed;
838 i = pcmcia_enable_device(link);
839 if (i)
840 goto config_failed;
841
842 if (smc->manfid == MANFID_MOTOROLA)
843 mot_config(link);
844
845 dev->irq = link->irq;
846
847 if ((if_port >= 0) && (if_port <= 2))
848 dev->if_port = if_port;
849 else
850 dev_notice(&link->dev, "invalid if_port requested\n");
851
852 switch (smc->manfid) {
853 case MANFID_OSITECH:
854 case MANFID_PSION:
855 i = osi_setup(link, smc->manfid, smc->cardid); break;
856 case MANFID_SMC:
857 case MANFID_NEW_MEDIA:
858 i = smc_setup(link); break;
859 case 0x128: /* For broken Megahertz cards */
860 case MANFID_MEGAHERTZ:
861 i = mhz_setup(link); break;
862 case MANFID_MOTOROLA:
863 default: /* get the hw address from EEPROM */
864 i = mot_setup(link); break;
865 }
866
867 if (i != 0) {
868 dev_notice(&link->dev, "Unable to find hardware address.\n");
869 goto config_failed;
870 }
871
872 smc->duplex = 0;
873 smc->rx_ovrn = 0;
874
875 rev = check_sig(link);
876 name = "???";
877 if (rev > 0)
878 switch (rev >> 4) {
879 case 3: name = "92"; break;
880 case 4: name = ((rev & 15) >= 6) ? "96" : "94"; break;
881 case 5: name = "95"; break;
882 case 7: name = "100"; break;
883 case 8: name = "100-FD"; break;
884 case 9: name = "110"; break;
885 }
886
887 ioaddr = dev->base_addr;
888 if (rev > 0) {
889 u_long mcr;
890 SMC_SELECT_BANK(0);
891 mir = inw(ioaddr + MEMINFO) & 0xff;
892 if (mir == 0xff) mir++;
893 /* Get scale factor for memory size */
894 mcr = ((rev >> 4) > 3) ? inw(ioaddr + MEMCFG) : 0x0200;
895 mir *= 128 * (1<<((mcr >> 9) & 7));
896 SMC_SELECT_BANK(1);
897 smc->cfg = inw(ioaddr + CONFIG) & ~CFG_AUI_SELECT;
898 smc->cfg |= CFG_NO_WAIT | CFG_16BIT | CFG_STATIC;
899 if (smc->manfid == MANFID_OSITECH)
900 smc->cfg |= CFG_IRQ_SEL_1 | CFG_IRQ_SEL_0;
901 if ((rev >> 4) >= 7)
902 smc->cfg |= CFG_MII_SELECT;
903 } else
904 mir = 0;
905
906 if (smc->cfg & CFG_MII_SELECT) {
907 SMC_SELECT_BANK(3);
908
909 for (i = 0; i < 32; i++) {
910 j = mdio_read(dev, i, 1);
911 if ((j != 0) && (j != 0xffff)) break;
912 }
913 smc->mii_if.phy_id = (i < 32) ? i : -1;
914
915 SMC_SELECT_BANK(0);
916 }
917
918 SET_NETDEV_DEV(dev, &link->dev);
919
920 if (register_netdev(dev) != 0) {
921 dev_err(&link->dev, "register_netdev() failed\n");
922 goto config_undo;
923 }
924
925 netdev_info(dev, "smc91c%s rev %d: io %#3lx, irq %d, hw_addr %pM\n",
926 name, (rev & 0x0f), dev->base_addr, dev->irq, dev->dev_addr);
927
928 if (rev > 0) {
929 if (mir & 0x3ff)
930 netdev_info(dev, " %lu byte", mir);
931 else
932 netdev_info(dev, " %lu kb", mir>>10);
933 pr_cont(" buffer, %s xcvr\n",
934 (smc->cfg & CFG_MII_SELECT) ? "MII" : if_names[dev->if_port]);
935 }
936
937 if (smc->cfg & CFG_MII_SELECT) {
938 if (smc->mii_if.phy_id != -1) {
939 netdev_dbg(dev, " MII transceiver at index %d, status %x\n",
940 smc->mii_if.phy_id, j);
941 } else {
942 netdev_notice(dev, " No MII transceivers found!\n");
943 }
944 }
945 return 0;
946
947config_undo:
948 unregister_netdev(dev);
949config_failed:
950 smc91c92_release(link);
951 free_netdev(dev);
952 return -ENODEV;
953} /* smc91c92_config */
954
955static void smc91c92_release(struct pcmcia_device *link)
956{
957 dev_dbg(&link->dev, "smc91c92_release\n");
958 if (link->resource[2]->end) {
959 struct net_device *dev = link->priv;
960 struct smc_private *smc = netdev_priv(dev);
961 iounmap(smc->base);
962 }
963 pcmcia_disable_device(link);
964}
965
966/*======================================================================
967
968 MII interface support for SMC91cXX based cards
969======================================================================*/
970
971#define MDIO_SHIFT_CLK 0x04
972#define MDIO_DATA_OUT 0x01
973#define MDIO_DIR_WRITE 0x08
974#define MDIO_DATA_WRITE0 (MDIO_DIR_WRITE)
975#define MDIO_DATA_WRITE1 (MDIO_DIR_WRITE | MDIO_DATA_OUT)
976#define MDIO_DATA_READ 0x02
977
978static void mdio_sync(unsigned int addr)
979{
980 int bits;
981 for (bits = 0; bits < 32; bits++) {
982 outb(MDIO_DATA_WRITE1, addr);
983 outb(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, addr);
984 }
985}
986
987static int mdio_read(struct net_device *dev, int phy_id, int loc)
988{
989 unsigned int addr = dev->base_addr + MGMT;
990 u_int cmd = (0x06<<10)|(phy_id<<5)|loc;
991 int i, retval = 0;
992
993 mdio_sync(addr);
994 for (i = 13; i >= 0; i--) {
995 int dat = (cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
996 outb(dat, addr);
997 outb(dat | MDIO_SHIFT_CLK, addr);
998 }
999 for (i = 19; i > 0; i--) {
1000 outb(0, addr);
1001 retval = (retval << 1) | ((inb(addr) & MDIO_DATA_READ) != 0);
1002 outb(MDIO_SHIFT_CLK, addr);
1003 }
1004 return (retval>>1) & 0xffff;
1005}
1006
1007static void mdio_write(struct net_device *dev, int phy_id, int loc, int value)
1008{
1009 unsigned int addr = dev->base_addr + MGMT;
1010 u_int cmd = (0x05<<28)|(phy_id<<23)|(loc<<18)|(1<<17)|value;
1011 int i;
1012
1013 mdio_sync(addr);
1014 for (i = 31; i >= 0; i--) {
1015 int dat = (cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
1016 outb(dat, addr);
1017 outb(dat | MDIO_SHIFT_CLK, addr);
1018 }
1019 for (i = 1; i >= 0; i--) {
1020 outb(0, addr);
1021 outb(MDIO_SHIFT_CLK, addr);
1022 }
1023}
1024
1025/*======================================================================
1026
1027 The driver core code, most of which should be common with a
1028 non-PCMCIA implementation.
1029
1030======================================================================*/
1031
1032#ifdef PCMCIA_DEBUG
1033static void smc_dump(struct net_device *dev)
1034{
1035 unsigned int ioaddr = dev->base_addr;
1036 u_short i, w, save;
1037 save = inw(ioaddr + BANK_SELECT);
1038 for (w = 0; w < 4; w++) {
1039 SMC_SELECT_BANK(w);
1040 netdev_printk(KERN_DEBUG, dev, "bank %d: ", w);
1041 for (i = 0; i < 14; i += 2)
1042 pr_cont(" %04x", inw(ioaddr + i));
1043 pr_cont("\n");
1044 }
1045 outw(save, ioaddr + BANK_SELECT);
1046}
1047#endif
1048
1049static int smc_open(struct net_device *dev)
1050{
1051 struct smc_private *smc = netdev_priv(dev);
1052 struct pcmcia_device *link = smc->p_dev;
1053
1054 dev_dbg(&link->dev, "%s: smc_open(%p), ID/Window %4.4x.\n",
1055 dev->name, dev, inw(dev->base_addr + BANK_SELECT));
1056#ifdef PCMCIA_DEBUG
1057 smc_dump(dev);
1058#endif
1059
1060 /* Check that the PCMCIA card is still here. */
1061 if (!pcmcia_dev_present(link))
1062 return -ENODEV;
1063 /* Physical device present signature. */
1064 if (check_sig(link) < 0) {
1065 netdev_info(dev, "Yikes! Bad chip signature!\n");
1066 return -ENODEV;
1067 }
1068 link->open++;
1069
1070 netif_start_queue(dev);
1071 smc->saved_skb = NULL;
1072 smc->packets_waiting = 0;
1073
1074 smc_reset(dev);
1075 init_timer(&smc->media);
1076 smc->media.function = media_check;
1077 smc->media.data = (u_long) dev;
1078 smc->media.expires = jiffies + HZ;
1079 add_timer(&smc->media);
1080
1081 return 0;
1082} /* smc_open */
1083
1084/*====================================================================*/
1085
1086static int smc_close(struct net_device *dev)
1087{
1088 struct smc_private *smc = netdev_priv(dev);
1089 struct pcmcia_device *link = smc->p_dev;
1090 unsigned int ioaddr = dev->base_addr;
1091
1092 dev_dbg(&link->dev, "%s: smc_close(), status %4.4x.\n",
1093 dev->name, inw(ioaddr + BANK_SELECT));
1094
1095 netif_stop_queue(dev);
1096
1097 /* Shut off all interrupts, and turn off the Tx and Rx sections.
1098 Don't bother to check for chip present. */
1099 SMC_SELECT_BANK(2); /* Nominally paranoia, but do no assume... */
1100 outw(0, ioaddr + INTERRUPT);
1101 SMC_SELECT_BANK(0);
1102 mask_bits(0xff00, ioaddr + RCR);
1103 mask_bits(0xff00, ioaddr + TCR);
1104
1105 /* Put the chip into power-down mode. */
1106 SMC_SELECT_BANK(1);
1107 outw(CTL_POWERDOWN, ioaddr + CONTROL );
1108
1109 link->open--;
1110 del_timer_sync(&smc->media);
1111
1112 return 0;
1113} /* smc_close */
1114
1115/*======================================================================
1116
1117 Transfer a packet to the hardware and trigger the packet send.
1118 This may be called at either from either the Tx queue code
1119 or the interrupt handler.
1120
1121======================================================================*/
1122
1123static void smc_hardware_send_packet(struct net_device * dev)
1124{
1125 struct smc_private *smc = netdev_priv(dev);
1126 struct sk_buff *skb = smc->saved_skb;
1127 unsigned int ioaddr = dev->base_addr;
1128 u_char packet_no;
1129
1130 if (!skb) {
1131 netdev_err(dev, "In XMIT with no packet to send\n");
1132 return;
1133 }
1134
1135 /* There should be a packet slot waiting. */
1136 packet_no = inw(ioaddr + PNR_ARR) >> 8;
1137 if (packet_no & 0x80) {
1138 /* If not, there is a hardware problem! Likely an ejected card. */
1139 netdev_warn(dev, "hardware Tx buffer allocation failed, status %#2.2x\n",
1140 packet_no);
1141 dev_kfree_skb_irq(skb);
1142 smc->saved_skb = NULL;
1143 netif_start_queue(dev);
1144 return;
1145 }
1146
1147 dev->stats.tx_bytes += skb->len;
1148 /* The card should use the just-allocated buffer. */
1149 outw(packet_no, ioaddr + PNR_ARR);
1150 /* point to the beginning of the packet */
1151 outw(PTR_AUTOINC , ioaddr + POINTER);
1152
1153 /* Send the packet length (+6 for status, length and ctl byte)
1154 and the status word (set to zeros). */
1155 {
1156 u_char *buf = skb->data;
1157 u_int length = skb->len; /* The chip will pad to ethernet min. */
1158
1159 netdev_dbg(dev, "Trying to xmit packet of length %d\n", length);
1160
1161 /* send the packet length: +6 for status word, length, and ctl */
1162 outw(0, ioaddr + DATA_1);
1163 outw(length + 6, ioaddr + DATA_1);
1164 outsw(ioaddr + DATA_1, buf, length >> 1);
1165
1166 /* The odd last byte, if there is one, goes in the control word. */
1167 outw((length & 1) ? 0x2000 | buf[length-1] : 0, ioaddr + DATA_1);
1168 }
1169
1170 /* Enable the Tx interrupts, both Tx (TxErr) and TxEmpty. */
1171 outw(((IM_TX_INT|IM_TX_EMPTY_INT)<<8) |
1172 (inw(ioaddr + INTERRUPT) & 0xff00),
1173 ioaddr + INTERRUPT);
1174
1175 /* The chip does the rest of the work. */
1176 outw(MC_ENQUEUE , ioaddr + MMU_CMD);
1177
1178 smc->saved_skb = NULL;
1179 dev_kfree_skb_irq(skb);
1180 dev->trans_start = jiffies;
1181 netif_start_queue(dev);
1182}
1183
1184/*====================================================================*/
1185
1186static void smc_tx_timeout(struct net_device *dev)
1187{
1188 struct smc_private *smc = netdev_priv(dev);
1189 unsigned int ioaddr = dev->base_addr;
1190
1191 netdev_notice(dev, "transmit timed out, Tx_status %2.2x status %4.4x.\n",
1192 inw(ioaddr)&0xff, inw(ioaddr + 2));
1193 dev->stats.tx_errors++;
1194 smc_reset(dev);
1195 dev->trans_start = jiffies; /* prevent tx timeout */
1196 smc->saved_skb = NULL;
1197 netif_wake_queue(dev);
1198}
1199
1200static netdev_tx_t smc_start_xmit(struct sk_buff *skb,
1201 struct net_device *dev)
1202{
1203 struct smc_private *smc = netdev_priv(dev);
1204 unsigned int ioaddr = dev->base_addr;
1205 u_short num_pages;
1206 short time_out, ir;
1207 unsigned long flags;
1208
1209 netif_stop_queue(dev);
1210
1211 netdev_dbg(dev, "smc_start_xmit(length = %d) called, status %04x\n",
1212 skb->len, inw(ioaddr + 2));
1213
1214 if (smc->saved_skb) {
1215 /* THIS SHOULD NEVER HAPPEN. */
1216 dev->stats.tx_aborted_errors++;
1217 netdev_printk(KERN_DEBUG, dev,
1218 "Internal error -- sent packet while busy\n");
1219 return NETDEV_TX_BUSY;
1220 }
1221 smc->saved_skb = skb;
1222
1223 num_pages = skb->len >> 8;
1224
1225 if (num_pages > 7) {
1226 netdev_err(dev, "Far too big packet error: %d pages\n", num_pages);
1227 dev_kfree_skb (skb);
1228 smc->saved_skb = NULL;
1229 dev->stats.tx_dropped++;
1230 return NETDEV_TX_OK; /* Do not re-queue this packet. */
1231 }
1232 /* A packet is now waiting. */
1233 smc->packets_waiting++;
1234
1235 spin_lock_irqsave(&smc->lock, flags);
1236 SMC_SELECT_BANK(2); /* Paranoia, we should always be in window 2 */
1237
1238 /* need MC_RESET to keep the memory consistent. errata? */
1239 if (smc->rx_ovrn) {
1240 outw(MC_RESET, ioaddr + MMU_CMD);
1241 smc->rx_ovrn = 0;
1242 }
1243
1244 /* Allocate the memory; send the packet now if we win. */
1245 outw(MC_ALLOC | num_pages, ioaddr + MMU_CMD);
1246 for (time_out = MEMORY_WAIT_TIME; time_out >= 0; time_out--) {
1247 ir = inw(ioaddr+INTERRUPT);
1248 if (ir & IM_ALLOC_INT) {
1249 /* Acknowledge the interrupt, send the packet. */
1250 outw((ir&0xff00) | IM_ALLOC_INT, ioaddr + INTERRUPT);
1251 smc_hardware_send_packet(dev); /* Send the packet now.. */
1252 spin_unlock_irqrestore(&smc->lock, flags);
1253 return NETDEV_TX_OK;
1254 }
1255 }
1256
1257 /* Otherwise defer until the Tx-space-allocated interrupt. */
1258 pr_debug("%s: memory allocation deferred.\n", dev->name);
1259 outw((IM_ALLOC_INT << 8) | (ir & 0xff00), ioaddr + INTERRUPT);
1260 spin_unlock_irqrestore(&smc->lock, flags);
1261
1262 return NETDEV_TX_OK;
1263}
1264
1265/*======================================================================
1266
1267 Handle a Tx anomalous event. Entered while in Window 2.
1268
1269======================================================================*/
1270
1271static void smc_tx_err(struct net_device * dev)
1272{
1273 struct smc_private *smc = netdev_priv(dev);
1274 unsigned int ioaddr = dev->base_addr;
1275 int saved_packet = inw(ioaddr + PNR_ARR) & 0xff;
1276 int packet_no = inw(ioaddr + FIFO_PORTS) & 0x7f;
1277 int tx_status;
1278
1279 /* select this as the packet to read from */
1280 outw(packet_no, ioaddr + PNR_ARR);
1281
1282 /* read the first word from this packet */
1283 outw(PTR_AUTOINC | PTR_READ | 0, ioaddr + POINTER);
1284
1285 tx_status = inw(ioaddr + DATA_1);
1286
1287 dev->stats.tx_errors++;
1288 if (tx_status & TS_LOSTCAR) dev->stats.tx_carrier_errors++;
1289 if (tx_status & TS_LATCOL) dev->stats.tx_window_errors++;
1290 if (tx_status & TS_16COL) {
1291 dev->stats.tx_aborted_errors++;
1292 smc->tx_err++;
1293 }
1294
1295 if (tx_status & TS_SUCCESS) {
1296 netdev_notice(dev, "Successful packet caused error interrupt?\n");
1297 }
1298 /* re-enable transmit */
1299 SMC_SELECT_BANK(0);
1300 outw(inw(ioaddr + TCR) | TCR_ENABLE | smc->duplex, ioaddr + TCR);
1301 SMC_SELECT_BANK(2);
1302
1303 outw(MC_FREEPKT, ioaddr + MMU_CMD); /* Free the packet memory. */
1304
1305 /* one less packet waiting for me */
1306 smc->packets_waiting--;
1307
1308 outw(saved_packet, ioaddr + PNR_ARR);
1309}
1310
1311/*====================================================================*/
1312
1313static void smc_eph_irq(struct net_device *dev)
1314{
1315 struct smc_private *smc = netdev_priv(dev);
1316 unsigned int ioaddr = dev->base_addr;
1317 u_short card_stats, ephs;
1318
1319 SMC_SELECT_BANK(0);
1320 ephs = inw(ioaddr + EPH);
1321 pr_debug("%s: Ethernet protocol handler interrupt, status"
1322 " %4.4x.\n", dev->name, ephs);
1323 /* Could be a counter roll-over warning: update stats. */
1324 card_stats = inw(ioaddr + COUNTER);
1325 /* single collisions */
1326 dev->stats.collisions += card_stats & 0xF;
1327 card_stats >>= 4;
1328 /* multiple collisions */
1329 dev->stats.collisions += card_stats & 0xF;
1330#if 0 /* These are for when linux supports these statistics */
1331 card_stats >>= 4; /* deferred */
1332 card_stats >>= 4; /* excess deferred */
1333#endif
1334 /* If we had a transmit error we must re-enable the transmitter. */
1335 outw(inw(ioaddr + TCR) | TCR_ENABLE | smc->duplex, ioaddr + TCR);
1336
1337 /* Clear a link error interrupt. */
1338 SMC_SELECT_BANK(1);
1339 outw(CTL_AUTO_RELEASE | 0x0000, ioaddr + CONTROL);
1340 outw(CTL_AUTO_RELEASE | CTL_TE_ENABLE | CTL_CR_ENABLE,
1341 ioaddr + CONTROL);
1342 SMC_SELECT_BANK(2);
1343}
1344
1345/*====================================================================*/
1346
1347static irqreturn_t smc_interrupt(int irq, void *dev_id)
1348{
1349 struct net_device *dev = dev_id;
1350 struct smc_private *smc = netdev_priv(dev);
1351 unsigned int ioaddr;
1352 u_short saved_bank, saved_pointer, mask, status;
1353 unsigned int handled = 1;
1354 char bogus_cnt = INTR_WORK; /* Work we are willing to do. */
1355
1356 if (!netif_device_present(dev))
1357 return IRQ_NONE;
1358
1359 ioaddr = dev->base_addr;
1360
1361 pr_debug("%s: SMC91c92 interrupt %d at %#x.\n", dev->name,
1362 irq, ioaddr);
1363
1364 spin_lock(&smc->lock);
1365 smc->watchdog = 0;
1366 saved_bank = inw(ioaddr + BANK_SELECT);
1367 if ((saved_bank & 0xff00) != 0x3300) {
1368 /* The device does not exist -- the card could be off-line, or
1369 maybe it has been ejected. */
1370 pr_debug("%s: SMC91c92 interrupt %d for non-existent"
1371 "/ejected device.\n", dev->name, irq);
1372 handled = 0;
1373 goto irq_done;
1374 }
1375
1376 SMC_SELECT_BANK(2);
1377 saved_pointer = inw(ioaddr + POINTER);
1378 mask = inw(ioaddr + INTERRUPT) >> 8;
1379 /* clear all interrupts */
1380 outw(0, ioaddr + INTERRUPT);
1381
1382 do { /* read the status flag, and mask it */
1383 status = inw(ioaddr + INTERRUPT) & 0xff;
1384 pr_debug("%s: Status is %#2.2x (mask %#2.2x).\n", dev->name,
1385 status, mask);
1386 if ((status & mask) == 0) {
1387 if (bogus_cnt == INTR_WORK)
1388 handled = 0;
1389 break;
1390 }
1391 if (status & IM_RCV_INT) {
1392 /* Got a packet(s). */
1393 smc_rx(dev);
1394 }
1395 if (status & IM_TX_INT) {
1396 smc_tx_err(dev);
1397 outw(IM_TX_INT, ioaddr + INTERRUPT);
1398 }
1399 status &= mask;
1400 if (status & IM_TX_EMPTY_INT) {
1401 outw(IM_TX_EMPTY_INT, ioaddr + INTERRUPT);
1402 mask &= ~IM_TX_EMPTY_INT;
1403 dev->stats.tx_packets += smc->packets_waiting;
1404 smc->packets_waiting = 0;
1405 }
1406 if (status & IM_ALLOC_INT) {
1407 /* Clear this interrupt so it doesn't happen again */
1408 mask &= ~IM_ALLOC_INT;
1409
1410 smc_hardware_send_packet(dev);
1411
1412 /* enable xmit interrupts based on this */
1413 mask |= (IM_TX_EMPTY_INT | IM_TX_INT);
1414
1415 /* and let the card send more packets to me */
1416 netif_wake_queue(dev);
1417 }
1418 if (status & IM_RX_OVRN_INT) {
1419 dev->stats.rx_errors++;
1420 dev->stats.rx_fifo_errors++;
1421 if (smc->duplex)
1422 smc->rx_ovrn = 1; /* need MC_RESET outside smc_interrupt */
1423 outw(IM_RX_OVRN_INT, ioaddr + INTERRUPT);
1424 }
1425 if (status & IM_EPH_INT)
1426 smc_eph_irq(dev);
1427 } while (--bogus_cnt);
1428
1429 pr_debug(" Restoring saved registers mask %2.2x bank %4.4x"
1430 " pointer %4.4x.\n", mask, saved_bank, saved_pointer);
1431
1432 /* restore state register */
1433 outw((mask<<8), ioaddr + INTERRUPT);
1434 outw(saved_pointer, ioaddr + POINTER);
1435 SMC_SELECT_BANK(saved_bank);
1436
1437 pr_debug("%s: Exiting interrupt IRQ%d.\n", dev->name, irq);
1438
1439irq_done:
1440
1441 if ((smc->manfid == MANFID_OSITECH) &&
1442 (smc->cardid != PRODID_OSITECH_SEVEN)) {
1443 /* Retrigger interrupt if needed */
1444 mask_bits(0x00ff, ioaddr-0x10+OSITECH_RESET_ISR);
1445 set_bits(0x0300, ioaddr-0x10+OSITECH_RESET_ISR);
1446 }
1447 if (smc->manfid == MANFID_MOTOROLA) {
1448 u_char cor;
1449 cor = readb(smc->base + MOT_UART + CISREG_COR);
1450 writeb(cor & ~COR_IREQ_ENA, smc->base + MOT_UART + CISREG_COR);
1451 writeb(cor, smc->base + MOT_UART + CISREG_COR);
1452 cor = readb(smc->base + MOT_LAN + CISREG_COR);
1453 writeb(cor & ~COR_IREQ_ENA, smc->base + MOT_LAN + CISREG_COR);
1454 writeb(cor, smc->base + MOT_LAN + CISREG_COR);
1455 }
1456
1457 if ((smc->base != NULL) && /* Megahertz MFC's */
1458 (smc->manfid == MANFID_MEGAHERTZ) &&
1459 (smc->cardid == PRODID_MEGAHERTZ_EM3288)) {
1460
1461 u_char tmp;
1462 tmp = readb(smc->base+MEGAHERTZ_ISR);
1463 tmp = readb(smc->base+MEGAHERTZ_ISR);
1464
1465 /* Retrigger interrupt if needed */
1466 writeb(tmp, smc->base + MEGAHERTZ_ISR);
1467 writeb(tmp, smc->base + MEGAHERTZ_ISR);
1468 }
1469
1470 spin_unlock(&smc->lock);
1471 return IRQ_RETVAL(handled);
1472}
1473
1474/*====================================================================*/
1475
1476static void smc_rx(struct net_device *dev)
1477{
1478 unsigned int ioaddr = dev->base_addr;
1479 int rx_status;
1480 int packet_length; /* Caution: not frame length, rather words
1481 to transfer from the chip. */
1482
1483 /* Assertion: we are in Window 2. */
1484
1485 if (inw(ioaddr + FIFO_PORTS) & FP_RXEMPTY) {
1486 netdev_err(dev, "smc_rx() with nothing on Rx FIFO\n");
1487 return;
1488 }
1489
1490 /* Reset the read pointer, and read the status and packet length. */
1491 outw(PTR_READ | PTR_RCV | PTR_AUTOINC, ioaddr + POINTER);
1492 rx_status = inw(ioaddr + DATA_1);
1493 packet_length = inw(ioaddr + DATA_1) & 0x07ff;
1494
1495 pr_debug("%s: Receive status %4.4x length %d.\n",
1496 dev->name, rx_status, packet_length);
1497
1498 if (!(rx_status & RS_ERRORS)) {
1499 /* do stuff to make a new packet */
1500 struct sk_buff *skb;
1501
1502 /* Note: packet_length adds 5 or 6 extra bytes here! */
1503 skb = dev_alloc_skb(packet_length+2);
1504
1505 if (skb == NULL) {
1506 pr_debug("%s: Low memory, packet dropped.\n", dev->name);
1507 dev->stats.rx_dropped++;
1508 outw(MC_RELEASE, ioaddr + MMU_CMD);
1509 return;
1510 }
1511
1512 packet_length -= (rx_status & RS_ODDFRAME ? 5 : 6);
1513 skb_reserve(skb, 2);
1514 insw(ioaddr+DATA_1, skb_put(skb, packet_length),
1515 (packet_length+1)>>1);
1516 skb->protocol = eth_type_trans(skb, dev);
1517
1518 netif_rx(skb);
1519 dev->last_rx = jiffies;
1520 dev->stats.rx_packets++;
1521 dev->stats.rx_bytes += packet_length;
1522 if (rx_status & RS_MULTICAST)
1523 dev->stats.multicast++;
1524 } else {
1525 /* error ... */
1526 dev->stats.rx_errors++;
1527
1528 if (rx_status & RS_ALGNERR) dev->stats.rx_frame_errors++;
1529 if (rx_status & (RS_TOOSHORT | RS_TOOLONG))
1530 dev->stats.rx_length_errors++;
1531 if (rx_status & RS_BADCRC) dev->stats.rx_crc_errors++;
1532 }
1533 /* Let the MMU free the memory of this packet. */
1534 outw(MC_RELEASE, ioaddr + MMU_CMD);
1535}
1536
1537/*======================================================================
1538
1539 Set the receive mode.
1540
1541 This routine is used by both the protocol level to notify us of
1542 promiscuous/multicast mode changes, and by the open/reset code to
1543 initialize the Rx registers. We always set the multicast list and
1544 leave the receiver running.
1545
1546======================================================================*/
1547
1548static void set_rx_mode(struct net_device *dev)
1549{
1550 unsigned int ioaddr = dev->base_addr;
1551 struct smc_private *smc = netdev_priv(dev);
1552 unsigned char multicast_table[8];
1553 unsigned long flags;
1554 u_short rx_cfg_setting;
1555 int i;
1556
1557 memset(multicast_table, 0, sizeof(multicast_table));
1558
1559 if (dev->flags & IFF_PROMISC) {
1560 rx_cfg_setting = RxStripCRC | RxEnable | RxPromisc | RxAllMulti;
1561 } else if (dev->flags & IFF_ALLMULTI)
1562 rx_cfg_setting = RxStripCRC | RxEnable | RxAllMulti;
1563 else {
1564 if (!netdev_mc_empty(dev)) {
1565 struct netdev_hw_addr *ha;
1566
1567 netdev_for_each_mc_addr(ha, dev) {
1568 u_int position = ether_crc(6, ha->addr);
1569 multicast_table[position >> 29] |= 1 << ((position >> 26) & 7);
1570 }
1571 }
1572 rx_cfg_setting = RxStripCRC | RxEnable;
1573 }
1574
1575 /* Load MC table and Rx setting into the chip without interrupts. */
1576 spin_lock_irqsave(&smc->lock, flags);
1577 SMC_SELECT_BANK(3);
1578 for (i = 0; i < 8; i++)
1579 outb(multicast_table[i], ioaddr + MULTICAST0 + i);
1580 SMC_SELECT_BANK(0);
1581 outw(rx_cfg_setting, ioaddr + RCR);
1582 SMC_SELECT_BANK(2);
1583 spin_unlock_irqrestore(&smc->lock, flags);
1584}
1585
1586/*======================================================================
1587
1588 Senses when a card's config changes. Here, it's coax or TP.
1589
1590======================================================================*/
1591
1592static int s9k_config(struct net_device *dev, struct ifmap *map)
1593{
1594 struct smc_private *smc = netdev_priv(dev);
1595 if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
1596 if (smc->cfg & CFG_MII_SELECT)
1597 return -EOPNOTSUPP;
1598 else if (map->port > 2)
1599 return -EINVAL;
1600 dev->if_port = map->port;
1601 netdev_info(dev, "switched to %s port\n", if_names[dev->if_port]);
1602 smc_reset(dev);
1603 }
1604 return 0;
1605}
1606
1607/*======================================================================
1608
1609 Reset the chip, reloading every register that might be corrupted.
1610
1611======================================================================*/
1612
1613/*
1614 Set transceiver type, perhaps to something other than what the user
1615 specified in dev->if_port.
1616*/
1617static void smc_set_xcvr(struct net_device *dev, int if_port)
1618{
1619 struct smc_private *smc = netdev_priv(dev);
1620 unsigned int ioaddr = dev->base_addr;
1621 u_short saved_bank;
1622
1623 saved_bank = inw(ioaddr + BANK_SELECT);
1624 SMC_SELECT_BANK(1);
1625 if (if_port == 2) {
1626 outw(smc->cfg | CFG_AUI_SELECT, ioaddr + CONFIG);
1627 if ((smc->manfid == MANFID_OSITECH) &&
1628 (smc->cardid != PRODID_OSITECH_SEVEN))
1629 set_bits(OSI_AUI_PWR, ioaddr - 0x10 + OSITECH_AUI_PWR);
1630 smc->media_status = ((dev->if_port == 0) ? 0x0001 : 0x0002);
1631 } else {
1632 outw(smc->cfg, ioaddr + CONFIG);
1633 if ((smc->manfid == MANFID_OSITECH) &&
1634 (smc->cardid != PRODID_OSITECH_SEVEN))
1635 mask_bits(~OSI_AUI_PWR, ioaddr - 0x10 + OSITECH_AUI_PWR);
1636 smc->media_status = ((dev->if_port == 0) ? 0x0012 : 0x4001);
1637 }
1638 SMC_SELECT_BANK(saved_bank);
1639}
1640
1641static void smc_reset(struct net_device *dev)
1642{
1643 unsigned int ioaddr = dev->base_addr;
1644 struct smc_private *smc = netdev_priv(dev);
1645 int i;
1646
1647 pr_debug("%s: smc91c92 reset called.\n", dev->name);
1648
1649 /* The first interaction must be a write to bring the chip out
1650 of sleep mode. */
1651 SMC_SELECT_BANK(0);
1652 /* Reset the chip. */
1653 outw(RCR_SOFTRESET, ioaddr + RCR);
1654 udelay(10);
1655
1656 /* Clear the transmit and receive configuration registers. */
1657 outw(RCR_CLEAR, ioaddr + RCR);
1658 outw(TCR_CLEAR, ioaddr + TCR);
1659
1660 /* Set the Window 1 control, configuration and station addr registers.
1661 No point in writing the I/O base register ;-> */
1662 SMC_SELECT_BANK(1);
1663 /* Automatically release successfully transmitted packets,
1664 Accept link errors, counter and Tx error interrupts. */
1665 outw(CTL_AUTO_RELEASE | CTL_TE_ENABLE | CTL_CR_ENABLE,
1666 ioaddr + CONTROL);
1667 smc_set_xcvr(dev, dev->if_port);
1668 if ((smc->manfid == MANFID_OSITECH) &&
1669 (smc->cardid != PRODID_OSITECH_SEVEN))
1670 outw((dev->if_port == 2 ? OSI_AUI_PWR : 0) |
1671 (inw(ioaddr-0x10+OSITECH_AUI_PWR) & 0xff00),
1672 ioaddr - 0x10 + OSITECH_AUI_PWR);
1673
1674 /* Fill in the physical address. The databook is wrong about the order! */
1675 for (i = 0; i < 6; i += 2)
1676 outw((dev->dev_addr[i+1]<<8)+dev->dev_addr[i],
1677 ioaddr + ADDR0 + i);
1678
1679 /* Reset the MMU */
1680 SMC_SELECT_BANK(2);
1681 outw(MC_RESET, ioaddr + MMU_CMD);
1682 outw(0, ioaddr + INTERRUPT);
1683
1684 /* Re-enable the chip. */
1685 SMC_SELECT_BANK(0);
1686 outw(((smc->cfg & CFG_MII_SELECT) ? 0 : TCR_MONCSN) |
1687 TCR_ENABLE | TCR_PAD_EN | smc->duplex, ioaddr + TCR);
1688 set_rx_mode(dev);
1689
1690 if (smc->cfg & CFG_MII_SELECT) {
1691 SMC_SELECT_BANK(3);
1692
1693 /* Reset MII */
1694 mdio_write(dev, smc->mii_if.phy_id, 0, 0x8000);
1695
1696 /* Advertise 100F, 100H, 10F, 10H */
1697 mdio_write(dev, smc->mii_if.phy_id, 4, 0x01e1);
1698
1699 /* Restart MII autonegotiation */
1700 mdio_write(dev, smc->mii_if.phy_id, 0, 0x0000);
1701 mdio_write(dev, smc->mii_if.phy_id, 0, 0x1200);
1702 }
1703
1704 /* Enable interrupts. */
1705 SMC_SELECT_BANK(2);
1706 outw((IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT) << 8,
1707 ioaddr + INTERRUPT);
1708}
1709
1710/*======================================================================
1711
1712 Media selection timer routine
1713
1714======================================================================*/
1715
1716static void media_check(u_long arg)
1717{
1718 struct net_device *dev = (struct net_device *) arg;
1719 struct smc_private *smc = netdev_priv(dev);
1720 unsigned int ioaddr = dev->base_addr;
1721 u_short i, media, saved_bank;
1722 u_short link;
1723 unsigned long flags;
1724
1725 spin_lock_irqsave(&smc->lock, flags);
1726
1727 saved_bank = inw(ioaddr + BANK_SELECT);
1728
1729 if (!netif_device_present(dev))
1730 goto reschedule;
1731
1732 SMC_SELECT_BANK(2);
1733
1734 /* need MC_RESET to keep the memory consistent. errata? */
1735 if (smc->rx_ovrn) {
1736 outw(MC_RESET, ioaddr + MMU_CMD);
1737 smc->rx_ovrn = 0;
1738 }
1739 i = inw(ioaddr + INTERRUPT);
1740 SMC_SELECT_BANK(0);
1741 media = inw(ioaddr + EPH) & EPH_LINK_OK;
1742 SMC_SELECT_BANK(1);
1743 media |= (inw(ioaddr + CONFIG) & CFG_AUI_SELECT) ? 2 : 1;
1744
1745 SMC_SELECT_BANK(saved_bank);
1746 spin_unlock_irqrestore(&smc->lock, flags);
1747
1748 /* Check for pending interrupt with watchdog flag set: with
1749 this, we can limp along even if the interrupt is blocked */
1750 if (smc->watchdog++ && ((i>>8) & i)) {
1751 if (!smc->fast_poll)
1752 netdev_info(dev, "interrupt(s) dropped!\n");
1753 local_irq_save(flags);
1754 smc_interrupt(dev->irq, dev);
1755 local_irq_restore(flags);
1756 smc->fast_poll = HZ;
1757 }
1758 if (smc->fast_poll) {
1759 smc->fast_poll--;
1760 smc->media.expires = jiffies + HZ/100;
1761 add_timer(&smc->media);
1762 return;
1763 }
1764
1765 spin_lock_irqsave(&smc->lock, flags);
1766
1767 saved_bank = inw(ioaddr + BANK_SELECT);
1768
1769 if (smc->cfg & CFG_MII_SELECT) {
1770 if (smc->mii_if.phy_id < 0)
1771 goto reschedule;
1772
1773 SMC_SELECT_BANK(3);
1774 link = mdio_read(dev, smc->mii_if.phy_id, 1);
1775 if (!link || (link == 0xffff)) {
1776 netdev_info(dev, "MII is missing!\n");
1777 smc->mii_if.phy_id = -1;
1778 goto reschedule;
1779 }
1780
1781 link &= 0x0004;
1782 if (link != smc->link_status) {
1783 u_short p = mdio_read(dev, smc->mii_if.phy_id, 5);
1784 netdev_info(dev, "%s link beat\n", link ? "found" : "lost");
1785 smc->duplex = (((p & 0x0100) || ((p & 0x1c0) == 0x40))
1786 ? TCR_FDUPLX : 0);
1787 if (link) {
1788 netdev_info(dev, "autonegotiation complete: "
1789 "%dbaseT-%cD selected\n",
1790 (p & 0x0180) ? 100 : 10, smc->duplex ? 'F' : 'H');
1791 }
1792 SMC_SELECT_BANK(0);
1793 outw(inw(ioaddr + TCR) | smc->duplex, ioaddr + TCR);
1794 smc->link_status = link;
1795 }
1796 goto reschedule;
1797 }
1798
1799 /* Ignore collisions unless we've had no rx's recently */
1800 if (time_after(jiffies, dev->last_rx + HZ)) {
1801 if (smc->tx_err || (smc->media_status & EPH_16COL))
1802 media |= EPH_16COL;
1803 }
1804 smc->tx_err = 0;
1805
1806 if (media != smc->media_status) {
1807 if ((media & smc->media_status & 1) &&
1808 ((smc->media_status ^ media) & EPH_LINK_OK))
1809 netdev_info(dev, "%s link beat\n",
1810 smc->media_status & EPH_LINK_OK ? "lost" : "found");
1811 else if ((media & smc->media_status & 2) &&
1812 ((smc->media_status ^ media) & EPH_16COL))
1813 netdev_info(dev, "coax cable %s\n",
1814 media & EPH_16COL ? "problem" : "ok");
1815 if (dev->if_port == 0) {
1816 if (media & 1) {
1817 if (media & EPH_LINK_OK)
1818 netdev_info(dev, "flipped to 10baseT\n");
1819 else
1820 smc_set_xcvr(dev, 2);
1821 } else {
1822 if (media & EPH_16COL)
1823 smc_set_xcvr(dev, 1);
1824 else
1825 netdev_info(dev, "flipped to 10base2\n");
1826 }
1827 }
1828 smc->media_status = media;
1829 }
1830
1831reschedule:
1832 smc->media.expires = jiffies + HZ;
1833 add_timer(&smc->media);
1834 SMC_SELECT_BANK(saved_bank);
1835 spin_unlock_irqrestore(&smc->lock, flags);
1836}
1837
1838static int smc_link_ok(struct net_device *dev)
1839{
1840 unsigned int ioaddr = dev->base_addr;
1841 struct smc_private *smc = netdev_priv(dev);
1842
1843 if (smc->cfg & CFG_MII_SELECT) {
1844 return mii_link_ok(&smc->mii_if);
1845 } else {
1846 SMC_SELECT_BANK(0);
1847 return inw(ioaddr + EPH) & EPH_LINK_OK;
1848 }
1849}
1850
1851static int smc_netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
1852{
1853 u16 tmp;
1854 unsigned int ioaddr = dev->base_addr;
1855
1856 ecmd->supported = (SUPPORTED_TP | SUPPORTED_AUI |
1857 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full);
1858
1859 SMC_SELECT_BANK(1);
1860 tmp = inw(ioaddr + CONFIG);
1861 ecmd->port = (tmp & CFG_AUI_SELECT) ? PORT_AUI : PORT_TP;
1862 ecmd->transceiver = XCVR_INTERNAL;
1863 ethtool_cmd_speed_set(ecmd, SPEED_10);
1864 ecmd->phy_address = ioaddr + MGMT;
1865
1866 SMC_SELECT_BANK(0);
1867 tmp = inw(ioaddr + TCR);
1868 ecmd->duplex = (tmp & TCR_FDUPLX) ? DUPLEX_FULL : DUPLEX_HALF;
1869
1870 return 0;
1871}
1872
1873static int smc_netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
1874{
1875 u16 tmp;
1876 unsigned int ioaddr = dev->base_addr;
1877
1878 if (ethtool_cmd_speed(ecmd) != SPEED_10)
1879 return -EINVAL;
1880 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
1881 return -EINVAL;
1882 if (ecmd->port != PORT_TP && ecmd->port != PORT_AUI)
1883 return -EINVAL;
1884 if (ecmd->transceiver != XCVR_INTERNAL)
1885 return -EINVAL;
1886
1887 if (ecmd->port == PORT_AUI)
1888 smc_set_xcvr(dev, 1);
1889 else
1890 smc_set_xcvr(dev, 0);
1891
1892 SMC_SELECT_BANK(0);
1893 tmp = inw(ioaddr + TCR);
1894 if (ecmd->duplex == DUPLEX_FULL)
1895 tmp |= TCR_FDUPLX;
1896 else
1897 tmp &= ~TCR_FDUPLX;
1898 outw(tmp, ioaddr + TCR);
1899
1900 return 0;
1901}
1902
1903static int check_if_running(struct net_device *dev)
1904{
1905 if (!netif_running(dev))
1906 return -EINVAL;
1907 return 0;
1908}
1909
1910static void smc_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1911{
1912 strcpy(info->driver, DRV_NAME);
1913 strcpy(info->version, DRV_VERSION);
1914}
1915
1916static int smc_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1917{
1918 struct smc_private *smc = netdev_priv(dev);
1919 unsigned int ioaddr = dev->base_addr;
1920 u16 saved_bank = inw(ioaddr + BANK_SELECT);
1921 int ret;
1922 unsigned long flags;
1923
1924 spin_lock_irqsave(&smc->lock, flags);
1925 SMC_SELECT_BANK(3);
1926 if (smc->cfg & CFG_MII_SELECT)
1927 ret = mii_ethtool_gset(&smc->mii_if, ecmd);
1928 else
1929 ret = smc_netdev_get_ecmd(dev, ecmd);
1930 SMC_SELECT_BANK(saved_bank);
1931 spin_unlock_irqrestore(&smc->lock, flags);
1932 return ret;
1933}
1934
1935static int smc_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1936{
1937 struct smc_private *smc = netdev_priv(dev);
1938 unsigned int ioaddr = dev->base_addr;
1939 u16 saved_bank = inw(ioaddr + BANK_SELECT);
1940 int ret;
1941 unsigned long flags;
1942
1943 spin_lock_irqsave(&smc->lock, flags);
1944 SMC_SELECT_BANK(3);
1945 if (smc->cfg & CFG_MII_SELECT)
1946 ret = mii_ethtool_sset(&smc->mii_if, ecmd);
1947 else
1948 ret = smc_netdev_set_ecmd(dev, ecmd);
1949 SMC_SELECT_BANK(saved_bank);
1950 spin_unlock_irqrestore(&smc->lock, flags);
1951 return ret;
1952}
1953
1954static u32 smc_get_link(struct net_device *dev)
1955{
1956 struct smc_private *smc = netdev_priv(dev);
1957 unsigned int ioaddr = dev->base_addr;
1958 u16 saved_bank = inw(ioaddr + BANK_SELECT);
1959 u32 ret;
1960 unsigned long flags;
1961
1962 spin_lock_irqsave(&smc->lock, flags);
1963 SMC_SELECT_BANK(3);
1964 ret = smc_link_ok(dev);
1965 SMC_SELECT_BANK(saved_bank);
1966 spin_unlock_irqrestore(&smc->lock, flags);
1967 return ret;
1968}
1969
1970static int smc_nway_reset(struct net_device *dev)
1971{
1972 struct smc_private *smc = netdev_priv(dev);
1973 if (smc->cfg & CFG_MII_SELECT) {
1974 unsigned int ioaddr = dev->base_addr;
1975 u16 saved_bank = inw(ioaddr + BANK_SELECT);
1976 int res;
1977
1978 SMC_SELECT_BANK(3);
1979 res = mii_nway_restart(&smc->mii_if);
1980 SMC_SELECT_BANK(saved_bank);
1981
1982 return res;
1983 } else
1984 return -EOPNOTSUPP;
1985}
1986
1987static const struct ethtool_ops ethtool_ops = {
1988 .begin = check_if_running,
1989 .get_drvinfo = smc_get_drvinfo,
1990 .get_settings = smc_get_settings,
1991 .set_settings = smc_set_settings,
1992 .get_link = smc_get_link,
1993 .nway_reset = smc_nway_reset,
1994};
1995
1996static int smc_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1997{
1998 struct smc_private *smc = netdev_priv(dev);
1999 struct mii_ioctl_data *mii = if_mii(rq);
2000 int rc = 0;
2001 u16 saved_bank;
2002 unsigned int ioaddr = dev->base_addr;
2003 unsigned long flags;
2004
2005 if (!netif_running(dev))
2006 return -EINVAL;
2007
2008 spin_lock_irqsave(&smc->lock, flags);
2009 saved_bank = inw(ioaddr + BANK_SELECT);
2010 SMC_SELECT_BANK(3);
2011 rc = generic_mii_ioctl(&smc->mii_if, mii, cmd, NULL);
2012 SMC_SELECT_BANK(saved_bank);
2013 spin_unlock_irqrestore(&smc->lock, flags);
2014 return rc;
2015}
2016
2017static const struct pcmcia_device_id smc91c92_ids[] = {
2018 PCMCIA_PFC_DEVICE_MANF_CARD(0, 0x0109, 0x0501),
2019 PCMCIA_PFC_DEVICE_MANF_CARD(0, 0x0140, 0x000a),
2020 PCMCIA_PFC_DEVICE_PROD_ID123(0, "MEGAHERTZ", "CC/XJEM3288", "DATA/FAX/CELL ETHERNET MODEM", 0xf510db04, 0x04cd2988, 0x46a52d63),
2021 PCMCIA_PFC_DEVICE_PROD_ID123(0, "MEGAHERTZ", "CC/XJEM3336", "DATA/FAX/CELL ETHERNET MODEM", 0xf510db04, 0x0143b773, 0x46a52d63),
2022 PCMCIA_PFC_DEVICE_PROD_ID123(0, "MEGAHERTZ", "EM1144T", "PCMCIA MODEM", 0xf510db04, 0x856d66c8, 0xbd6c43ef),
2023 PCMCIA_PFC_DEVICE_PROD_ID123(0, "MEGAHERTZ", "XJEM1144/CCEM1144", "PCMCIA MODEM", 0xf510db04, 0x52d21e1e, 0xbd6c43ef),
2024 PCMCIA_PFC_DEVICE_PROD_ID12(0, "Gateway 2000", "XJEM3336", 0xdd9989be, 0x662c394c),
2025 PCMCIA_PFC_DEVICE_PROD_ID12(0, "MEGAHERTZ", "XJEM1144/CCEM1144", 0xf510db04, 0x52d21e1e),
2026 PCMCIA_PFC_DEVICE_PROD_ID12(0, "Ositech", "Trumpcard:Jack of Diamonds Modem+Ethernet", 0xc2f80cd, 0x656947b9),
2027 PCMCIA_PFC_DEVICE_PROD_ID12(0, "Ositech", "Trumpcard:Jack of Hearts Modem+Ethernet", 0xc2f80cd, 0xdc9ba5ed),
2028 PCMCIA_MFC_DEVICE_MANF_CARD(0, 0x016c, 0x0020),
2029 PCMCIA_DEVICE_MANF_CARD(0x016c, 0x0023),
2030 PCMCIA_DEVICE_PROD_ID123("BASICS by New Media Corporation", "Ethernet", "SMC91C94", 0x23c78a9d, 0x00b2e941, 0xcef397fb),
2031 PCMCIA_DEVICE_PROD_ID12("ARGOSY", "Fast Ethernet PCCard", 0x78f308dc, 0xdcea68bc),
2032 PCMCIA_DEVICE_PROD_ID12("dit Co., Ltd.", "PC Card-10/100BTX", 0xe59365c8, 0x6a2161d1),
2033 PCMCIA_DEVICE_PROD_ID12("DYNALINK", "L100C", 0x6a26d1cf, 0xc16ce9c5),
2034 PCMCIA_DEVICE_PROD_ID12("Farallon", "Farallon Enet", 0x58d93fc4, 0x244734e9),
2035 PCMCIA_DEVICE_PROD_ID12("Megahertz", "CC10BT/2", 0x33234748, 0x3c95b953),
2036 PCMCIA_DEVICE_PROD_ID12("MELCO/SMC", "LPC-TX", 0xa2cd8e6d, 0x42da662a),
2037 PCMCIA_DEVICE_PROD_ID12("Ositech", "Trumpcard:Four of Diamonds Ethernet", 0xc2f80cd, 0xb3466314),
2038 PCMCIA_DEVICE_PROD_ID12("Ositech", "Trumpcard:Seven of Diamonds Ethernet", 0xc2f80cd, 0x194b650a),
2039 PCMCIA_DEVICE_PROD_ID12("PCMCIA", "Fast Ethernet PCCard", 0x281f1c5d, 0xdcea68bc),
2040 PCMCIA_DEVICE_PROD_ID12("Psion", "10Mb Ethernet", 0x4ef00b21, 0x844be9e9),
2041 PCMCIA_DEVICE_PROD_ID12("SMC", "EtherEZ Ethernet 8020", 0xc4f8b18b, 0x4a0eeb2d),
2042 /* These conflict with other cards! */
2043 /* PCMCIA_DEVICE_MANF_CARD(0x0186, 0x0100), */
2044 /* PCMCIA_DEVICE_MANF_CARD(0x8a01, 0xc1ab), */
2045 PCMCIA_DEVICE_NULL,
2046};
2047MODULE_DEVICE_TABLE(pcmcia, smc91c92_ids);
2048
2049static struct pcmcia_driver smc91c92_cs_driver = {
2050 .owner = THIS_MODULE,
2051 .name = "smc91c92_cs",
2052 .probe = smc91c92_probe,
2053 .remove = smc91c92_detach,
2054 .id_table = smc91c92_ids,
2055 .suspend = smc91c92_suspend,
2056 .resume = smc91c92_resume,
2057};
2058
2059static int __init init_smc91c92_cs(void)
2060{
2061 return pcmcia_register_driver(&smc91c92_cs_driver);
2062}
2063
2064static void __exit exit_smc91c92_cs(void)
2065{
2066 pcmcia_unregister_driver(&smc91c92_cs_driver);
2067}
2068
2069module_init(init_smc91c92_cs);
2070module_exit(exit_smc91c92_cs);
diff --git a/drivers/net/ethernet/smsc/smc91x.c b/drivers/net/ethernet/smsc/smc91x.c
new file mode 100644
index 000000000000..2b1d254d59af
--- /dev/null
+++ b/drivers/net/ethernet/smsc/smc91x.c
@@ -0,0 +1,2431 @@
1/*
2 * smc91x.c
3 * This is a driver for SMSC's 91C9x/91C1xx single-chip Ethernet devices.
4 *
5 * Copyright (C) 1996 by Erik Stahlman
6 * Copyright (C) 2001 Standard Microsystems Corporation
7 * Developed by Simple Network Magic Corporation
8 * Copyright (C) 2003 Monta Vista Software, Inc.
9 * Unified SMC91x driver by Nicolas Pitre
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 * Arguments:
26 * io = for the base address
27 * irq = for the IRQ
28 * nowait = 0 for normal wait states, 1 eliminates additional wait states
29 *
30 * original author:
31 * Erik Stahlman <erik@vt.edu>
32 *
33 * hardware multicast code:
34 * Peter Cammaert <pc@denkart.be>
35 *
36 * contributors:
37 * Daris A Nevil <dnevil@snmc.com>
38 * Nicolas Pitre <nico@fluxnic.net>
39 * Russell King <rmk@arm.linux.org.uk>
40 *
41 * History:
42 * 08/20/00 Arnaldo Melo fix kfree(skb) in smc_hardware_send_packet
43 * 12/15/00 Christian Jullien fix "Warning: kfree_skb on hard IRQ"
44 * 03/16/01 Daris A Nevil modified smc9194.c for use with LAN91C111
45 * 08/22/01 Scott Anderson merge changes from smc9194 to smc91111
46 * 08/21/01 Pramod B Bhardwaj added support for RevB of LAN91C111
47 * 12/20/01 Jeff Sutherland initial port to Xscale PXA with DMA support
48 * 04/07/03 Nicolas Pitre unified SMC91x driver, killed irq races,
49 * more bus abstraction, big cleanup, etc.
50 * 29/09/03 Russell King - add driver model support
51 * - ethtool support
52 * - convert to use generic MII interface
53 * - add link up/down notification
54 * - don't try to handle full negotiation in
55 * smc_phy_configure
56 * - clean up (and fix stack overrun) in PHY
57 * MII read/write functions
58 * 22/09/04 Nicolas Pitre big update (see commit log for details)
59 */
60static const char version[] =
61 "smc91x.c: v1.1, sep 22 2004 by Nicolas Pitre <nico@fluxnic.net>\n";
62
63/* Debugging level */
64#ifndef SMC_DEBUG
65#define SMC_DEBUG 0
66#endif
67
68
69#include <linux/init.h>
70#include <linux/module.h>
71#include <linux/kernel.h>
72#include <linux/sched.h>
73#include <linux/delay.h>
74#include <linux/interrupt.h>
75#include <linux/irq.h>
76#include <linux/errno.h>
77#include <linux/ioport.h>
78#include <linux/crc32.h>
79#include <linux/platform_device.h>
80#include <linux/spinlock.h>
81#include <linux/ethtool.h>
82#include <linux/mii.h>
83#include <linux/workqueue.h>
84#include <linux/of.h>
85
86#include <linux/netdevice.h>
87#include <linux/etherdevice.h>
88#include <linux/skbuff.h>
89
90#include <asm/io.h>
91
92#include "smc91x.h"
93
94#ifndef SMC_NOWAIT
95# define SMC_NOWAIT 0
96#endif
97static int nowait = SMC_NOWAIT;
98module_param(nowait, int, 0400);
99MODULE_PARM_DESC(nowait, "set to 1 for no wait state");
100
101/*
102 * Transmit timeout, default 5 seconds.
103 */
104static int watchdog = 1000;
105module_param(watchdog, int, 0400);
106MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
107
108MODULE_LICENSE("GPL");
109MODULE_ALIAS("platform:smc91x");
110
111/*
112 * The internal workings of the driver. If you are changing anything
113 * here with the SMC stuff, you should have the datasheet and know
114 * what you are doing.
115 */
116#define CARDNAME "smc91x"
117
118/*
119 * Use power-down feature of the chip
120 */
121#define POWER_DOWN 1
122
123/*
124 * Wait time for memory to be free. This probably shouldn't be
125 * tuned that much, as waiting for this means nothing else happens
126 * in the system
127 */
128#define MEMORY_WAIT_TIME 16
129
130/*
131 * The maximum number of processing loops allowed for each call to the
132 * IRQ handler.
133 */
134#define MAX_IRQ_LOOPS 8
135
136/*
137 * This selects whether TX packets are sent one by one to the SMC91x internal
138 * memory and throttled until transmission completes. This may prevent
139 * RX overruns a litle by keeping much of the memory free for RX packets
140 * but to the expense of reduced TX throughput and increased IRQ overhead.
141 * Note this is not a cure for a too slow data bus or too high IRQ latency.
142 */
143#define THROTTLE_TX_PKTS 0
144
145/*
146 * The MII clock high/low times. 2x this number gives the MII clock period
147 * in microseconds. (was 50, but this gives 6.4ms for each MII transaction!)
148 */
149#define MII_DELAY 1
150
151#if SMC_DEBUG > 0
152#define DBG(n, args...) \
153 do { \
154 if (SMC_DEBUG >= (n)) \
155 printk(args); \
156 } while (0)
157
158#define PRINTK(args...) printk(args)
159#else
160#define DBG(n, args...) do { } while(0)
161#define PRINTK(args...) printk(KERN_DEBUG args)
162#endif
163
164#if SMC_DEBUG > 3
165static void PRINT_PKT(u_char *buf, int length)
166{
167 int i;
168 int remainder;
169 int lines;
170
171 lines = length / 16;
172 remainder = length % 16;
173
174 for (i = 0; i < lines ; i ++) {
175 int cur;
176 for (cur = 0; cur < 8; cur++) {
177 u_char a, b;
178 a = *buf++;
179 b = *buf++;
180 printk("%02x%02x ", a, b);
181 }
182 printk("\n");
183 }
184 for (i = 0; i < remainder/2 ; i++) {
185 u_char a, b;
186 a = *buf++;
187 b = *buf++;
188 printk("%02x%02x ", a, b);
189 }
190 printk("\n");
191}
192#else
193#define PRINT_PKT(x...) do { } while(0)
194#endif
195
196
197/* this enables an interrupt in the interrupt mask register */
198#define SMC_ENABLE_INT(lp, x) do { \
199 unsigned char mask; \
200 unsigned long smc_enable_flags; \
201 spin_lock_irqsave(&lp->lock, smc_enable_flags); \
202 mask = SMC_GET_INT_MASK(lp); \
203 mask |= (x); \
204 SMC_SET_INT_MASK(lp, mask); \
205 spin_unlock_irqrestore(&lp->lock, smc_enable_flags); \
206} while (0)
207
208/* this disables an interrupt from the interrupt mask register */
209#define SMC_DISABLE_INT(lp, x) do { \
210 unsigned char mask; \
211 unsigned long smc_disable_flags; \
212 spin_lock_irqsave(&lp->lock, smc_disable_flags); \
213 mask = SMC_GET_INT_MASK(lp); \
214 mask &= ~(x); \
215 SMC_SET_INT_MASK(lp, mask); \
216 spin_unlock_irqrestore(&lp->lock, smc_disable_flags); \
217} while (0)
218
219/*
220 * Wait while MMU is busy. This is usually in the order of a few nanosecs
221 * if at all, but let's avoid deadlocking the system if the hardware
222 * decides to go south.
223 */
224#define SMC_WAIT_MMU_BUSY(lp) do { \
225 if (unlikely(SMC_GET_MMU_CMD(lp) & MC_BUSY)) { \
226 unsigned long timeout = jiffies + 2; \
227 while (SMC_GET_MMU_CMD(lp) & MC_BUSY) { \
228 if (time_after(jiffies, timeout)) { \
229 printk("%s: timeout %s line %d\n", \
230 dev->name, __FILE__, __LINE__); \
231 break; \
232 } \
233 cpu_relax(); \
234 } \
235 } \
236} while (0)
237
238
239/*
240 * this does a soft reset on the device
241 */
242static void smc_reset(struct net_device *dev)
243{
244 struct smc_local *lp = netdev_priv(dev);
245 void __iomem *ioaddr = lp->base;
246 unsigned int ctl, cfg;
247 struct sk_buff *pending_skb;
248
249 DBG(2, "%s: %s\n", dev->name, __func__);
250
251 /* Disable all interrupts, block TX tasklet */
252 spin_lock_irq(&lp->lock);
253 SMC_SELECT_BANK(lp, 2);
254 SMC_SET_INT_MASK(lp, 0);
255 pending_skb = lp->pending_tx_skb;
256 lp->pending_tx_skb = NULL;
257 spin_unlock_irq(&lp->lock);
258
259 /* free any pending tx skb */
260 if (pending_skb) {
261 dev_kfree_skb(pending_skb);
262 dev->stats.tx_errors++;
263 dev->stats.tx_aborted_errors++;
264 }
265
266 /*
267 * This resets the registers mostly to defaults, but doesn't
268 * affect EEPROM. That seems unnecessary
269 */
270 SMC_SELECT_BANK(lp, 0);
271 SMC_SET_RCR(lp, RCR_SOFTRST);
272
273 /*
274 * Setup the Configuration Register
275 * This is necessary because the CONFIG_REG is not affected
276 * by a soft reset
277 */
278 SMC_SELECT_BANK(lp, 1);
279
280 cfg = CONFIG_DEFAULT;
281
282 /*
283 * Setup for fast accesses if requested. If the card/system
284 * can't handle it then there will be no recovery except for
285 * a hard reset or power cycle
286 */
287 if (lp->cfg.flags & SMC91X_NOWAIT)
288 cfg |= CONFIG_NO_WAIT;
289
290 /*
291 * Release from possible power-down state
292 * Configuration register is not affected by Soft Reset
293 */
294 cfg |= CONFIG_EPH_POWER_EN;
295
296 SMC_SET_CONFIG(lp, cfg);
297
298 /* this should pause enough for the chip to be happy */
299 /*
300 * elaborate? What does the chip _need_? --jgarzik
301 *
302 * This seems to be undocumented, but something the original
303 * driver(s) have always done. Suspect undocumented timing
304 * info/determined empirically. --rmk
305 */
306 udelay(1);
307
308 /* Disable transmit and receive functionality */
309 SMC_SELECT_BANK(lp, 0);
310 SMC_SET_RCR(lp, RCR_CLEAR);
311 SMC_SET_TCR(lp, TCR_CLEAR);
312
313 SMC_SELECT_BANK(lp, 1);
314 ctl = SMC_GET_CTL(lp) | CTL_LE_ENABLE;
315
316 /*
317 * Set the control register to automatically release successfully
318 * transmitted packets, to make the best use out of our limited
319 * memory
320 */
321 if(!THROTTLE_TX_PKTS)
322 ctl |= CTL_AUTO_RELEASE;
323 else
324 ctl &= ~CTL_AUTO_RELEASE;
325 SMC_SET_CTL(lp, ctl);
326
327 /* Reset the MMU */
328 SMC_SELECT_BANK(lp, 2);
329 SMC_SET_MMU_CMD(lp, MC_RESET);
330 SMC_WAIT_MMU_BUSY(lp);
331}
332
333/*
334 * Enable Interrupts, Receive, and Transmit
335 */
336static void smc_enable(struct net_device *dev)
337{
338 struct smc_local *lp = netdev_priv(dev);
339 void __iomem *ioaddr = lp->base;
340 int mask;
341
342 DBG(2, "%s: %s\n", dev->name, __func__);
343
344 /* see the header file for options in TCR/RCR DEFAULT */
345 SMC_SELECT_BANK(lp, 0);
346 SMC_SET_TCR(lp, lp->tcr_cur_mode);
347 SMC_SET_RCR(lp, lp->rcr_cur_mode);
348
349 SMC_SELECT_BANK(lp, 1);
350 SMC_SET_MAC_ADDR(lp, dev->dev_addr);
351
352 /* now, enable interrupts */
353 mask = IM_EPH_INT|IM_RX_OVRN_INT|IM_RCV_INT;
354 if (lp->version >= (CHIP_91100 << 4))
355 mask |= IM_MDINT;
356 SMC_SELECT_BANK(lp, 2);
357 SMC_SET_INT_MASK(lp, mask);
358
359 /*
360 * From this point the register bank must _NOT_ be switched away
361 * to something else than bank 2 without proper locking against
362 * races with any tasklet or interrupt handlers until smc_shutdown()
363 * or smc_reset() is called.
364 */
365}
366
367/*
368 * this puts the device in an inactive state
369 */
370static void smc_shutdown(struct net_device *dev)
371{
372 struct smc_local *lp = netdev_priv(dev);
373 void __iomem *ioaddr = lp->base;
374 struct sk_buff *pending_skb;
375
376 DBG(2, "%s: %s\n", CARDNAME, __func__);
377
378 /* no more interrupts for me */
379 spin_lock_irq(&lp->lock);
380 SMC_SELECT_BANK(lp, 2);
381 SMC_SET_INT_MASK(lp, 0);
382 pending_skb = lp->pending_tx_skb;
383 lp->pending_tx_skb = NULL;
384 spin_unlock_irq(&lp->lock);
385 if (pending_skb)
386 dev_kfree_skb(pending_skb);
387
388 /* and tell the card to stay away from that nasty outside world */
389 SMC_SELECT_BANK(lp, 0);
390 SMC_SET_RCR(lp, RCR_CLEAR);
391 SMC_SET_TCR(lp, TCR_CLEAR);
392
393#ifdef POWER_DOWN
394 /* finally, shut the chip down */
395 SMC_SELECT_BANK(lp, 1);
396 SMC_SET_CONFIG(lp, SMC_GET_CONFIG(lp) & ~CONFIG_EPH_POWER_EN);
397#endif
398}
399
400/*
401 * This is the procedure to handle the receipt of a packet.
402 */
403static inline void smc_rcv(struct net_device *dev)
404{
405 struct smc_local *lp = netdev_priv(dev);
406 void __iomem *ioaddr = lp->base;
407 unsigned int packet_number, status, packet_len;
408
409 DBG(3, "%s: %s\n", dev->name, __func__);
410
411 packet_number = SMC_GET_RXFIFO(lp);
412 if (unlikely(packet_number & RXFIFO_REMPTY)) {
413 PRINTK("%s: smc_rcv with nothing on FIFO.\n", dev->name);
414 return;
415 }
416
417 /* read from start of packet */
418 SMC_SET_PTR(lp, PTR_READ | PTR_RCV | PTR_AUTOINC);
419
420 /* First two words are status and packet length */
421 SMC_GET_PKT_HDR(lp, status, packet_len);
422 packet_len &= 0x07ff; /* mask off top bits */
423 DBG(2, "%s: RX PNR 0x%x STATUS 0x%04x LENGTH 0x%04x (%d)\n",
424 dev->name, packet_number, status,
425 packet_len, packet_len);
426
427 back:
428 if (unlikely(packet_len < 6 || status & RS_ERRORS)) {
429 if (status & RS_TOOLONG && packet_len <= (1514 + 4 + 6)) {
430 /* accept VLAN packets */
431 status &= ~RS_TOOLONG;
432 goto back;
433 }
434 if (packet_len < 6) {
435 /* bloody hardware */
436 printk(KERN_ERR "%s: fubar (rxlen %u status %x\n",
437 dev->name, packet_len, status);
438 status |= RS_TOOSHORT;
439 }
440 SMC_WAIT_MMU_BUSY(lp);
441 SMC_SET_MMU_CMD(lp, MC_RELEASE);
442 dev->stats.rx_errors++;
443 if (status & RS_ALGNERR)
444 dev->stats.rx_frame_errors++;
445 if (status & (RS_TOOSHORT | RS_TOOLONG))
446 dev->stats.rx_length_errors++;
447 if (status & RS_BADCRC)
448 dev->stats.rx_crc_errors++;
449 } else {
450 struct sk_buff *skb;
451 unsigned char *data;
452 unsigned int data_len;
453
454 /* set multicast stats */
455 if (status & RS_MULTICAST)
456 dev->stats.multicast++;
457
458 /*
459 * Actual payload is packet_len - 6 (or 5 if odd byte).
460 * We want skb_reserve(2) and the final ctrl word
461 * (2 bytes, possibly containing the payload odd byte).
462 * Furthermore, we add 2 bytes to allow rounding up to
463 * multiple of 4 bytes on 32 bit buses.
464 * Hence packet_len - 6 + 2 + 2 + 2.
465 */
466 skb = dev_alloc_skb(packet_len);
467 if (unlikely(skb == NULL)) {
468 printk(KERN_NOTICE "%s: Low memory, packet dropped.\n",
469 dev->name);
470 SMC_WAIT_MMU_BUSY(lp);
471 SMC_SET_MMU_CMD(lp, MC_RELEASE);
472 dev->stats.rx_dropped++;
473 return;
474 }
475
476 /* Align IP header to 32 bits */
477 skb_reserve(skb, 2);
478
479 /* BUG: the LAN91C111 rev A never sets this bit. Force it. */
480 if (lp->version == 0x90)
481 status |= RS_ODDFRAME;
482
483 /*
484 * If odd length: packet_len - 5,
485 * otherwise packet_len - 6.
486 * With the trailing ctrl byte it's packet_len - 4.
487 */
488 data_len = packet_len - ((status & RS_ODDFRAME) ? 5 : 6);
489 data = skb_put(skb, data_len);
490 SMC_PULL_DATA(lp, data, packet_len - 4);
491
492 SMC_WAIT_MMU_BUSY(lp);
493 SMC_SET_MMU_CMD(lp, MC_RELEASE);
494
495 PRINT_PKT(data, packet_len - 4);
496
497 skb->protocol = eth_type_trans(skb, dev);
498 netif_rx(skb);
499 dev->stats.rx_packets++;
500 dev->stats.rx_bytes += data_len;
501 }
502}
503
504#ifdef CONFIG_SMP
505/*
506 * On SMP we have the following problem:
507 *
508 * A = smc_hardware_send_pkt()
509 * B = smc_hard_start_xmit()
510 * C = smc_interrupt()
511 *
512 * A and B can never be executed simultaneously. However, at least on UP,
513 * it is possible (and even desirable) for C to interrupt execution of
514 * A or B in order to have better RX reliability and avoid overruns.
515 * C, just like A and B, must have exclusive access to the chip and
516 * each of them must lock against any other concurrent access.
517 * Unfortunately this is not possible to have C suspend execution of A or
518 * B taking place on another CPU. On UP this is no an issue since A and B
519 * are run from softirq context and C from hard IRQ context, and there is
520 * no other CPU where concurrent access can happen.
521 * If ever there is a way to force at least B and C to always be executed
522 * on the same CPU then we could use read/write locks to protect against
523 * any other concurrent access and C would always interrupt B. But life
524 * isn't that easy in a SMP world...
525 */
526#define smc_special_trylock(lock, flags) \
527({ \
528 int __ret; \
529 local_irq_save(flags); \
530 __ret = spin_trylock(lock); \
531 if (!__ret) \
532 local_irq_restore(flags); \
533 __ret; \
534})
535#define smc_special_lock(lock, flags) spin_lock_irqsave(lock, flags)
536#define smc_special_unlock(lock, flags) spin_unlock_irqrestore(lock, flags)
537#else
538#define smc_special_trylock(lock, flags) (flags == flags)
539#define smc_special_lock(lock, flags) do { flags = 0; } while (0)
540#define smc_special_unlock(lock, flags) do { flags = 0; } while (0)
541#endif
542
543/*
544 * This is called to actually send a packet to the chip.
545 */
546static void smc_hardware_send_pkt(unsigned long data)
547{
548 struct net_device *dev = (struct net_device *)data;
549 struct smc_local *lp = netdev_priv(dev);
550 void __iomem *ioaddr = lp->base;
551 struct sk_buff *skb;
552 unsigned int packet_no, len;
553 unsigned char *buf;
554 unsigned long flags;
555
556 DBG(3, "%s: %s\n", dev->name, __func__);
557
558 if (!smc_special_trylock(&lp->lock, flags)) {
559 netif_stop_queue(dev);
560 tasklet_schedule(&lp->tx_task);
561 return;
562 }
563
564 skb = lp->pending_tx_skb;
565 if (unlikely(!skb)) {
566 smc_special_unlock(&lp->lock, flags);
567 return;
568 }
569 lp->pending_tx_skb = NULL;
570
571 packet_no = SMC_GET_AR(lp);
572 if (unlikely(packet_no & AR_FAILED)) {
573 printk("%s: Memory allocation failed.\n", dev->name);
574 dev->stats.tx_errors++;
575 dev->stats.tx_fifo_errors++;
576 smc_special_unlock(&lp->lock, flags);
577 goto done;
578 }
579
580 /* point to the beginning of the packet */
581 SMC_SET_PN(lp, packet_no);
582 SMC_SET_PTR(lp, PTR_AUTOINC);
583
584 buf = skb->data;
585 len = skb->len;
586 DBG(2, "%s: TX PNR 0x%x LENGTH 0x%04x (%d) BUF 0x%p\n",
587 dev->name, packet_no, len, len, buf);
588 PRINT_PKT(buf, len);
589
590 /*
591 * Send the packet length (+6 for status words, length, and ctl.
592 * The card will pad to 64 bytes with zeroes if packet is too small.
593 */
594 SMC_PUT_PKT_HDR(lp, 0, len + 6);
595
596 /* send the actual data */
597 SMC_PUSH_DATA(lp, buf, len & ~1);
598
599 /* Send final ctl word with the last byte if there is one */
600 SMC_outw(((len & 1) ? (0x2000 | buf[len-1]) : 0), ioaddr, DATA_REG(lp));
601
602 /*
603 * If THROTTLE_TX_PKTS is set, we stop the queue here. This will
604 * have the effect of having at most one packet queued for TX
605 * in the chip's memory at all time.
606 *
607 * If THROTTLE_TX_PKTS is not set then the queue is stopped only
608 * when memory allocation (MC_ALLOC) does not succeed right away.
609 */
610 if (THROTTLE_TX_PKTS)
611 netif_stop_queue(dev);
612
613 /* queue the packet for TX */
614 SMC_SET_MMU_CMD(lp, MC_ENQUEUE);
615 smc_special_unlock(&lp->lock, flags);
616
617 dev->trans_start = jiffies;
618 dev->stats.tx_packets++;
619 dev->stats.tx_bytes += len;
620
621 SMC_ENABLE_INT(lp, IM_TX_INT | IM_TX_EMPTY_INT);
622
623done: if (!THROTTLE_TX_PKTS)
624 netif_wake_queue(dev);
625
626 dev_kfree_skb(skb);
627}
628
629/*
630 * Since I am not sure if I will have enough room in the chip's ram
631 * to store the packet, I call this routine which either sends it
632 * now, or set the card to generates an interrupt when ready
633 * for the packet.
634 */
635static int smc_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
636{
637 struct smc_local *lp = netdev_priv(dev);
638 void __iomem *ioaddr = lp->base;
639 unsigned int numPages, poll_count, status;
640 unsigned long flags;
641
642 DBG(3, "%s: %s\n", dev->name, __func__);
643
644 BUG_ON(lp->pending_tx_skb != NULL);
645
646 /*
647 * The MMU wants the number of pages to be the number of 256 bytes
648 * 'pages', minus 1 (since a packet can't ever have 0 pages :))
649 *
650 * The 91C111 ignores the size bits, but earlier models don't.
651 *
652 * Pkt size for allocating is data length +6 (for additional status
653 * words, length and ctl)
654 *
655 * If odd size then last byte is included in ctl word.
656 */
657 numPages = ((skb->len & ~1) + (6 - 1)) >> 8;
658 if (unlikely(numPages > 7)) {
659 printk("%s: Far too big packet error.\n", dev->name);
660 dev->stats.tx_errors++;
661 dev->stats.tx_dropped++;
662 dev_kfree_skb(skb);
663 return NETDEV_TX_OK;
664 }
665
666 smc_special_lock(&lp->lock, flags);
667
668 /* now, try to allocate the memory */
669 SMC_SET_MMU_CMD(lp, MC_ALLOC | numPages);
670
671 /*
672 * Poll the chip for a short amount of time in case the
673 * allocation succeeds quickly.
674 */
675 poll_count = MEMORY_WAIT_TIME;
676 do {
677 status = SMC_GET_INT(lp);
678 if (status & IM_ALLOC_INT) {
679 SMC_ACK_INT(lp, IM_ALLOC_INT);
680 break;
681 }
682 } while (--poll_count);
683
684 smc_special_unlock(&lp->lock, flags);
685
686 lp->pending_tx_skb = skb;
687 if (!poll_count) {
688 /* oh well, wait until the chip finds memory later */
689 netif_stop_queue(dev);
690 DBG(2, "%s: TX memory allocation deferred.\n", dev->name);
691 SMC_ENABLE_INT(lp, IM_ALLOC_INT);
692 } else {
693 /*
694 * Allocation succeeded: push packet to the chip's own memory
695 * immediately.
696 */
697 smc_hardware_send_pkt((unsigned long)dev);
698 }
699
700 return NETDEV_TX_OK;
701}
702
703/*
704 * This handles a TX interrupt, which is only called when:
705 * - a TX error occurred, or
706 * - CTL_AUTO_RELEASE is not set and TX of a packet completed.
707 */
708static void smc_tx(struct net_device *dev)
709{
710 struct smc_local *lp = netdev_priv(dev);
711 void __iomem *ioaddr = lp->base;
712 unsigned int saved_packet, packet_no, tx_status, pkt_len;
713
714 DBG(3, "%s: %s\n", dev->name, __func__);
715
716 /* If the TX FIFO is empty then nothing to do */
717 packet_no = SMC_GET_TXFIFO(lp);
718 if (unlikely(packet_no & TXFIFO_TEMPTY)) {
719 PRINTK("%s: smc_tx with nothing on FIFO.\n", dev->name);
720 return;
721 }
722
723 /* select packet to read from */
724 saved_packet = SMC_GET_PN(lp);
725 SMC_SET_PN(lp, packet_no);
726
727 /* read the first word (status word) from this packet */
728 SMC_SET_PTR(lp, PTR_AUTOINC | PTR_READ);
729 SMC_GET_PKT_HDR(lp, tx_status, pkt_len);
730 DBG(2, "%s: TX STATUS 0x%04x PNR 0x%02x\n",
731 dev->name, tx_status, packet_no);
732
733 if (!(tx_status & ES_TX_SUC))
734 dev->stats.tx_errors++;
735
736 if (tx_status & ES_LOSTCARR)
737 dev->stats.tx_carrier_errors++;
738
739 if (tx_status & (ES_LATCOL | ES_16COL)) {
740 PRINTK("%s: %s occurred on last xmit\n", dev->name,
741 (tx_status & ES_LATCOL) ?
742 "late collision" : "too many collisions");
743 dev->stats.tx_window_errors++;
744 if (!(dev->stats.tx_window_errors & 63) && net_ratelimit()) {
745 printk(KERN_INFO "%s: unexpectedly large number of "
746 "bad collisions. Please check duplex "
747 "setting.\n", dev->name);
748 }
749 }
750
751 /* kill the packet */
752 SMC_WAIT_MMU_BUSY(lp);
753 SMC_SET_MMU_CMD(lp, MC_FREEPKT);
754
755 /* Don't restore Packet Number Reg until busy bit is cleared */
756 SMC_WAIT_MMU_BUSY(lp);
757 SMC_SET_PN(lp, saved_packet);
758
759 /* re-enable transmit */
760 SMC_SELECT_BANK(lp, 0);
761 SMC_SET_TCR(lp, lp->tcr_cur_mode);
762 SMC_SELECT_BANK(lp, 2);
763}
764
765
766/*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
767
768static void smc_mii_out(struct net_device *dev, unsigned int val, int bits)
769{
770 struct smc_local *lp = netdev_priv(dev);
771 void __iomem *ioaddr = lp->base;
772 unsigned int mii_reg, mask;
773
774 mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO);
775 mii_reg |= MII_MDOE;
776
777 for (mask = 1 << (bits - 1); mask; mask >>= 1) {
778 if (val & mask)
779 mii_reg |= MII_MDO;
780 else
781 mii_reg &= ~MII_MDO;
782
783 SMC_SET_MII(lp, mii_reg);
784 udelay(MII_DELAY);
785 SMC_SET_MII(lp, mii_reg | MII_MCLK);
786 udelay(MII_DELAY);
787 }
788}
789
790static unsigned int smc_mii_in(struct net_device *dev, int bits)
791{
792 struct smc_local *lp = netdev_priv(dev);
793 void __iomem *ioaddr = lp->base;
794 unsigned int mii_reg, mask, val;
795
796 mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO);
797 SMC_SET_MII(lp, mii_reg);
798
799 for (mask = 1 << (bits - 1), val = 0; mask; mask >>= 1) {
800 if (SMC_GET_MII(lp) & MII_MDI)
801 val |= mask;
802
803 SMC_SET_MII(lp, mii_reg);
804 udelay(MII_DELAY);
805 SMC_SET_MII(lp, mii_reg | MII_MCLK);
806 udelay(MII_DELAY);
807 }
808
809 return val;
810}
811
812/*
813 * Reads a register from the MII Management serial interface
814 */
815static int smc_phy_read(struct net_device *dev, int phyaddr, int phyreg)
816{
817 struct smc_local *lp = netdev_priv(dev);
818 void __iomem *ioaddr = lp->base;
819 unsigned int phydata;
820
821 SMC_SELECT_BANK(lp, 3);
822
823 /* Idle - 32 ones */
824 smc_mii_out(dev, 0xffffffff, 32);
825
826 /* Start code (01) + read (10) + phyaddr + phyreg */
827 smc_mii_out(dev, 6 << 10 | phyaddr << 5 | phyreg, 14);
828
829 /* Turnaround (2bits) + phydata */
830 phydata = smc_mii_in(dev, 18);
831
832 /* Return to idle state */
833 SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO));
834
835 DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
836 __func__, phyaddr, phyreg, phydata);
837
838 SMC_SELECT_BANK(lp, 2);
839 return phydata;
840}
841
842/*
843 * Writes a register to the MII Management serial interface
844 */
845static void smc_phy_write(struct net_device *dev, int phyaddr, int phyreg,
846 int phydata)
847{
848 struct smc_local *lp = netdev_priv(dev);
849 void __iomem *ioaddr = lp->base;
850
851 SMC_SELECT_BANK(lp, 3);
852
853 /* Idle - 32 ones */
854 smc_mii_out(dev, 0xffffffff, 32);
855
856 /* Start code (01) + write (01) + phyaddr + phyreg + turnaround + phydata */
857 smc_mii_out(dev, 5 << 28 | phyaddr << 23 | phyreg << 18 | 2 << 16 | phydata, 32);
858
859 /* Return to idle state */
860 SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO));
861
862 DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
863 __func__, phyaddr, phyreg, phydata);
864
865 SMC_SELECT_BANK(lp, 2);
866}
867
868/*
869 * Finds and reports the PHY address
870 */
871static void smc_phy_detect(struct net_device *dev)
872{
873 struct smc_local *lp = netdev_priv(dev);
874 int phyaddr;
875
876 DBG(2, "%s: %s\n", dev->name, __func__);
877
878 lp->phy_type = 0;
879
880 /*
881 * Scan all 32 PHY addresses if necessary, starting at
882 * PHY#1 to PHY#31, and then PHY#0 last.
883 */
884 for (phyaddr = 1; phyaddr < 33; ++phyaddr) {
885 unsigned int id1, id2;
886
887 /* Read the PHY identifiers */
888 id1 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID1);
889 id2 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID2);
890
891 DBG(3, "%s: phy_id1=0x%x, phy_id2=0x%x\n",
892 dev->name, id1, id2);
893
894 /* Make sure it is a valid identifier */
895 if (id1 != 0x0000 && id1 != 0xffff && id1 != 0x8000 &&
896 id2 != 0x0000 && id2 != 0xffff && id2 != 0x8000) {
897 /* Save the PHY's address */
898 lp->mii.phy_id = phyaddr & 31;
899 lp->phy_type = id1 << 16 | id2;
900 break;
901 }
902 }
903}
904
905/*
906 * Sets the PHY to a configuration as determined by the user
907 */
908static int smc_phy_fixed(struct net_device *dev)
909{
910 struct smc_local *lp = netdev_priv(dev);
911 void __iomem *ioaddr = lp->base;
912 int phyaddr = lp->mii.phy_id;
913 int bmcr, cfg1;
914
915 DBG(3, "%s: %s\n", dev->name, __func__);
916
917 /* Enter Link Disable state */
918 cfg1 = smc_phy_read(dev, phyaddr, PHY_CFG1_REG);
919 cfg1 |= PHY_CFG1_LNKDIS;
920 smc_phy_write(dev, phyaddr, PHY_CFG1_REG, cfg1);
921
922 /*
923 * Set our fixed capabilities
924 * Disable auto-negotiation
925 */
926 bmcr = 0;
927
928 if (lp->ctl_rfduplx)
929 bmcr |= BMCR_FULLDPLX;
930
931 if (lp->ctl_rspeed == 100)
932 bmcr |= BMCR_SPEED100;
933
934 /* Write our capabilities to the phy control register */
935 smc_phy_write(dev, phyaddr, MII_BMCR, bmcr);
936
937 /* Re-Configure the Receive/Phy Control register */
938 SMC_SELECT_BANK(lp, 0);
939 SMC_SET_RPC(lp, lp->rpc_cur_mode);
940 SMC_SELECT_BANK(lp, 2);
941
942 return 1;
943}
944
945/*
946 * smc_phy_reset - reset the phy
947 * @dev: net device
948 * @phy: phy address
949 *
950 * Issue a software reset for the specified PHY and
951 * wait up to 100ms for the reset to complete. We should
952 * not access the PHY for 50ms after issuing the reset.
953 *
954 * The time to wait appears to be dependent on the PHY.
955 *
956 * Must be called with lp->lock locked.
957 */
958static int smc_phy_reset(struct net_device *dev, int phy)
959{
960 struct smc_local *lp = netdev_priv(dev);
961 unsigned int bmcr;
962 int timeout;
963
964 smc_phy_write(dev, phy, MII_BMCR, BMCR_RESET);
965
966 for (timeout = 2; timeout; timeout--) {
967 spin_unlock_irq(&lp->lock);
968 msleep(50);
969 spin_lock_irq(&lp->lock);
970
971 bmcr = smc_phy_read(dev, phy, MII_BMCR);
972 if (!(bmcr & BMCR_RESET))
973 break;
974 }
975
976 return bmcr & BMCR_RESET;
977}
978
979/*
980 * smc_phy_powerdown - powerdown phy
981 * @dev: net device
982 *
983 * Power down the specified PHY
984 */
985static void smc_phy_powerdown(struct net_device *dev)
986{
987 struct smc_local *lp = netdev_priv(dev);
988 unsigned int bmcr;
989 int phy = lp->mii.phy_id;
990
991 if (lp->phy_type == 0)
992 return;
993
994 /* We need to ensure that no calls to smc_phy_configure are
995 pending.
996 */
997 cancel_work_sync(&lp->phy_configure);
998
999 bmcr = smc_phy_read(dev, phy, MII_BMCR);
1000 smc_phy_write(dev, phy, MII_BMCR, bmcr | BMCR_PDOWN);
1001}
1002
1003/*
1004 * smc_phy_check_media - check the media status and adjust TCR
1005 * @dev: net device
1006 * @init: set true for initialisation
1007 *
1008 * Select duplex mode depending on negotiation state. This
1009 * also updates our carrier state.
1010 */
1011static void smc_phy_check_media(struct net_device *dev, int init)
1012{
1013 struct smc_local *lp = netdev_priv(dev);
1014 void __iomem *ioaddr = lp->base;
1015
1016 if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) {
1017 /* duplex state has changed */
1018 if (lp->mii.full_duplex) {
1019 lp->tcr_cur_mode |= TCR_SWFDUP;
1020 } else {
1021 lp->tcr_cur_mode &= ~TCR_SWFDUP;
1022 }
1023
1024 SMC_SELECT_BANK(lp, 0);
1025 SMC_SET_TCR(lp, lp->tcr_cur_mode);
1026 }
1027}
1028
1029/*
1030 * Configures the specified PHY through the MII management interface
1031 * using Autonegotiation.
1032 * Calls smc_phy_fixed() if the user has requested a certain config.
1033 * If RPC ANEG bit is set, the media selection is dependent purely on
1034 * the selection by the MII (either in the MII BMCR reg or the result
1035 * of autonegotiation.) If the RPC ANEG bit is cleared, the selection
1036 * is controlled by the RPC SPEED and RPC DPLX bits.
1037 */
1038static void smc_phy_configure(struct work_struct *work)
1039{
1040 struct smc_local *lp =
1041 container_of(work, struct smc_local, phy_configure);
1042 struct net_device *dev = lp->dev;
1043 void __iomem *ioaddr = lp->base;
1044 int phyaddr = lp->mii.phy_id;
1045 int my_phy_caps; /* My PHY capabilities */
1046 int my_ad_caps; /* My Advertised capabilities */
1047 int status;
1048
1049 DBG(3, "%s:smc_program_phy()\n", dev->name);
1050
1051 spin_lock_irq(&lp->lock);
1052
1053 /*
1054 * We should not be called if phy_type is zero.
1055 */
1056 if (lp->phy_type == 0)
1057 goto smc_phy_configure_exit;
1058
1059 if (smc_phy_reset(dev, phyaddr)) {
1060 printk("%s: PHY reset timed out\n", dev->name);
1061 goto smc_phy_configure_exit;
1062 }
1063
1064 /*
1065 * Enable PHY Interrupts (for register 18)
1066 * Interrupts listed here are disabled
1067 */
1068 smc_phy_write(dev, phyaddr, PHY_MASK_REG,
1069 PHY_INT_LOSSSYNC | PHY_INT_CWRD | PHY_INT_SSD |
1070 PHY_INT_ESD | PHY_INT_RPOL | PHY_INT_JAB |
1071 PHY_INT_SPDDET | PHY_INT_DPLXDET);
1072
1073 /* Configure the Receive/Phy Control register */
1074 SMC_SELECT_BANK(lp, 0);
1075 SMC_SET_RPC(lp, lp->rpc_cur_mode);
1076
1077 /* If the user requested no auto neg, then go set his request */
1078 if (lp->mii.force_media) {
1079 smc_phy_fixed(dev);
1080 goto smc_phy_configure_exit;
1081 }
1082
1083 /* Copy our capabilities from MII_BMSR to MII_ADVERTISE */
1084 my_phy_caps = smc_phy_read(dev, phyaddr, MII_BMSR);
1085
1086 if (!(my_phy_caps & BMSR_ANEGCAPABLE)) {
1087 printk(KERN_INFO "Auto negotiation NOT supported\n");
1088 smc_phy_fixed(dev);
1089 goto smc_phy_configure_exit;
1090 }
1091
1092 my_ad_caps = ADVERTISE_CSMA; /* I am CSMA capable */
1093
1094 if (my_phy_caps & BMSR_100BASE4)
1095 my_ad_caps |= ADVERTISE_100BASE4;
1096 if (my_phy_caps & BMSR_100FULL)
1097 my_ad_caps |= ADVERTISE_100FULL;
1098 if (my_phy_caps & BMSR_100HALF)
1099 my_ad_caps |= ADVERTISE_100HALF;
1100 if (my_phy_caps & BMSR_10FULL)
1101 my_ad_caps |= ADVERTISE_10FULL;
1102 if (my_phy_caps & BMSR_10HALF)
1103 my_ad_caps |= ADVERTISE_10HALF;
1104
1105 /* Disable capabilities not selected by our user */
1106 if (lp->ctl_rspeed != 100)
1107 my_ad_caps &= ~(ADVERTISE_100BASE4|ADVERTISE_100FULL|ADVERTISE_100HALF);
1108
1109 if (!lp->ctl_rfduplx)
1110 my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL);
1111
1112 /* Update our Auto-Neg Advertisement Register */
1113 smc_phy_write(dev, phyaddr, MII_ADVERTISE, my_ad_caps);
1114 lp->mii.advertising = my_ad_caps;
1115
1116 /*
1117 * Read the register back. Without this, it appears that when
1118 * auto-negotiation is restarted, sometimes it isn't ready and
1119 * the link does not come up.
1120 */
1121 status = smc_phy_read(dev, phyaddr, MII_ADVERTISE);
1122
1123 DBG(2, "%s: phy caps=%x\n", dev->name, my_phy_caps);
1124 DBG(2, "%s: phy advertised caps=%x\n", dev->name, my_ad_caps);
1125
1126 /* Restart auto-negotiation process in order to advertise my caps */
1127 smc_phy_write(dev, phyaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1128
1129 smc_phy_check_media(dev, 1);
1130
1131smc_phy_configure_exit:
1132 SMC_SELECT_BANK(lp, 2);
1133 spin_unlock_irq(&lp->lock);
1134}
1135
1136/*
1137 * smc_phy_interrupt
1138 *
1139 * Purpose: Handle interrupts relating to PHY register 18. This is
1140 * called from the "hard" interrupt handler under our private spinlock.
1141 */
1142static void smc_phy_interrupt(struct net_device *dev)
1143{
1144 struct smc_local *lp = netdev_priv(dev);
1145 int phyaddr = lp->mii.phy_id;
1146 int phy18;
1147
1148 DBG(2, "%s: %s\n", dev->name, __func__);
1149
1150 if (lp->phy_type == 0)
1151 return;
1152
1153 for(;;) {
1154 smc_phy_check_media(dev, 0);
1155
1156 /* Read PHY Register 18, Status Output */
1157 phy18 = smc_phy_read(dev, phyaddr, PHY_INT_REG);
1158 if ((phy18 & PHY_INT_INT) == 0)
1159 break;
1160 }
1161}
1162
1163/*--- END PHY CONTROL AND CONFIGURATION-------------------------------------*/
1164
1165static void smc_10bt_check_media(struct net_device *dev, int init)
1166{
1167 struct smc_local *lp = netdev_priv(dev);
1168 void __iomem *ioaddr = lp->base;
1169 unsigned int old_carrier, new_carrier;
1170
1171 old_carrier = netif_carrier_ok(dev) ? 1 : 0;
1172
1173 SMC_SELECT_BANK(lp, 0);
1174 new_carrier = (SMC_GET_EPH_STATUS(lp) & ES_LINK_OK) ? 1 : 0;
1175 SMC_SELECT_BANK(lp, 2);
1176
1177 if (init || (old_carrier != new_carrier)) {
1178 if (!new_carrier) {
1179 netif_carrier_off(dev);
1180 } else {
1181 netif_carrier_on(dev);
1182 }
1183 if (netif_msg_link(lp))
1184 printk(KERN_INFO "%s: link %s\n", dev->name,
1185 new_carrier ? "up" : "down");
1186 }
1187}
1188
1189static void smc_eph_interrupt(struct net_device *dev)
1190{
1191 struct smc_local *lp = netdev_priv(dev);
1192 void __iomem *ioaddr = lp->base;
1193 unsigned int ctl;
1194
1195 smc_10bt_check_media(dev, 0);
1196
1197 SMC_SELECT_BANK(lp, 1);
1198 ctl = SMC_GET_CTL(lp);
1199 SMC_SET_CTL(lp, ctl & ~CTL_LE_ENABLE);
1200 SMC_SET_CTL(lp, ctl);
1201 SMC_SELECT_BANK(lp, 2);
1202}
1203
1204/*
1205 * This is the main routine of the driver, to handle the device when
1206 * it needs some attention.
1207 */
1208static irqreturn_t smc_interrupt(int irq, void *dev_id)
1209{
1210 struct net_device *dev = dev_id;
1211 struct smc_local *lp = netdev_priv(dev);
1212 void __iomem *ioaddr = lp->base;
1213 int status, mask, timeout, card_stats;
1214 int saved_pointer;
1215
1216 DBG(3, "%s: %s\n", dev->name, __func__);
1217
1218 spin_lock(&lp->lock);
1219
1220 /* A preamble may be used when there is a potential race
1221 * between the interruptible transmit functions and this
1222 * ISR. */
1223 SMC_INTERRUPT_PREAMBLE;
1224
1225 saved_pointer = SMC_GET_PTR(lp);
1226 mask = SMC_GET_INT_MASK(lp);
1227 SMC_SET_INT_MASK(lp, 0);
1228
1229 /* set a timeout value, so I don't stay here forever */
1230 timeout = MAX_IRQ_LOOPS;
1231
1232 do {
1233 status = SMC_GET_INT(lp);
1234
1235 DBG(2, "%s: INT 0x%02x MASK 0x%02x MEM 0x%04x FIFO 0x%04x\n",
1236 dev->name, status, mask,
1237 ({ int meminfo; SMC_SELECT_BANK(lp, 0);
1238 meminfo = SMC_GET_MIR(lp);
1239 SMC_SELECT_BANK(lp, 2); meminfo; }),
1240 SMC_GET_FIFO(lp));
1241
1242 status &= mask;
1243 if (!status)
1244 break;
1245
1246 if (status & IM_TX_INT) {
1247 /* do this before RX as it will free memory quickly */
1248 DBG(3, "%s: TX int\n", dev->name);
1249 smc_tx(dev);
1250 SMC_ACK_INT(lp, IM_TX_INT);
1251 if (THROTTLE_TX_PKTS)
1252 netif_wake_queue(dev);
1253 } else if (status & IM_RCV_INT) {
1254 DBG(3, "%s: RX irq\n", dev->name);
1255 smc_rcv(dev);
1256 } else if (status & IM_ALLOC_INT) {
1257 DBG(3, "%s: Allocation irq\n", dev->name);
1258 tasklet_hi_schedule(&lp->tx_task);
1259 mask &= ~IM_ALLOC_INT;
1260 } else if (status & IM_TX_EMPTY_INT) {
1261 DBG(3, "%s: TX empty\n", dev->name);
1262 mask &= ~IM_TX_EMPTY_INT;
1263
1264 /* update stats */
1265 SMC_SELECT_BANK(lp, 0);
1266 card_stats = SMC_GET_COUNTER(lp);
1267 SMC_SELECT_BANK(lp, 2);
1268
1269 /* single collisions */
1270 dev->stats.collisions += card_stats & 0xF;
1271 card_stats >>= 4;
1272
1273 /* multiple collisions */
1274 dev->stats.collisions += card_stats & 0xF;
1275 } else if (status & IM_RX_OVRN_INT) {
1276 DBG(1, "%s: RX overrun (EPH_ST 0x%04x)\n", dev->name,
1277 ({ int eph_st; SMC_SELECT_BANK(lp, 0);
1278 eph_st = SMC_GET_EPH_STATUS(lp);
1279 SMC_SELECT_BANK(lp, 2); eph_st; }));
1280 SMC_ACK_INT(lp, IM_RX_OVRN_INT);
1281 dev->stats.rx_errors++;
1282 dev->stats.rx_fifo_errors++;
1283 } else if (status & IM_EPH_INT) {
1284 smc_eph_interrupt(dev);
1285 } else if (status & IM_MDINT) {
1286 SMC_ACK_INT(lp, IM_MDINT);
1287 smc_phy_interrupt(dev);
1288 } else if (status & IM_ERCV_INT) {
1289 SMC_ACK_INT(lp, IM_ERCV_INT);
1290 PRINTK("%s: UNSUPPORTED: ERCV INTERRUPT\n", dev->name);
1291 }
1292 } while (--timeout);
1293
1294 /* restore register states */
1295 SMC_SET_PTR(lp, saved_pointer);
1296 SMC_SET_INT_MASK(lp, mask);
1297 spin_unlock(&lp->lock);
1298
1299#ifndef CONFIG_NET_POLL_CONTROLLER
1300 if (timeout == MAX_IRQ_LOOPS)
1301 PRINTK("%s: spurious interrupt (mask = 0x%02x)\n",
1302 dev->name, mask);
1303#endif
1304 DBG(3, "%s: Interrupt done (%d loops)\n",
1305 dev->name, MAX_IRQ_LOOPS - timeout);
1306
1307 /*
1308 * We return IRQ_HANDLED unconditionally here even if there was
1309 * nothing to do. There is a possibility that a packet might
1310 * get enqueued into the chip right after TX_EMPTY_INT is raised
1311 * but just before the CPU acknowledges the IRQ.
1312 * Better take an unneeded IRQ in some occasions than complexifying
1313 * the code for all cases.
1314 */
1315 return IRQ_HANDLED;
1316}
1317
1318#ifdef CONFIG_NET_POLL_CONTROLLER
1319/*
1320 * Polling receive - used by netconsole and other diagnostic tools
1321 * to allow network i/o with interrupts disabled.
1322 */
1323static void smc_poll_controller(struct net_device *dev)
1324{
1325 disable_irq(dev->irq);
1326 smc_interrupt(dev->irq, dev);
1327 enable_irq(dev->irq);
1328}
1329#endif
1330
1331/* Our watchdog timed out. Called by the networking layer */
1332static void smc_timeout(struct net_device *dev)
1333{
1334 struct smc_local *lp = netdev_priv(dev);
1335 void __iomem *ioaddr = lp->base;
1336 int status, mask, eph_st, meminfo, fifo;
1337
1338 DBG(2, "%s: %s\n", dev->name, __func__);
1339
1340 spin_lock_irq(&lp->lock);
1341 status = SMC_GET_INT(lp);
1342 mask = SMC_GET_INT_MASK(lp);
1343 fifo = SMC_GET_FIFO(lp);
1344 SMC_SELECT_BANK(lp, 0);
1345 eph_st = SMC_GET_EPH_STATUS(lp);
1346 meminfo = SMC_GET_MIR(lp);
1347 SMC_SELECT_BANK(lp, 2);
1348 spin_unlock_irq(&lp->lock);
1349 PRINTK( "%s: TX timeout (INT 0x%02x INTMASK 0x%02x "
1350 "MEM 0x%04x FIFO 0x%04x EPH_ST 0x%04x)\n",
1351 dev->name, status, mask, meminfo, fifo, eph_st );
1352
1353 smc_reset(dev);
1354 smc_enable(dev);
1355
1356 /*
1357 * Reconfiguring the PHY doesn't seem like a bad idea here, but
1358 * smc_phy_configure() calls msleep() which calls schedule_timeout()
1359 * which calls schedule(). Hence we use a work queue.
1360 */
1361 if (lp->phy_type != 0)
1362 schedule_work(&lp->phy_configure);
1363
1364 /* We can accept TX packets again */
1365 dev->trans_start = jiffies; /* prevent tx timeout */
1366 netif_wake_queue(dev);
1367}
1368
1369/*
1370 * This routine will, depending on the values passed to it,
1371 * either make it accept multicast packets, go into
1372 * promiscuous mode (for TCPDUMP and cousins) or accept
1373 * a select set of multicast packets
1374 */
1375static void smc_set_multicast_list(struct net_device *dev)
1376{
1377 struct smc_local *lp = netdev_priv(dev);
1378 void __iomem *ioaddr = lp->base;
1379 unsigned char multicast_table[8];
1380 int update_multicast = 0;
1381
1382 DBG(2, "%s: %s\n", dev->name, __func__);
1383
1384 if (dev->flags & IFF_PROMISC) {
1385 DBG(2, "%s: RCR_PRMS\n", dev->name);
1386 lp->rcr_cur_mode |= RCR_PRMS;
1387 }
1388
1389/* BUG? I never disable promiscuous mode if multicasting was turned on.
1390 Now, I turn off promiscuous mode, but I don't do anything to multicasting
1391 when promiscuous mode is turned on.
1392*/
1393
1394 /*
1395 * Here, I am setting this to accept all multicast packets.
1396 * I don't need to zero the multicast table, because the flag is
1397 * checked before the table is
1398 */
1399 else if (dev->flags & IFF_ALLMULTI || netdev_mc_count(dev) > 16) {
1400 DBG(2, "%s: RCR_ALMUL\n", dev->name);
1401 lp->rcr_cur_mode |= RCR_ALMUL;
1402 }
1403
1404 /*
1405 * This sets the internal hardware table to filter out unwanted
1406 * multicast packets before they take up memory.
1407 *
1408 * The SMC chip uses a hash table where the high 6 bits of the CRC of
1409 * address are the offset into the table. If that bit is 1, then the
1410 * multicast packet is accepted. Otherwise, it's dropped silently.
1411 *
1412 * To use the 6 bits as an offset into the table, the high 3 bits are
1413 * the number of the 8 bit register, while the low 3 bits are the bit
1414 * within that register.
1415 */
1416 else if (!netdev_mc_empty(dev)) {
1417 struct netdev_hw_addr *ha;
1418
1419 /* table for flipping the order of 3 bits */
1420 static const unsigned char invert3[] = {0, 4, 2, 6, 1, 5, 3, 7};
1421
1422 /* start with a table of all zeros: reject all */
1423 memset(multicast_table, 0, sizeof(multicast_table));
1424
1425 netdev_for_each_mc_addr(ha, dev) {
1426 int position;
1427
1428 /* only use the low order bits */
1429 position = crc32_le(~0, ha->addr, 6) & 0x3f;
1430
1431 /* do some messy swapping to put the bit in the right spot */
1432 multicast_table[invert3[position&7]] |=
1433 (1<<invert3[(position>>3)&7]);
1434 }
1435
1436 /* be sure I get rid of flags I might have set */
1437 lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL);
1438
1439 /* now, the table can be loaded into the chipset */
1440 update_multicast = 1;
1441 } else {
1442 DBG(2, "%s: ~(RCR_PRMS|RCR_ALMUL)\n", dev->name);
1443 lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL);
1444
1445 /*
1446 * since I'm disabling all multicast entirely, I need to
1447 * clear the multicast list
1448 */
1449 memset(multicast_table, 0, sizeof(multicast_table));
1450 update_multicast = 1;
1451 }
1452
1453 spin_lock_irq(&lp->lock);
1454 SMC_SELECT_BANK(lp, 0);
1455 SMC_SET_RCR(lp, lp->rcr_cur_mode);
1456 if (update_multicast) {
1457 SMC_SELECT_BANK(lp, 3);
1458 SMC_SET_MCAST(lp, multicast_table);
1459 }
1460 SMC_SELECT_BANK(lp, 2);
1461 spin_unlock_irq(&lp->lock);
1462}
1463
1464
1465/*
1466 * Open and Initialize the board
1467 *
1468 * Set up everything, reset the card, etc..
1469 */
1470static int
1471smc_open(struct net_device *dev)
1472{
1473 struct smc_local *lp = netdev_priv(dev);
1474
1475 DBG(2, "%s: %s\n", dev->name, __func__);
1476
1477 /*
1478 * Check that the address is valid. If its not, refuse
1479 * to bring the device up. The user must specify an
1480 * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
1481 */
1482 if (!is_valid_ether_addr(dev->dev_addr)) {
1483 PRINTK("%s: no valid ethernet hw addr\n", __func__);
1484 return -EINVAL;
1485 }
1486
1487 /* Setup the default Register Modes */
1488 lp->tcr_cur_mode = TCR_DEFAULT;
1489 lp->rcr_cur_mode = RCR_DEFAULT;
1490 lp->rpc_cur_mode = RPC_DEFAULT |
1491 lp->cfg.leda << RPC_LSXA_SHFT |
1492 lp->cfg.ledb << RPC_LSXB_SHFT;
1493
1494 /*
1495 * If we are not using a MII interface, we need to
1496 * monitor our own carrier signal to detect faults.
1497 */
1498 if (lp->phy_type == 0)
1499 lp->tcr_cur_mode |= TCR_MON_CSN;
1500
1501 /* reset the hardware */
1502 smc_reset(dev);
1503 smc_enable(dev);
1504
1505 /* Configure the PHY, initialize the link state */
1506 if (lp->phy_type != 0)
1507 smc_phy_configure(&lp->phy_configure);
1508 else {
1509 spin_lock_irq(&lp->lock);
1510 smc_10bt_check_media(dev, 1);
1511 spin_unlock_irq(&lp->lock);
1512 }
1513
1514 netif_start_queue(dev);
1515 return 0;
1516}
1517
1518/*
1519 * smc_close
1520 *
1521 * this makes the board clean up everything that it can
1522 * and not talk to the outside world. Caused by
1523 * an 'ifconfig ethX down'
1524 */
1525static int smc_close(struct net_device *dev)
1526{
1527 struct smc_local *lp = netdev_priv(dev);
1528
1529 DBG(2, "%s: %s\n", dev->name, __func__);
1530
1531 netif_stop_queue(dev);
1532 netif_carrier_off(dev);
1533
1534 /* clear everything */
1535 smc_shutdown(dev);
1536 tasklet_kill(&lp->tx_task);
1537 smc_phy_powerdown(dev);
1538 return 0;
1539}
1540
1541/*
1542 * Ethtool support
1543 */
1544static int
1545smc_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1546{
1547 struct smc_local *lp = netdev_priv(dev);
1548 int ret;
1549
1550 cmd->maxtxpkt = 1;
1551 cmd->maxrxpkt = 1;
1552
1553 if (lp->phy_type != 0) {
1554 spin_lock_irq(&lp->lock);
1555 ret = mii_ethtool_gset(&lp->mii, cmd);
1556 spin_unlock_irq(&lp->lock);
1557 } else {
1558 cmd->supported = SUPPORTED_10baseT_Half |
1559 SUPPORTED_10baseT_Full |
1560 SUPPORTED_TP | SUPPORTED_AUI;
1561
1562 if (lp->ctl_rspeed == 10)
1563 ethtool_cmd_speed_set(cmd, SPEED_10);
1564 else if (lp->ctl_rspeed == 100)
1565 ethtool_cmd_speed_set(cmd, SPEED_100);
1566
1567 cmd->autoneg = AUTONEG_DISABLE;
1568 cmd->transceiver = XCVR_INTERNAL;
1569 cmd->port = 0;
1570 cmd->duplex = lp->tcr_cur_mode & TCR_SWFDUP ? DUPLEX_FULL : DUPLEX_HALF;
1571
1572 ret = 0;
1573 }
1574
1575 return ret;
1576}
1577
1578static int
1579smc_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1580{
1581 struct smc_local *lp = netdev_priv(dev);
1582 int ret;
1583
1584 if (lp->phy_type != 0) {
1585 spin_lock_irq(&lp->lock);
1586 ret = mii_ethtool_sset(&lp->mii, cmd);
1587 spin_unlock_irq(&lp->lock);
1588 } else {
1589 if (cmd->autoneg != AUTONEG_DISABLE ||
1590 cmd->speed != SPEED_10 ||
1591 (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL) ||
1592 (cmd->port != PORT_TP && cmd->port != PORT_AUI))
1593 return -EINVAL;
1594
1595// lp->port = cmd->port;
1596 lp->ctl_rfduplx = cmd->duplex == DUPLEX_FULL;
1597
1598// if (netif_running(dev))
1599// smc_set_port(dev);
1600
1601 ret = 0;
1602 }
1603
1604 return ret;
1605}
1606
1607static void
1608smc_ethtool_getdrvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1609{
1610 strncpy(info->driver, CARDNAME, sizeof(info->driver));
1611 strncpy(info->version, version, sizeof(info->version));
1612 strncpy(info->bus_info, dev_name(dev->dev.parent), sizeof(info->bus_info));
1613}
1614
1615static int smc_ethtool_nwayreset(struct net_device *dev)
1616{
1617 struct smc_local *lp = netdev_priv(dev);
1618 int ret = -EINVAL;
1619
1620 if (lp->phy_type != 0) {
1621 spin_lock_irq(&lp->lock);
1622 ret = mii_nway_restart(&lp->mii);
1623 spin_unlock_irq(&lp->lock);
1624 }
1625
1626 return ret;
1627}
1628
1629static u32 smc_ethtool_getmsglevel(struct net_device *dev)
1630{
1631 struct smc_local *lp = netdev_priv(dev);
1632 return lp->msg_enable;
1633}
1634
1635static void smc_ethtool_setmsglevel(struct net_device *dev, u32 level)
1636{
1637 struct smc_local *lp = netdev_priv(dev);
1638 lp->msg_enable = level;
1639}
1640
1641static int smc_write_eeprom_word(struct net_device *dev, u16 addr, u16 word)
1642{
1643 u16 ctl;
1644 struct smc_local *lp = netdev_priv(dev);
1645 void __iomem *ioaddr = lp->base;
1646
1647 spin_lock_irq(&lp->lock);
1648 /* load word into GP register */
1649 SMC_SELECT_BANK(lp, 1);
1650 SMC_SET_GP(lp, word);
1651 /* set the address to put the data in EEPROM */
1652 SMC_SELECT_BANK(lp, 2);
1653 SMC_SET_PTR(lp, addr);
1654 /* tell it to write */
1655 SMC_SELECT_BANK(lp, 1);
1656 ctl = SMC_GET_CTL(lp);
1657 SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_STORE));
1658 /* wait for it to finish */
1659 do {
1660 udelay(1);
1661 } while (SMC_GET_CTL(lp) & CTL_STORE);
1662 /* clean up */
1663 SMC_SET_CTL(lp, ctl);
1664 SMC_SELECT_BANK(lp, 2);
1665 spin_unlock_irq(&lp->lock);
1666 return 0;
1667}
1668
1669static int smc_read_eeprom_word(struct net_device *dev, u16 addr, u16 *word)
1670{
1671 u16 ctl;
1672 struct smc_local *lp = netdev_priv(dev);
1673 void __iomem *ioaddr = lp->base;
1674
1675 spin_lock_irq(&lp->lock);
1676 /* set the EEPROM address to get the data from */
1677 SMC_SELECT_BANK(lp, 2);
1678 SMC_SET_PTR(lp, addr | PTR_READ);
1679 /* tell it to load */
1680 SMC_SELECT_BANK(lp, 1);
1681 SMC_SET_GP(lp, 0xffff); /* init to known */
1682 ctl = SMC_GET_CTL(lp);
1683 SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_RELOAD));
1684 /* wait for it to finish */
1685 do {
1686 udelay(1);
1687 } while (SMC_GET_CTL(lp) & CTL_RELOAD);
1688 /* read word from GP register */
1689 *word = SMC_GET_GP(lp);
1690 /* clean up */
1691 SMC_SET_CTL(lp, ctl);
1692 SMC_SELECT_BANK(lp, 2);
1693 spin_unlock_irq(&lp->lock);
1694 return 0;
1695}
1696
1697static int smc_ethtool_geteeprom_len(struct net_device *dev)
1698{
1699 return 0x23 * 2;
1700}
1701
1702static int smc_ethtool_geteeprom(struct net_device *dev,
1703 struct ethtool_eeprom *eeprom, u8 *data)
1704{
1705 int i;
1706 int imax;
1707
1708 DBG(1, "Reading %d bytes at %d(0x%x)\n",
1709 eeprom->len, eeprom->offset, eeprom->offset);
1710 imax = smc_ethtool_geteeprom_len(dev);
1711 for (i = 0; i < eeprom->len; i += 2) {
1712 int ret;
1713 u16 wbuf;
1714 int offset = i + eeprom->offset;
1715 if (offset > imax)
1716 break;
1717 ret = smc_read_eeprom_word(dev, offset >> 1, &wbuf);
1718 if (ret != 0)
1719 return ret;
1720 DBG(2, "Read 0x%x from 0x%x\n", wbuf, offset >> 1);
1721 data[i] = (wbuf >> 8) & 0xff;
1722 data[i+1] = wbuf & 0xff;
1723 }
1724 return 0;
1725}
1726
1727static int smc_ethtool_seteeprom(struct net_device *dev,
1728 struct ethtool_eeprom *eeprom, u8 *data)
1729{
1730 int i;
1731 int imax;
1732
1733 DBG(1, "Writing %d bytes to %d(0x%x)\n",
1734 eeprom->len, eeprom->offset, eeprom->offset);
1735 imax = smc_ethtool_geteeprom_len(dev);
1736 for (i = 0; i < eeprom->len; i += 2) {
1737 int ret;
1738 u16 wbuf;
1739 int offset = i + eeprom->offset;
1740 if (offset > imax)
1741 break;
1742 wbuf = (data[i] << 8) | data[i + 1];
1743 DBG(2, "Writing 0x%x to 0x%x\n", wbuf, offset >> 1);
1744 ret = smc_write_eeprom_word(dev, offset >> 1, wbuf);
1745 if (ret != 0)
1746 return ret;
1747 }
1748 return 0;
1749}
1750
1751
1752static const struct ethtool_ops smc_ethtool_ops = {
1753 .get_settings = smc_ethtool_getsettings,
1754 .set_settings = smc_ethtool_setsettings,
1755 .get_drvinfo = smc_ethtool_getdrvinfo,
1756
1757 .get_msglevel = smc_ethtool_getmsglevel,
1758 .set_msglevel = smc_ethtool_setmsglevel,
1759 .nway_reset = smc_ethtool_nwayreset,
1760 .get_link = ethtool_op_get_link,
1761 .get_eeprom_len = smc_ethtool_geteeprom_len,
1762 .get_eeprom = smc_ethtool_geteeprom,
1763 .set_eeprom = smc_ethtool_seteeprom,
1764};
1765
1766static const struct net_device_ops smc_netdev_ops = {
1767 .ndo_open = smc_open,
1768 .ndo_stop = smc_close,
1769 .ndo_start_xmit = smc_hard_start_xmit,
1770 .ndo_tx_timeout = smc_timeout,
1771 .ndo_set_multicast_list = smc_set_multicast_list,
1772 .ndo_change_mtu = eth_change_mtu,
1773 .ndo_validate_addr = eth_validate_addr,
1774 .ndo_set_mac_address = eth_mac_addr,
1775#ifdef CONFIG_NET_POLL_CONTROLLER
1776 .ndo_poll_controller = smc_poll_controller,
1777#endif
1778};
1779
1780/*
1781 * smc_findirq
1782 *
1783 * This routine has a simple purpose -- make the SMC chip generate an
1784 * interrupt, so an auto-detect routine can detect it, and find the IRQ,
1785 */
1786/*
1787 * does this still work?
1788 *
1789 * I just deleted auto_irq.c, since it was never built...
1790 * --jgarzik
1791 */
1792static int __devinit smc_findirq(struct smc_local *lp)
1793{
1794 void __iomem *ioaddr = lp->base;
1795 int timeout = 20;
1796 unsigned long cookie;
1797
1798 DBG(2, "%s: %s\n", CARDNAME, __func__);
1799
1800 cookie = probe_irq_on();
1801
1802 /*
1803 * What I try to do here is trigger an ALLOC_INT. This is done
1804 * by allocating a small chunk of memory, which will give an interrupt
1805 * when done.
1806 */
1807 /* enable ALLOCation interrupts ONLY */
1808 SMC_SELECT_BANK(lp, 2);
1809 SMC_SET_INT_MASK(lp, IM_ALLOC_INT);
1810
1811 /*
1812 * Allocate 512 bytes of memory. Note that the chip was just
1813 * reset so all the memory is available
1814 */
1815 SMC_SET_MMU_CMD(lp, MC_ALLOC | 1);
1816
1817 /*
1818 * Wait until positive that the interrupt has been generated
1819 */
1820 do {
1821 int int_status;
1822 udelay(10);
1823 int_status = SMC_GET_INT(lp);
1824 if (int_status & IM_ALLOC_INT)
1825 break; /* got the interrupt */
1826 } while (--timeout);
1827
1828 /*
1829 * there is really nothing that I can do here if timeout fails,
1830 * as autoirq_report will return a 0 anyway, which is what I
1831 * want in this case. Plus, the clean up is needed in both
1832 * cases.
1833 */
1834
1835 /* and disable all interrupts again */
1836 SMC_SET_INT_MASK(lp, 0);
1837
1838 /* and return what I found */
1839 return probe_irq_off(cookie);
1840}
1841
1842/*
1843 * Function: smc_probe(unsigned long ioaddr)
1844 *
1845 * Purpose:
1846 * Tests to see if a given ioaddr points to an SMC91x chip.
1847 * Returns a 0 on success
1848 *
1849 * Algorithm:
1850 * (1) see if the high byte of BANK_SELECT is 0x33
1851 * (2) compare the ioaddr with the base register's address
1852 * (3) see if I recognize the chip ID in the appropriate register
1853 *
1854 * Here I do typical initialization tasks.
1855 *
1856 * o Initialize the structure if needed
1857 * o print out my vanity message if not done so already
1858 * o print out what type of hardware is detected
1859 * o print out the ethernet address
1860 * o find the IRQ
1861 * o set up my private data
1862 * o configure the dev structure with my subroutines
1863 * o actually GRAB the irq.
1864 * o GRAB the region
1865 */
1866static int __devinit smc_probe(struct net_device *dev, void __iomem *ioaddr,
1867 unsigned long irq_flags)
1868{
1869 struct smc_local *lp = netdev_priv(dev);
1870 static int version_printed = 0;
1871 int retval;
1872 unsigned int val, revision_register;
1873 const char *version_string;
1874
1875 DBG(2, "%s: %s\n", CARDNAME, __func__);
1876
1877 /* First, see if the high byte is 0x33 */
1878 val = SMC_CURRENT_BANK(lp);
1879 DBG(2, "%s: bank signature probe returned 0x%04x\n", CARDNAME, val);
1880 if ((val & 0xFF00) != 0x3300) {
1881 if ((val & 0xFF) == 0x33) {
1882 printk(KERN_WARNING
1883 "%s: Detected possible byte-swapped interface"
1884 " at IOADDR %p\n", CARDNAME, ioaddr);
1885 }
1886 retval = -ENODEV;
1887 goto err_out;
1888 }
1889
1890 /*
1891 * The above MIGHT indicate a device, but I need to write to
1892 * further test this.
1893 */
1894 SMC_SELECT_BANK(lp, 0);
1895 val = SMC_CURRENT_BANK(lp);
1896 if ((val & 0xFF00) != 0x3300) {
1897 retval = -ENODEV;
1898 goto err_out;
1899 }
1900
1901 /*
1902 * well, we've already written once, so hopefully another
1903 * time won't hurt. This time, I need to switch the bank
1904 * register to bank 1, so I can access the base address
1905 * register
1906 */
1907 SMC_SELECT_BANK(lp, 1);
1908 val = SMC_GET_BASE(lp);
1909 val = ((val & 0x1F00) >> 3) << SMC_IO_SHIFT;
1910 if (((unsigned int)ioaddr & (0x3e0 << SMC_IO_SHIFT)) != val) {
1911 printk("%s: IOADDR %p doesn't match configuration (%x).\n",
1912 CARDNAME, ioaddr, val);
1913 }
1914
1915 /*
1916 * check if the revision register is something that I
1917 * recognize. These might need to be added to later,
1918 * as future revisions could be added.
1919 */
1920 SMC_SELECT_BANK(lp, 3);
1921 revision_register = SMC_GET_REV(lp);
1922 DBG(2, "%s: revision = 0x%04x\n", CARDNAME, revision_register);
1923 version_string = chip_ids[ (revision_register >> 4) & 0xF];
1924 if (!version_string || (revision_register & 0xff00) != 0x3300) {
1925 /* I don't recognize this chip, so... */
1926 printk("%s: IO %p: Unrecognized revision register 0x%04x"
1927 ", Contact author.\n", CARDNAME,
1928 ioaddr, revision_register);
1929
1930 retval = -ENODEV;
1931 goto err_out;
1932 }
1933
1934 /* At this point I'll assume that the chip is an SMC91x. */
1935 if (version_printed++ == 0)
1936 printk("%s", version);
1937
1938 /* fill in some of the fields */
1939 dev->base_addr = (unsigned long)ioaddr;
1940 lp->base = ioaddr;
1941 lp->version = revision_register & 0xff;
1942 spin_lock_init(&lp->lock);
1943
1944 /* Get the MAC address */
1945 SMC_SELECT_BANK(lp, 1);
1946 SMC_GET_MAC_ADDR(lp, dev->dev_addr);
1947
1948 /* now, reset the chip, and put it into a known state */
1949 smc_reset(dev);
1950
1951 /*
1952 * If dev->irq is 0, then the device has to be banged on to see
1953 * what the IRQ is.
1954 *
1955 * This banging doesn't always detect the IRQ, for unknown reasons.
1956 * a workaround is to reset the chip and try again.
1957 *
1958 * Interestingly, the DOS packet driver *SETS* the IRQ on the card to
1959 * be what is requested on the command line. I don't do that, mostly
1960 * because the card that I have uses a non-standard method of accessing
1961 * the IRQs, and because this _should_ work in most configurations.
1962 *
1963 * Specifying an IRQ is done with the assumption that the user knows
1964 * what (s)he is doing. No checking is done!!!!
1965 */
1966 if (dev->irq < 1) {
1967 int trials;
1968
1969 trials = 3;
1970 while (trials--) {
1971 dev->irq = smc_findirq(lp);
1972 if (dev->irq)
1973 break;
1974 /* kick the card and try again */
1975 smc_reset(dev);
1976 }
1977 }
1978 if (dev->irq == 0) {
1979 printk("%s: Couldn't autodetect your IRQ. Use irq=xx.\n",
1980 dev->name);
1981 retval = -ENODEV;
1982 goto err_out;
1983 }
1984 dev->irq = irq_canonicalize(dev->irq);
1985
1986 /* Fill in the fields of the device structure with ethernet values. */
1987 ether_setup(dev);
1988
1989 dev->watchdog_timeo = msecs_to_jiffies(watchdog);
1990 dev->netdev_ops = &smc_netdev_ops;
1991 dev->ethtool_ops = &smc_ethtool_ops;
1992
1993 tasklet_init(&lp->tx_task, smc_hardware_send_pkt, (unsigned long)dev);
1994 INIT_WORK(&lp->phy_configure, smc_phy_configure);
1995 lp->dev = dev;
1996 lp->mii.phy_id_mask = 0x1f;
1997 lp->mii.reg_num_mask = 0x1f;
1998 lp->mii.force_media = 0;
1999 lp->mii.full_duplex = 0;
2000 lp->mii.dev = dev;
2001 lp->mii.mdio_read = smc_phy_read;
2002 lp->mii.mdio_write = smc_phy_write;
2003
2004 /*
2005 * Locate the phy, if any.
2006 */
2007 if (lp->version >= (CHIP_91100 << 4))
2008 smc_phy_detect(dev);
2009
2010 /* then shut everything down to save power */
2011 smc_shutdown(dev);
2012 smc_phy_powerdown(dev);
2013
2014 /* Set default parameters */
2015 lp->msg_enable = NETIF_MSG_LINK;
2016 lp->ctl_rfduplx = 0;
2017 lp->ctl_rspeed = 10;
2018
2019 if (lp->version >= (CHIP_91100 << 4)) {
2020 lp->ctl_rfduplx = 1;
2021 lp->ctl_rspeed = 100;
2022 }
2023
2024 /* Grab the IRQ */
2025 retval = request_irq(dev->irq, smc_interrupt, irq_flags, dev->name, dev);
2026 if (retval)
2027 goto err_out;
2028
2029#ifdef CONFIG_ARCH_PXA
2030# ifdef SMC_USE_PXA_DMA
2031 lp->cfg.flags |= SMC91X_USE_DMA;
2032# endif
2033 if (lp->cfg.flags & SMC91X_USE_DMA) {
2034 int dma = pxa_request_dma(dev->name, DMA_PRIO_LOW,
2035 smc_pxa_dma_irq, NULL);
2036 if (dma >= 0)
2037 dev->dma = dma;
2038 }
2039#endif
2040
2041 retval = register_netdev(dev);
2042 if (retval == 0) {
2043 /* now, print out the card info, in a short format.. */
2044 printk("%s: %s (rev %d) at %p IRQ %d",
2045 dev->name, version_string, revision_register & 0x0f,
2046 lp->base, dev->irq);
2047
2048 if (dev->dma != (unsigned char)-1)
2049 printk(" DMA %d", dev->dma);
2050
2051 printk("%s%s\n",
2052 lp->cfg.flags & SMC91X_NOWAIT ? " [nowait]" : "",
2053 THROTTLE_TX_PKTS ? " [throttle_tx]" : "");
2054
2055 if (!is_valid_ether_addr(dev->dev_addr)) {
2056 printk("%s: Invalid ethernet MAC address. Please "
2057 "set using ifconfig\n", dev->name);
2058 } else {
2059 /* Print the Ethernet address */
2060 printk("%s: Ethernet addr: %pM\n",
2061 dev->name, dev->dev_addr);
2062 }
2063
2064 if (lp->phy_type == 0) {
2065 PRINTK("%s: No PHY found\n", dev->name);
2066 } else if ((lp->phy_type & 0xfffffff0) == 0x0016f840) {
2067 PRINTK("%s: PHY LAN83C183 (LAN91C111 Internal)\n", dev->name);
2068 } else if ((lp->phy_type & 0xfffffff0) == 0x02821c50) {
2069 PRINTK("%s: PHY LAN83C180\n", dev->name);
2070 }
2071 }
2072
2073err_out:
2074#ifdef CONFIG_ARCH_PXA
2075 if (retval && dev->dma != (unsigned char)-1)
2076 pxa_free_dma(dev->dma);
2077#endif
2078 return retval;
2079}
2080
2081static int smc_enable_device(struct platform_device *pdev)
2082{
2083 struct net_device *ndev = platform_get_drvdata(pdev);
2084 struct smc_local *lp = netdev_priv(ndev);
2085 unsigned long flags;
2086 unsigned char ecor, ecsr;
2087 void __iomem *addr;
2088 struct resource * res;
2089
2090 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib");
2091 if (!res)
2092 return 0;
2093
2094 /*
2095 * Map the attribute space. This is overkill, but clean.
2096 */
2097 addr = ioremap(res->start, ATTRIB_SIZE);
2098 if (!addr)
2099 return -ENOMEM;
2100
2101 /*
2102 * Reset the device. We must disable IRQs around this
2103 * since a reset causes the IRQ line become active.
2104 */
2105 local_irq_save(flags);
2106 ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET;
2107 writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT));
2108 readb(addr + (ECOR << SMC_IO_SHIFT));
2109
2110 /*
2111 * Wait 100us for the chip to reset.
2112 */
2113 udelay(100);
2114
2115 /*
2116 * The device will ignore all writes to the enable bit while
2117 * reset is asserted, even if the reset bit is cleared in the
2118 * same write. Must clear reset first, then enable the device.
2119 */
2120 writeb(ecor, addr + (ECOR << SMC_IO_SHIFT));
2121 writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT));
2122
2123 /*
2124 * Set the appropriate byte/word mode.
2125 */
2126 ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8;
2127 if (!SMC_16BIT(lp))
2128 ecsr |= ECSR_IOIS8;
2129 writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT));
2130 local_irq_restore(flags);
2131
2132 iounmap(addr);
2133
2134 /*
2135 * Wait for the chip to wake up. We could poll the control
2136 * register in the main register space, but that isn't mapped
2137 * yet. We know this is going to take 750us.
2138 */
2139 msleep(1);
2140
2141 return 0;
2142}
2143
2144static int smc_request_attrib(struct platform_device *pdev,
2145 struct net_device *ndev)
2146{
2147 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib");
2148 struct smc_local *lp __maybe_unused = netdev_priv(ndev);
2149
2150 if (!res)
2151 return 0;
2152
2153 if (!request_mem_region(res->start, ATTRIB_SIZE, CARDNAME))
2154 return -EBUSY;
2155
2156 return 0;
2157}
2158
2159static void smc_release_attrib(struct platform_device *pdev,
2160 struct net_device *ndev)
2161{
2162 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib");
2163 struct smc_local *lp __maybe_unused = netdev_priv(ndev);
2164
2165 if (res)
2166 release_mem_region(res->start, ATTRIB_SIZE);
2167}
2168
2169static inline void smc_request_datacs(struct platform_device *pdev, struct net_device *ndev)
2170{
2171 if (SMC_CAN_USE_DATACS) {
2172 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32");
2173 struct smc_local *lp = netdev_priv(ndev);
2174
2175 if (!res)
2176 return;
2177
2178 if(!request_mem_region(res->start, SMC_DATA_EXTENT, CARDNAME)) {
2179 printk(KERN_INFO "%s: failed to request datacs memory region.\n", CARDNAME);
2180 return;
2181 }
2182
2183 lp->datacs = ioremap(res->start, SMC_DATA_EXTENT);
2184 }
2185}
2186
2187static void smc_release_datacs(struct platform_device *pdev, struct net_device *ndev)
2188{
2189 if (SMC_CAN_USE_DATACS) {
2190 struct smc_local *lp = netdev_priv(ndev);
2191 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32");
2192
2193 if (lp->datacs)
2194 iounmap(lp->datacs);
2195
2196 lp->datacs = NULL;
2197
2198 if (res)
2199 release_mem_region(res->start, SMC_DATA_EXTENT);
2200 }
2201}
2202
2203/*
2204 * smc_init(void)
2205 * Input parameters:
2206 * dev->base_addr == 0, try to find all possible locations
2207 * dev->base_addr > 0x1ff, this is the address to check
2208 * dev->base_addr == <anything else>, return failure code
2209 *
2210 * Output:
2211 * 0 --> there is a device
2212 * anything else, error
2213 */
2214static int __devinit smc_drv_probe(struct platform_device *pdev)
2215{
2216 struct smc91x_platdata *pd = pdev->dev.platform_data;
2217 struct smc_local *lp;
2218 struct net_device *ndev;
2219 struct resource *res, *ires;
2220 unsigned int __iomem *addr;
2221 unsigned long irq_flags = SMC_IRQ_FLAGS;
2222 int ret;
2223
2224 ndev = alloc_etherdev(sizeof(struct smc_local));
2225 if (!ndev) {
2226 printk("%s: could not allocate device.\n", CARDNAME);
2227 ret = -ENOMEM;
2228 goto out;
2229 }
2230 SET_NETDEV_DEV(ndev, &pdev->dev);
2231
2232 /* get configuration from platform data, only allow use of
2233 * bus width if both SMC_CAN_USE_xxx and SMC91X_USE_xxx are set.
2234 */
2235
2236 lp = netdev_priv(ndev);
2237
2238 if (pd) {
2239 memcpy(&lp->cfg, pd, sizeof(lp->cfg));
2240 lp->io_shift = SMC91X_IO_SHIFT(lp->cfg.flags);
2241 } else {
2242 lp->cfg.flags |= (SMC_CAN_USE_8BIT) ? SMC91X_USE_8BIT : 0;
2243 lp->cfg.flags |= (SMC_CAN_USE_16BIT) ? SMC91X_USE_16BIT : 0;
2244 lp->cfg.flags |= (SMC_CAN_USE_32BIT) ? SMC91X_USE_32BIT : 0;
2245 lp->cfg.flags |= (nowait) ? SMC91X_NOWAIT : 0;
2246 }
2247
2248 if (!lp->cfg.leda && !lp->cfg.ledb) {
2249 lp->cfg.leda = RPC_LSA_DEFAULT;
2250 lp->cfg.ledb = RPC_LSB_DEFAULT;
2251 }
2252
2253 ndev->dma = (unsigned char)-1;
2254
2255 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs");
2256 if (!res)
2257 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2258 if (!res) {
2259 ret = -ENODEV;
2260 goto out_free_netdev;
2261 }
2262
2263
2264 if (!request_mem_region(res->start, SMC_IO_EXTENT, CARDNAME)) {
2265 ret = -EBUSY;
2266 goto out_free_netdev;
2267 }
2268
2269 ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2270 if (!ires) {
2271 ret = -ENODEV;
2272 goto out_release_io;
2273 }
2274
2275 ndev->irq = ires->start;
2276
2277 if (irq_flags == -1 || ires->flags & IRQF_TRIGGER_MASK)
2278 irq_flags = ires->flags & IRQF_TRIGGER_MASK;
2279
2280 ret = smc_request_attrib(pdev, ndev);
2281 if (ret)
2282 goto out_release_io;
2283#if defined(CONFIG_SA1100_ASSABET)
2284 NCR_0 |= NCR_ENET_OSC_EN;
2285#endif
2286 platform_set_drvdata(pdev, ndev);
2287 ret = smc_enable_device(pdev);
2288 if (ret)
2289 goto out_release_attrib;
2290
2291 addr = ioremap(res->start, SMC_IO_EXTENT);
2292 if (!addr) {
2293 ret = -ENOMEM;
2294 goto out_release_attrib;
2295 }
2296
2297#ifdef CONFIG_ARCH_PXA
2298 {
2299 struct smc_local *lp = netdev_priv(ndev);
2300 lp->device = &pdev->dev;
2301 lp->physaddr = res->start;
2302 }
2303#endif
2304
2305 ret = smc_probe(ndev, addr, irq_flags);
2306 if (ret != 0)
2307 goto out_iounmap;
2308
2309 smc_request_datacs(pdev, ndev);
2310
2311 return 0;
2312
2313 out_iounmap:
2314 platform_set_drvdata(pdev, NULL);
2315 iounmap(addr);
2316 out_release_attrib:
2317 smc_release_attrib(pdev, ndev);
2318 out_release_io:
2319 release_mem_region(res->start, SMC_IO_EXTENT);
2320 out_free_netdev:
2321 free_netdev(ndev);
2322 out:
2323 printk("%s: not found (%d).\n", CARDNAME, ret);
2324
2325 return ret;
2326}
2327
2328static int __devexit smc_drv_remove(struct platform_device *pdev)
2329{
2330 struct net_device *ndev = platform_get_drvdata(pdev);
2331 struct smc_local *lp = netdev_priv(ndev);
2332 struct resource *res;
2333
2334 platform_set_drvdata(pdev, NULL);
2335
2336 unregister_netdev(ndev);
2337
2338 free_irq(ndev->irq, ndev);
2339
2340#ifdef CONFIG_ARCH_PXA
2341 if (ndev->dma != (unsigned char)-1)
2342 pxa_free_dma(ndev->dma);
2343#endif
2344 iounmap(lp->base);
2345
2346 smc_release_datacs(pdev,ndev);
2347 smc_release_attrib(pdev,ndev);
2348
2349 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs");
2350 if (!res)
2351 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2352 release_mem_region(res->start, SMC_IO_EXTENT);
2353
2354 free_netdev(ndev);
2355
2356 return 0;
2357}
2358
2359static int smc_drv_suspend(struct device *dev)
2360{
2361 struct platform_device *pdev = to_platform_device(dev);
2362 struct net_device *ndev = platform_get_drvdata(pdev);
2363
2364 if (ndev) {
2365 if (netif_running(ndev)) {
2366 netif_device_detach(ndev);
2367 smc_shutdown(ndev);
2368 smc_phy_powerdown(ndev);
2369 }
2370 }
2371 return 0;
2372}
2373
2374static int smc_drv_resume(struct device *dev)
2375{
2376 struct platform_device *pdev = to_platform_device(dev);
2377 struct net_device *ndev = platform_get_drvdata(pdev);
2378
2379 if (ndev) {
2380 struct smc_local *lp = netdev_priv(ndev);
2381 smc_enable_device(pdev);
2382 if (netif_running(ndev)) {
2383 smc_reset(ndev);
2384 smc_enable(ndev);
2385 if (lp->phy_type != 0)
2386 smc_phy_configure(&lp->phy_configure);
2387 netif_device_attach(ndev);
2388 }
2389 }
2390 return 0;
2391}
2392
2393#ifdef CONFIG_OF
2394static const struct of_device_id smc91x_match[] = {
2395 { .compatible = "smsc,lan91c94", },
2396 { .compatible = "smsc,lan91c111", },
2397 {},
2398};
2399MODULE_DEVICE_TABLE(of, smc91x_match);
2400#else
2401#define smc91x_match NULL
2402#endif
2403
2404static struct dev_pm_ops smc_drv_pm_ops = {
2405 .suspend = smc_drv_suspend,
2406 .resume = smc_drv_resume,
2407};
2408
2409static struct platform_driver smc_driver = {
2410 .probe = smc_drv_probe,
2411 .remove = __devexit_p(smc_drv_remove),
2412 .driver = {
2413 .name = CARDNAME,
2414 .owner = THIS_MODULE,
2415 .pm = &smc_drv_pm_ops,
2416 .of_match_table = smc91x_match,
2417 },
2418};
2419
2420static int __init smc_init(void)
2421{
2422 return platform_driver_register(&smc_driver);
2423}
2424
2425static void __exit smc_cleanup(void)
2426{
2427 platform_driver_unregister(&smc_driver);
2428}
2429
2430module_init(smc_init);
2431module_exit(smc_cleanup);
diff --git a/drivers/net/ethernet/smsc/smc91x.h b/drivers/net/ethernet/smsc/smc91x.h
new file mode 100644
index 000000000000..5f53fbbf67be
--- /dev/null
+++ b/drivers/net/ethernet/smsc/smc91x.h
@@ -0,0 +1,1180 @@
1/*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 .
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
27 .
28 . Authors
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@fluxnic.net>
32 .
33 ---------------------------------------------------------------------------*/
34#ifndef _SMC91X_H_
35#define _SMC91X_H_
36
37#include <linux/smc91x.h>
38
39/*
40 * Define your architecture specific bus configuration parameters here.
41 */
42
43#if defined(CONFIG_ARCH_LUBBOCK) ||\
44 defined(CONFIG_MACH_MAINSTONE) ||\
45 defined(CONFIG_MACH_ZYLONITE) ||\
46 defined(CONFIG_MACH_LITTLETON) ||\
47 defined(CONFIG_MACH_ZYLONITE2) ||\
48 defined(CONFIG_ARCH_VIPER) ||\
49 defined(CONFIG_MACH_STARGATE2)
50
51#include <asm/mach-types.h>
52
53/* Now the bus width is specified in the platform data
54 * pretend here to support all I/O access types
55 */
56#define SMC_CAN_USE_8BIT 1
57#define SMC_CAN_USE_16BIT 1
58#define SMC_CAN_USE_32BIT 1
59#define SMC_NOWAIT 1
60
61#define SMC_IO_SHIFT (lp->io_shift)
62
63#define SMC_inb(a, r) readb((a) + (r))
64#define SMC_inw(a, r) readw((a) + (r))
65#define SMC_inl(a, r) readl((a) + (r))
66#define SMC_outb(v, a, r) writeb(v, (a) + (r))
67#define SMC_outl(v, a, r) writel(v, (a) + (r))
68#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
69#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
70#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
71#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
72#define SMC_IRQ_FLAGS (-1) /* from resource */
73
74/* We actually can't write halfwords properly if not word aligned */
75static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg)
76{
77 if ((machine_is_mainstone() || machine_is_stargate2()) && reg & 2) {
78 unsigned int v = val << 16;
79 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
80 writel(v, ioaddr + (reg & ~2));
81 } else {
82 writew(val, ioaddr + reg);
83 }
84}
85
86#elif defined(CONFIG_SA1100_PLEB)
87/* We can only do 16-bit reads and writes in the static memory space. */
88#define SMC_CAN_USE_8BIT 1
89#define SMC_CAN_USE_16BIT 1
90#define SMC_CAN_USE_32BIT 0
91#define SMC_IO_SHIFT 0
92#define SMC_NOWAIT 1
93
94#define SMC_inb(a, r) readb((a) + (r))
95#define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
96#define SMC_inw(a, r) readw((a) + (r))
97#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
98#define SMC_outb(v, a, r) writeb(v, (a) + (r))
99#define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
100#define SMC_outw(v, a, r) writew(v, (a) + (r))
101#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
102
103#define SMC_IRQ_FLAGS (-1)
104
105#elif defined(CONFIG_SA1100_ASSABET)
106
107#include <mach/neponset.h>
108
109/* We can only do 8-bit reads and writes in the static memory space. */
110#define SMC_CAN_USE_8BIT 1
111#define SMC_CAN_USE_16BIT 0
112#define SMC_CAN_USE_32BIT 0
113#define SMC_NOWAIT 1
114
115/* The first two address lines aren't connected... */
116#define SMC_IO_SHIFT 2
117
118#define SMC_inb(a, r) readb((a) + (r))
119#define SMC_outb(v, a, r) writeb(v, (a) + (r))
120#define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
121#define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
122#define SMC_IRQ_FLAGS (-1) /* from resource */
123
124#elif defined(CONFIG_MACH_LOGICPD_PXA270) || \
125 defined(CONFIG_MACH_NOMADIK_8815NHK)
126
127#define SMC_CAN_USE_8BIT 0
128#define SMC_CAN_USE_16BIT 1
129#define SMC_CAN_USE_32BIT 0
130#define SMC_IO_SHIFT 0
131#define SMC_NOWAIT 1
132
133#define SMC_inw(a, r) readw((a) + (r))
134#define SMC_outw(v, a, r) writew(v, (a) + (r))
135#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
136#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
137
138#elif defined(CONFIG_ARCH_INNOKOM) || \
139 defined(CONFIG_ARCH_PXA_IDP) || \
140 defined(CONFIG_ARCH_RAMSES) || \
141 defined(CONFIG_ARCH_PCM027)
142
143#define SMC_CAN_USE_8BIT 1
144#define SMC_CAN_USE_16BIT 1
145#define SMC_CAN_USE_32BIT 1
146#define SMC_IO_SHIFT 0
147#define SMC_NOWAIT 1
148#define SMC_USE_PXA_DMA 1
149
150#define SMC_inb(a, r) readb((a) + (r))
151#define SMC_inw(a, r) readw((a) + (r))
152#define SMC_inl(a, r) readl((a) + (r))
153#define SMC_outb(v, a, r) writeb(v, (a) + (r))
154#define SMC_outl(v, a, r) writel(v, (a) + (r))
155#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
156#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
157#define SMC_IRQ_FLAGS (-1) /* from resource */
158
159/* We actually can't write halfwords properly if not word aligned */
160static inline void
161SMC_outw(u16 val, void __iomem *ioaddr, int reg)
162{
163 if (reg & 2) {
164 unsigned int v = val << 16;
165 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
166 writel(v, ioaddr + (reg & ~2));
167 } else {
168 writew(val, ioaddr + reg);
169 }
170}
171
172#elif defined(CONFIG_SH_SH4202_MICRODEV)
173
174#define SMC_CAN_USE_8BIT 0
175#define SMC_CAN_USE_16BIT 1
176#define SMC_CAN_USE_32BIT 0
177
178#define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
179#define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
180#define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
181#define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
182#define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
183#define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
184#define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
185#define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
186#define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
187#define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
188
189#define SMC_IRQ_FLAGS (0)
190
191#elif defined(CONFIG_M32R)
192
193#define SMC_CAN_USE_8BIT 0
194#define SMC_CAN_USE_16BIT 1
195#define SMC_CAN_USE_32BIT 0
196
197#define SMC_inb(a, r) inb(((u32)a) + (r))
198#define SMC_inw(a, r) inw(((u32)a) + (r))
199#define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
200#define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
201#define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
202#define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
203
204#define SMC_IRQ_FLAGS (0)
205
206#define RPC_LSA_DEFAULT RPC_LED_TX_RX
207#define RPC_LSB_DEFAULT RPC_LED_100_10
208
209#elif defined(CONFIG_ARCH_VERSATILE)
210
211#define SMC_CAN_USE_8BIT 1
212#define SMC_CAN_USE_16BIT 1
213#define SMC_CAN_USE_32BIT 1
214#define SMC_NOWAIT 1
215
216#define SMC_inb(a, r) readb((a) + (r))
217#define SMC_inw(a, r) readw((a) + (r))
218#define SMC_inl(a, r) readl((a) + (r))
219#define SMC_outb(v, a, r) writeb(v, (a) + (r))
220#define SMC_outw(v, a, r) writew(v, (a) + (r))
221#define SMC_outl(v, a, r) writel(v, (a) + (r))
222#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
223#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
224#define SMC_IRQ_FLAGS (-1) /* from resource */
225
226#elif defined(CONFIG_MN10300)
227
228/*
229 * MN10300/AM33 configuration
230 */
231
232#include <unit/smc91111.h>
233
234#elif defined(CONFIG_ARCH_MSM)
235
236#define SMC_CAN_USE_8BIT 0
237#define SMC_CAN_USE_16BIT 1
238#define SMC_CAN_USE_32BIT 0
239#define SMC_NOWAIT 1
240
241#define SMC_inw(a, r) readw((a) + (r))
242#define SMC_outw(v, a, r) writew(v, (a) + (r))
243#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
244#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
245
246#define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH
247
248#elif defined(CONFIG_COLDFIRE)
249
250#define SMC_CAN_USE_8BIT 0
251#define SMC_CAN_USE_16BIT 1
252#define SMC_CAN_USE_32BIT 0
253#define SMC_NOWAIT 1
254
255static inline void mcf_insw(void *a, unsigned char *p, int l)
256{
257 u16 *wp = (u16 *) p;
258 while (l-- > 0)
259 *wp++ = readw(a);
260}
261
262static inline void mcf_outsw(void *a, unsigned char *p, int l)
263{
264 u16 *wp = (u16 *) p;
265 while (l-- > 0)
266 writew(*wp++, a);
267}
268
269#define SMC_inw(a, r) _swapw(readw((a) + (r)))
270#define SMC_outw(v, a, r) writew(_swapw(v), (a) + (r))
271#define SMC_insw(a, r, p, l) mcf_insw(a + r, p, l)
272#define SMC_outsw(a, r, p, l) mcf_outsw(a + r, p, l)
273
274#define SMC_IRQ_FLAGS (IRQF_DISABLED)
275
276#else
277
278/*
279 * Default configuration
280 */
281
282#define SMC_CAN_USE_8BIT 1
283#define SMC_CAN_USE_16BIT 1
284#define SMC_CAN_USE_32BIT 1
285#define SMC_NOWAIT 1
286
287#define SMC_IO_SHIFT (lp->io_shift)
288
289#define SMC_inb(a, r) readb((a) + (r))
290#define SMC_inw(a, r) readw((a) + (r))
291#define SMC_inl(a, r) readl((a) + (r))
292#define SMC_outb(v, a, r) writeb(v, (a) + (r))
293#define SMC_outw(v, a, r) writew(v, (a) + (r))
294#define SMC_outl(v, a, r) writel(v, (a) + (r))
295#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
296#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
297#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
298#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
299
300#define RPC_LSA_DEFAULT RPC_LED_100_10
301#define RPC_LSB_DEFAULT RPC_LED_TX_RX
302
303#endif
304
305
306/* store this information for the driver.. */
307struct smc_local {
308 /*
309 * If I have to wait until memory is available to send a
310 * packet, I will store the skbuff here, until I get the
311 * desired memory. Then, I'll send it out and free it.
312 */
313 struct sk_buff *pending_tx_skb;
314 struct tasklet_struct tx_task;
315
316 /* version/revision of the SMC91x chip */
317 int version;
318
319 /* Contains the current active transmission mode */
320 int tcr_cur_mode;
321
322 /* Contains the current active receive mode */
323 int rcr_cur_mode;
324
325 /* Contains the current active receive/phy mode */
326 int rpc_cur_mode;
327 int ctl_rfduplx;
328 int ctl_rspeed;
329
330 u32 msg_enable;
331 u32 phy_type;
332 struct mii_if_info mii;
333
334 /* work queue */
335 struct work_struct phy_configure;
336 struct net_device *dev;
337 int work_pending;
338
339 spinlock_t lock;
340
341#ifdef CONFIG_ARCH_PXA
342 /* DMA needs the physical address of the chip */
343 u_long physaddr;
344 struct device *device;
345#endif
346 void __iomem *base;
347 void __iomem *datacs;
348
349 /* the low address lines on some platforms aren't connected... */
350 int io_shift;
351
352 struct smc91x_platdata cfg;
353};
354
355#define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT)
356#define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT)
357#define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT)
358
359#ifdef CONFIG_ARCH_PXA
360/*
361 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
362 * always happening in irq context so no need to worry about races. TX is
363 * different and probably not worth it for that reason, and not as critical
364 * as RX which can overrun memory and lose packets.
365 */
366#include <linux/dma-mapping.h>
367#include <mach/dma.h>
368
369#ifdef SMC_insl
370#undef SMC_insl
371#define SMC_insl(a, r, p, l) \
372 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
373static inline void
374smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
375 u_char *buf, int len)
376{
377 u_long physaddr = lp->physaddr;
378 dma_addr_t dmabuf;
379
380 /* fallback if no DMA available */
381 if (dma == (unsigned char)-1) {
382 readsl(ioaddr + reg, buf, len);
383 return;
384 }
385
386 /* 64 bit alignment is required for memory to memory DMA */
387 if ((long)buf & 4) {
388 *((u32 *)buf) = SMC_inl(ioaddr, reg);
389 buf += 4;
390 len--;
391 }
392
393 len *= 4;
394 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
395 DCSR(dma) = DCSR_NODESC;
396 DTADR(dma) = dmabuf;
397 DSADR(dma) = physaddr + reg;
398 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
399 DCMD_WIDTH4 | (DCMD_LENGTH & len));
400 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
401 while (!(DCSR(dma) & DCSR_STOPSTATE))
402 cpu_relax();
403 DCSR(dma) = 0;
404 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
405}
406#endif
407
408#ifdef SMC_insw
409#undef SMC_insw
410#define SMC_insw(a, r, p, l) \
411 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
412static inline void
413smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
414 u_char *buf, int len)
415{
416 u_long physaddr = lp->physaddr;
417 dma_addr_t dmabuf;
418
419 /* fallback if no DMA available */
420 if (dma == (unsigned char)-1) {
421 readsw(ioaddr + reg, buf, len);
422 return;
423 }
424
425 /* 64 bit alignment is required for memory to memory DMA */
426 while ((long)buf & 6) {
427 *((u16 *)buf) = SMC_inw(ioaddr, reg);
428 buf += 2;
429 len--;
430 }
431
432 len *= 2;
433 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
434 DCSR(dma) = DCSR_NODESC;
435 DTADR(dma) = dmabuf;
436 DSADR(dma) = physaddr + reg;
437 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
438 DCMD_WIDTH2 | (DCMD_LENGTH & len));
439 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
440 while (!(DCSR(dma) & DCSR_STOPSTATE))
441 cpu_relax();
442 DCSR(dma) = 0;
443 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
444}
445#endif
446
447static void
448smc_pxa_dma_irq(int dma, void *dummy)
449{
450 DCSR(dma) = 0;
451}
452#endif /* CONFIG_ARCH_PXA */
453
454
455/*
456 * Everything a particular hardware setup needs should have been defined
457 * at this point. Add stubs for the undefined cases, mainly to avoid
458 * compilation warnings since they'll be optimized away, or to prevent buggy
459 * use of them.
460 */
461
462#if ! SMC_CAN_USE_32BIT
463#define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
464#define SMC_outl(x, ioaddr, reg) BUG()
465#define SMC_insl(a, r, p, l) BUG()
466#define SMC_outsl(a, r, p, l) BUG()
467#endif
468
469#if !defined(SMC_insl) || !defined(SMC_outsl)
470#define SMC_insl(a, r, p, l) BUG()
471#define SMC_outsl(a, r, p, l) BUG()
472#endif
473
474#if ! SMC_CAN_USE_16BIT
475
476/*
477 * Any 16-bit access is performed with two 8-bit accesses if the hardware
478 * can't do it directly. Most registers are 16-bit so those are mandatory.
479 */
480#define SMC_outw(x, ioaddr, reg) \
481 do { \
482 unsigned int __val16 = (x); \
483 SMC_outb( __val16, ioaddr, reg ); \
484 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
485 } while (0)
486#define SMC_inw(ioaddr, reg) \
487 ({ \
488 unsigned int __val16; \
489 __val16 = SMC_inb( ioaddr, reg ); \
490 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
491 __val16; \
492 })
493
494#define SMC_insw(a, r, p, l) BUG()
495#define SMC_outsw(a, r, p, l) BUG()
496
497#endif
498
499#if !defined(SMC_insw) || !defined(SMC_outsw)
500#define SMC_insw(a, r, p, l) BUG()
501#define SMC_outsw(a, r, p, l) BUG()
502#endif
503
504#if ! SMC_CAN_USE_8BIT
505#define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
506#define SMC_outb(x, ioaddr, reg) BUG()
507#define SMC_insb(a, r, p, l) BUG()
508#define SMC_outsb(a, r, p, l) BUG()
509#endif
510
511#if !defined(SMC_insb) || !defined(SMC_outsb)
512#define SMC_insb(a, r, p, l) BUG()
513#define SMC_outsb(a, r, p, l) BUG()
514#endif
515
516#ifndef SMC_CAN_USE_DATACS
517#define SMC_CAN_USE_DATACS 0
518#endif
519
520#ifndef SMC_IO_SHIFT
521#define SMC_IO_SHIFT 0
522#endif
523
524#ifndef SMC_IRQ_FLAGS
525#define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
526#endif
527
528#ifndef SMC_INTERRUPT_PREAMBLE
529#define SMC_INTERRUPT_PREAMBLE
530#endif
531
532
533/* Because of bank switching, the LAN91x uses only 16 I/O ports */
534#define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
535#define SMC_DATA_EXTENT (4)
536
537/*
538 . Bank Select Register:
539 .
540 . yyyy yyyy 0000 00xx
541 . xx = bank number
542 . yyyy yyyy = 0x33, for identification purposes.
543*/
544#define BANK_SELECT (14 << SMC_IO_SHIFT)
545
546
547// Transmit Control Register
548/* BANK 0 */
549#define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
550#define TCR_ENABLE 0x0001 // When 1 we can transmit
551#define TCR_LOOP 0x0002 // Controls output pin LBK
552#define TCR_FORCOL 0x0004 // When 1 will force a collision
553#define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
554#define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
555#define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
556#define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
557#define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
558#define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
559#define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
560
561#define TCR_CLEAR 0 /* do NOTHING */
562/* the default settings for the TCR register : */
563#define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
564
565
566// EPH Status Register
567/* BANK 0 */
568#define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
569#define ES_TX_SUC 0x0001 // Last TX was successful
570#define ES_SNGL_COL 0x0002 // Single collision detected for last tx
571#define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
572#define ES_LTX_MULT 0x0008 // Last tx was a multicast
573#define ES_16COL 0x0010 // 16 Collisions Reached
574#define ES_SQET 0x0020 // Signal Quality Error Test
575#define ES_LTXBRD 0x0040 // Last tx was a broadcast
576#define ES_TXDEFR 0x0080 // Transmit Deferred
577#define ES_LATCOL 0x0200 // Late collision detected on last tx
578#define ES_LOSTCARR 0x0400 // Lost Carrier Sense
579#define ES_EXC_DEF 0x0800 // Excessive Deferral
580#define ES_CTR_ROL 0x1000 // Counter Roll Over indication
581#define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
582#define ES_TXUNRN 0x8000 // Tx Underrun
583
584
585// Receive Control Register
586/* BANK 0 */
587#define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
588#define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
589#define RCR_PRMS 0x0002 // Enable promiscuous mode
590#define RCR_ALMUL 0x0004 // When set accepts all multicast frames
591#define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
592#define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
593#define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
594#define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
595#define RCR_SOFTRST 0x8000 // resets the chip
596
597/* the normal settings for the RCR register : */
598#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
599#define RCR_CLEAR 0x0 // set it to a base state
600
601
602// Counter Register
603/* BANK 0 */
604#define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
605
606
607// Memory Information Register
608/* BANK 0 */
609#define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
610
611
612// Receive/Phy Control Register
613/* BANK 0 */
614#define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
615#define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
616#define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
617#define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
618#define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
619#define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
620
621#ifndef RPC_LSA_DEFAULT
622#define RPC_LSA_DEFAULT RPC_LED_100
623#endif
624#ifndef RPC_LSB_DEFAULT
625#define RPC_LSB_DEFAULT RPC_LED_FD
626#endif
627
628#define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX)
629
630
631/* Bank 0 0x0C is reserved */
632
633// Bank Select Register
634/* All Banks */
635#define BSR_REG 0x000E
636
637
638// Configuration Reg
639/* BANK 1 */
640#define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
641#define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
642#define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
643#define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
644#define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
645
646// Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
647#define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
648
649
650// Base Address Register
651/* BANK 1 */
652#define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
653
654
655// Individual Address Registers
656/* BANK 1 */
657#define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
658#define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
659#define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
660
661
662// General Purpose Register
663/* BANK 1 */
664#define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
665
666
667// Control Register
668/* BANK 1 */
669#define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
670#define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
671#define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
672#define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
673#define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
674#define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
675#define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
676#define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
677#define CTL_STORE 0x0001 // When set stores registers into EEPROM
678
679
680// MMU Command Register
681/* BANK 2 */
682#define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
683#define MC_BUSY 1 // When 1 the last release has not completed
684#define MC_NOP (0<<5) // No Op
685#define MC_ALLOC (1<<5) // OR with number of 256 byte packets
686#define MC_RESET (2<<5) // Reset MMU to initial state
687#define MC_REMOVE (3<<5) // Remove the current rx packet
688#define MC_RELEASE (4<<5) // Remove and release the current rx packet
689#define MC_FREEPKT (5<<5) // Release packet in PNR register
690#define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
691#define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
692
693
694// Packet Number Register
695/* BANK 2 */
696#define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
697
698
699// Allocation Result Register
700/* BANK 2 */
701#define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
702#define AR_FAILED 0x80 // Alocation Failed
703
704
705// TX FIFO Ports Register
706/* BANK 2 */
707#define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
708#define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
709
710// RX FIFO Ports Register
711/* BANK 2 */
712#define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
713#define RXFIFO_REMPTY 0x80 // RX FIFO Empty
714
715#define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
716
717// Pointer Register
718/* BANK 2 */
719#define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
720#define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
721#define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
722#define PTR_READ 0x2000 // When 1 the operation is a read
723
724
725// Data Register
726/* BANK 2 */
727#define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
728
729
730// Interrupt Status/Acknowledge Register
731/* BANK 2 */
732#define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
733
734
735// Interrupt Mask Register
736/* BANK 2 */
737#define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
738#define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
739#define IM_ERCV_INT 0x40 // Early Receive Interrupt
740#define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
741#define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
742#define IM_ALLOC_INT 0x08 // Set when allocation request is completed
743#define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
744#define IM_TX_INT 0x02 // Transmit Interrupt
745#define IM_RCV_INT 0x01 // Receive Interrupt
746
747
748// Multicast Table Registers
749/* BANK 3 */
750#define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
751#define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
752#define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
753#define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
754
755
756// Management Interface Register (MII)
757/* BANK 3 */
758#define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
759#define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
760#define MII_MDOE 0x0008 // MII Output Enable
761#define MII_MCLK 0x0004 // MII Clock, pin MDCLK
762#define MII_MDI 0x0002 // MII Input, pin MDI
763#define MII_MDO 0x0001 // MII Output, pin MDO
764
765
766// Revision Register
767/* BANK 3 */
768/* ( hi: chip id low: rev # ) */
769#define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
770
771
772// Early RCV Register
773/* BANK 3 */
774/* this is NOT on SMC9192 */
775#define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
776#define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
777#define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
778
779
780// External Register
781/* BANK 7 */
782#define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
783
784
785#define CHIP_9192 3
786#define CHIP_9194 4
787#define CHIP_9195 5
788#define CHIP_9196 6
789#define CHIP_91100 7
790#define CHIP_91100FD 8
791#define CHIP_91111FD 9
792
793static const char * chip_ids[ 16 ] = {
794 NULL, NULL, NULL,
795 /* 3 */ "SMC91C90/91C92",
796 /* 4 */ "SMC91C94",
797 /* 5 */ "SMC91C95",
798 /* 6 */ "SMC91C96",
799 /* 7 */ "SMC91C100",
800 /* 8 */ "SMC91C100FD",
801 /* 9 */ "SMC91C11xFD",
802 NULL, NULL, NULL,
803 NULL, NULL, NULL};
804
805
806/*
807 . Receive status bits
808*/
809#define RS_ALGNERR 0x8000
810#define RS_BRODCAST 0x4000
811#define RS_BADCRC 0x2000
812#define RS_ODDFRAME 0x1000
813#define RS_TOOLONG 0x0800
814#define RS_TOOSHORT 0x0400
815#define RS_MULTICAST 0x0001
816#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
817
818
819/*
820 * PHY IDs
821 * LAN83C183 == LAN91C111 Internal PHY
822 */
823#define PHY_LAN83C183 0x0016f840
824#define PHY_LAN83C180 0x02821c50
825
826/*
827 * PHY Register Addresses (LAN91C111 Internal PHY)
828 *
829 * Generic PHY registers can be found in <linux/mii.h>
830 *
831 * These phy registers are specific to our on-board phy.
832 */
833
834// PHY Configuration Register 1
835#define PHY_CFG1_REG 0x10
836#define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
837#define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
838#define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
839#define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
840#define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
841#define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
842#define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
843#define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
844#define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
845#define PHY_CFG1_TLVL_MASK 0x003C
846#define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
847
848
849// PHY Configuration Register 2
850#define PHY_CFG2_REG 0x11
851#define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
852#define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
853#define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
854#define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
855
856// PHY Status Output (and Interrupt status) Register
857#define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
858#define PHY_INT_INT 0x8000 // 1=bits have changed since last read
859#define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
860#define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
861#define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
862#define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
863#define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
864#define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
865#define PHY_INT_JAB 0x0100 // 1=Jabber detected
866#define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
867#define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
868
869// PHY Interrupt/Status Mask Register
870#define PHY_MASK_REG 0x13 // Interrupt Mask
871// Uses the same bit definitions as PHY_INT_REG
872
873
874/*
875 * SMC91C96 ethernet config and status registers.
876 * These are in the "attribute" space.
877 */
878#define ECOR 0x8000
879#define ECOR_RESET 0x80
880#define ECOR_LEVEL_IRQ 0x40
881#define ECOR_WR_ATTRIB 0x04
882#define ECOR_ENABLE 0x01
883
884#define ECSR 0x8002
885#define ECSR_IOIS8 0x20
886#define ECSR_PWRDWN 0x04
887#define ECSR_INT 0x02
888
889#define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
890
891
892/*
893 * Macros to abstract register access according to the data bus
894 * capabilities. Please use those and not the in/out primitives.
895 * Note: the following macros do *not* select the bank -- this must
896 * be done separately as needed in the main code. The SMC_REG() macro
897 * only uses the bank argument for debugging purposes (when enabled).
898 *
899 * Note: despite inline functions being safer, everything leading to this
900 * should preferably be macros to let BUG() display the line number in
901 * the core source code since we're interested in the top call site
902 * not in any inline function location.
903 */
904
905#if SMC_DEBUG > 0
906#define SMC_REG(lp, reg, bank) \
907 ({ \
908 int __b = SMC_CURRENT_BANK(lp); \
909 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
910 printk( "%s: bank reg screwed (0x%04x)\n", \
911 CARDNAME, __b ); \
912 BUG(); \
913 } \
914 reg<<SMC_IO_SHIFT; \
915 })
916#else
917#define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)
918#endif
919
920/*
921 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
922 * aligned to a 32 bit boundary. I tell you that does exist!
923 * Fortunately the affected register accesses can be easily worked around
924 * since we can write zeroes to the preceding 16 bits without adverse
925 * effects and use a 32-bit access.
926 *
927 * Enforce it on any 32-bit capable setup for now.
928 */
929#define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp)
930
931#define SMC_GET_PN(lp) \
932 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
933 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
934
935#define SMC_SET_PN(lp, x) \
936 do { \
937 if (SMC_MUST_ALIGN_WRITE(lp)) \
938 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
939 else if (SMC_8BIT(lp)) \
940 SMC_outb(x, ioaddr, PN_REG(lp)); \
941 else \
942 SMC_outw(x, ioaddr, PN_REG(lp)); \
943 } while (0)
944
945#define SMC_GET_AR(lp) \
946 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
947 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
948
949#define SMC_GET_TXFIFO(lp) \
950 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
951 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
952
953#define SMC_GET_RXFIFO(lp) \
954 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
955 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
956
957#define SMC_GET_INT(lp) \
958 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
959 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
960
961#define SMC_ACK_INT(lp, x) \
962 do { \
963 if (SMC_8BIT(lp)) \
964 SMC_outb(x, ioaddr, INT_REG(lp)); \
965 else { \
966 unsigned long __flags; \
967 int __mask; \
968 local_irq_save(__flags); \
969 __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
970 SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \
971 local_irq_restore(__flags); \
972 } \
973 } while (0)
974
975#define SMC_GET_INT_MASK(lp) \
976 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
977 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
978
979#define SMC_SET_INT_MASK(lp, x) \
980 do { \
981 if (SMC_8BIT(lp)) \
982 SMC_outb(x, ioaddr, IM_REG(lp)); \
983 else \
984 SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \
985 } while (0)
986
987#define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
988
989#define SMC_SELECT_BANK(lp, x) \
990 do { \
991 if (SMC_MUST_ALIGN_WRITE(lp)) \
992 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
993 else \
994 SMC_outw(x, ioaddr, BANK_SELECT); \
995 } while (0)
996
997#define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
998
999#define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp))
1000
1001#define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
1002
1003#define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp))
1004
1005#define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
1006
1007#define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
1008
1009#define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp))
1010
1011#define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
1012
1013#define SMC_GET_GP(lp) SMC_inw(ioaddr, GP_REG(lp))
1014
1015#define SMC_SET_GP(lp, x) \
1016 do { \
1017 if (SMC_MUST_ALIGN_WRITE(lp)) \
1018 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1)); \
1019 else \
1020 SMC_outw(x, ioaddr, GP_REG(lp)); \
1021 } while (0)
1022
1023#define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp))
1024
1025#define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
1026
1027#define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp))
1028
1029#define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
1030
1031#define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
1032
1033#define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
1034
1035#define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
1036
1037#define SMC_SET_PTR(lp, x) \
1038 do { \
1039 if (SMC_MUST_ALIGN_WRITE(lp)) \
1040 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
1041 else \
1042 SMC_outw(x, ioaddr, PTR_REG(lp)); \
1043 } while (0)
1044
1045#define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
1046
1047#define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
1048
1049#define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp))
1050
1051#define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
1052
1053#define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp))
1054
1055#define SMC_SET_RPC(lp, x) \
1056 do { \
1057 if (SMC_MUST_ALIGN_WRITE(lp)) \
1058 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
1059 else \
1060 SMC_outw(x, ioaddr, RPC_REG(lp)); \
1061 } while (0)
1062
1063#define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
1064
1065#define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp))
1066
1067#ifndef SMC_GET_MAC_ADDR
1068#define SMC_GET_MAC_ADDR(lp, addr) \
1069 do { \
1070 unsigned int __v; \
1071 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
1072 addr[0] = __v; addr[1] = __v >> 8; \
1073 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
1074 addr[2] = __v; addr[3] = __v >> 8; \
1075 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
1076 addr[4] = __v; addr[5] = __v >> 8; \
1077 } while (0)
1078#endif
1079
1080#define SMC_SET_MAC_ADDR(lp, addr) \
1081 do { \
1082 SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1083 SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1084 SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1085 } while (0)
1086
1087#define SMC_SET_MCAST(lp, x) \
1088 do { \
1089 const unsigned char *mt = (x); \
1090 SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1091 SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1092 SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1093 SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1094 } while (0)
1095
1096#define SMC_PUT_PKT_HDR(lp, status, length) \
1097 do { \
1098 if (SMC_32BIT(lp)) \
1099 SMC_outl((status) | (length)<<16, ioaddr, \
1100 DATA_REG(lp)); \
1101 else { \
1102 SMC_outw(status, ioaddr, DATA_REG(lp)); \
1103 SMC_outw(length, ioaddr, DATA_REG(lp)); \
1104 } \
1105 } while (0)
1106
1107#define SMC_GET_PKT_HDR(lp, status, length) \
1108 do { \
1109 if (SMC_32BIT(lp)) { \
1110 unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1111 (status) = __val & 0xffff; \
1112 (length) = __val >> 16; \
1113 } else { \
1114 (status) = SMC_inw(ioaddr, DATA_REG(lp)); \
1115 (length) = SMC_inw(ioaddr, DATA_REG(lp)); \
1116 } \
1117 } while (0)
1118
1119#define SMC_PUSH_DATA(lp, p, l) \
1120 do { \
1121 if (SMC_32BIT(lp)) { \
1122 void *__ptr = (p); \
1123 int __len = (l); \
1124 void __iomem *__ioaddr = ioaddr; \
1125 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1126 __len -= 2; \
1127 SMC_outw(*(u16 *)__ptr, ioaddr, \
1128 DATA_REG(lp)); \
1129 __ptr += 2; \
1130 } \
1131 if (SMC_CAN_USE_DATACS && lp->datacs) \
1132 __ioaddr = lp->datacs; \
1133 SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1134 if (__len & 2) { \
1135 __ptr += (__len & ~3); \
1136 SMC_outw(*((u16 *)__ptr), ioaddr, \
1137 DATA_REG(lp)); \
1138 } \
1139 } else if (SMC_16BIT(lp)) \
1140 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1141 else if (SMC_8BIT(lp)) \
1142 SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
1143 } while (0)
1144
1145#define SMC_PULL_DATA(lp, p, l) \
1146 do { \
1147 if (SMC_32BIT(lp)) { \
1148 void *__ptr = (p); \
1149 int __len = (l); \
1150 void __iomem *__ioaddr = ioaddr; \
1151 if ((unsigned long)__ptr & 2) { \
1152 /* \
1153 * We want 32bit alignment here. \
1154 * Since some buses perform a full \
1155 * 32bit fetch even for 16bit data \
1156 * we can't use SMC_inw() here. \
1157 * Back both source (on-chip) and \
1158 * destination pointers of 2 bytes. \
1159 * This is possible since the call to \
1160 * SMC_GET_PKT_HDR() already advanced \
1161 * the source pointer of 4 bytes, and \
1162 * the skb_reserve(skb, 2) advanced \
1163 * the destination pointer of 2 bytes. \
1164 */ \
1165 __ptr -= 2; \
1166 __len += 2; \
1167 SMC_SET_PTR(lp, \
1168 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1169 } \
1170 if (SMC_CAN_USE_DATACS && lp->datacs) \
1171 __ioaddr = lp->datacs; \
1172 __len += 2; \
1173 SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1174 } else if (SMC_16BIT(lp)) \
1175 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1176 else if (SMC_8BIT(lp)) \
1177 SMC_insb(ioaddr, DATA_REG(lp), p, l); \
1178 } while (0)
1179
1180#endif /* _SMC91X_H_ */
diff --git a/drivers/net/ethernet/smsc/smsc911x.c b/drivers/net/ethernet/smsc/smsc911x.c
new file mode 100644
index 000000000000..75c08a55582c
--- /dev/null
+++ b/drivers/net/ethernet/smsc/smsc911x.c
@@ -0,0 +1,2404 @@
1/***************************************************************************
2 *
3 * Copyright (C) 2004-2008 SMSC
4 * Copyright (C) 2005-2008 ARM
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 *
20 ***************************************************************************
21 * Rewritten, heavily based on smsc911x simple driver by SMSC.
22 * Partly uses io macros from smc91x.c by Nicolas Pitre
23 *
24 * Supported devices:
25 * LAN9115, LAN9116, LAN9117, LAN9118
26 * LAN9215, LAN9216, LAN9217, LAN9218
27 * LAN9210, LAN9211
28 * LAN9220, LAN9221
29 *
30 */
31
32#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
33
34#include <linux/crc32.h>
35#include <linux/delay.h>
36#include <linux/errno.h>
37#include <linux/etherdevice.h>
38#include <linux/ethtool.h>
39#include <linux/init.h>
40#include <linux/interrupt.h>
41#include <linux/ioport.h>
42#include <linux/kernel.h>
43#include <linux/module.h>
44#include <linux/netdevice.h>
45#include <linux/platform_device.h>
46#include <linux/sched.h>
47#include <linux/timer.h>
48#include <linux/bug.h>
49#include <linux/bitops.h>
50#include <linux/irq.h>
51#include <linux/io.h>
52#include <linux/swab.h>
53#include <linux/phy.h>
54#include <linux/smsc911x.h>
55#include <linux/device.h>
56#include <linux/of.h>
57#include <linux/of_device.h>
58#include <linux/of_gpio.h>
59#include <linux/of_net.h>
60#include "smsc911x.h"
61
62#define SMSC_CHIPNAME "smsc911x"
63#define SMSC_MDIONAME "smsc911x-mdio"
64#define SMSC_DRV_VERSION "2008-10-21"
65
66MODULE_LICENSE("GPL");
67MODULE_VERSION(SMSC_DRV_VERSION);
68MODULE_ALIAS("platform:smsc911x");
69
70#if USE_DEBUG > 0
71static int debug = 16;
72#else
73static int debug = 3;
74#endif
75
76module_param(debug, int, 0);
77MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
78
79struct smsc911x_data;
80
81struct smsc911x_ops {
82 u32 (*reg_read)(struct smsc911x_data *pdata, u32 reg);
83 void (*reg_write)(struct smsc911x_data *pdata, u32 reg, u32 val);
84 void (*rx_readfifo)(struct smsc911x_data *pdata,
85 unsigned int *buf, unsigned int wordcount);
86 void (*tx_writefifo)(struct smsc911x_data *pdata,
87 unsigned int *buf, unsigned int wordcount);
88};
89
90struct smsc911x_data {
91 void __iomem *ioaddr;
92
93 unsigned int idrev;
94
95 /* used to decide which workarounds apply */
96 unsigned int generation;
97
98 /* device configuration (copied from platform_data during probe) */
99 struct smsc911x_platform_config config;
100
101 /* This needs to be acquired before calling any of below:
102 * smsc911x_mac_read(), smsc911x_mac_write()
103 */
104 spinlock_t mac_lock;
105
106 /* spinlock to ensure register accesses are serialised */
107 spinlock_t dev_lock;
108
109 struct phy_device *phy_dev;
110 struct mii_bus *mii_bus;
111 int phy_irq[PHY_MAX_ADDR];
112 unsigned int using_extphy;
113 int last_duplex;
114 int last_carrier;
115
116 u32 msg_enable;
117 unsigned int gpio_setting;
118 unsigned int gpio_orig_setting;
119 struct net_device *dev;
120 struct napi_struct napi;
121
122 unsigned int software_irq_signal;
123
124#ifdef USE_PHY_WORK_AROUND
125#define MIN_PACKET_SIZE (64)
126 char loopback_tx_pkt[MIN_PACKET_SIZE];
127 char loopback_rx_pkt[MIN_PACKET_SIZE];
128 unsigned int resetcount;
129#endif
130
131 /* Members for Multicast filter workaround */
132 unsigned int multicast_update_pending;
133 unsigned int set_bits_mask;
134 unsigned int clear_bits_mask;
135 unsigned int hashhi;
136 unsigned int hashlo;
137
138 /* register access functions */
139 const struct smsc911x_ops *ops;
140};
141
142/* Easy access to information */
143#define __smsc_shift(pdata, reg) ((reg) << ((pdata)->config.shift))
144
145static inline u32 __smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
146{
147 if (pdata->config.flags & SMSC911X_USE_32BIT)
148 return readl(pdata->ioaddr + reg);
149
150 if (pdata->config.flags & SMSC911X_USE_16BIT)
151 return ((readw(pdata->ioaddr + reg) & 0xFFFF) |
152 ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16));
153
154 BUG();
155 return 0;
156}
157
158static inline u32
159__smsc911x_reg_read_shift(struct smsc911x_data *pdata, u32 reg)
160{
161 if (pdata->config.flags & SMSC911X_USE_32BIT)
162 return readl(pdata->ioaddr + __smsc_shift(pdata, reg));
163
164 if (pdata->config.flags & SMSC911X_USE_16BIT)
165 return (readw(pdata->ioaddr +
166 __smsc_shift(pdata, reg)) & 0xFFFF) |
167 ((readw(pdata->ioaddr +
168 __smsc_shift(pdata, reg + 2)) & 0xFFFF) << 16);
169
170 BUG();
171 return 0;
172}
173
174static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
175{
176 u32 data;
177 unsigned long flags;
178
179 spin_lock_irqsave(&pdata->dev_lock, flags);
180 data = pdata->ops->reg_read(pdata, reg);
181 spin_unlock_irqrestore(&pdata->dev_lock, flags);
182
183 return data;
184}
185
186static inline void __smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
187 u32 val)
188{
189 if (pdata->config.flags & SMSC911X_USE_32BIT) {
190 writel(val, pdata->ioaddr + reg);
191 return;
192 }
193
194 if (pdata->config.flags & SMSC911X_USE_16BIT) {
195 writew(val & 0xFFFF, pdata->ioaddr + reg);
196 writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2);
197 return;
198 }
199
200 BUG();
201}
202
203static inline void
204__smsc911x_reg_write_shift(struct smsc911x_data *pdata, u32 reg, u32 val)
205{
206 if (pdata->config.flags & SMSC911X_USE_32BIT) {
207 writel(val, pdata->ioaddr + __smsc_shift(pdata, reg));
208 return;
209 }
210
211 if (pdata->config.flags & SMSC911X_USE_16BIT) {
212 writew(val & 0xFFFF,
213 pdata->ioaddr + __smsc_shift(pdata, reg));
214 writew((val >> 16) & 0xFFFF,
215 pdata->ioaddr + __smsc_shift(pdata, reg + 2));
216 return;
217 }
218
219 BUG();
220}
221
222static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
223 u32 val)
224{
225 unsigned long flags;
226
227 spin_lock_irqsave(&pdata->dev_lock, flags);
228 pdata->ops->reg_write(pdata, reg, val);
229 spin_unlock_irqrestore(&pdata->dev_lock, flags);
230}
231
232/* Writes a packet to the TX_DATA_FIFO */
233static inline void
234smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf,
235 unsigned int wordcount)
236{
237 unsigned long flags;
238
239 spin_lock_irqsave(&pdata->dev_lock, flags);
240
241 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
242 while (wordcount--)
243 __smsc911x_reg_write(pdata, TX_DATA_FIFO,
244 swab32(*buf++));
245 goto out;
246 }
247
248 if (pdata->config.flags & SMSC911X_USE_32BIT) {
249 writesl(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount);
250 goto out;
251 }
252
253 if (pdata->config.flags & SMSC911X_USE_16BIT) {
254 while (wordcount--)
255 __smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++);
256 goto out;
257 }
258
259 BUG();
260out:
261 spin_unlock_irqrestore(&pdata->dev_lock, flags);
262}
263
264/* Writes a packet to the TX_DATA_FIFO - shifted version */
265static inline void
266smsc911x_tx_writefifo_shift(struct smsc911x_data *pdata, unsigned int *buf,
267 unsigned int wordcount)
268{
269 unsigned long flags;
270
271 spin_lock_irqsave(&pdata->dev_lock, flags);
272
273 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
274 while (wordcount--)
275 __smsc911x_reg_write_shift(pdata, TX_DATA_FIFO,
276 swab32(*buf++));
277 goto out;
278 }
279
280 if (pdata->config.flags & SMSC911X_USE_32BIT) {
281 writesl(pdata->ioaddr + __smsc_shift(pdata,
282 TX_DATA_FIFO), buf, wordcount);
283 goto out;
284 }
285
286 if (pdata->config.flags & SMSC911X_USE_16BIT) {
287 while (wordcount--)
288 __smsc911x_reg_write_shift(pdata,
289 TX_DATA_FIFO, *buf++);
290 goto out;
291 }
292
293 BUG();
294out:
295 spin_unlock_irqrestore(&pdata->dev_lock, flags);
296}
297
298/* Reads a packet out of the RX_DATA_FIFO */
299static inline void
300smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf,
301 unsigned int wordcount)
302{
303 unsigned long flags;
304
305 spin_lock_irqsave(&pdata->dev_lock, flags);
306
307 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
308 while (wordcount--)
309 *buf++ = swab32(__smsc911x_reg_read(pdata,
310 RX_DATA_FIFO));
311 goto out;
312 }
313
314 if (pdata->config.flags & SMSC911X_USE_32BIT) {
315 readsl(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount);
316 goto out;
317 }
318
319 if (pdata->config.flags & SMSC911X_USE_16BIT) {
320 while (wordcount--)
321 *buf++ = __smsc911x_reg_read(pdata, RX_DATA_FIFO);
322 goto out;
323 }
324
325 BUG();
326out:
327 spin_unlock_irqrestore(&pdata->dev_lock, flags);
328}
329
330/* Reads a packet out of the RX_DATA_FIFO - shifted version */
331static inline void
332smsc911x_rx_readfifo_shift(struct smsc911x_data *pdata, unsigned int *buf,
333 unsigned int wordcount)
334{
335 unsigned long flags;
336
337 spin_lock_irqsave(&pdata->dev_lock, flags);
338
339 if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
340 while (wordcount--)
341 *buf++ = swab32(__smsc911x_reg_read_shift(pdata,
342 RX_DATA_FIFO));
343 goto out;
344 }
345
346 if (pdata->config.flags & SMSC911X_USE_32BIT) {
347 readsl(pdata->ioaddr + __smsc_shift(pdata,
348 RX_DATA_FIFO), buf, wordcount);
349 goto out;
350 }
351
352 if (pdata->config.flags & SMSC911X_USE_16BIT) {
353 while (wordcount--)
354 *buf++ = __smsc911x_reg_read_shift(pdata,
355 RX_DATA_FIFO);
356 goto out;
357 }
358
359 BUG();
360out:
361 spin_unlock_irqrestore(&pdata->dev_lock, flags);
362}
363
364/* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read
365 * and smsc911x_mac_write, so assumes mac_lock is held */
366static int smsc911x_mac_complete(struct smsc911x_data *pdata)
367{
368 int i;
369 u32 val;
370
371 SMSC_ASSERT_MAC_LOCK(pdata);
372
373 for (i = 0; i < 40; i++) {
374 val = smsc911x_reg_read(pdata, MAC_CSR_CMD);
375 if (!(val & MAC_CSR_CMD_CSR_BUSY_))
376 return 0;
377 }
378 SMSC_WARN(pdata, hw, "Timed out waiting for MAC not BUSY. "
379 "MAC_CSR_CMD: 0x%08X", val);
380 return -EIO;
381}
382
383/* Fetches a MAC register value. Assumes mac_lock is acquired */
384static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset)
385{
386 unsigned int temp;
387
388 SMSC_ASSERT_MAC_LOCK(pdata);
389
390 temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
391 if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
392 SMSC_WARN(pdata, hw, "MAC busy at entry");
393 return 0xFFFFFFFF;
394 }
395
396 /* Send the MAC cmd */
397 smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
398 MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_));
399
400 /* Workaround for hardware read-after-write restriction */
401 temp = smsc911x_reg_read(pdata, BYTE_TEST);
402
403 /* Wait for the read to complete */
404 if (likely(smsc911x_mac_complete(pdata) == 0))
405 return smsc911x_reg_read(pdata, MAC_CSR_DATA);
406
407 SMSC_WARN(pdata, hw, "MAC busy after read");
408 return 0xFFFFFFFF;
409}
410
411/* Set a mac register, mac_lock must be acquired before calling */
412static void smsc911x_mac_write(struct smsc911x_data *pdata,
413 unsigned int offset, u32 val)
414{
415 unsigned int temp;
416
417 SMSC_ASSERT_MAC_LOCK(pdata);
418
419 temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
420 if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
421 SMSC_WARN(pdata, hw,
422 "smsc911x_mac_write failed, MAC busy at entry");
423 return;
424 }
425
426 /* Send data to write */
427 smsc911x_reg_write(pdata, MAC_CSR_DATA, val);
428
429 /* Write the actual data */
430 smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
431 MAC_CSR_CMD_CSR_BUSY_));
432
433 /* Workaround for hardware read-after-write restriction */
434 temp = smsc911x_reg_read(pdata, BYTE_TEST);
435
436 /* Wait for the write to complete */
437 if (likely(smsc911x_mac_complete(pdata) == 0))
438 return;
439
440 SMSC_WARN(pdata, hw, "smsc911x_mac_write failed, MAC busy after write");
441}
442
443/* Get a phy register */
444static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
445{
446 struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
447 unsigned long flags;
448 unsigned int addr;
449 int i, reg;
450
451 spin_lock_irqsave(&pdata->mac_lock, flags);
452
453 /* Confirm MII not busy */
454 if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
455 SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_read???");
456 reg = -EIO;
457 goto out;
458 }
459
460 /* Set the address, index & direction (read from PHY) */
461 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6);
462 smsc911x_mac_write(pdata, MII_ACC, addr);
463
464 /* Wait for read to complete w/ timeout */
465 for (i = 0; i < 100; i++)
466 if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
467 reg = smsc911x_mac_read(pdata, MII_DATA);
468 goto out;
469 }
470
471 SMSC_WARN(pdata, hw, "Timed out waiting for MII read to finish");
472 reg = -EIO;
473
474out:
475 spin_unlock_irqrestore(&pdata->mac_lock, flags);
476 return reg;
477}
478
479/* Set a phy register */
480static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
481 u16 val)
482{
483 struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
484 unsigned long flags;
485 unsigned int addr;
486 int i, reg;
487
488 spin_lock_irqsave(&pdata->mac_lock, flags);
489
490 /* Confirm MII not busy */
491 if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
492 SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_write???");
493 reg = -EIO;
494 goto out;
495 }
496
497 /* Put the data to write in the MAC */
498 smsc911x_mac_write(pdata, MII_DATA, val);
499
500 /* Set the address, index & direction (write to PHY) */
501 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
502 MII_ACC_MII_WRITE_;
503 smsc911x_mac_write(pdata, MII_ACC, addr);
504
505 /* Wait for write to complete w/ timeout */
506 for (i = 0; i < 100; i++)
507 if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
508 reg = 0;
509 goto out;
510 }
511
512 SMSC_WARN(pdata, hw, "Timed out waiting for MII write to finish");
513 reg = -EIO;
514
515out:
516 spin_unlock_irqrestore(&pdata->mac_lock, flags);
517 return reg;
518}
519
520/* Switch to external phy. Assumes tx and rx are stopped. */
521static void smsc911x_phy_enable_external(struct smsc911x_data *pdata)
522{
523 unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
524
525 /* Disable phy clocks to the MAC */
526 hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
527 hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
528 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
529 udelay(10); /* Enough time for clocks to stop */
530
531 /* Switch to external phy */
532 hwcfg |= HW_CFG_EXT_PHY_EN_;
533 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
534
535 /* Enable phy clocks to the MAC */
536 hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
537 hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
538 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
539 udelay(10); /* Enough time for clocks to restart */
540
541 hwcfg |= HW_CFG_SMI_SEL_;
542 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
543}
544
545/* Autodetects and enables external phy if present on supported chips.
546 * autodetection can be overridden by specifying SMSC911X_FORCE_INTERNAL_PHY
547 * or SMSC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */
548static void smsc911x_phy_initialise_external(struct smsc911x_data *pdata)
549{
550 unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
551
552 if (pdata->config.flags & SMSC911X_FORCE_INTERNAL_PHY) {
553 SMSC_TRACE(pdata, hw, "Forcing internal PHY");
554 pdata->using_extphy = 0;
555 } else if (pdata->config.flags & SMSC911X_FORCE_EXTERNAL_PHY) {
556 SMSC_TRACE(pdata, hw, "Forcing external PHY");
557 smsc911x_phy_enable_external(pdata);
558 pdata->using_extphy = 1;
559 } else if (hwcfg & HW_CFG_EXT_PHY_DET_) {
560 SMSC_TRACE(pdata, hw,
561 "HW_CFG EXT_PHY_DET set, using external PHY");
562 smsc911x_phy_enable_external(pdata);
563 pdata->using_extphy = 1;
564 } else {
565 SMSC_TRACE(pdata, hw,
566 "HW_CFG EXT_PHY_DET clear, using internal PHY");
567 pdata->using_extphy = 0;
568 }
569}
570
571/* Fetches a tx status out of the status fifo */
572static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata)
573{
574 unsigned int result =
575 smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_;
576
577 if (result != 0)
578 result = smsc911x_reg_read(pdata, TX_STATUS_FIFO);
579
580 return result;
581}
582
583/* Fetches the next rx status */
584static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata)
585{
586 unsigned int result =
587 smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_;
588
589 if (result != 0)
590 result = smsc911x_reg_read(pdata, RX_STATUS_FIFO);
591
592 return result;
593}
594
595#ifdef USE_PHY_WORK_AROUND
596static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata)
597{
598 unsigned int tries;
599 u32 wrsz;
600 u32 rdsz;
601 ulong bufp;
602
603 for (tries = 0; tries < 10; tries++) {
604 unsigned int txcmd_a;
605 unsigned int txcmd_b;
606 unsigned int status;
607 unsigned int pktlength;
608 unsigned int i;
609
610 /* Zero-out rx packet memory */
611 memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE);
612
613 /* Write tx packet to 118 */
614 txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16;
615 txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
616 txcmd_a |= MIN_PACKET_SIZE;
617
618 txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE;
619
620 smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a);
621 smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b);
622
623 bufp = (ulong)pdata->loopback_tx_pkt & (~0x3);
624 wrsz = MIN_PACKET_SIZE + 3;
625 wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3);
626 wrsz >>= 2;
627
628 pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
629
630 /* Wait till transmit is done */
631 i = 60;
632 do {
633 udelay(5);
634 status = smsc911x_tx_get_txstatus(pdata);
635 } while ((i--) && (!status));
636
637 if (!status) {
638 SMSC_WARN(pdata, hw,
639 "Failed to transmit during loopback test");
640 continue;
641 }
642 if (status & TX_STS_ES_) {
643 SMSC_WARN(pdata, hw,
644 "Transmit encountered errors during loopback test");
645 continue;
646 }
647
648 /* Wait till receive is done */
649 i = 60;
650 do {
651 udelay(5);
652 status = smsc911x_rx_get_rxstatus(pdata);
653 } while ((i--) && (!status));
654
655 if (!status) {
656 SMSC_WARN(pdata, hw,
657 "Failed to receive during loopback test");
658 continue;
659 }
660 if (status & RX_STS_ES_) {
661 SMSC_WARN(pdata, hw,
662 "Receive encountered errors during loopback test");
663 continue;
664 }
665
666 pktlength = ((status & 0x3FFF0000UL) >> 16);
667 bufp = (ulong)pdata->loopback_rx_pkt;
668 rdsz = pktlength + 3;
669 rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3);
670 rdsz >>= 2;
671
672 pdata->ops->rx_readfifo(pdata, (unsigned int *)bufp, rdsz);
673
674 if (pktlength != (MIN_PACKET_SIZE + 4)) {
675 SMSC_WARN(pdata, hw, "Unexpected packet size "
676 "during loop back test, size=%d, will retry",
677 pktlength);
678 } else {
679 unsigned int j;
680 int mismatch = 0;
681 for (j = 0; j < MIN_PACKET_SIZE; j++) {
682 if (pdata->loopback_tx_pkt[j]
683 != pdata->loopback_rx_pkt[j]) {
684 mismatch = 1;
685 break;
686 }
687 }
688 if (!mismatch) {
689 SMSC_TRACE(pdata, hw, "Successfully verified "
690 "loopback packet");
691 return 0;
692 } else {
693 SMSC_WARN(pdata, hw, "Data mismatch "
694 "during loop back test, will retry");
695 }
696 }
697 }
698
699 return -EIO;
700}
701
702static int smsc911x_phy_reset(struct smsc911x_data *pdata)
703{
704 struct phy_device *phy_dev = pdata->phy_dev;
705 unsigned int temp;
706 unsigned int i = 100000;
707
708 BUG_ON(!phy_dev);
709 BUG_ON(!phy_dev->bus);
710
711 SMSC_TRACE(pdata, hw, "Performing PHY BCR Reset");
712 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, BMCR_RESET);
713 do {
714 msleep(1);
715 temp = smsc911x_mii_read(phy_dev->bus, phy_dev->addr,
716 MII_BMCR);
717 } while ((i--) && (temp & BMCR_RESET));
718
719 if (temp & BMCR_RESET) {
720 SMSC_WARN(pdata, hw, "PHY reset failed to complete");
721 return -EIO;
722 }
723 /* Extra delay required because the phy may not be completed with
724 * its reset when BMCR_RESET is cleared. Specs say 256 uS is
725 * enough delay but using 1ms here to be safe */
726 msleep(1);
727
728 return 0;
729}
730
731static int smsc911x_phy_loopbacktest(struct net_device *dev)
732{
733 struct smsc911x_data *pdata = netdev_priv(dev);
734 struct phy_device *phy_dev = pdata->phy_dev;
735 int result = -EIO;
736 unsigned int i, val;
737 unsigned long flags;
738
739 /* Initialise tx packet using broadcast destination address */
740 memset(pdata->loopback_tx_pkt, 0xff, ETH_ALEN);
741
742 /* Use incrementing source address */
743 for (i = 6; i < 12; i++)
744 pdata->loopback_tx_pkt[i] = (char)i;
745
746 /* Set length type field */
747 pdata->loopback_tx_pkt[12] = 0x00;
748 pdata->loopback_tx_pkt[13] = 0x00;
749
750 for (i = 14; i < MIN_PACKET_SIZE; i++)
751 pdata->loopback_tx_pkt[i] = (char)i;
752
753 val = smsc911x_reg_read(pdata, HW_CFG);
754 val &= HW_CFG_TX_FIF_SZ_;
755 val |= HW_CFG_SF_;
756 smsc911x_reg_write(pdata, HW_CFG, val);
757
758 smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
759 smsc911x_reg_write(pdata, RX_CFG,
760 (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8);
761
762 for (i = 0; i < 10; i++) {
763 /* Set PHY to 10/FD, no ANEG, and loopback mode */
764 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR,
765 BMCR_LOOPBACK | BMCR_FULLDPLX);
766
767 /* Enable MAC tx/rx, FD */
768 spin_lock_irqsave(&pdata->mac_lock, flags);
769 smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_
770 | MAC_CR_TXEN_ | MAC_CR_RXEN_);
771 spin_unlock_irqrestore(&pdata->mac_lock, flags);
772
773 if (smsc911x_phy_check_loopbackpkt(pdata) == 0) {
774 result = 0;
775 break;
776 }
777 pdata->resetcount++;
778
779 /* Disable MAC rx */
780 spin_lock_irqsave(&pdata->mac_lock, flags);
781 smsc911x_mac_write(pdata, MAC_CR, 0);
782 spin_unlock_irqrestore(&pdata->mac_lock, flags);
783
784 smsc911x_phy_reset(pdata);
785 }
786
787 /* Disable MAC */
788 spin_lock_irqsave(&pdata->mac_lock, flags);
789 smsc911x_mac_write(pdata, MAC_CR, 0);
790 spin_unlock_irqrestore(&pdata->mac_lock, flags);
791
792 /* Cancel PHY loopback mode */
793 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, 0);
794
795 smsc911x_reg_write(pdata, TX_CFG, 0);
796 smsc911x_reg_write(pdata, RX_CFG, 0);
797
798 return result;
799}
800#endif /* USE_PHY_WORK_AROUND */
801
802static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata)
803{
804 struct phy_device *phy_dev = pdata->phy_dev;
805 u32 afc = smsc911x_reg_read(pdata, AFC_CFG);
806 u32 flow;
807 unsigned long flags;
808
809 if (phy_dev->duplex == DUPLEX_FULL) {
810 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
811 u16 rmtadv = phy_read(phy_dev, MII_LPA);
812 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
813
814 if (cap & FLOW_CTRL_RX)
815 flow = 0xFFFF0002;
816 else
817 flow = 0;
818
819 if (cap & FLOW_CTRL_TX)
820 afc |= 0xF;
821 else
822 afc &= ~0xF;
823
824 SMSC_TRACE(pdata, hw, "rx pause %s, tx pause %s",
825 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
826 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
827 } else {
828 SMSC_TRACE(pdata, hw, "half duplex");
829 flow = 0;
830 afc |= 0xF;
831 }
832
833 spin_lock_irqsave(&pdata->mac_lock, flags);
834 smsc911x_mac_write(pdata, FLOW, flow);
835 spin_unlock_irqrestore(&pdata->mac_lock, flags);
836
837 smsc911x_reg_write(pdata, AFC_CFG, afc);
838}
839
840/* Update link mode if anything has changed. Called periodically when the
841 * PHY is in polling mode, even if nothing has changed. */
842static void smsc911x_phy_adjust_link(struct net_device *dev)
843{
844 struct smsc911x_data *pdata = netdev_priv(dev);
845 struct phy_device *phy_dev = pdata->phy_dev;
846 unsigned long flags;
847 int carrier;
848
849 if (phy_dev->duplex != pdata->last_duplex) {
850 unsigned int mac_cr;
851 SMSC_TRACE(pdata, hw, "duplex state has changed");
852
853 spin_lock_irqsave(&pdata->mac_lock, flags);
854 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
855 if (phy_dev->duplex) {
856 SMSC_TRACE(pdata, hw,
857 "configuring for full duplex mode");
858 mac_cr |= MAC_CR_FDPX_;
859 } else {
860 SMSC_TRACE(pdata, hw,
861 "configuring for half duplex mode");
862 mac_cr &= ~MAC_CR_FDPX_;
863 }
864 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
865 spin_unlock_irqrestore(&pdata->mac_lock, flags);
866
867 smsc911x_phy_update_flowcontrol(pdata);
868 pdata->last_duplex = phy_dev->duplex;
869 }
870
871 carrier = netif_carrier_ok(dev);
872 if (carrier != pdata->last_carrier) {
873 SMSC_TRACE(pdata, hw, "carrier state has changed");
874 if (carrier) {
875 SMSC_TRACE(pdata, hw, "configuring for carrier OK");
876 if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) &&
877 (!pdata->using_extphy)) {
878 /* Restore original GPIO configuration */
879 pdata->gpio_setting = pdata->gpio_orig_setting;
880 smsc911x_reg_write(pdata, GPIO_CFG,
881 pdata->gpio_setting);
882 }
883 } else {
884 SMSC_TRACE(pdata, hw, "configuring for no carrier");
885 /* Check global setting that LED1
886 * usage is 10/100 indicator */
887 pdata->gpio_setting = smsc911x_reg_read(pdata,
888 GPIO_CFG);
889 if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_) &&
890 (!pdata->using_extphy)) {
891 /* Force 10/100 LED off, after saving
892 * original GPIO configuration */
893 pdata->gpio_orig_setting = pdata->gpio_setting;
894
895 pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_;
896 pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_
897 | GPIO_CFG_GPIODIR0_
898 | GPIO_CFG_GPIOD0_);
899 smsc911x_reg_write(pdata, GPIO_CFG,
900 pdata->gpio_setting);
901 }
902 }
903 pdata->last_carrier = carrier;
904 }
905}
906
907static int smsc911x_mii_probe(struct net_device *dev)
908{
909 struct smsc911x_data *pdata = netdev_priv(dev);
910 struct phy_device *phydev = NULL;
911 int ret;
912
913 /* find the first phy */
914 phydev = phy_find_first(pdata->mii_bus);
915 if (!phydev) {
916 netdev_err(dev, "no PHY found\n");
917 return -ENODEV;
918 }
919
920 SMSC_TRACE(pdata, probe, "PHY: addr %d, phy_id 0x%08X",
921 phydev->addr, phydev->phy_id);
922
923 ret = phy_connect_direct(dev, phydev,
924 &smsc911x_phy_adjust_link, 0,
925 pdata->config.phy_interface);
926
927 if (ret) {
928 netdev_err(dev, "Could not attach to PHY\n");
929 return ret;
930 }
931
932 netdev_info(dev,
933 "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
934 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
935
936 /* mask with MAC supported features */
937 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
938 SUPPORTED_Asym_Pause);
939 phydev->advertising = phydev->supported;
940
941 pdata->phy_dev = phydev;
942 pdata->last_duplex = -1;
943 pdata->last_carrier = -1;
944
945#ifdef USE_PHY_WORK_AROUND
946 if (smsc911x_phy_loopbacktest(dev) < 0) {
947 SMSC_WARN(pdata, hw, "Failed Loop Back Test");
948 return -ENODEV;
949 }
950 SMSC_TRACE(pdata, hw, "Passed Loop Back Test");
951#endif /* USE_PHY_WORK_AROUND */
952
953 SMSC_TRACE(pdata, hw, "phy initialised successfully");
954 return 0;
955}
956
957static int __devinit smsc911x_mii_init(struct platform_device *pdev,
958 struct net_device *dev)
959{
960 struct smsc911x_data *pdata = netdev_priv(dev);
961 int err = -ENXIO, i;
962
963 pdata->mii_bus = mdiobus_alloc();
964 if (!pdata->mii_bus) {
965 err = -ENOMEM;
966 goto err_out_1;
967 }
968
969 pdata->mii_bus->name = SMSC_MDIONAME;
970 snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
971 pdata->mii_bus->priv = pdata;
972 pdata->mii_bus->read = smsc911x_mii_read;
973 pdata->mii_bus->write = smsc911x_mii_write;
974 pdata->mii_bus->irq = pdata->phy_irq;
975 for (i = 0; i < PHY_MAX_ADDR; ++i)
976 pdata->mii_bus->irq[i] = PHY_POLL;
977
978 pdata->mii_bus->parent = &pdev->dev;
979
980 switch (pdata->idrev & 0xFFFF0000) {
981 case 0x01170000:
982 case 0x01150000:
983 case 0x117A0000:
984 case 0x115A0000:
985 /* External PHY supported, try to autodetect */
986 smsc911x_phy_initialise_external(pdata);
987 break;
988 default:
989 SMSC_TRACE(pdata, hw, "External PHY is not supported, "
990 "using internal PHY");
991 pdata->using_extphy = 0;
992 break;
993 }
994
995 if (!pdata->using_extphy) {
996 /* Mask all PHYs except ID 1 (internal) */
997 pdata->mii_bus->phy_mask = ~(1 << 1);
998 }
999
1000 if (mdiobus_register(pdata->mii_bus)) {
1001 SMSC_WARN(pdata, probe, "Error registering mii bus");
1002 goto err_out_free_bus_2;
1003 }
1004
1005 if (smsc911x_mii_probe(dev) < 0) {
1006 SMSC_WARN(pdata, probe, "Error registering mii bus");
1007 goto err_out_unregister_bus_3;
1008 }
1009
1010 return 0;
1011
1012err_out_unregister_bus_3:
1013 mdiobus_unregister(pdata->mii_bus);
1014err_out_free_bus_2:
1015 mdiobus_free(pdata->mii_bus);
1016err_out_1:
1017 return err;
1018}
1019
1020/* Gets the number of tx statuses in the fifo */
1021static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata)
1022{
1023 return (smsc911x_reg_read(pdata, TX_FIFO_INF)
1024 & TX_FIFO_INF_TSUSED_) >> 16;
1025}
1026
1027/* Reads tx statuses and increments counters where necessary */
1028static void smsc911x_tx_update_txcounters(struct net_device *dev)
1029{
1030 struct smsc911x_data *pdata = netdev_priv(dev);
1031 unsigned int tx_stat;
1032
1033 while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) {
1034 if (unlikely(tx_stat & 0x80000000)) {
1035 /* In this driver the packet tag is used as the packet
1036 * length. Since a packet length can never reach the
1037 * size of 0x8000, this bit is reserved. It is worth
1038 * noting that the "reserved bit" in the warning above
1039 * does not reference a hardware defined reserved bit
1040 * but rather a driver defined one.
1041 */
1042 SMSC_WARN(pdata, hw, "Packet tag reserved bit is high");
1043 } else {
1044 if (unlikely(tx_stat & TX_STS_ES_)) {
1045 dev->stats.tx_errors++;
1046 } else {
1047 dev->stats.tx_packets++;
1048 dev->stats.tx_bytes += (tx_stat >> 16);
1049 }
1050 if (unlikely(tx_stat & TX_STS_EXCESS_COL_)) {
1051 dev->stats.collisions += 16;
1052 dev->stats.tx_aborted_errors += 1;
1053 } else {
1054 dev->stats.collisions +=
1055 ((tx_stat >> 3) & 0xF);
1056 }
1057 if (unlikely(tx_stat & TX_STS_LOST_CARRIER_))
1058 dev->stats.tx_carrier_errors += 1;
1059 if (unlikely(tx_stat & TX_STS_LATE_COL_)) {
1060 dev->stats.collisions++;
1061 dev->stats.tx_aborted_errors++;
1062 }
1063 }
1064 }
1065}
1066
1067/* Increments the Rx error counters */
1068static void
1069smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat)
1070{
1071 int crc_err = 0;
1072
1073 if (unlikely(rxstat & RX_STS_ES_)) {
1074 dev->stats.rx_errors++;
1075 if (unlikely(rxstat & RX_STS_CRC_ERR_)) {
1076 dev->stats.rx_crc_errors++;
1077 crc_err = 1;
1078 }
1079 }
1080 if (likely(!crc_err)) {
1081 if (unlikely((rxstat & RX_STS_FRAME_TYPE_) &&
1082 (rxstat & RX_STS_LENGTH_ERR_)))
1083 dev->stats.rx_length_errors++;
1084 if (rxstat & RX_STS_MCAST_)
1085 dev->stats.multicast++;
1086 }
1087}
1088
1089/* Quickly dumps bad packets */
1090static void
1091smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktbytes)
1092{
1093 unsigned int pktwords = (pktbytes + NET_IP_ALIGN + 3) >> 2;
1094
1095 if (likely(pktwords >= 4)) {
1096 unsigned int timeout = 500;
1097 unsigned int val;
1098 smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_);
1099 do {
1100 udelay(1);
1101 val = smsc911x_reg_read(pdata, RX_DP_CTRL);
1102 } while ((val & RX_DP_CTRL_RX_FFWD_) && --timeout);
1103
1104 if (unlikely(timeout == 0))
1105 SMSC_WARN(pdata, hw, "Timed out waiting for "
1106 "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val);
1107 } else {
1108 unsigned int temp;
1109 while (pktwords--)
1110 temp = smsc911x_reg_read(pdata, RX_DATA_FIFO);
1111 }
1112}
1113
1114/* NAPI poll function */
1115static int smsc911x_poll(struct napi_struct *napi, int budget)
1116{
1117 struct smsc911x_data *pdata =
1118 container_of(napi, struct smsc911x_data, napi);
1119 struct net_device *dev = pdata->dev;
1120 int npackets = 0;
1121
1122 while (npackets < budget) {
1123 unsigned int pktlength;
1124 unsigned int pktwords;
1125 struct sk_buff *skb;
1126 unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata);
1127
1128 if (!rxstat) {
1129 unsigned int temp;
1130 /* We processed all packets available. Tell NAPI it can
1131 * stop polling then re-enable rx interrupts */
1132 smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_);
1133 napi_complete(napi);
1134 temp = smsc911x_reg_read(pdata, INT_EN);
1135 temp |= INT_EN_RSFL_EN_;
1136 smsc911x_reg_write(pdata, INT_EN, temp);
1137 break;
1138 }
1139
1140 /* Count packet for NAPI scheduling, even if it has an error.
1141 * Error packets still require cycles to discard */
1142 npackets++;
1143
1144 pktlength = ((rxstat & 0x3FFF0000) >> 16);
1145 pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2;
1146 smsc911x_rx_counterrors(dev, rxstat);
1147
1148 if (unlikely(rxstat & RX_STS_ES_)) {
1149 SMSC_WARN(pdata, rx_err,
1150 "Discarding packet with error bit set");
1151 /* Packet has an error, discard it and continue with
1152 * the next */
1153 smsc911x_rx_fastforward(pdata, pktwords);
1154 dev->stats.rx_dropped++;
1155 continue;
1156 }
1157
1158 skb = netdev_alloc_skb(dev, pktlength + NET_IP_ALIGN);
1159 if (unlikely(!skb)) {
1160 SMSC_WARN(pdata, rx_err,
1161 "Unable to allocate skb for rx packet");
1162 /* Drop the packet and stop this polling iteration */
1163 smsc911x_rx_fastforward(pdata, pktwords);
1164 dev->stats.rx_dropped++;
1165 break;
1166 }
1167
1168 skb->data = skb->head;
1169 skb_reset_tail_pointer(skb);
1170
1171 /* Align IP on 16B boundary */
1172 skb_reserve(skb, NET_IP_ALIGN);
1173 skb_put(skb, pktlength - 4);
1174 pdata->ops->rx_readfifo(pdata,
1175 (unsigned int *)skb->head, pktwords);
1176 skb->protocol = eth_type_trans(skb, dev);
1177 skb_checksum_none_assert(skb);
1178 netif_receive_skb(skb);
1179
1180 /* Update counters */
1181 dev->stats.rx_packets++;
1182 dev->stats.rx_bytes += (pktlength - 4);
1183 }
1184
1185 /* Return total received packets */
1186 return npackets;
1187}
1188
1189/* Returns hash bit number for given MAC address
1190 * Example:
1191 * 01 00 5E 00 00 01 -> returns bit number 31 */
1192static unsigned int smsc911x_hash(char addr[ETH_ALEN])
1193{
1194 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
1195}
1196
1197static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata)
1198{
1199 /* Performs the multicast & mac_cr update. This is called when
1200 * safe on the current hardware, and with the mac_lock held */
1201 unsigned int mac_cr;
1202
1203 SMSC_ASSERT_MAC_LOCK(pdata);
1204
1205 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
1206 mac_cr |= pdata->set_bits_mask;
1207 mac_cr &= ~(pdata->clear_bits_mask);
1208 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
1209 smsc911x_mac_write(pdata, HASHH, pdata->hashhi);
1210 smsc911x_mac_write(pdata, HASHL, pdata->hashlo);
1211 SMSC_TRACE(pdata, hw, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X",
1212 mac_cr, pdata->hashhi, pdata->hashlo);
1213}
1214
1215static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata)
1216{
1217 unsigned int mac_cr;
1218
1219 /* This function is only called for older LAN911x devices
1220 * (revA or revB), where MAC_CR, HASHH and HASHL should not
1221 * be modified during Rx - newer devices immediately update the
1222 * registers.
1223 *
1224 * This is called from interrupt context */
1225
1226 spin_lock(&pdata->mac_lock);
1227
1228 /* Check Rx has stopped */
1229 if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_)
1230 SMSC_WARN(pdata, drv, "Rx not stopped");
1231
1232 /* Perform the update - safe to do now Rx has stopped */
1233 smsc911x_rx_multicast_update(pdata);
1234
1235 /* Re-enable Rx */
1236 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
1237 mac_cr |= MAC_CR_RXEN_;
1238 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
1239
1240 pdata->multicast_update_pending = 0;
1241
1242 spin_unlock(&pdata->mac_lock);
1243}
1244
1245static int smsc911x_soft_reset(struct smsc911x_data *pdata)
1246{
1247 unsigned int timeout;
1248 unsigned int temp;
1249
1250 /* Reset the LAN911x */
1251 smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_);
1252 timeout = 10;
1253 do {
1254 udelay(10);
1255 temp = smsc911x_reg_read(pdata, HW_CFG);
1256 } while ((--timeout) && (temp & HW_CFG_SRST_));
1257
1258 if (unlikely(temp & HW_CFG_SRST_)) {
1259 SMSC_WARN(pdata, drv, "Failed to complete reset");
1260 return -EIO;
1261 }
1262 return 0;
1263}
1264
1265/* Sets the device MAC address to dev_addr, called with mac_lock held */
1266static void
1267smsc911x_set_hw_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6])
1268{
1269 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
1270 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
1271 (dev_addr[1] << 8) | dev_addr[0];
1272
1273 SMSC_ASSERT_MAC_LOCK(pdata);
1274
1275 smsc911x_mac_write(pdata, ADDRH, mac_high16);
1276 smsc911x_mac_write(pdata, ADDRL, mac_low32);
1277}
1278
1279static int smsc911x_open(struct net_device *dev)
1280{
1281 struct smsc911x_data *pdata = netdev_priv(dev);
1282 unsigned int timeout;
1283 unsigned int temp;
1284 unsigned int intcfg;
1285
1286 /* if the phy is not yet registered, retry later*/
1287 if (!pdata->phy_dev) {
1288 SMSC_WARN(pdata, hw, "phy_dev is NULL");
1289 return -EAGAIN;
1290 }
1291
1292 if (!is_valid_ether_addr(dev->dev_addr)) {
1293 SMSC_WARN(pdata, hw, "dev_addr is not a valid MAC address");
1294 return -EADDRNOTAVAIL;
1295 }
1296
1297 /* Reset the LAN911x */
1298 if (smsc911x_soft_reset(pdata)) {
1299 SMSC_WARN(pdata, hw, "soft reset failed");
1300 return -EIO;
1301 }
1302
1303 smsc911x_reg_write(pdata, HW_CFG, 0x00050000);
1304 smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740);
1305
1306 /* Increase the legal frame size of VLAN tagged frames to 1522 bytes */
1307 spin_lock_irq(&pdata->mac_lock);
1308 smsc911x_mac_write(pdata, VLAN1, ETH_P_8021Q);
1309 spin_unlock_irq(&pdata->mac_lock);
1310
1311 /* Make sure EEPROM has finished loading before setting GPIO_CFG */
1312 timeout = 50;
1313 while ((smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) &&
1314 --timeout) {
1315 udelay(10);
1316 }
1317
1318 if (unlikely(timeout == 0))
1319 SMSC_WARN(pdata, ifup,
1320 "Timed out waiting for EEPROM busy bit to clear");
1321
1322 smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000);
1323
1324 /* The soft reset above cleared the device's MAC address,
1325 * restore it from local copy (set in probe) */
1326 spin_lock_irq(&pdata->mac_lock);
1327 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
1328 spin_unlock_irq(&pdata->mac_lock);
1329
1330 /* Initialise irqs, but leave all sources disabled */
1331 smsc911x_reg_write(pdata, INT_EN, 0);
1332 smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
1333
1334 /* Set interrupt deassertion to 100uS */
1335 intcfg = ((10 << 24) | INT_CFG_IRQ_EN_);
1336
1337 if (pdata->config.irq_polarity) {
1338 SMSC_TRACE(pdata, ifup, "irq polarity: active high");
1339 intcfg |= INT_CFG_IRQ_POL_;
1340 } else {
1341 SMSC_TRACE(pdata, ifup, "irq polarity: active low");
1342 }
1343
1344 if (pdata->config.irq_type) {
1345 SMSC_TRACE(pdata, ifup, "irq type: push-pull");
1346 intcfg |= INT_CFG_IRQ_TYPE_;
1347 } else {
1348 SMSC_TRACE(pdata, ifup, "irq type: open drain");
1349 }
1350
1351 smsc911x_reg_write(pdata, INT_CFG, intcfg);
1352
1353 SMSC_TRACE(pdata, ifup, "Testing irq handler using IRQ %d", dev->irq);
1354 pdata->software_irq_signal = 0;
1355 smp_wmb();
1356
1357 temp = smsc911x_reg_read(pdata, INT_EN);
1358 temp |= INT_EN_SW_INT_EN_;
1359 smsc911x_reg_write(pdata, INT_EN, temp);
1360
1361 timeout = 1000;
1362 while (timeout--) {
1363 if (pdata->software_irq_signal)
1364 break;
1365 msleep(1);
1366 }
1367
1368 if (!pdata->software_irq_signal) {
1369 netdev_warn(dev, "ISR failed signaling test (IRQ %d)\n",
1370 dev->irq);
1371 return -ENODEV;
1372 }
1373 SMSC_TRACE(pdata, ifup, "IRQ handler passed test using IRQ %d",
1374 dev->irq);
1375
1376 netdev_info(dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n",
1377 (unsigned long)pdata->ioaddr, dev->irq);
1378
1379 /* Reset the last known duplex and carrier */
1380 pdata->last_duplex = -1;
1381 pdata->last_carrier = -1;
1382
1383 /* Bring the PHY up */
1384 phy_start(pdata->phy_dev);
1385
1386 temp = smsc911x_reg_read(pdata, HW_CFG);
1387 /* Preserve TX FIFO size and external PHY configuration */
1388 temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF);
1389 temp |= HW_CFG_SF_;
1390 smsc911x_reg_write(pdata, HW_CFG, temp);
1391
1392 temp = smsc911x_reg_read(pdata, FIFO_INT);
1393 temp |= FIFO_INT_TX_AVAIL_LEVEL_;
1394 temp &= ~(FIFO_INT_RX_STS_LEVEL_);
1395 smsc911x_reg_write(pdata, FIFO_INT, temp);
1396
1397 /* set RX Data offset to 2 bytes for alignment */
1398 smsc911x_reg_write(pdata, RX_CFG, (2 << 8));
1399
1400 /* enable NAPI polling before enabling RX interrupts */
1401 napi_enable(&pdata->napi);
1402
1403 temp = smsc911x_reg_read(pdata, INT_EN);
1404 temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_ | INT_EN_RXSTOP_INT_EN_);
1405 smsc911x_reg_write(pdata, INT_EN, temp);
1406
1407 spin_lock_irq(&pdata->mac_lock);
1408 temp = smsc911x_mac_read(pdata, MAC_CR);
1409 temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
1410 smsc911x_mac_write(pdata, MAC_CR, temp);
1411 spin_unlock_irq(&pdata->mac_lock);
1412
1413 smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
1414
1415 netif_start_queue(dev);
1416 return 0;
1417}
1418
1419/* Entry point for stopping the interface */
1420static int smsc911x_stop(struct net_device *dev)
1421{
1422 struct smsc911x_data *pdata = netdev_priv(dev);
1423 unsigned int temp;
1424
1425 /* Disable all device interrupts */
1426 temp = smsc911x_reg_read(pdata, INT_CFG);
1427 temp &= ~INT_CFG_IRQ_EN_;
1428 smsc911x_reg_write(pdata, INT_CFG, temp);
1429
1430 /* Stop Tx and Rx polling */
1431 netif_stop_queue(dev);
1432 napi_disable(&pdata->napi);
1433
1434 /* At this point all Rx and Tx activity is stopped */
1435 dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
1436 smsc911x_tx_update_txcounters(dev);
1437
1438 /* Bring the PHY down */
1439 if (pdata->phy_dev)
1440 phy_stop(pdata->phy_dev);
1441
1442 SMSC_TRACE(pdata, ifdown, "Interface stopped");
1443 return 0;
1444}
1445
1446/* Entry point for transmitting a packet */
1447static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
1448{
1449 struct smsc911x_data *pdata = netdev_priv(dev);
1450 unsigned int freespace;
1451 unsigned int tx_cmd_a;
1452 unsigned int tx_cmd_b;
1453 unsigned int temp;
1454 u32 wrsz;
1455 ulong bufp;
1456
1457 freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_;
1458
1459 if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD))
1460 SMSC_WARN(pdata, tx_err,
1461 "Tx data fifo low, space available: %d", freespace);
1462
1463 /* Word alignment adjustment */
1464 tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16;
1465 tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
1466 tx_cmd_a |= (unsigned int)skb->len;
1467
1468 tx_cmd_b = ((unsigned int)skb->len) << 16;
1469 tx_cmd_b |= (unsigned int)skb->len;
1470
1471 smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a);
1472 smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b);
1473
1474 bufp = (ulong)skb->data & (~0x3);
1475 wrsz = (u32)skb->len + 3;
1476 wrsz += (u32)((ulong)skb->data & 0x3);
1477 wrsz >>= 2;
1478
1479 pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
1480 freespace -= (skb->len + 32);
1481 skb_tx_timestamp(skb);
1482 dev_kfree_skb(skb);
1483
1484 if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30))
1485 smsc911x_tx_update_txcounters(dev);
1486
1487 if (freespace < TX_FIFO_LOW_THRESHOLD) {
1488 netif_stop_queue(dev);
1489 temp = smsc911x_reg_read(pdata, FIFO_INT);
1490 temp &= 0x00FFFFFF;
1491 temp |= 0x32000000;
1492 smsc911x_reg_write(pdata, FIFO_INT, temp);
1493 }
1494
1495 return NETDEV_TX_OK;
1496}
1497
1498/* Entry point for getting status counters */
1499static struct net_device_stats *smsc911x_get_stats(struct net_device *dev)
1500{
1501 struct smsc911x_data *pdata = netdev_priv(dev);
1502 smsc911x_tx_update_txcounters(dev);
1503 dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
1504 return &dev->stats;
1505}
1506
1507/* Entry point for setting addressing modes */
1508static void smsc911x_set_multicast_list(struct net_device *dev)
1509{
1510 struct smsc911x_data *pdata = netdev_priv(dev);
1511 unsigned long flags;
1512
1513 if (dev->flags & IFF_PROMISC) {
1514 /* Enabling promiscuous mode */
1515 pdata->set_bits_mask = MAC_CR_PRMS_;
1516 pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
1517 pdata->hashhi = 0;
1518 pdata->hashlo = 0;
1519 } else if (dev->flags & IFF_ALLMULTI) {
1520 /* Enabling all multicast mode */
1521 pdata->set_bits_mask = MAC_CR_MCPAS_;
1522 pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_);
1523 pdata->hashhi = 0;
1524 pdata->hashlo = 0;
1525 } else if (!netdev_mc_empty(dev)) {
1526 /* Enabling specific multicast addresses */
1527 unsigned int hash_high = 0;
1528 unsigned int hash_low = 0;
1529 struct netdev_hw_addr *ha;
1530
1531 pdata->set_bits_mask = MAC_CR_HPFILT_;
1532 pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_);
1533
1534 netdev_for_each_mc_addr(ha, dev) {
1535 unsigned int bitnum = smsc911x_hash(ha->addr);
1536 unsigned int mask = 0x01 << (bitnum & 0x1F);
1537
1538 if (bitnum & 0x20)
1539 hash_high |= mask;
1540 else
1541 hash_low |= mask;
1542 }
1543
1544 pdata->hashhi = hash_high;
1545 pdata->hashlo = hash_low;
1546 } else {
1547 /* Enabling local MAC address only */
1548 pdata->set_bits_mask = 0;
1549 pdata->clear_bits_mask =
1550 (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
1551 pdata->hashhi = 0;
1552 pdata->hashlo = 0;
1553 }
1554
1555 spin_lock_irqsave(&pdata->mac_lock, flags);
1556
1557 if (pdata->generation <= 1) {
1558 /* Older hardware revision - cannot change these flags while
1559 * receiving data */
1560 if (!pdata->multicast_update_pending) {
1561 unsigned int temp;
1562 SMSC_TRACE(pdata, hw, "scheduling mcast update");
1563 pdata->multicast_update_pending = 1;
1564
1565 /* Request the hardware to stop, then perform the
1566 * update when we get an RX_STOP interrupt */
1567 temp = smsc911x_mac_read(pdata, MAC_CR);
1568 temp &= ~(MAC_CR_RXEN_);
1569 smsc911x_mac_write(pdata, MAC_CR, temp);
1570 } else {
1571 /* There is another update pending, this should now
1572 * use the newer values */
1573 }
1574 } else {
1575 /* Newer hardware revision - can write immediately */
1576 smsc911x_rx_multicast_update(pdata);
1577 }
1578
1579 spin_unlock_irqrestore(&pdata->mac_lock, flags);
1580}
1581
1582static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id)
1583{
1584 struct net_device *dev = dev_id;
1585 struct smsc911x_data *pdata = netdev_priv(dev);
1586 u32 intsts = smsc911x_reg_read(pdata, INT_STS);
1587 u32 inten = smsc911x_reg_read(pdata, INT_EN);
1588 int serviced = IRQ_NONE;
1589 u32 temp;
1590
1591 if (unlikely(intsts & inten & INT_STS_SW_INT_)) {
1592 temp = smsc911x_reg_read(pdata, INT_EN);
1593 temp &= (~INT_EN_SW_INT_EN_);
1594 smsc911x_reg_write(pdata, INT_EN, temp);
1595 smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_);
1596 pdata->software_irq_signal = 1;
1597 smp_wmb();
1598 serviced = IRQ_HANDLED;
1599 }
1600
1601 if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) {
1602 /* Called when there is a multicast update scheduled and
1603 * it is now safe to complete the update */
1604 SMSC_TRACE(pdata, intr, "RX Stop interrupt");
1605 smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_);
1606 if (pdata->multicast_update_pending)
1607 smsc911x_rx_multicast_update_workaround(pdata);
1608 serviced = IRQ_HANDLED;
1609 }
1610
1611 if (intsts & inten & INT_STS_TDFA_) {
1612 temp = smsc911x_reg_read(pdata, FIFO_INT);
1613 temp |= FIFO_INT_TX_AVAIL_LEVEL_;
1614 smsc911x_reg_write(pdata, FIFO_INT, temp);
1615 smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_);
1616 netif_wake_queue(dev);
1617 serviced = IRQ_HANDLED;
1618 }
1619
1620 if (unlikely(intsts & inten & INT_STS_RXE_)) {
1621 SMSC_TRACE(pdata, intr, "RX Error interrupt");
1622 smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_);
1623 serviced = IRQ_HANDLED;
1624 }
1625
1626 if (likely(intsts & inten & INT_STS_RSFL_)) {
1627 if (likely(napi_schedule_prep(&pdata->napi))) {
1628 /* Disable Rx interrupts */
1629 temp = smsc911x_reg_read(pdata, INT_EN);
1630 temp &= (~INT_EN_RSFL_EN_);
1631 smsc911x_reg_write(pdata, INT_EN, temp);
1632 /* Schedule a NAPI poll */
1633 __napi_schedule(&pdata->napi);
1634 } else {
1635 SMSC_WARN(pdata, rx_err, "napi_schedule_prep failed");
1636 }
1637 serviced = IRQ_HANDLED;
1638 }
1639
1640 return serviced;
1641}
1642
1643#ifdef CONFIG_NET_POLL_CONTROLLER
1644static void smsc911x_poll_controller(struct net_device *dev)
1645{
1646 disable_irq(dev->irq);
1647 smsc911x_irqhandler(0, dev);
1648 enable_irq(dev->irq);
1649}
1650#endif /* CONFIG_NET_POLL_CONTROLLER */
1651
1652static int smsc911x_set_mac_address(struct net_device *dev, void *p)
1653{
1654 struct smsc911x_data *pdata = netdev_priv(dev);
1655 struct sockaddr *addr = p;
1656
1657 /* On older hardware revisions we cannot change the mac address
1658 * registers while receiving data. Newer devices can safely change
1659 * this at any time. */
1660 if (pdata->generation <= 1 && netif_running(dev))
1661 return -EBUSY;
1662
1663 if (!is_valid_ether_addr(addr->sa_data))
1664 return -EADDRNOTAVAIL;
1665
1666 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
1667
1668 spin_lock_irq(&pdata->mac_lock);
1669 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
1670 spin_unlock_irq(&pdata->mac_lock);
1671
1672 netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr);
1673
1674 return 0;
1675}
1676
1677/* Standard ioctls for mii-tool */
1678static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1679{
1680 struct smsc911x_data *pdata = netdev_priv(dev);
1681
1682 if (!netif_running(dev) || !pdata->phy_dev)
1683 return -EINVAL;
1684
1685 return phy_mii_ioctl(pdata->phy_dev, ifr, cmd);
1686}
1687
1688static int
1689smsc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1690{
1691 struct smsc911x_data *pdata = netdev_priv(dev);
1692
1693 cmd->maxtxpkt = 1;
1694 cmd->maxrxpkt = 1;
1695 return phy_ethtool_gset(pdata->phy_dev, cmd);
1696}
1697
1698static int
1699smsc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1700{
1701 struct smsc911x_data *pdata = netdev_priv(dev);
1702
1703 return phy_ethtool_sset(pdata->phy_dev, cmd);
1704}
1705
1706static void smsc911x_ethtool_getdrvinfo(struct net_device *dev,
1707 struct ethtool_drvinfo *info)
1708{
1709 strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver));
1710 strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version));
1711 strlcpy(info->bus_info, dev_name(dev->dev.parent),
1712 sizeof(info->bus_info));
1713}
1714
1715static int smsc911x_ethtool_nwayreset(struct net_device *dev)
1716{
1717 struct smsc911x_data *pdata = netdev_priv(dev);
1718
1719 return phy_start_aneg(pdata->phy_dev);
1720}
1721
1722static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev)
1723{
1724 struct smsc911x_data *pdata = netdev_priv(dev);
1725 return pdata->msg_enable;
1726}
1727
1728static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
1729{
1730 struct smsc911x_data *pdata = netdev_priv(dev);
1731 pdata->msg_enable = level;
1732}
1733
1734static int smsc911x_ethtool_getregslen(struct net_device *dev)
1735{
1736 return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) *
1737 sizeof(u32);
1738}
1739
1740static void
1741smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
1742 void *buf)
1743{
1744 struct smsc911x_data *pdata = netdev_priv(dev);
1745 struct phy_device *phy_dev = pdata->phy_dev;
1746 unsigned long flags;
1747 unsigned int i;
1748 unsigned int j = 0;
1749 u32 *data = buf;
1750
1751 regs->version = pdata->idrev;
1752 for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32)))
1753 data[j++] = smsc911x_reg_read(pdata, i);
1754
1755 for (i = MAC_CR; i <= WUCSR; i++) {
1756 spin_lock_irqsave(&pdata->mac_lock, flags);
1757 data[j++] = smsc911x_mac_read(pdata, i);
1758 spin_unlock_irqrestore(&pdata->mac_lock, flags);
1759 }
1760
1761 for (i = 0; i <= 31; i++)
1762 data[j++] = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, i);
1763}
1764
1765static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata)
1766{
1767 unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG);
1768 temp &= ~GPIO_CFG_EEPR_EN_;
1769 smsc911x_reg_write(pdata, GPIO_CFG, temp);
1770 msleep(1);
1771}
1772
1773static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op)
1774{
1775 int timeout = 100;
1776 u32 e2cmd;
1777
1778 SMSC_TRACE(pdata, drv, "op 0x%08x", op);
1779 if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
1780 SMSC_WARN(pdata, drv, "Busy at start");
1781 return -EBUSY;
1782 }
1783
1784 e2cmd = op | E2P_CMD_EPC_BUSY_;
1785 smsc911x_reg_write(pdata, E2P_CMD, e2cmd);
1786
1787 do {
1788 msleep(1);
1789 e2cmd = smsc911x_reg_read(pdata, E2P_CMD);
1790 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
1791
1792 if (!timeout) {
1793 SMSC_TRACE(pdata, drv, "TIMED OUT");
1794 return -EAGAIN;
1795 }
1796
1797 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
1798 SMSC_TRACE(pdata, drv, "Error occurred during eeprom operation");
1799 return -EINVAL;
1800 }
1801
1802 return 0;
1803}
1804
1805static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata,
1806 u8 address, u8 *data)
1807{
1808 u32 op = E2P_CMD_EPC_CMD_READ_ | address;
1809 int ret;
1810
1811 SMSC_TRACE(pdata, drv, "address 0x%x", address);
1812 ret = smsc911x_eeprom_send_cmd(pdata, op);
1813
1814 if (!ret)
1815 data[address] = smsc911x_reg_read(pdata, E2P_DATA);
1816
1817 return ret;
1818}
1819
1820static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata,
1821 u8 address, u8 data)
1822{
1823 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
1824 u32 temp;
1825 int ret;
1826
1827 SMSC_TRACE(pdata, drv, "address 0x%x, data 0x%x", address, data);
1828 ret = smsc911x_eeprom_send_cmd(pdata, op);
1829
1830 if (!ret) {
1831 op = E2P_CMD_EPC_CMD_WRITE_ | address;
1832 smsc911x_reg_write(pdata, E2P_DATA, (u32)data);
1833
1834 /* Workaround for hardware read-after-write restriction */
1835 temp = smsc911x_reg_read(pdata, BYTE_TEST);
1836
1837 ret = smsc911x_eeprom_send_cmd(pdata, op);
1838 }
1839
1840 return ret;
1841}
1842
1843static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev)
1844{
1845 return SMSC911X_EEPROM_SIZE;
1846}
1847
1848static int smsc911x_ethtool_get_eeprom(struct net_device *dev,
1849 struct ethtool_eeprom *eeprom, u8 *data)
1850{
1851 struct smsc911x_data *pdata = netdev_priv(dev);
1852 u8 eeprom_data[SMSC911X_EEPROM_SIZE];
1853 int len;
1854 int i;
1855
1856 smsc911x_eeprom_enable_access(pdata);
1857
1858 len = min(eeprom->len, SMSC911X_EEPROM_SIZE);
1859 for (i = 0; i < len; i++) {
1860 int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data);
1861 if (ret < 0) {
1862 eeprom->len = 0;
1863 return ret;
1864 }
1865 }
1866
1867 memcpy(data, &eeprom_data[eeprom->offset], len);
1868 eeprom->len = len;
1869 return 0;
1870}
1871
1872static int smsc911x_ethtool_set_eeprom(struct net_device *dev,
1873 struct ethtool_eeprom *eeprom, u8 *data)
1874{
1875 int ret;
1876 struct smsc911x_data *pdata = netdev_priv(dev);
1877
1878 smsc911x_eeprom_enable_access(pdata);
1879 smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_);
1880 ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data);
1881 smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_);
1882
1883 /* Single byte write, according to man page */
1884 eeprom->len = 1;
1885
1886 return ret;
1887}
1888
1889static const struct ethtool_ops smsc911x_ethtool_ops = {
1890 .get_settings = smsc911x_ethtool_getsettings,
1891 .set_settings = smsc911x_ethtool_setsettings,
1892 .get_link = ethtool_op_get_link,
1893 .get_drvinfo = smsc911x_ethtool_getdrvinfo,
1894 .nway_reset = smsc911x_ethtool_nwayreset,
1895 .get_msglevel = smsc911x_ethtool_getmsglevel,
1896 .set_msglevel = smsc911x_ethtool_setmsglevel,
1897 .get_regs_len = smsc911x_ethtool_getregslen,
1898 .get_regs = smsc911x_ethtool_getregs,
1899 .get_eeprom_len = smsc911x_ethtool_get_eeprom_len,
1900 .get_eeprom = smsc911x_ethtool_get_eeprom,
1901 .set_eeprom = smsc911x_ethtool_set_eeprom,
1902};
1903
1904static const struct net_device_ops smsc911x_netdev_ops = {
1905 .ndo_open = smsc911x_open,
1906 .ndo_stop = smsc911x_stop,
1907 .ndo_start_xmit = smsc911x_hard_start_xmit,
1908 .ndo_get_stats = smsc911x_get_stats,
1909 .ndo_set_multicast_list = smsc911x_set_multicast_list,
1910 .ndo_do_ioctl = smsc911x_do_ioctl,
1911 .ndo_change_mtu = eth_change_mtu,
1912 .ndo_validate_addr = eth_validate_addr,
1913 .ndo_set_mac_address = smsc911x_set_mac_address,
1914#ifdef CONFIG_NET_POLL_CONTROLLER
1915 .ndo_poll_controller = smsc911x_poll_controller,
1916#endif
1917};
1918
1919/* copies the current mac address from hardware to dev->dev_addr */
1920static void __devinit smsc911x_read_mac_address(struct net_device *dev)
1921{
1922 struct smsc911x_data *pdata = netdev_priv(dev);
1923 u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH);
1924 u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL);
1925
1926 dev->dev_addr[0] = (u8)(mac_low32);
1927 dev->dev_addr[1] = (u8)(mac_low32 >> 8);
1928 dev->dev_addr[2] = (u8)(mac_low32 >> 16);
1929 dev->dev_addr[3] = (u8)(mac_low32 >> 24);
1930 dev->dev_addr[4] = (u8)(mac_high16);
1931 dev->dev_addr[5] = (u8)(mac_high16 >> 8);
1932}
1933
1934/* Initializing private device structures, only called from probe */
1935static int __devinit smsc911x_init(struct net_device *dev)
1936{
1937 struct smsc911x_data *pdata = netdev_priv(dev);
1938 unsigned int byte_test;
1939
1940 SMSC_TRACE(pdata, probe, "Driver Parameters:");
1941 SMSC_TRACE(pdata, probe, "LAN base: 0x%08lX",
1942 (unsigned long)pdata->ioaddr);
1943 SMSC_TRACE(pdata, probe, "IRQ: %d", dev->irq);
1944 SMSC_TRACE(pdata, probe, "PHY will be autodetected.");
1945
1946 spin_lock_init(&pdata->dev_lock);
1947 spin_lock_init(&pdata->mac_lock);
1948
1949 if (pdata->ioaddr == 0) {
1950 SMSC_WARN(pdata, probe, "pdata->ioaddr: 0x00000000");
1951 return -ENODEV;
1952 }
1953
1954 /* Check byte ordering */
1955 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1956 SMSC_TRACE(pdata, probe, "BYTE_TEST: 0x%08X", byte_test);
1957 if (byte_test == 0x43218765) {
1958 SMSC_TRACE(pdata, probe, "BYTE_TEST looks swapped, "
1959 "applying WORD_SWAP");
1960 smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff);
1961
1962 /* 1 dummy read of BYTE_TEST is needed after a write to
1963 * WORD_SWAP before its contents are valid */
1964 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1965
1966 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1967 }
1968
1969 if (byte_test != 0x87654321) {
1970 SMSC_WARN(pdata, drv, "BYTE_TEST: 0x%08X", byte_test);
1971 if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) {
1972 SMSC_WARN(pdata, probe,
1973 "top 16 bits equal to bottom 16 bits");
1974 SMSC_TRACE(pdata, probe,
1975 "This may mean the chip is set "
1976 "for 32 bit while the bus is reading 16 bit");
1977 }
1978 return -ENODEV;
1979 }
1980
1981 /* Default generation to zero (all workarounds apply) */
1982 pdata->generation = 0;
1983
1984 pdata->idrev = smsc911x_reg_read(pdata, ID_REV);
1985 switch (pdata->idrev & 0xFFFF0000) {
1986 case 0x01180000:
1987 case 0x01170000:
1988 case 0x01160000:
1989 case 0x01150000:
1990 /* LAN911[5678] family */
1991 pdata->generation = pdata->idrev & 0x0000FFFF;
1992 break;
1993
1994 case 0x118A0000:
1995 case 0x117A0000:
1996 case 0x116A0000:
1997 case 0x115A0000:
1998 /* LAN921[5678] family */
1999 pdata->generation = 3;
2000 break;
2001
2002 case 0x92100000:
2003 case 0x92110000:
2004 case 0x92200000:
2005 case 0x92210000:
2006 /* LAN9210/LAN9211/LAN9220/LAN9221 */
2007 pdata->generation = 4;
2008 break;
2009
2010 default:
2011 SMSC_WARN(pdata, probe, "LAN911x not identified, idrev: 0x%08X",
2012 pdata->idrev);
2013 return -ENODEV;
2014 }
2015
2016 SMSC_TRACE(pdata, probe,
2017 "LAN911x identified, idrev: 0x%08X, generation: %d",
2018 pdata->idrev, pdata->generation);
2019
2020 if (pdata->generation == 0)
2021 SMSC_WARN(pdata, probe,
2022 "This driver is not intended for this chip revision");
2023
2024 /* workaround for platforms without an eeprom, where the mac address
2025 * is stored elsewhere and set by the bootloader. This saves the
2026 * mac address before resetting the device */
2027 if (pdata->config.flags & SMSC911X_SAVE_MAC_ADDRESS) {
2028 spin_lock_irq(&pdata->mac_lock);
2029 smsc911x_read_mac_address(dev);
2030 spin_unlock_irq(&pdata->mac_lock);
2031 }
2032
2033 /* Reset the LAN911x */
2034 if (smsc911x_soft_reset(pdata))
2035 return -ENODEV;
2036
2037 /* Disable all interrupt sources until we bring the device up */
2038 smsc911x_reg_write(pdata, INT_EN, 0);
2039
2040 ether_setup(dev);
2041 dev->flags |= IFF_MULTICAST;
2042 netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT);
2043 dev->netdev_ops = &smsc911x_netdev_ops;
2044 dev->ethtool_ops = &smsc911x_ethtool_ops;
2045
2046 return 0;
2047}
2048
2049static int __devexit smsc911x_drv_remove(struct platform_device *pdev)
2050{
2051 struct net_device *dev;
2052 struct smsc911x_data *pdata;
2053 struct resource *res;
2054
2055 dev = platform_get_drvdata(pdev);
2056 BUG_ON(!dev);
2057 pdata = netdev_priv(dev);
2058 BUG_ON(!pdata);
2059 BUG_ON(!pdata->ioaddr);
2060 BUG_ON(!pdata->phy_dev);
2061
2062 SMSC_TRACE(pdata, ifdown, "Stopping driver");
2063
2064 phy_disconnect(pdata->phy_dev);
2065 pdata->phy_dev = NULL;
2066 mdiobus_unregister(pdata->mii_bus);
2067 mdiobus_free(pdata->mii_bus);
2068
2069 platform_set_drvdata(pdev, NULL);
2070 unregister_netdev(dev);
2071 free_irq(dev->irq, dev);
2072 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2073 "smsc911x-memory");
2074 if (!res)
2075 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2076
2077 release_mem_region(res->start, resource_size(res));
2078
2079 iounmap(pdata->ioaddr);
2080
2081 free_netdev(dev);
2082
2083 return 0;
2084}
2085
2086/* standard register acces */
2087static const struct smsc911x_ops standard_smsc911x_ops = {
2088 .reg_read = __smsc911x_reg_read,
2089 .reg_write = __smsc911x_reg_write,
2090 .rx_readfifo = smsc911x_rx_readfifo,
2091 .tx_writefifo = smsc911x_tx_writefifo,
2092};
2093
2094/* shifted register access */
2095static const struct smsc911x_ops shifted_smsc911x_ops = {
2096 .reg_read = __smsc911x_reg_read_shift,
2097 .reg_write = __smsc911x_reg_write_shift,
2098 .rx_readfifo = smsc911x_rx_readfifo_shift,
2099 .tx_writefifo = smsc911x_tx_writefifo_shift,
2100};
2101
2102#ifdef CONFIG_OF
2103static int __devinit smsc911x_probe_config_dt(
2104 struct smsc911x_platform_config *config,
2105 struct device_node *np)
2106{
2107 const char *mac;
2108 u32 width = 0;
2109
2110 if (!np)
2111 return -ENODEV;
2112
2113 config->phy_interface = of_get_phy_mode(np);
2114
2115 mac = of_get_mac_address(np);
2116 if (mac)
2117 memcpy(config->mac, mac, ETH_ALEN);
2118
2119 of_property_read_u32(np, "reg-shift", &config->shift);
2120
2121 of_property_read_u32(np, "reg-io-width", &width);
2122 if (width == 4)
2123 config->flags |= SMSC911X_USE_32BIT;
2124
2125 if (of_get_property(np, "smsc,irq-active-high", NULL))
2126 config->irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH;
2127
2128 if (of_get_property(np, "smsc,irq-push-pull", NULL))
2129 config->irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL;
2130
2131 if (of_get_property(np, "smsc,force-internal-phy", NULL))
2132 config->flags |= SMSC911X_FORCE_INTERNAL_PHY;
2133
2134 if (of_get_property(np, "smsc,force-external-phy", NULL))
2135 config->flags |= SMSC911X_FORCE_EXTERNAL_PHY;
2136
2137 if (of_get_property(np, "smsc,save-mac-address", NULL))
2138 config->flags |= SMSC911X_SAVE_MAC_ADDRESS;
2139
2140 return 0;
2141}
2142#else
2143static inline int smsc911x_probe_config_dt(
2144 struct smsc911x_platform_config *config,
2145 struct device_node *np)
2146{
2147 return -ENODEV;
2148}
2149#endif /* CONFIG_OF */
2150
2151static int __devinit smsc911x_drv_probe(struct platform_device *pdev)
2152{
2153 struct device_node *np = pdev->dev.of_node;
2154 struct net_device *dev;
2155 struct smsc911x_data *pdata;
2156 struct smsc911x_platform_config *config = pdev->dev.platform_data;
2157 struct resource *res, *irq_res;
2158 unsigned int intcfg = 0;
2159 int res_size, irq_flags;
2160 int retval;
2161
2162 pr_info("Driver version %s\n", SMSC_DRV_VERSION);
2163
2164 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2165 "smsc911x-memory");
2166 if (!res)
2167 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2168 if (!res) {
2169 pr_warn("Could not allocate resource\n");
2170 retval = -ENODEV;
2171 goto out_0;
2172 }
2173 res_size = resource_size(res);
2174
2175 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2176 if (!irq_res) {
2177 pr_warn("Could not allocate irq resource\n");
2178 retval = -ENODEV;
2179 goto out_0;
2180 }
2181
2182 if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) {
2183 retval = -EBUSY;
2184 goto out_0;
2185 }
2186
2187 dev = alloc_etherdev(sizeof(struct smsc911x_data));
2188 if (!dev) {
2189 pr_warn("Could not allocate device\n");
2190 retval = -ENOMEM;
2191 goto out_release_io_1;
2192 }
2193
2194 SET_NETDEV_DEV(dev, &pdev->dev);
2195
2196 pdata = netdev_priv(dev);
2197
2198 dev->irq = irq_res->start;
2199 irq_flags = irq_res->flags & IRQF_TRIGGER_MASK;
2200 pdata->ioaddr = ioremap_nocache(res->start, res_size);
2201
2202 pdata->dev = dev;
2203 pdata->msg_enable = ((1 << debug) - 1);
2204
2205 if (pdata->ioaddr == NULL) {
2206 SMSC_WARN(pdata, probe, "Error smsc911x base address invalid");
2207 retval = -ENOMEM;
2208 goto out_free_netdev_2;
2209 }
2210
2211 retval = smsc911x_probe_config_dt(&pdata->config, np);
2212 if (retval && config) {
2213 /* copy config parameters across to pdata */
2214 memcpy(&pdata->config, config, sizeof(pdata->config));
2215 retval = 0;
2216 }
2217
2218 if (retval) {
2219 SMSC_WARN(pdata, probe, "Error smsc911x config not found");
2220 goto out_unmap_io_3;
2221 }
2222
2223 /* assume standard, non-shifted, access to HW registers */
2224 pdata->ops = &standard_smsc911x_ops;
2225 /* apply the right access if shifting is needed */
2226 if (pdata->config.shift)
2227 pdata->ops = &shifted_smsc911x_ops;
2228
2229 retval = smsc911x_init(dev);
2230 if (retval < 0)
2231 goto out_unmap_io_3;
2232
2233 /* configure irq polarity and type before connecting isr */
2234 if (pdata->config.irq_polarity == SMSC911X_IRQ_POLARITY_ACTIVE_HIGH)
2235 intcfg |= INT_CFG_IRQ_POL_;
2236
2237 if (pdata->config.irq_type == SMSC911X_IRQ_TYPE_PUSH_PULL)
2238 intcfg |= INT_CFG_IRQ_TYPE_;
2239
2240 smsc911x_reg_write(pdata, INT_CFG, intcfg);
2241
2242 /* Ensure interrupts are globally disabled before connecting ISR */
2243 smsc911x_reg_write(pdata, INT_EN, 0);
2244 smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
2245
2246 retval = request_irq(dev->irq, smsc911x_irqhandler,
2247 irq_flags | IRQF_SHARED, dev->name, dev);
2248 if (retval) {
2249 SMSC_WARN(pdata, probe,
2250 "Unable to claim requested irq: %d", dev->irq);
2251 goto out_unmap_io_3;
2252 }
2253
2254 platform_set_drvdata(pdev, dev);
2255
2256 retval = register_netdev(dev);
2257 if (retval) {
2258 SMSC_WARN(pdata, probe, "Error %i registering device", retval);
2259 goto out_unset_drvdata_4;
2260 } else {
2261 SMSC_TRACE(pdata, probe,
2262 "Network interface: \"%s\"", dev->name);
2263 }
2264
2265 retval = smsc911x_mii_init(pdev, dev);
2266 if (retval) {
2267 SMSC_WARN(pdata, probe, "Error %i initialising mii", retval);
2268 goto out_unregister_netdev_5;
2269 }
2270
2271 spin_lock_irq(&pdata->mac_lock);
2272
2273 /* Check if mac address has been specified when bringing interface up */
2274 if (is_valid_ether_addr(dev->dev_addr)) {
2275 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
2276 SMSC_TRACE(pdata, probe,
2277 "MAC Address is specified by configuration");
2278 } else if (is_valid_ether_addr(pdata->config.mac)) {
2279 memcpy(dev->dev_addr, pdata->config.mac, 6);
2280 SMSC_TRACE(pdata, probe,
2281 "MAC Address specified by platform data");
2282 } else {
2283 /* Try reading mac address from device. if EEPROM is present
2284 * it will already have been set */
2285 smsc_get_mac(dev);
2286
2287 if (is_valid_ether_addr(dev->dev_addr)) {
2288 /* eeprom values are valid so use them */
2289 SMSC_TRACE(pdata, probe,
2290 "Mac Address is read from LAN911x EEPROM");
2291 } else {
2292 /* eeprom values are invalid, generate random MAC */
2293 random_ether_addr(dev->dev_addr);
2294 smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
2295 SMSC_TRACE(pdata, probe,
2296 "MAC Address is set to random_ether_addr");
2297 }
2298 }
2299
2300 spin_unlock_irq(&pdata->mac_lock);
2301
2302 netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr);
2303
2304 return 0;
2305
2306out_unregister_netdev_5:
2307 unregister_netdev(dev);
2308out_unset_drvdata_4:
2309 platform_set_drvdata(pdev, NULL);
2310 free_irq(dev->irq, dev);
2311out_unmap_io_3:
2312 iounmap(pdata->ioaddr);
2313out_free_netdev_2:
2314 free_netdev(dev);
2315out_release_io_1:
2316 release_mem_region(res->start, resource_size(res));
2317out_0:
2318 return retval;
2319}
2320
2321#ifdef CONFIG_PM
2322/* This implementation assumes the devices remains powered on its VDDVARIO
2323 * pins during suspend. */
2324
2325/* TODO: implement freeze/thaw callbacks for hibernation.*/
2326
2327static int smsc911x_suspend(struct device *dev)
2328{
2329 struct net_device *ndev = dev_get_drvdata(dev);
2330 struct smsc911x_data *pdata = netdev_priv(ndev);
2331
2332 /* enable wake on LAN, energy detection and the external PME
2333 * signal. */
2334 smsc911x_reg_write(pdata, PMT_CTRL,
2335 PMT_CTRL_PM_MODE_D1_ | PMT_CTRL_WOL_EN_ |
2336 PMT_CTRL_ED_EN_ | PMT_CTRL_PME_EN_);
2337
2338 return 0;
2339}
2340
2341static int smsc911x_resume(struct device *dev)
2342{
2343 struct net_device *ndev = dev_get_drvdata(dev);
2344 struct smsc911x_data *pdata = netdev_priv(ndev);
2345 unsigned int to = 100;
2346
2347 /* Note 3.11 from the datasheet:
2348 * "When the LAN9220 is in a power saving state, a write of any
2349 * data to the BYTE_TEST register will wake-up the device."
2350 */
2351 smsc911x_reg_write(pdata, BYTE_TEST, 0);
2352
2353 /* poll the READY bit in PMT_CTRL. Any other access to the device is
2354 * forbidden while this bit isn't set. Try for 100ms and return -EIO
2355 * if it failed. */
2356 while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to)
2357 udelay(1000);
2358
2359 return (to == 0) ? -EIO : 0;
2360}
2361
2362static const struct dev_pm_ops smsc911x_pm_ops = {
2363 .suspend = smsc911x_suspend,
2364 .resume = smsc911x_resume,
2365};
2366
2367#define SMSC911X_PM_OPS (&smsc911x_pm_ops)
2368
2369#else
2370#define SMSC911X_PM_OPS NULL
2371#endif
2372
2373static const struct of_device_id smsc911x_dt_ids[] = {
2374 { .compatible = "smsc,lan9115", },
2375 { /* sentinel */ }
2376};
2377MODULE_DEVICE_TABLE(of, smsc911x_dt_ids);
2378
2379static struct platform_driver smsc911x_driver = {
2380 .probe = smsc911x_drv_probe,
2381 .remove = __devexit_p(smsc911x_drv_remove),
2382 .driver = {
2383 .name = SMSC_CHIPNAME,
2384 .owner = THIS_MODULE,
2385 .pm = SMSC911X_PM_OPS,
2386 .of_match_table = smsc911x_dt_ids,
2387 },
2388};
2389
2390/* Entry point for loading the module */
2391static int __init smsc911x_init_module(void)
2392{
2393 SMSC_INITIALIZE();
2394 return platform_driver_register(&smsc911x_driver);
2395}
2396
2397/* entry point for unloading the module */
2398static void __exit smsc911x_cleanup_module(void)
2399{
2400 platform_driver_unregister(&smsc911x_driver);
2401}
2402
2403module_init(smsc911x_init_module);
2404module_exit(smsc911x_cleanup_module);
diff --git a/drivers/net/ethernet/smsc/smsc911x.h b/drivers/net/ethernet/smsc/smsc911x.h
new file mode 100644
index 000000000000..8d67aacf8867
--- /dev/null
+++ b/drivers/net/ethernet/smsc/smsc911x.h
@@ -0,0 +1,404 @@
1/***************************************************************************
2 *
3 * Copyright (C) 2004-2008 SMSC
4 * Copyright (C) 2005-2008 ARM
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 *
20 ***************************************************************************/
21#ifndef __SMSC911X_H__
22#define __SMSC911X_H__
23
24#define TX_FIFO_LOW_THRESHOLD ((u32)1600)
25#define SMSC911X_EEPROM_SIZE ((u32)128)
26#define USE_DEBUG 0
27
28/* This is the maximum number of packets to be received every
29 * NAPI poll */
30#define SMSC_NAPI_WEIGHT 16
31
32/* implements a PHY loopback test at initialisation time, to ensure a packet
33 * can be successfully looped back */
34#define USE_PHY_WORK_AROUND
35
36#if USE_DEBUG >= 1
37#define SMSC_WARN(pdata, nlevel, fmt, args...) \
38 netif_warn(pdata, nlevel, (pdata)->dev, \
39 "%s: " fmt "\n", __func__, ##args)
40#else
41#define SMSC_WARN(pdata, nlevel, fmt, args...) \
42 no_printk(fmt "\n", ##args)
43#endif
44
45#if USE_DEBUG >= 2
46#define SMSC_TRACE(pdata, nlevel, fmt, args...) \
47 netif_info(pdata, nlevel, pdata->dev, fmt "\n", ##args)
48#else
49#define SMSC_TRACE(pdata, nlevel, fmt, args...) \
50 no_printk(fmt "\n", ##args)
51#endif
52
53#ifdef CONFIG_DEBUG_SPINLOCK
54#define SMSC_ASSERT_MAC_LOCK(pdata) \
55 WARN_ON(!spin_is_locked(&pdata->mac_lock))
56#else
57#define SMSC_ASSERT_MAC_LOCK(pdata) do {} while (0)
58#endif /* CONFIG_DEBUG_SPINLOCK */
59
60/* SMSC911x registers and bitfields */
61#define RX_DATA_FIFO 0x00
62
63#define TX_DATA_FIFO 0x20
64#define TX_CMD_A_ON_COMP_ 0x80000000
65#define TX_CMD_A_BUF_END_ALGN_ 0x03000000
66#define TX_CMD_A_4_BYTE_ALGN_ 0x00000000
67#define TX_CMD_A_16_BYTE_ALGN_ 0x01000000
68#define TX_CMD_A_32_BYTE_ALGN_ 0x02000000
69#define TX_CMD_A_DATA_OFFSET_ 0x001F0000
70#define TX_CMD_A_FIRST_SEG_ 0x00002000
71#define TX_CMD_A_LAST_SEG_ 0x00001000
72#define TX_CMD_A_BUF_SIZE_ 0x000007FF
73#define TX_CMD_B_PKT_TAG_ 0xFFFF0000
74#define TX_CMD_B_ADD_CRC_DISABLE_ 0x00002000
75#define TX_CMD_B_DISABLE_PADDING_ 0x00001000
76#define TX_CMD_B_PKT_BYTE_LENGTH_ 0x000007FF
77
78#define RX_STATUS_FIFO 0x40
79#define RX_STS_ES_ 0x00008000
80#define RX_STS_LENGTH_ERR_ 0x00001000
81#define RX_STS_MCAST_ 0x00000400
82#define RX_STS_FRAME_TYPE_ 0x00000020
83#define RX_STS_CRC_ERR_ 0x00000002
84
85#define RX_STATUS_FIFO_PEEK 0x44
86
87#define TX_STATUS_FIFO 0x48
88#define TX_STS_ES_ 0x00008000
89#define TX_STS_LOST_CARRIER_ 0x00000800
90#define TX_STS_NO_CARRIER_ 0x00000400
91#define TX_STS_LATE_COL_ 0x00000200
92#define TX_STS_EXCESS_COL_ 0x00000100
93
94#define TX_STATUS_FIFO_PEEK 0x4C
95
96#define ID_REV 0x50
97#define ID_REV_CHIP_ID_ 0xFFFF0000
98#define ID_REV_REV_ID_ 0x0000FFFF
99
100#define INT_CFG 0x54
101#define INT_CFG_INT_DEAS_ 0xFF000000
102#define INT_CFG_INT_DEAS_CLR_ 0x00004000
103#define INT_CFG_INT_DEAS_STS_ 0x00002000
104#define INT_CFG_IRQ_INT_ 0x00001000
105#define INT_CFG_IRQ_EN_ 0x00000100
106#define INT_CFG_IRQ_POL_ 0x00000010
107#define INT_CFG_IRQ_TYPE_ 0x00000001
108
109#define INT_STS 0x58
110#define INT_STS_SW_INT_ 0x80000000
111#define INT_STS_TXSTOP_INT_ 0x02000000
112#define INT_STS_RXSTOP_INT_ 0x01000000
113#define INT_STS_RXDFH_INT_ 0x00800000
114#define INT_STS_RXDF_INT_ 0x00400000
115#define INT_STS_TX_IOC_ 0x00200000
116#define INT_STS_RXD_INT_ 0x00100000
117#define INT_STS_GPT_INT_ 0x00080000
118#define INT_STS_PHY_INT_ 0x00040000
119#define INT_STS_PME_INT_ 0x00020000
120#define INT_STS_TXSO_ 0x00010000
121#define INT_STS_RWT_ 0x00008000
122#define INT_STS_RXE_ 0x00004000
123#define INT_STS_TXE_ 0x00002000
124#define INT_STS_TDFU_ 0x00000800
125#define INT_STS_TDFO_ 0x00000400
126#define INT_STS_TDFA_ 0x00000200
127#define INT_STS_TSFF_ 0x00000100
128#define INT_STS_TSFL_ 0x00000080
129#define INT_STS_RXDF_ 0x00000040
130#define INT_STS_RDFL_ 0x00000020
131#define INT_STS_RSFF_ 0x00000010
132#define INT_STS_RSFL_ 0x00000008
133#define INT_STS_GPIO2_INT_ 0x00000004
134#define INT_STS_GPIO1_INT_ 0x00000002
135#define INT_STS_GPIO0_INT_ 0x00000001
136
137#define INT_EN 0x5C
138#define INT_EN_SW_INT_EN_ 0x80000000
139#define INT_EN_TXSTOP_INT_EN_ 0x02000000
140#define INT_EN_RXSTOP_INT_EN_ 0x01000000
141#define INT_EN_RXDFH_INT_EN_ 0x00800000
142#define INT_EN_TIOC_INT_EN_ 0x00200000
143#define INT_EN_RXD_INT_EN_ 0x00100000
144#define INT_EN_GPT_INT_EN_ 0x00080000
145#define INT_EN_PHY_INT_EN_ 0x00040000
146#define INT_EN_PME_INT_EN_ 0x00020000
147#define INT_EN_TXSO_EN_ 0x00010000
148#define INT_EN_RWT_EN_ 0x00008000
149#define INT_EN_RXE_EN_ 0x00004000
150#define INT_EN_TXE_EN_ 0x00002000
151#define INT_EN_TDFU_EN_ 0x00000800
152#define INT_EN_TDFO_EN_ 0x00000400
153#define INT_EN_TDFA_EN_ 0x00000200
154#define INT_EN_TSFF_EN_ 0x00000100
155#define INT_EN_TSFL_EN_ 0x00000080
156#define INT_EN_RXDF_EN_ 0x00000040
157#define INT_EN_RDFL_EN_ 0x00000020
158#define INT_EN_RSFF_EN_ 0x00000010
159#define INT_EN_RSFL_EN_ 0x00000008
160#define INT_EN_GPIO2_INT_ 0x00000004
161#define INT_EN_GPIO1_INT_ 0x00000002
162#define INT_EN_GPIO0_INT_ 0x00000001
163
164#define BYTE_TEST 0x64
165
166#define FIFO_INT 0x68
167#define FIFO_INT_TX_AVAIL_LEVEL_ 0xFF000000
168#define FIFO_INT_TX_STS_LEVEL_ 0x00FF0000
169#define FIFO_INT_RX_AVAIL_LEVEL_ 0x0000FF00
170#define FIFO_INT_RX_STS_LEVEL_ 0x000000FF
171
172#define RX_CFG 0x6C
173#define RX_CFG_RX_END_ALGN_ 0xC0000000
174#define RX_CFG_RX_END_ALGN4_ 0x00000000
175#define RX_CFG_RX_END_ALGN16_ 0x40000000
176#define RX_CFG_RX_END_ALGN32_ 0x80000000
177#define RX_CFG_RX_DMA_CNT_ 0x0FFF0000
178#define RX_CFG_RX_DUMP_ 0x00008000
179#define RX_CFG_RXDOFF_ 0x00001F00
180
181#define TX_CFG 0x70
182#define TX_CFG_TXS_DUMP_ 0x00008000
183#define TX_CFG_TXD_DUMP_ 0x00004000
184#define TX_CFG_TXSAO_ 0x00000004
185#define TX_CFG_TX_ON_ 0x00000002
186#define TX_CFG_STOP_TX_ 0x00000001
187
188#define HW_CFG 0x74
189#define HW_CFG_TTM_ 0x00200000
190#define HW_CFG_SF_ 0x00100000
191#define HW_CFG_TX_FIF_SZ_ 0x000F0000
192#define HW_CFG_TR_ 0x00003000
193#define HW_CFG_SRST_ 0x00000001
194
195/* only available on 115/117 */
196#define HW_CFG_PHY_CLK_SEL_ 0x00000060
197#define HW_CFG_PHY_CLK_SEL_INT_PHY_ 0x00000000
198#define HW_CFG_PHY_CLK_SEL_EXT_PHY_ 0x00000020
199#define HW_CFG_PHY_CLK_SEL_CLK_DIS_ 0x00000040
200#define HW_CFG_SMI_SEL_ 0x00000010
201#define HW_CFG_EXT_PHY_DET_ 0x00000008
202#define HW_CFG_EXT_PHY_EN_ 0x00000004
203#define HW_CFG_SRST_TO_ 0x00000002
204
205/* only available on 116/118 */
206#define HW_CFG_32_16_BIT_MODE_ 0x00000004
207
208#define RX_DP_CTRL 0x78
209#define RX_DP_CTRL_RX_FFWD_ 0x80000000
210
211#define RX_FIFO_INF 0x7C
212#define RX_FIFO_INF_RXSUSED_ 0x00FF0000
213#define RX_FIFO_INF_RXDUSED_ 0x0000FFFF
214
215#define TX_FIFO_INF 0x80
216#define TX_FIFO_INF_TSUSED_ 0x00FF0000
217#define TX_FIFO_INF_TDFREE_ 0x0000FFFF
218
219#define PMT_CTRL 0x84
220#define PMT_CTRL_PM_MODE_ 0x00003000
221#define PMT_CTRL_PM_MODE_D0_ 0x00000000
222#define PMT_CTRL_PM_MODE_D1_ 0x00001000
223#define PMT_CTRL_PM_MODE_D2_ 0x00002000
224#define PMT_CTRL_PM_MODE_D3_ 0x00003000
225#define PMT_CTRL_PHY_RST_ 0x00000400
226#define PMT_CTRL_WOL_EN_ 0x00000200
227#define PMT_CTRL_ED_EN_ 0x00000100
228#define PMT_CTRL_PME_TYPE_ 0x00000040
229#define PMT_CTRL_WUPS_ 0x00000030
230#define PMT_CTRL_WUPS_NOWAKE_ 0x00000000
231#define PMT_CTRL_WUPS_ED_ 0x00000010
232#define PMT_CTRL_WUPS_WOL_ 0x00000020
233#define PMT_CTRL_WUPS_MULTI_ 0x00000030
234#define PMT_CTRL_PME_IND_ 0x00000008
235#define PMT_CTRL_PME_POL_ 0x00000004
236#define PMT_CTRL_PME_EN_ 0x00000002
237#define PMT_CTRL_READY_ 0x00000001
238
239#define GPIO_CFG 0x88
240#define GPIO_CFG_LED3_EN_ 0x40000000
241#define GPIO_CFG_LED2_EN_ 0x20000000
242#define GPIO_CFG_LED1_EN_ 0x10000000
243#define GPIO_CFG_GPIO2_INT_POL_ 0x04000000
244#define GPIO_CFG_GPIO1_INT_POL_ 0x02000000
245#define GPIO_CFG_GPIO0_INT_POL_ 0x01000000
246#define GPIO_CFG_EEPR_EN_ 0x00700000
247#define GPIO_CFG_GPIOBUF2_ 0x00040000
248#define GPIO_CFG_GPIOBUF1_ 0x00020000
249#define GPIO_CFG_GPIOBUF0_ 0x00010000
250#define GPIO_CFG_GPIODIR2_ 0x00000400
251#define GPIO_CFG_GPIODIR1_ 0x00000200
252#define GPIO_CFG_GPIODIR0_ 0x00000100
253#define GPIO_CFG_GPIOD4_ 0x00000020
254#define GPIO_CFG_GPIOD3_ 0x00000010
255#define GPIO_CFG_GPIOD2_ 0x00000004
256#define GPIO_CFG_GPIOD1_ 0x00000002
257#define GPIO_CFG_GPIOD0_ 0x00000001
258
259#define GPT_CFG 0x8C
260#define GPT_CFG_TIMER_EN_ 0x20000000
261#define GPT_CFG_GPT_LOAD_ 0x0000FFFF
262
263#define GPT_CNT 0x90
264#define GPT_CNT_GPT_CNT_ 0x0000FFFF
265
266#define WORD_SWAP 0x98
267
268#define FREE_RUN 0x9C
269
270#define RX_DROP 0xA0
271
272#define MAC_CSR_CMD 0xA4
273#define MAC_CSR_CMD_CSR_BUSY_ 0x80000000
274#define MAC_CSR_CMD_R_NOT_W_ 0x40000000
275#define MAC_CSR_CMD_CSR_ADDR_ 0x000000FF
276
277#define MAC_CSR_DATA 0xA8
278
279#define AFC_CFG 0xAC
280#define AFC_CFG_AFC_HI_ 0x00FF0000
281#define AFC_CFG_AFC_LO_ 0x0000FF00
282#define AFC_CFG_BACK_DUR_ 0x000000F0
283#define AFC_CFG_FCMULT_ 0x00000008
284#define AFC_CFG_FCBRD_ 0x00000004
285#define AFC_CFG_FCADD_ 0x00000002
286#define AFC_CFG_FCANY_ 0x00000001
287
288#define E2P_CMD 0xB0
289#define E2P_CMD_EPC_BUSY_ 0x80000000
290#define E2P_CMD_EPC_CMD_ 0x70000000
291#define E2P_CMD_EPC_CMD_READ_ 0x00000000
292#define E2P_CMD_EPC_CMD_EWDS_ 0x10000000
293#define E2P_CMD_EPC_CMD_EWEN_ 0x20000000
294#define E2P_CMD_EPC_CMD_WRITE_ 0x30000000
295#define E2P_CMD_EPC_CMD_WRAL_ 0x40000000
296#define E2P_CMD_EPC_CMD_ERASE_ 0x50000000
297#define E2P_CMD_EPC_CMD_ERAL_ 0x60000000
298#define E2P_CMD_EPC_CMD_RELOAD_ 0x70000000
299#define E2P_CMD_EPC_TIMEOUT_ 0x00000200
300#define E2P_CMD_MAC_ADDR_LOADED_ 0x00000100
301#define E2P_CMD_EPC_ADDR_ 0x000000FF
302
303#define E2P_DATA 0xB4
304#define E2P_DATA_EEPROM_DATA_ 0x000000FF
305#define LAN_REGISTER_EXTENT 0x00000100
306
307/*
308 * MAC Control and Status Register (Indirect Address)
309 * Offset (through the MAC_CSR CMD and DATA port)
310 */
311#define MAC_CR 0x01
312#define MAC_CR_RXALL_ 0x80000000
313#define MAC_CR_HBDIS_ 0x10000000
314#define MAC_CR_RCVOWN_ 0x00800000
315#define MAC_CR_LOOPBK_ 0x00200000
316#define MAC_CR_FDPX_ 0x00100000
317#define MAC_CR_MCPAS_ 0x00080000
318#define MAC_CR_PRMS_ 0x00040000
319#define MAC_CR_INVFILT_ 0x00020000
320#define MAC_CR_PASSBAD_ 0x00010000
321#define MAC_CR_HFILT_ 0x00008000
322#define MAC_CR_HPFILT_ 0x00002000
323#define MAC_CR_LCOLL_ 0x00001000
324#define MAC_CR_BCAST_ 0x00000800
325#define MAC_CR_DISRTY_ 0x00000400
326#define MAC_CR_PADSTR_ 0x00000100
327#define MAC_CR_BOLMT_MASK_ 0x000000C0
328#define MAC_CR_DFCHK_ 0x00000020
329#define MAC_CR_TXEN_ 0x00000008
330#define MAC_CR_RXEN_ 0x00000004
331
332#define ADDRH 0x02
333
334#define ADDRL 0x03
335
336#define HASHH 0x04
337
338#define HASHL 0x05
339
340#define MII_ACC 0x06
341#define MII_ACC_PHY_ADDR_ 0x0000F800
342#define MII_ACC_MIIRINDA_ 0x000007C0
343#define MII_ACC_MII_WRITE_ 0x00000002
344#define MII_ACC_MII_BUSY_ 0x00000001
345
346#define MII_DATA 0x07
347
348#define FLOW 0x08
349#define FLOW_FCPT_ 0xFFFF0000
350#define FLOW_FCPASS_ 0x00000004
351#define FLOW_FCEN_ 0x00000002
352#define FLOW_FCBSY_ 0x00000001
353
354#define VLAN1 0x09
355
356#define VLAN2 0x0A
357
358#define WUFF 0x0B
359
360#define WUCSR 0x0C
361#define WUCSR_GUE_ 0x00000200
362#define WUCSR_WUFR_ 0x00000040
363#define WUCSR_MPR_ 0x00000020
364#define WUCSR_WAKE_EN_ 0x00000004
365#define WUCSR_MPEN_ 0x00000002
366
367/*
368 * Phy definitions (vendor-specific)
369 */
370#define LAN9118_PHY_ID 0x00C0001C
371
372#define MII_INTSTS 0x1D
373
374#define MII_INTMSK 0x1E
375#define PHY_INTMSK_AN_RCV_ (1 << 1)
376#define PHY_INTMSK_PDFAULT_ (1 << 2)
377#define PHY_INTMSK_AN_ACK_ (1 << 3)
378#define PHY_INTMSK_LNKDOWN_ (1 << 4)
379#define PHY_INTMSK_RFAULT_ (1 << 5)
380#define PHY_INTMSK_AN_COMP_ (1 << 6)
381#define PHY_INTMSK_ENERGYON_ (1 << 7)
382#define PHY_INTMSK_DEFAULT_ (PHY_INTMSK_ENERGYON_ | \
383 PHY_INTMSK_AN_COMP_ | \
384 PHY_INTMSK_RFAULT_ | \
385 PHY_INTMSK_LNKDOWN_)
386
387#define ADVERTISE_PAUSE_ALL (ADVERTISE_PAUSE_CAP | \
388 ADVERTISE_PAUSE_ASYM)
389
390#define LPA_PAUSE_ALL (LPA_PAUSE_CAP | \
391 LPA_PAUSE_ASYM)
392
393/*
394 * Provide hooks to let the arch add to the initialisation procedure
395 * and to override the source of the MAC address.
396 */
397#define SMSC_INITIALIZE() do {} while (0)
398#define smsc_get_mac(dev) smsc911x_read_mac_address((dev))
399
400#ifdef CONFIG_SMSC911X_ARCH_HOOKS
401#include <asm/smsc911x.h>
402#endif
403
404#endif /* __SMSC911X_H__ */
diff --git a/drivers/net/ethernet/smsc/smsc9420.c b/drivers/net/ethernet/smsc/smsc9420.c
new file mode 100644
index 000000000000..459726f54754
--- /dev/null
+++ b/drivers/net/ethernet/smsc/smsc9420.c
@@ -0,0 +1,1763 @@
1 /***************************************************************************
2 *
3 * Copyright (C) 2007,2008 SMSC
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 *
19 ***************************************************************************
20 */
21
22#include <linux/interrupt.h>
23#include <linux/kernel.h>
24#include <linux/netdevice.h>
25#include <linux/phy.h>
26#include <linux/pci.h>
27#include <linux/if_vlan.h>
28#include <linux/dma-mapping.h>
29#include <linux/crc32.h>
30#include <linux/slab.h>
31#include <asm/unaligned.h>
32#include "smsc9420.h"
33
34#define DRV_NAME "smsc9420"
35#define PFX DRV_NAME ": "
36#define DRV_MDIONAME "smsc9420-mdio"
37#define DRV_DESCRIPTION "SMSC LAN9420 driver"
38#define DRV_VERSION "1.01"
39
40MODULE_LICENSE("GPL");
41MODULE_VERSION(DRV_VERSION);
42
43struct smsc9420_dma_desc {
44 u32 status;
45 u32 length;
46 u32 buffer1;
47 u32 buffer2;
48};
49
50struct smsc9420_ring_info {
51 struct sk_buff *skb;
52 dma_addr_t mapping;
53};
54
55struct smsc9420_pdata {
56 void __iomem *base_addr;
57 struct pci_dev *pdev;
58 struct net_device *dev;
59
60 struct smsc9420_dma_desc *rx_ring;
61 struct smsc9420_dma_desc *tx_ring;
62 struct smsc9420_ring_info *tx_buffers;
63 struct smsc9420_ring_info *rx_buffers;
64 dma_addr_t rx_dma_addr;
65 dma_addr_t tx_dma_addr;
66 int tx_ring_head, tx_ring_tail;
67 int rx_ring_head, rx_ring_tail;
68
69 spinlock_t int_lock;
70 spinlock_t phy_lock;
71
72 struct napi_struct napi;
73
74 bool software_irq_signal;
75 bool rx_csum;
76 u32 msg_enable;
77
78 struct phy_device *phy_dev;
79 struct mii_bus *mii_bus;
80 int phy_irq[PHY_MAX_ADDR];
81 int last_duplex;
82 int last_carrier;
83};
84
85static DEFINE_PCI_DEVICE_TABLE(smsc9420_id_table) = {
86 { PCI_VENDOR_ID_9420, PCI_DEVICE_ID_9420, PCI_ANY_ID, PCI_ANY_ID, },
87 { 0, }
88};
89
90MODULE_DEVICE_TABLE(pci, smsc9420_id_table);
91
92#define SMSC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
93
94static uint smsc_debug;
95static uint debug = -1;
96module_param(debug, uint, 0);
97MODULE_PARM_DESC(debug, "debug level");
98
99#define smsc_dbg(TYPE, f, a...) \
100do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
101 printk(KERN_DEBUG PFX f "\n", ## a); \
102} while (0)
103
104#define smsc_info(TYPE, f, a...) \
105do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
106 printk(KERN_INFO PFX f "\n", ## a); \
107} while (0)
108
109#define smsc_warn(TYPE, f, a...) \
110do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
111 printk(KERN_WARNING PFX f "\n", ## a); \
112} while (0)
113
114static inline u32 smsc9420_reg_read(struct smsc9420_pdata *pd, u32 offset)
115{
116 return ioread32(pd->base_addr + offset);
117}
118
119static inline void
120smsc9420_reg_write(struct smsc9420_pdata *pd, u32 offset, u32 value)
121{
122 iowrite32(value, pd->base_addr + offset);
123}
124
125static inline void smsc9420_pci_flush_write(struct smsc9420_pdata *pd)
126{
127 /* to ensure PCI write completion, we must perform a PCI read */
128 smsc9420_reg_read(pd, ID_REV);
129}
130
131static int smsc9420_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
132{
133 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
134 unsigned long flags;
135 u32 addr;
136 int i, reg = -EIO;
137
138 spin_lock_irqsave(&pd->phy_lock, flags);
139
140 /* confirm MII not busy */
141 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
142 smsc_warn(DRV, "MII is busy???");
143 goto out;
144 }
145
146 /* set the address, index & direction (read from PHY) */
147 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
148 MII_ACCESS_MII_READ_;
149 smsc9420_reg_write(pd, MII_ACCESS, addr);
150
151 /* wait for read to complete with 50us timeout */
152 for (i = 0; i < 5; i++) {
153 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
154 MII_ACCESS_MII_BUSY_)) {
155 reg = (u16)smsc9420_reg_read(pd, MII_DATA);
156 goto out;
157 }
158 udelay(10);
159 }
160
161 smsc_warn(DRV, "MII busy timeout!");
162
163out:
164 spin_unlock_irqrestore(&pd->phy_lock, flags);
165 return reg;
166}
167
168static int smsc9420_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
169 u16 val)
170{
171 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
172 unsigned long flags;
173 u32 addr;
174 int i, reg = -EIO;
175
176 spin_lock_irqsave(&pd->phy_lock, flags);
177
178 /* confirm MII not busy */
179 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
180 smsc_warn(DRV, "MII is busy???");
181 goto out;
182 }
183
184 /* put the data to write in the MAC */
185 smsc9420_reg_write(pd, MII_DATA, (u32)val);
186
187 /* set the address, index & direction (write to PHY) */
188 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
189 MII_ACCESS_MII_WRITE_;
190 smsc9420_reg_write(pd, MII_ACCESS, addr);
191
192 /* wait for write to complete with 50us timeout */
193 for (i = 0; i < 5; i++) {
194 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
195 MII_ACCESS_MII_BUSY_)) {
196 reg = 0;
197 goto out;
198 }
199 udelay(10);
200 }
201
202 smsc_warn(DRV, "MII busy timeout!");
203
204out:
205 spin_unlock_irqrestore(&pd->phy_lock, flags);
206 return reg;
207}
208
209/* Returns hash bit number for given MAC address
210 * Example:
211 * 01 00 5E 00 00 01 -> returns bit number 31 */
212static u32 smsc9420_hash(u8 addr[ETH_ALEN])
213{
214 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
215}
216
217static int smsc9420_eeprom_reload(struct smsc9420_pdata *pd)
218{
219 int timeout = 100000;
220
221 BUG_ON(!pd);
222
223 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
224 smsc_dbg(DRV, "smsc9420_eeprom_reload: Eeprom busy");
225 return -EIO;
226 }
227
228 smsc9420_reg_write(pd, E2P_CMD,
229 (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_));
230
231 do {
232 udelay(10);
233 if (!(smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_))
234 return 0;
235 } while (timeout--);
236
237 smsc_warn(DRV, "smsc9420_eeprom_reload: Eeprom timed out");
238 return -EIO;
239}
240
241/* Standard ioctls for mii-tool */
242static int smsc9420_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
243{
244 struct smsc9420_pdata *pd = netdev_priv(dev);
245
246 if (!netif_running(dev) || !pd->phy_dev)
247 return -EINVAL;
248
249 return phy_mii_ioctl(pd->phy_dev, ifr, cmd);
250}
251
252static int smsc9420_ethtool_get_settings(struct net_device *dev,
253 struct ethtool_cmd *cmd)
254{
255 struct smsc9420_pdata *pd = netdev_priv(dev);
256
257 if (!pd->phy_dev)
258 return -ENODEV;
259
260 cmd->maxtxpkt = 1;
261 cmd->maxrxpkt = 1;
262 return phy_ethtool_gset(pd->phy_dev, cmd);
263}
264
265static int smsc9420_ethtool_set_settings(struct net_device *dev,
266 struct ethtool_cmd *cmd)
267{
268 struct smsc9420_pdata *pd = netdev_priv(dev);
269
270 if (!pd->phy_dev)
271 return -ENODEV;
272
273 return phy_ethtool_sset(pd->phy_dev, cmd);
274}
275
276static void smsc9420_ethtool_get_drvinfo(struct net_device *netdev,
277 struct ethtool_drvinfo *drvinfo)
278{
279 struct smsc9420_pdata *pd = netdev_priv(netdev);
280
281 strcpy(drvinfo->driver, DRV_NAME);
282 strcpy(drvinfo->bus_info, pci_name(pd->pdev));
283 strcpy(drvinfo->version, DRV_VERSION);
284}
285
286static u32 smsc9420_ethtool_get_msglevel(struct net_device *netdev)
287{
288 struct smsc9420_pdata *pd = netdev_priv(netdev);
289 return pd->msg_enable;
290}
291
292static void smsc9420_ethtool_set_msglevel(struct net_device *netdev, u32 data)
293{
294 struct smsc9420_pdata *pd = netdev_priv(netdev);
295 pd->msg_enable = data;
296}
297
298static int smsc9420_ethtool_nway_reset(struct net_device *netdev)
299{
300 struct smsc9420_pdata *pd = netdev_priv(netdev);
301
302 if (!pd->phy_dev)
303 return -ENODEV;
304
305 return phy_start_aneg(pd->phy_dev);
306}
307
308static int smsc9420_ethtool_getregslen(struct net_device *dev)
309{
310 /* all smsc9420 registers plus all phy registers */
311 return 0x100 + (32 * sizeof(u32));
312}
313
314static void
315smsc9420_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
316 void *buf)
317{
318 struct smsc9420_pdata *pd = netdev_priv(dev);
319 struct phy_device *phy_dev = pd->phy_dev;
320 unsigned int i, j = 0;
321 u32 *data = buf;
322
323 regs->version = smsc9420_reg_read(pd, ID_REV);
324 for (i = 0; i < 0x100; i += (sizeof(u32)))
325 data[j++] = smsc9420_reg_read(pd, i);
326
327 // cannot read phy registers if the net device is down
328 if (!phy_dev)
329 return;
330
331 for (i = 0; i <= 31; i++)
332 data[j++] = smsc9420_mii_read(phy_dev->bus, phy_dev->addr, i);
333}
334
335static void smsc9420_eeprom_enable_access(struct smsc9420_pdata *pd)
336{
337 unsigned int temp = smsc9420_reg_read(pd, GPIO_CFG);
338 temp &= ~GPIO_CFG_EEPR_EN_;
339 smsc9420_reg_write(pd, GPIO_CFG, temp);
340 msleep(1);
341}
342
343static int smsc9420_eeprom_send_cmd(struct smsc9420_pdata *pd, u32 op)
344{
345 int timeout = 100;
346 u32 e2cmd;
347
348 smsc_dbg(HW, "op 0x%08x", op);
349 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
350 smsc_warn(HW, "Busy at start");
351 return -EBUSY;
352 }
353
354 e2cmd = op | E2P_CMD_EPC_BUSY_;
355 smsc9420_reg_write(pd, E2P_CMD, e2cmd);
356
357 do {
358 msleep(1);
359 e2cmd = smsc9420_reg_read(pd, E2P_CMD);
360 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
361
362 if (!timeout) {
363 smsc_info(HW, "TIMED OUT");
364 return -EAGAIN;
365 }
366
367 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
368 smsc_info(HW, "Error occurred during eeprom operation");
369 return -EINVAL;
370 }
371
372 return 0;
373}
374
375static int smsc9420_eeprom_read_location(struct smsc9420_pdata *pd,
376 u8 address, u8 *data)
377{
378 u32 op = E2P_CMD_EPC_CMD_READ_ | address;
379 int ret;
380
381 smsc_dbg(HW, "address 0x%x", address);
382 ret = smsc9420_eeprom_send_cmd(pd, op);
383
384 if (!ret)
385 data[address] = smsc9420_reg_read(pd, E2P_DATA);
386
387 return ret;
388}
389
390static int smsc9420_eeprom_write_location(struct smsc9420_pdata *pd,
391 u8 address, u8 data)
392{
393 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
394 int ret;
395
396 smsc_dbg(HW, "address 0x%x, data 0x%x", address, data);
397 ret = smsc9420_eeprom_send_cmd(pd, op);
398
399 if (!ret) {
400 op = E2P_CMD_EPC_CMD_WRITE_ | address;
401 smsc9420_reg_write(pd, E2P_DATA, (u32)data);
402 ret = smsc9420_eeprom_send_cmd(pd, op);
403 }
404
405 return ret;
406}
407
408static int smsc9420_ethtool_get_eeprom_len(struct net_device *dev)
409{
410 return SMSC9420_EEPROM_SIZE;
411}
412
413static int smsc9420_ethtool_get_eeprom(struct net_device *dev,
414 struct ethtool_eeprom *eeprom, u8 *data)
415{
416 struct smsc9420_pdata *pd = netdev_priv(dev);
417 u8 eeprom_data[SMSC9420_EEPROM_SIZE];
418 int len, i;
419
420 smsc9420_eeprom_enable_access(pd);
421
422 len = min(eeprom->len, SMSC9420_EEPROM_SIZE);
423 for (i = 0; i < len; i++) {
424 int ret = smsc9420_eeprom_read_location(pd, i, eeprom_data);
425 if (ret < 0) {
426 eeprom->len = 0;
427 return ret;
428 }
429 }
430
431 memcpy(data, &eeprom_data[eeprom->offset], len);
432 eeprom->magic = SMSC9420_EEPROM_MAGIC;
433 eeprom->len = len;
434 return 0;
435}
436
437static int smsc9420_ethtool_set_eeprom(struct net_device *dev,
438 struct ethtool_eeprom *eeprom, u8 *data)
439{
440 struct smsc9420_pdata *pd = netdev_priv(dev);
441 int ret;
442
443 if (eeprom->magic != SMSC9420_EEPROM_MAGIC)
444 return -EINVAL;
445
446 smsc9420_eeprom_enable_access(pd);
447 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWEN_);
448 ret = smsc9420_eeprom_write_location(pd, eeprom->offset, *data);
449 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWDS_);
450
451 /* Single byte write, according to man page */
452 eeprom->len = 1;
453
454 return ret;
455}
456
457static const struct ethtool_ops smsc9420_ethtool_ops = {
458 .get_settings = smsc9420_ethtool_get_settings,
459 .set_settings = smsc9420_ethtool_set_settings,
460 .get_drvinfo = smsc9420_ethtool_get_drvinfo,
461 .get_msglevel = smsc9420_ethtool_get_msglevel,
462 .set_msglevel = smsc9420_ethtool_set_msglevel,
463 .nway_reset = smsc9420_ethtool_nway_reset,
464 .get_link = ethtool_op_get_link,
465 .get_eeprom_len = smsc9420_ethtool_get_eeprom_len,
466 .get_eeprom = smsc9420_ethtool_get_eeprom,
467 .set_eeprom = smsc9420_ethtool_set_eeprom,
468 .get_regs_len = smsc9420_ethtool_getregslen,
469 .get_regs = smsc9420_ethtool_getregs,
470};
471
472/* Sets the device MAC address to dev_addr */
473static void smsc9420_set_mac_address(struct net_device *dev)
474{
475 struct smsc9420_pdata *pd = netdev_priv(dev);
476 u8 *dev_addr = dev->dev_addr;
477 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
478 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
479 (dev_addr[1] << 8) | dev_addr[0];
480
481 smsc9420_reg_write(pd, ADDRH, mac_high16);
482 smsc9420_reg_write(pd, ADDRL, mac_low32);
483}
484
485static void smsc9420_check_mac_address(struct net_device *dev)
486{
487 struct smsc9420_pdata *pd = netdev_priv(dev);
488
489 /* Check if mac address has been specified when bringing interface up */
490 if (is_valid_ether_addr(dev->dev_addr)) {
491 smsc9420_set_mac_address(dev);
492 smsc_dbg(PROBE, "MAC Address is specified by configuration");
493 } else {
494 /* Try reading mac address from device. if EEPROM is present
495 * it will already have been set */
496 u32 mac_high16 = smsc9420_reg_read(pd, ADDRH);
497 u32 mac_low32 = smsc9420_reg_read(pd, ADDRL);
498 dev->dev_addr[0] = (u8)(mac_low32);
499 dev->dev_addr[1] = (u8)(mac_low32 >> 8);
500 dev->dev_addr[2] = (u8)(mac_low32 >> 16);
501 dev->dev_addr[3] = (u8)(mac_low32 >> 24);
502 dev->dev_addr[4] = (u8)(mac_high16);
503 dev->dev_addr[5] = (u8)(mac_high16 >> 8);
504
505 if (is_valid_ether_addr(dev->dev_addr)) {
506 /* eeprom values are valid so use them */
507 smsc_dbg(PROBE, "Mac Address is read from EEPROM");
508 } else {
509 /* eeprom values are invalid, generate random MAC */
510 random_ether_addr(dev->dev_addr);
511 smsc9420_set_mac_address(dev);
512 smsc_dbg(PROBE,
513 "MAC Address is set to random_ether_addr");
514 }
515 }
516}
517
518static void smsc9420_stop_tx(struct smsc9420_pdata *pd)
519{
520 u32 dmac_control, mac_cr, dma_intr_ena;
521 int timeout = 1000;
522
523 /* disable TX DMAC */
524 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
525 dmac_control &= (~DMAC_CONTROL_ST_);
526 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
527
528 /* Wait max 10ms for transmit process to stop */
529 while (--timeout) {
530 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_TS_)
531 break;
532 udelay(10);
533 }
534
535 if (!timeout)
536 smsc_warn(IFDOWN, "TX DMAC failed to stop");
537
538 /* ACK Tx DMAC stop bit */
539 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_TXPS_);
540
541 /* mask TX DMAC interrupts */
542 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
543 dma_intr_ena &= ~(DMAC_INTR_ENA_TX_);
544 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
545 smsc9420_pci_flush_write(pd);
546
547 /* stop MAC TX */
548 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_TXEN_);
549 smsc9420_reg_write(pd, MAC_CR, mac_cr);
550 smsc9420_pci_flush_write(pd);
551}
552
553static void smsc9420_free_tx_ring(struct smsc9420_pdata *pd)
554{
555 int i;
556
557 BUG_ON(!pd->tx_ring);
558
559 if (!pd->tx_buffers)
560 return;
561
562 for (i = 0; i < TX_RING_SIZE; i++) {
563 struct sk_buff *skb = pd->tx_buffers[i].skb;
564
565 if (skb) {
566 BUG_ON(!pd->tx_buffers[i].mapping);
567 pci_unmap_single(pd->pdev, pd->tx_buffers[i].mapping,
568 skb->len, PCI_DMA_TODEVICE);
569 dev_kfree_skb_any(skb);
570 }
571
572 pd->tx_ring[i].status = 0;
573 pd->tx_ring[i].length = 0;
574 pd->tx_ring[i].buffer1 = 0;
575 pd->tx_ring[i].buffer2 = 0;
576 }
577 wmb();
578
579 kfree(pd->tx_buffers);
580 pd->tx_buffers = NULL;
581
582 pd->tx_ring_head = 0;
583 pd->tx_ring_tail = 0;
584}
585
586static void smsc9420_free_rx_ring(struct smsc9420_pdata *pd)
587{
588 int i;
589
590 BUG_ON(!pd->rx_ring);
591
592 if (!pd->rx_buffers)
593 return;
594
595 for (i = 0; i < RX_RING_SIZE; i++) {
596 if (pd->rx_buffers[i].skb)
597 dev_kfree_skb_any(pd->rx_buffers[i].skb);
598
599 if (pd->rx_buffers[i].mapping)
600 pci_unmap_single(pd->pdev, pd->rx_buffers[i].mapping,
601 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
602
603 pd->rx_ring[i].status = 0;
604 pd->rx_ring[i].length = 0;
605 pd->rx_ring[i].buffer1 = 0;
606 pd->rx_ring[i].buffer2 = 0;
607 }
608 wmb();
609
610 kfree(pd->rx_buffers);
611 pd->rx_buffers = NULL;
612
613 pd->rx_ring_head = 0;
614 pd->rx_ring_tail = 0;
615}
616
617static void smsc9420_stop_rx(struct smsc9420_pdata *pd)
618{
619 int timeout = 1000;
620 u32 mac_cr, dmac_control, dma_intr_ena;
621
622 /* mask RX DMAC interrupts */
623 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
624 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
625 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
626 smsc9420_pci_flush_write(pd);
627
628 /* stop RX MAC prior to stoping DMA */
629 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_RXEN_);
630 smsc9420_reg_write(pd, MAC_CR, mac_cr);
631 smsc9420_pci_flush_write(pd);
632
633 /* stop RX DMAC */
634 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
635 dmac_control &= (~DMAC_CONTROL_SR_);
636 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
637 smsc9420_pci_flush_write(pd);
638
639 /* wait up to 10ms for receive to stop */
640 while (--timeout) {
641 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_RS_)
642 break;
643 udelay(10);
644 }
645
646 if (!timeout)
647 smsc_warn(IFDOWN, "RX DMAC did not stop! timeout.");
648
649 /* ACK the Rx DMAC stop bit */
650 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_RXPS_);
651}
652
653static irqreturn_t smsc9420_isr(int irq, void *dev_id)
654{
655 struct smsc9420_pdata *pd = dev_id;
656 u32 int_cfg, int_sts, int_ctl;
657 irqreturn_t ret = IRQ_NONE;
658 ulong flags;
659
660 BUG_ON(!pd);
661 BUG_ON(!pd->base_addr);
662
663 int_cfg = smsc9420_reg_read(pd, INT_CFG);
664
665 /* check if it's our interrupt */
666 if ((int_cfg & (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) !=
667 (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_))
668 return IRQ_NONE;
669
670 int_sts = smsc9420_reg_read(pd, INT_STAT);
671
672 if (likely(INT_STAT_DMAC_INT_ & int_sts)) {
673 u32 status = smsc9420_reg_read(pd, DMAC_STATUS);
674 u32 ints_to_clear = 0;
675
676 if (status & DMAC_STS_TX_) {
677 ints_to_clear |= (DMAC_STS_TX_ | DMAC_STS_NIS_);
678 netif_wake_queue(pd->dev);
679 }
680
681 if (status & DMAC_STS_RX_) {
682 /* mask RX DMAC interrupts */
683 u32 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
684 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
685 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
686 smsc9420_pci_flush_write(pd);
687
688 ints_to_clear |= (DMAC_STS_RX_ | DMAC_STS_NIS_);
689 napi_schedule(&pd->napi);
690 }
691
692 if (ints_to_clear)
693 smsc9420_reg_write(pd, DMAC_STATUS, ints_to_clear);
694
695 ret = IRQ_HANDLED;
696 }
697
698 if (unlikely(INT_STAT_SW_INT_ & int_sts)) {
699 /* mask software interrupt */
700 spin_lock_irqsave(&pd->int_lock, flags);
701 int_ctl = smsc9420_reg_read(pd, INT_CTL);
702 int_ctl &= (~INT_CTL_SW_INT_EN_);
703 smsc9420_reg_write(pd, INT_CTL, int_ctl);
704 spin_unlock_irqrestore(&pd->int_lock, flags);
705
706 smsc9420_reg_write(pd, INT_STAT, INT_STAT_SW_INT_);
707 pd->software_irq_signal = true;
708 smp_wmb();
709
710 ret = IRQ_HANDLED;
711 }
712
713 /* to ensure PCI write completion, we must perform a PCI read */
714 smsc9420_pci_flush_write(pd);
715
716 return ret;
717}
718
719#ifdef CONFIG_NET_POLL_CONTROLLER
720static void smsc9420_poll_controller(struct net_device *dev)
721{
722 disable_irq(dev->irq);
723 smsc9420_isr(0, dev);
724 enable_irq(dev->irq);
725}
726#endif /* CONFIG_NET_POLL_CONTROLLER */
727
728static void smsc9420_dmac_soft_reset(struct smsc9420_pdata *pd)
729{
730 smsc9420_reg_write(pd, BUS_MODE, BUS_MODE_SWR_);
731 smsc9420_reg_read(pd, BUS_MODE);
732 udelay(2);
733 if (smsc9420_reg_read(pd, BUS_MODE) & BUS_MODE_SWR_)
734 smsc_warn(DRV, "Software reset not cleared");
735}
736
737static int smsc9420_stop(struct net_device *dev)
738{
739 struct smsc9420_pdata *pd = netdev_priv(dev);
740 u32 int_cfg;
741 ulong flags;
742
743 BUG_ON(!pd);
744 BUG_ON(!pd->phy_dev);
745
746 /* disable master interrupt */
747 spin_lock_irqsave(&pd->int_lock, flags);
748 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
749 smsc9420_reg_write(pd, INT_CFG, int_cfg);
750 spin_unlock_irqrestore(&pd->int_lock, flags);
751
752 netif_tx_disable(dev);
753 napi_disable(&pd->napi);
754
755 smsc9420_stop_tx(pd);
756 smsc9420_free_tx_ring(pd);
757
758 smsc9420_stop_rx(pd);
759 smsc9420_free_rx_ring(pd);
760
761 free_irq(dev->irq, pd);
762
763 smsc9420_dmac_soft_reset(pd);
764
765 phy_stop(pd->phy_dev);
766
767 phy_disconnect(pd->phy_dev);
768 pd->phy_dev = NULL;
769 mdiobus_unregister(pd->mii_bus);
770 mdiobus_free(pd->mii_bus);
771
772 return 0;
773}
774
775static void smsc9420_rx_count_stats(struct net_device *dev, u32 desc_status)
776{
777 if (unlikely(desc_status & RDES0_ERROR_SUMMARY_)) {
778 dev->stats.rx_errors++;
779 if (desc_status & RDES0_DESCRIPTOR_ERROR_)
780 dev->stats.rx_over_errors++;
781 else if (desc_status & (RDES0_FRAME_TOO_LONG_ |
782 RDES0_RUNT_FRAME_ | RDES0_COLLISION_SEEN_))
783 dev->stats.rx_frame_errors++;
784 else if (desc_status & RDES0_CRC_ERROR_)
785 dev->stats.rx_crc_errors++;
786 }
787
788 if (unlikely(desc_status & RDES0_LENGTH_ERROR_))
789 dev->stats.rx_length_errors++;
790
791 if (unlikely(!((desc_status & RDES0_LAST_DESCRIPTOR_) &&
792 (desc_status & RDES0_FIRST_DESCRIPTOR_))))
793 dev->stats.rx_length_errors++;
794
795 if (desc_status & RDES0_MULTICAST_FRAME_)
796 dev->stats.multicast++;
797}
798
799static void smsc9420_rx_handoff(struct smsc9420_pdata *pd, const int index,
800 const u32 status)
801{
802 struct net_device *dev = pd->dev;
803 struct sk_buff *skb;
804 u16 packet_length = (status & RDES0_FRAME_LENGTH_MASK_)
805 >> RDES0_FRAME_LENGTH_SHFT_;
806
807 /* remove crc from packet lendth */
808 packet_length -= 4;
809
810 if (pd->rx_csum)
811 packet_length -= 2;
812
813 dev->stats.rx_packets++;
814 dev->stats.rx_bytes += packet_length;
815
816 pci_unmap_single(pd->pdev, pd->rx_buffers[index].mapping,
817 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
818 pd->rx_buffers[index].mapping = 0;
819
820 skb = pd->rx_buffers[index].skb;
821 pd->rx_buffers[index].skb = NULL;
822
823 if (pd->rx_csum) {
824 u16 hw_csum = get_unaligned_le16(skb_tail_pointer(skb) +
825 NET_IP_ALIGN + packet_length + 4);
826 put_unaligned_le16(hw_csum, &skb->csum);
827 skb->ip_summed = CHECKSUM_COMPLETE;
828 }
829
830 skb_reserve(skb, NET_IP_ALIGN);
831 skb_put(skb, packet_length);
832
833 skb->protocol = eth_type_trans(skb, dev);
834
835 netif_receive_skb(skb);
836}
837
838static int smsc9420_alloc_rx_buffer(struct smsc9420_pdata *pd, int index)
839{
840 struct sk_buff *skb = netdev_alloc_skb(pd->dev, PKT_BUF_SZ);
841 dma_addr_t mapping;
842
843 BUG_ON(pd->rx_buffers[index].skb);
844 BUG_ON(pd->rx_buffers[index].mapping);
845
846 if (unlikely(!skb)) {
847 smsc_warn(RX_ERR, "Failed to allocate new skb!");
848 return -ENOMEM;
849 }
850
851 skb->dev = pd->dev;
852
853 mapping = pci_map_single(pd->pdev, skb_tail_pointer(skb),
854 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
855 if (pci_dma_mapping_error(pd->pdev, mapping)) {
856 dev_kfree_skb_any(skb);
857 smsc_warn(RX_ERR, "pci_map_single failed!");
858 return -ENOMEM;
859 }
860
861 pd->rx_buffers[index].skb = skb;
862 pd->rx_buffers[index].mapping = mapping;
863 pd->rx_ring[index].buffer1 = mapping + NET_IP_ALIGN;
864 pd->rx_ring[index].status = RDES0_OWN_;
865 wmb();
866
867 return 0;
868}
869
870static void smsc9420_alloc_new_rx_buffers(struct smsc9420_pdata *pd)
871{
872 while (pd->rx_ring_tail != pd->rx_ring_head) {
873 if (smsc9420_alloc_rx_buffer(pd, pd->rx_ring_tail))
874 break;
875
876 pd->rx_ring_tail = (pd->rx_ring_tail + 1) % RX_RING_SIZE;
877 }
878}
879
880static int smsc9420_rx_poll(struct napi_struct *napi, int budget)
881{
882 struct smsc9420_pdata *pd =
883 container_of(napi, struct smsc9420_pdata, napi);
884 struct net_device *dev = pd->dev;
885 u32 drop_frame_cnt, dma_intr_ena, status;
886 int work_done;
887
888 for (work_done = 0; work_done < budget; work_done++) {
889 rmb();
890 status = pd->rx_ring[pd->rx_ring_head].status;
891
892 /* stop if DMAC owns this dma descriptor */
893 if (status & RDES0_OWN_)
894 break;
895
896 smsc9420_rx_count_stats(dev, status);
897 smsc9420_rx_handoff(pd, pd->rx_ring_head, status);
898 pd->rx_ring_head = (pd->rx_ring_head + 1) % RX_RING_SIZE;
899 smsc9420_alloc_new_rx_buffers(pd);
900 }
901
902 drop_frame_cnt = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
903 dev->stats.rx_dropped +=
904 (drop_frame_cnt & 0xFFFF) + ((drop_frame_cnt >> 17) & 0x3FF);
905
906 /* Kick RXDMA */
907 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
908 smsc9420_pci_flush_write(pd);
909
910 if (work_done < budget) {
911 napi_complete(&pd->napi);
912
913 /* re-enable RX DMA interrupts */
914 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
915 dma_intr_ena |= (DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
916 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
917 smsc9420_pci_flush_write(pd);
918 }
919 return work_done;
920}
921
922static void
923smsc9420_tx_update_stats(struct net_device *dev, u32 status, u32 length)
924{
925 if (unlikely(status & TDES0_ERROR_SUMMARY_)) {
926 dev->stats.tx_errors++;
927 if (status & (TDES0_EXCESSIVE_DEFERRAL_ |
928 TDES0_EXCESSIVE_COLLISIONS_))
929 dev->stats.tx_aborted_errors++;
930
931 if (status & (TDES0_LOSS_OF_CARRIER_ | TDES0_NO_CARRIER_))
932 dev->stats.tx_carrier_errors++;
933 } else {
934 dev->stats.tx_packets++;
935 dev->stats.tx_bytes += (length & 0x7FF);
936 }
937
938 if (unlikely(status & TDES0_EXCESSIVE_COLLISIONS_)) {
939 dev->stats.collisions += 16;
940 } else {
941 dev->stats.collisions +=
942 (status & TDES0_COLLISION_COUNT_MASK_) >>
943 TDES0_COLLISION_COUNT_SHFT_;
944 }
945
946 if (unlikely(status & TDES0_HEARTBEAT_FAIL_))
947 dev->stats.tx_heartbeat_errors++;
948}
949
950/* Check for completed dma transfers, update stats and free skbs */
951static void smsc9420_complete_tx(struct net_device *dev)
952{
953 struct smsc9420_pdata *pd = netdev_priv(dev);
954
955 while (pd->tx_ring_tail != pd->tx_ring_head) {
956 int index = pd->tx_ring_tail;
957 u32 status, length;
958
959 rmb();
960 status = pd->tx_ring[index].status;
961 length = pd->tx_ring[index].length;
962
963 /* Check if DMA still owns this descriptor */
964 if (unlikely(TDES0_OWN_ & status))
965 break;
966
967 smsc9420_tx_update_stats(dev, status, length);
968
969 BUG_ON(!pd->tx_buffers[index].skb);
970 BUG_ON(!pd->tx_buffers[index].mapping);
971
972 pci_unmap_single(pd->pdev, pd->tx_buffers[index].mapping,
973 pd->tx_buffers[index].skb->len, PCI_DMA_TODEVICE);
974 pd->tx_buffers[index].mapping = 0;
975
976 dev_kfree_skb_any(pd->tx_buffers[index].skb);
977 pd->tx_buffers[index].skb = NULL;
978
979 pd->tx_ring[index].buffer1 = 0;
980 wmb();
981
982 pd->tx_ring_tail = (pd->tx_ring_tail + 1) % TX_RING_SIZE;
983 }
984}
985
986static netdev_tx_t smsc9420_hard_start_xmit(struct sk_buff *skb,
987 struct net_device *dev)
988{
989 struct smsc9420_pdata *pd = netdev_priv(dev);
990 dma_addr_t mapping;
991 int index = pd->tx_ring_head;
992 u32 tmp_desc1;
993 bool about_to_take_last_desc =
994 (((pd->tx_ring_head + 2) % TX_RING_SIZE) == pd->tx_ring_tail);
995
996 smsc9420_complete_tx(dev);
997
998 rmb();
999 BUG_ON(pd->tx_ring[index].status & TDES0_OWN_);
1000 BUG_ON(pd->tx_buffers[index].skb);
1001 BUG_ON(pd->tx_buffers[index].mapping);
1002
1003 mapping = pci_map_single(pd->pdev, skb->data,
1004 skb->len, PCI_DMA_TODEVICE);
1005 if (pci_dma_mapping_error(pd->pdev, mapping)) {
1006 smsc_warn(TX_ERR, "pci_map_single failed, dropping packet");
1007 return NETDEV_TX_BUSY;
1008 }
1009
1010 pd->tx_buffers[index].skb = skb;
1011 pd->tx_buffers[index].mapping = mapping;
1012
1013 tmp_desc1 = (TDES1_LS_ | ((u32)skb->len & 0x7FF));
1014 if (unlikely(about_to_take_last_desc)) {
1015 tmp_desc1 |= TDES1_IC_;
1016 netif_stop_queue(pd->dev);
1017 }
1018
1019 /* check if we are at the last descriptor and need to set EOR */
1020 if (unlikely(index == (TX_RING_SIZE - 1)))
1021 tmp_desc1 |= TDES1_TER_;
1022
1023 pd->tx_ring[index].buffer1 = mapping;
1024 pd->tx_ring[index].length = tmp_desc1;
1025 wmb();
1026
1027 /* increment head */
1028 pd->tx_ring_head = (pd->tx_ring_head + 1) % TX_RING_SIZE;
1029
1030 /* assign ownership to DMAC */
1031 pd->tx_ring[index].status = TDES0_OWN_;
1032 wmb();
1033
1034 skb_tx_timestamp(skb);
1035
1036 /* kick the DMA */
1037 smsc9420_reg_write(pd, TX_POLL_DEMAND, 1);
1038 smsc9420_pci_flush_write(pd);
1039
1040 return NETDEV_TX_OK;
1041}
1042
1043static struct net_device_stats *smsc9420_get_stats(struct net_device *dev)
1044{
1045 struct smsc9420_pdata *pd = netdev_priv(dev);
1046 u32 counter = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
1047 dev->stats.rx_dropped +=
1048 (counter & 0x0000FFFF) + ((counter >> 17) & 0x000003FF);
1049 return &dev->stats;
1050}
1051
1052static void smsc9420_set_multicast_list(struct net_device *dev)
1053{
1054 struct smsc9420_pdata *pd = netdev_priv(dev);
1055 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
1056
1057 if (dev->flags & IFF_PROMISC) {
1058 smsc_dbg(HW, "Promiscuous Mode Enabled");
1059 mac_cr |= MAC_CR_PRMS_;
1060 mac_cr &= (~MAC_CR_MCPAS_);
1061 mac_cr &= (~MAC_CR_HPFILT_);
1062 } else if (dev->flags & IFF_ALLMULTI) {
1063 smsc_dbg(HW, "Receive all Multicast Enabled");
1064 mac_cr &= (~MAC_CR_PRMS_);
1065 mac_cr |= MAC_CR_MCPAS_;
1066 mac_cr &= (~MAC_CR_HPFILT_);
1067 } else if (!netdev_mc_empty(dev)) {
1068 struct netdev_hw_addr *ha;
1069 u32 hash_lo = 0, hash_hi = 0;
1070
1071 smsc_dbg(HW, "Multicast filter enabled");
1072 netdev_for_each_mc_addr(ha, dev) {
1073 u32 bit_num = smsc9420_hash(ha->addr);
1074 u32 mask = 1 << (bit_num & 0x1F);
1075
1076 if (bit_num & 0x20)
1077 hash_hi |= mask;
1078 else
1079 hash_lo |= mask;
1080
1081 }
1082 smsc9420_reg_write(pd, HASHH, hash_hi);
1083 smsc9420_reg_write(pd, HASHL, hash_lo);
1084
1085 mac_cr &= (~MAC_CR_PRMS_);
1086 mac_cr &= (~MAC_CR_MCPAS_);
1087 mac_cr |= MAC_CR_HPFILT_;
1088 } else {
1089 smsc_dbg(HW, "Receive own packets only.");
1090 smsc9420_reg_write(pd, HASHH, 0);
1091 smsc9420_reg_write(pd, HASHL, 0);
1092
1093 mac_cr &= (~MAC_CR_PRMS_);
1094 mac_cr &= (~MAC_CR_MCPAS_);
1095 mac_cr &= (~MAC_CR_HPFILT_);
1096 }
1097
1098 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1099 smsc9420_pci_flush_write(pd);
1100}
1101
1102static void smsc9420_phy_update_flowcontrol(struct smsc9420_pdata *pd)
1103{
1104 struct phy_device *phy_dev = pd->phy_dev;
1105 u32 flow;
1106
1107 if (phy_dev->duplex == DUPLEX_FULL) {
1108 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
1109 u16 rmtadv = phy_read(phy_dev, MII_LPA);
1110 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1111
1112 if (cap & FLOW_CTRL_RX)
1113 flow = 0xFFFF0002;
1114 else
1115 flow = 0;
1116
1117 smsc_info(LINK, "rx pause %s, tx pause %s",
1118 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
1119 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
1120 } else {
1121 smsc_info(LINK, "half duplex");
1122 flow = 0;
1123 }
1124
1125 smsc9420_reg_write(pd, FLOW, flow);
1126}
1127
1128/* Update link mode if anything has changed. Called periodically when the
1129 * PHY is in polling mode, even if nothing has changed. */
1130static void smsc9420_phy_adjust_link(struct net_device *dev)
1131{
1132 struct smsc9420_pdata *pd = netdev_priv(dev);
1133 struct phy_device *phy_dev = pd->phy_dev;
1134 int carrier;
1135
1136 if (phy_dev->duplex != pd->last_duplex) {
1137 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
1138 if (phy_dev->duplex) {
1139 smsc_dbg(LINK, "full duplex mode");
1140 mac_cr |= MAC_CR_FDPX_;
1141 } else {
1142 smsc_dbg(LINK, "half duplex mode");
1143 mac_cr &= ~MAC_CR_FDPX_;
1144 }
1145 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1146
1147 smsc9420_phy_update_flowcontrol(pd);
1148 pd->last_duplex = phy_dev->duplex;
1149 }
1150
1151 carrier = netif_carrier_ok(dev);
1152 if (carrier != pd->last_carrier) {
1153 if (carrier)
1154 smsc_dbg(LINK, "carrier OK");
1155 else
1156 smsc_dbg(LINK, "no carrier");
1157 pd->last_carrier = carrier;
1158 }
1159}
1160
1161static int smsc9420_mii_probe(struct net_device *dev)
1162{
1163 struct smsc9420_pdata *pd = netdev_priv(dev);
1164 struct phy_device *phydev = NULL;
1165
1166 BUG_ON(pd->phy_dev);
1167
1168 /* Device only supports internal PHY at address 1 */
1169 if (!pd->mii_bus->phy_map[1]) {
1170 pr_err("%s: no PHY found at address 1\n", dev->name);
1171 return -ENODEV;
1172 }
1173
1174 phydev = pd->mii_bus->phy_map[1];
1175 smsc_info(PROBE, "PHY addr %d, phy_id 0x%08X", phydev->addr,
1176 phydev->phy_id);
1177
1178 phydev = phy_connect(dev, dev_name(&phydev->dev),
1179 smsc9420_phy_adjust_link, 0, PHY_INTERFACE_MODE_MII);
1180
1181 if (IS_ERR(phydev)) {
1182 pr_err("%s: Could not attach to PHY\n", dev->name);
1183 return PTR_ERR(phydev);
1184 }
1185
1186 pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1187 dev->name, phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
1188
1189 /* mask with MAC supported features */
1190 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
1191 SUPPORTED_Asym_Pause);
1192 phydev->advertising = phydev->supported;
1193
1194 pd->phy_dev = phydev;
1195 pd->last_duplex = -1;
1196 pd->last_carrier = -1;
1197
1198 return 0;
1199}
1200
1201static int smsc9420_mii_init(struct net_device *dev)
1202{
1203 struct smsc9420_pdata *pd = netdev_priv(dev);
1204 int err = -ENXIO, i;
1205
1206 pd->mii_bus = mdiobus_alloc();
1207 if (!pd->mii_bus) {
1208 err = -ENOMEM;
1209 goto err_out_1;
1210 }
1211 pd->mii_bus->name = DRV_MDIONAME;
1212 snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x",
1213 (pd->pdev->bus->number << 8) | pd->pdev->devfn);
1214 pd->mii_bus->priv = pd;
1215 pd->mii_bus->read = smsc9420_mii_read;
1216 pd->mii_bus->write = smsc9420_mii_write;
1217 pd->mii_bus->irq = pd->phy_irq;
1218 for (i = 0; i < PHY_MAX_ADDR; ++i)
1219 pd->mii_bus->irq[i] = PHY_POLL;
1220
1221 /* Mask all PHYs except ID 1 (internal) */
1222 pd->mii_bus->phy_mask = ~(1 << 1);
1223
1224 if (mdiobus_register(pd->mii_bus)) {
1225 smsc_warn(PROBE, "Error registering mii bus");
1226 goto err_out_free_bus_2;
1227 }
1228
1229 if (smsc9420_mii_probe(dev) < 0) {
1230 smsc_warn(PROBE, "Error probing mii bus");
1231 goto err_out_unregister_bus_3;
1232 }
1233
1234 return 0;
1235
1236err_out_unregister_bus_3:
1237 mdiobus_unregister(pd->mii_bus);
1238err_out_free_bus_2:
1239 mdiobus_free(pd->mii_bus);
1240err_out_1:
1241 return err;
1242}
1243
1244static int smsc9420_alloc_tx_ring(struct smsc9420_pdata *pd)
1245{
1246 int i;
1247
1248 BUG_ON(!pd->tx_ring);
1249
1250 pd->tx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) *
1251 TX_RING_SIZE), GFP_KERNEL);
1252 if (!pd->tx_buffers) {
1253 smsc_warn(IFUP, "Failed to allocated tx_buffers");
1254 return -ENOMEM;
1255 }
1256
1257 /* Initialize the TX Ring */
1258 for (i = 0; i < TX_RING_SIZE; i++) {
1259 pd->tx_buffers[i].skb = NULL;
1260 pd->tx_buffers[i].mapping = 0;
1261 pd->tx_ring[i].status = 0;
1262 pd->tx_ring[i].length = 0;
1263 pd->tx_ring[i].buffer1 = 0;
1264 pd->tx_ring[i].buffer2 = 0;
1265 }
1266 pd->tx_ring[TX_RING_SIZE - 1].length = TDES1_TER_;
1267 wmb();
1268
1269 pd->tx_ring_head = 0;
1270 pd->tx_ring_tail = 0;
1271
1272 smsc9420_reg_write(pd, TX_BASE_ADDR, pd->tx_dma_addr);
1273 smsc9420_pci_flush_write(pd);
1274
1275 return 0;
1276}
1277
1278static int smsc9420_alloc_rx_ring(struct smsc9420_pdata *pd)
1279{
1280 int i;
1281
1282 BUG_ON(!pd->rx_ring);
1283
1284 pd->rx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) *
1285 RX_RING_SIZE), GFP_KERNEL);
1286 if (pd->rx_buffers == NULL) {
1287 smsc_warn(IFUP, "Failed to allocated rx_buffers");
1288 goto out;
1289 }
1290
1291 /* initialize the rx ring */
1292 for (i = 0; i < RX_RING_SIZE; i++) {
1293 pd->rx_ring[i].status = 0;
1294 pd->rx_ring[i].length = PKT_BUF_SZ;
1295 pd->rx_ring[i].buffer2 = 0;
1296 pd->rx_buffers[i].skb = NULL;
1297 pd->rx_buffers[i].mapping = 0;
1298 }
1299 pd->rx_ring[RX_RING_SIZE - 1].length = (PKT_BUF_SZ | RDES1_RER_);
1300
1301 /* now allocate the entire ring of skbs */
1302 for (i = 0; i < RX_RING_SIZE; i++) {
1303 if (smsc9420_alloc_rx_buffer(pd, i)) {
1304 smsc_warn(IFUP, "failed to allocate rx skb %d", i);
1305 goto out_free_rx_skbs;
1306 }
1307 }
1308
1309 pd->rx_ring_head = 0;
1310 pd->rx_ring_tail = 0;
1311
1312 smsc9420_reg_write(pd, VLAN1, ETH_P_8021Q);
1313 smsc_dbg(IFUP, "VLAN1 = 0x%08x", smsc9420_reg_read(pd, VLAN1));
1314
1315 if (pd->rx_csum) {
1316 /* Enable RX COE */
1317 u32 coe = smsc9420_reg_read(pd, COE_CR) | RX_COE_EN;
1318 smsc9420_reg_write(pd, COE_CR, coe);
1319 smsc_dbg(IFUP, "COE_CR = 0x%08x", coe);
1320 }
1321
1322 smsc9420_reg_write(pd, RX_BASE_ADDR, pd->rx_dma_addr);
1323 smsc9420_pci_flush_write(pd);
1324
1325 return 0;
1326
1327out_free_rx_skbs:
1328 smsc9420_free_rx_ring(pd);
1329out:
1330 return -ENOMEM;
1331}
1332
1333static int smsc9420_open(struct net_device *dev)
1334{
1335 struct smsc9420_pdata *pd;
1336 u32 bus_mode, mac_cr, dmac_control, int_cfg, dma_intr_ena, int_ctl;
1337 unsigned long flags;
1338 int result = 0, timeout;
1339
1340 BUG_ON(!dev);
1341 pd = netdev_priv(dev);
1342 BUG_ON(!pd);
1343
1344 if (!is_valid_ether_addr(dev->dev_addr)) {
1345 smsc_warn(IFUP, "dev_addr is not a valid MAC address");
1346 result = -EADDRNOTAVAIL;
1347 goto out_0;
1348 }
1349
1350 netif_carrier_off(dev);
1351
1352 /* disable, mask and acknowledge all interrupts */
1353 spin_lock_irqsave(&pd->int_lock, flags);
1354 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1355 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1356 smsc9420_reg_write(pd, INT_CTL, 0);
1357 spin_unlock_irqrestore(&pd->int_lock, flags);
1358 smsc9420_reg_write(pd, DMAC_INTR_ENA, 0);
1359 smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF);
1360 smsc9420_pci_flush_write(pd);
1361
1362 if (request_irq(dev->irq, smsc9420_isr, IRQF_SHARED | IRQF_DISABLED,
1363 DRV_NAME, pd)) {
1364 smsc_warn(IFUP, "Unable to use IRQ = %d", dev->irq);
1365 result = -ENODEV;
1366 goto out_0;
1367 }
1368
1369 smsc9420_dmac_soft_reset(pd);
1370
1371 /* make sure MAC_CR is sane */
1372 smsc9420_reg_write(pd, MAC_CR, 0);
1373
1374 smsc9420_set_mac_address(dev);
1375
1376 /* Configure GPIO pins to drive LEDs */
1377 smsc9420_reg_write(pd, GPIO_CFG,
1378 (GPIO_CFG_LED_3_ | GPIO_CFG_LED_2_ | GPIO_CFG_LED_1_));
1379
1380 bus_mode = BUS_MODE_DMA_BURST_LENGTH_16;
1381
1382#ifdef __BIG_ENDIAN
1383 bus_mode |= BUS_MODE_DBO_;
1384#endif
1385
1386 smsc9420_reg_write(pd, BUS_MODE, bus_mode);
1387
1388 smsc9420_pci_flush_write(pd);
1389
1390 /* set bus master bridge arbitration priority for Rx and TX DMA */
1391 smsc9420_reg_write(pd, BUS_CFG, BUS_CFG_RXTXWEIGHT_4_1);
1392
1393 smsc9420_reg_write(pd, DMAC_CONTROL,
1394 (DMAC_CONTROL_SF_ | DMAC_CONTROL_OSF_));
1395
1396 smsc9420_pci_flush_write(pd);
1397
1398 /* test the IRQ connection to the ISR */
1399 smsc_dbg(IFUP, "Testing ISR using IRQ %d", dev->irq);
1400 pd->software_irq_signal = false;
1401
1402 spin_lock_irqsave(&pd->int_lock, flags);
1403 /* configure interrupt deassertion timer and enable interrupts */
1404 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1405 int_cfg &= ~(INT_CFG_INT_DEAS_MASK);
1406 int_cfg |= (INT_DEAS_TIME & INT_CFG_INT_DEAS_MASK);
1407 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1408
1409 /* unmask software interrupt */
1410 int_ctl = smsc9420_reg_read(pd, INT_CTL) | INT_CTL_SW_INT_EN_;
1411 smsc9420_reg_write(pd, INT_CTL, int_ctl);
1412 spin_unlock_irqrestore(&pd->int_lock, flags);
1413 smsc9420_pci_flush_write(pd);
1414
1415 timeout = 1000;
1416 while (timeout--) {
1417 if (pd->software_irq_signal)
1418 break;
1419 msleep(1);
1420 }
1421
1422 /* disable interrupts */
1423 spin_lock_irqsave(&pd->int_lock, flags);
1424 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1425 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1426 spin_unlock_irqrestore(&pd->int_lock, flags);
1427
1428 if (!pd->software_irq_signal) {
1429 smsc_warn(IFUP, "ISR failed signaling test");
1430 result = -ENODEV;
1431 goto out_free_irq_1;
1432 }
1433
1434 smsc_dbg(IFUP, "ISR passed test using IRQ %d", dev->irq);
1435
1436 result = smsc9420_alloc_tx_ring(pd);
1437 if (result) {
1438 smsc_warn(IFUP, "Failed to Initialize tx dma ring");
1439 result = -ENOMEM;
1440 goto out_free_irq_1;
1441 }
1442
1443 result = smsc9420_alloc_rx_ring(pd);
1444 if (result) {
1445 smsc_warn(IFUP, "Failed to Initialize rx dma ring");
1446 result = -ENOMEM;
1447 goto out_free_tx_ring_2;
1448 }
1449
1450 result = smsc9420_mii_init(dev);
1451 if (result) {
1452 smsc_warn(IFUP, "Failed to initialize Phy");
1453 result = -ENODEV;
1454 goto out_free_rx_ring_3;
1455 }
1456
1457 /* Bring the PHY up */
1458 phy_start(pd->phy_dev);
1459
1460 napi_enable(&pd->napi);
1461
1462 /* start tx and rx */
1463 mac_cr = smsc9420_reg_read(pd, MAC_CR) | MAC_CR_TXEN_ | MAC_CR_RXEN_;
1464 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1465
1466 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
1467 dmac_control |= DMAC_CONTROL_ST_ | DMAC_CONTROL_SR_;
1468 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
1469 smsc9420_pci_flush_write(pd);
1470
1471 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
1472 dma_intr_ena |=
1473 (DMAC_INTR_ENA_TX_ | DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
1474 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
1475 smsc9420_pci_flush_write(pd);
1476
1477 netif_wake_queue(dev);
1478
1479 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
1480
1481 /* enable interrupts */
1482 spin_lock_irqsave(&pd->int_lock, flags);
1483 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1484 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1485 spin_unlock_irqrestore(&pd->int_lock, flags);
1486
1487 return 0;
1488
1489out_free_rx_ring_3:
1490 smsc9420_free_rx_ring(pd);
1491out_free_tx_ring_2:
1492 smsc9420_free_tx_ring(pd);
1493out_free_irq_1:
1494 free_irq(dev->irq, pd);
1495out_0:
1496 return result;
1497}
1498
1499#ifdef CONFIG_PM
1500
1501static int smsc9420_suspend(struct pci_dev *pdev, pm_message_t state)
1502{
1503 struct net_device *dev = pci_get_drvdata(pdev);
1504 struct smsc9420_pdata *pd = netdev_priv(dev);
1505 u32 int_cfg;
1506 ulong flags;
1507
1508 /* disable interrupts */
1509 spin_lock_irqsave(&pd->int_lock, flags);
1510 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1511 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1512 spin_unlock_irqrestore(&pd->int_lock, flags);
1513
1514 if (netif_running(dev)) {
1515 netif_tx_disable(dev);
1516 smsc9420_stop_tx(pd);
1517 smsc9420_free_tx_ring(pd);
1518
1519 napi_disable(&pd->napi);
1520 smsc9420_stop_rx(pd);
1521 smsc9420_free_rx_ring(pd);
1522
1523 free_irq(dev->irq, pd);
1524
1525 netif_device_detach(dev);
1526 }
1527
1528 pci_save_state(pdev);
1529 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1530 pci_disable_device(pdev);
1531 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1532
1533 return 0;
1534}
1535
1536static int smsc9420_resume(struct pci_dev *pdev)
1537{
1538 struct net_device *dev = pci_get_drvdata(pdev);
1539 struct smsc9420_pdata *pd = netdev_priv(dev);
1540 int err;
1541
1542 pci_set_power_state(pdev, PCI_D0);
1543 pci_restore_state(pdev);
1544
1545 err = pci_enable_device(pdev);
1546 if (err)
1547 return err;
1548
1549 pci_set_master(pdev);
1550
1551 err = pci_enable_wake(pdev, 0, 0);
1552 if (err)
1553 smsc_warn(IFUP, "pci_enable_wake failed: %d", err);
1554
1555 if (netif_running(dev)) {
1556 err = smsc9420_open(dev);
1557 netif_device_attach(dev);
1558 }
1559 return err;
1560}
1561
1562#endif /* CONFIG_PM */
1563
1564static const struct net_device_ops smsc9420_netdev_ops = {
1565 .ndo_open = smsc9420_open,
1566 .ndo_stop = smsc9420_stop,
1567 .ndo_start_xmit = smsc9420_hard_start_xmit,
1568 .ndo_get_stats = smsc9420_get_stats,
1569 .ndo_set_multicast_list = smsc9420_set_multicast_list,
1570 .ndo_do_ioctl = smsc9420_do_ioctl,
1571 .ndo_validate_addr = eth_validate_addr,
1572 .ndo_set_mac_address = eth_mac_addr,
1573#ifdef CONFIG_NET_POLL_CONTROLLER
1574 .ndo_poll_controller = smsc9420_poll_controller,
1575#endif /* CONFIG_NET_POLL_CONTROLLER */
1576};
1577
1578static int __devinit
1579smsc9420_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1580{
1581 struct net_device *dev;
1582 struct smsc9420_pdata *pd;
1583 void __iomem *virt_addr;
1584 int result = 0;
1585 u32 id_rev;
1586
1587 printk(KERN_INFO DRV_DESCRIPTION " version " DRV_VERSION "\n");
1588
1589 /* First do the PCI initialisation */
1590 result = pci_enable_device(pdev);
1591 if (unlikely(result)) {
1592 printk(KERN_ERR "Cannot enable smsc9420\n");
1593 goto out_0;
1594 }
1595
1596 pci_set_master(pdev);
1597
1598 dev = alloc_etherdev(sizeof(*pd));
1599 if (!dev) {
1600 printk(KERN_ERR "ether device alloc failed\n");
1601 goto out_disable_pci_device_1;
1602 }
1603
1604 SET_NETDEV_DEV(dev, &pdev->dev);
1605
1606 if (!(pci_resource_flags(pdev, SMSC_BAR) & IORESOURCE_MEM)) {
1607 printk(KERN_ERR "Cannot find PCI device base address\n");
1608 goto out_free_netdev_2;
1609 }
1610
1611 if ((pci_request_regions(pdev, DRV_NAME))) {
1612 printk(KERN_ERR "Cannot obtain PCI resources, aborting.\n");
1613 goto out_free_netdev_2;
1614 }
1615
1616 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1617 printk(KERN_ERR "No usable DMA configuration, aborting.\n");
1618 goto out_free_regions_3;
1619 }
1620
1621 virt_addr = ioremap(pci_resource_start(pdev, SMSC_BAR),
1622 pci_resource_len(pdev, SMSC_BAR));
1623 if (!virt_addr) {
1624 printk(KERN_ERR "Cannot map device registers, aborting.\n");
1625 goto out_free_regions_3;
1626 }
1627
1628 /* registers are double mapped with 0 offset for LE and 0x200 for BE */
1629 virt_addr += LAN9420_CPSR_ENDIAN_OFFSET;
1630
1631 dev->base_addr = (ulong)virt_addr;
1632
1633 pd = netdev_priv(dev);
1634
1635 /* pci descriptors are created in the PCI consistent area */
1636 pd->rx_ring = pci_alloc_consistent(pdev,
1637 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE +
1638 sizeof(struct smsc9420_dma_desc) * TX_RING_SIZE,
1639 &pd->rx_dma_addr);
1640
1641 if (!pd->rx_ring)
1642 goto out_free_io_4;
1643
1644 /* descriptors are aligned due to the nature of pci_alloc_consistent */
1645 pd->tx_ring = (struct smsc9420_dma_desc *)
1646 (pd->rx_ring + RX_RING_SIZE);
1647 pd->tx_dma_addr = pd->rx_dma_addr +
1648 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE;
1649
1650 pd->pdev = pdev;
1651 pd->dev = dev;
1652 pd->base_addr = virt_addr;
1653 pd->msg_enable = smsc_debug;
1654 pd->rx_csum = true;
1655
1656 smsc_dbg(PROBE, "lan_base=0x%08lx", (ulong)virt_addr);
1657
1658 id_rev = smsc9420_reg_read(pd, ID_REV);
1659 switch (id_rev & 0xFFFF0000) {
1660 case 0x94200000:
1661 smsc_info(PROBE, "LAN9420 identified, ID_REV=0x%08X", id_rev);
1662 break;
1663 default:
1664 smsc_warn(PROBE, "LAN9420 NOT identified");
1665 smsc_warn(PROBE, "ID_REV=0x%08X", id_rev);
1666 goto out_free_dmadesc_5;
1667 }
1668
1669 smsc9420_dmac_soft_reset(pd);
1670 smsc9420_eeprom_reload(pd);
1671 smsc9420_check_mac_address(dev);
1672
1673 dev->netdev_ops = &smsc9420_netdev_ops;
1674 dev->ethtool_ops = &smsc9420_ethtool_ops;
1675 dev->irq = pdev->irq;
1676
1677 netif_napi_add(dev, &pd->napi, smsc9420_rx_poll, NAPI_WEIGHT);
1678
1679 result = register_netdev(dev);
1680 if (result) {
1681 smsc_warn(PROBE, "error %i registering device", result);
1682 goto out_free_dmadesc_5;
1683 }
1684
1685 pci_set_drvdata(pdev, dev);
1686
1687 spin_lock_init(&pd->int_lock);
1688 spin_lock_init(&pd->phy_lock);
1689
1690 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
1691
1692 return 0;
1693
1694out_free_dmadesc_5:
1695 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) *
1696 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr);
1697out_free_io_4:
1698 iounmap(virt_addr - LAN9420_CPSR_ENDIAN_OFFSET);
1699out_free_regions_3:
1700 pci_release_regions(pdev);
1701out_free_netdev_2:
1702 free_netdev(dev);
1703out_disable_pci_device_1:
1704 pci_disable_device(pdev);
1705out_0:
1706 return -ENODEV;
1707}
1708
1709static void __devexit smsc9420_remove(struct pci_dev *pdev)
1710{
1711 struct net_device *dev;
1712 struct smsc9420_pdata *pd;
1713
1714 dev = pci_get_drvdata(pdev);
1715 if (!dev)
1716 return;
1717
1718 pci_set_drvdata(pdev, NULL);
1719
1720 pd = netdev_priv(dev);
1721 unregister_netdev(dev);
1722
1723 /* tx_buffers and rx_buffers are freed in stop */
1724 BUG_ON(pd->tx_buffers);
1725 BUG_ON(pd->rx_buffers);
1726
1727 BUG_ON(!pd->tx_ring);
1728 BUG_ON(!pd->rx_ring);
1729
1730 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) *
1731 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr);
1732
1733 iounmap(pd->base_addr - LAN9420_CPSR_ENDIAN_OFFSET);
1734 pci_release_regions(pdev);
1735 free_netdev(dev);
1736 pci_disable_device(pdev);
1737}
1738
1739static struct pci_driver smsc9420_driver = {
1740 .name = DRV_NAME,
1741 .id_table = smsc9420_id_table,
1742 .probe = smsc9420_probe,
1743 .remove = __devexit_p(smsc9420_remove),
1744#ifdef CONFIG_PM
1745 .suspend = smsc9420_suspend,
1746 .resume = smsc9420_resume,
1747#endif /* CONFIG_PM */
1748};
1749
1750static int __init smsc9420_init_module(void)
1751{
1752 smsc_debug = netif_msg_init(debug, SMSC_MSG_DEFAULT);
1753
1754 return pci_register_driver(&smsc9420_driver);
1755}
1756
1757static void __exit smsc9420_exit_module(void)
1758{
1759 pci_unregister_driver(&smsc9420_driver);
1760}
1761
1762module_init(smsc9420_init_module);
1763module_exit(smsc9420_exit_module);
diff --git a/drivers/net/ethernet/smsc/smsc9420.h b/drivers/net/ethernet/smsc/smsc9420.h
new file mode 100644
index 000000000000..e441402f77a2
--- /dev/null
+++ b/drivers/net/ethernet/smsc/smsc9420.h
@@ -0,0 +1,276 @@
1 /***************************************************************************
2 *
3 * Copyright (C) 2007,2008 SMSC
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 *
19 ***************************************************************************
20 */
21
22#ifndef _SMSC9420_H
23#define _SMSC9420_H
24
25#define TX_RING_SIZE (32)
26#define RX_RING_SIZE (128)
27
28/* interrupt deassertion in multiples of 10us */
29#define INT_DEAS_TIME (50)
30
31#define NAPI_WEIGHT (64)
32#define SMSC_BAR (3)
33
34#ifdef __BIG_ENDIAN
35/* Register set is duplicated for BE at an offset of 0x200 */
36#define LAN9420_CPSR_ENDIAN_OFFSET (0x200)
37#else
38#define LAN9420_CPSR_ENDIAN_OFFSET (0)
39#endif
40
41#define PCI_VENDOR_ID_9420 (0x1055)
42#define PCI_DEVICE_ID_9420 (0xE420)
43
44#define LAN_REGISTER_EXTENT (0x400)
45
46#define SMSC9420_EEPROM_SIZE ((u32)11)
47#define SMSC9420_EEPROM_MAGIC (0x9420)
48
49#define PKT_BUF_SZ (VLAN_ETH_FRAME_LEN + NET_IP_ALIGN + 4)
50
51/***********************************************/
52/* DMA Controller Control and Status Registers */
53/***********************************************/
54#define BUS_MODE (0x00)
55#define BUS_MODE_SWR_ (BIT(0))
56#define BUS_MODE_DMA_BURST_LENGTH_1 (BIT(8))
57#define BUS_MODE_DMA_BURST_LENGTH_2 (BIT(9))
58#define BUS_MODE_DMA_BURST_LENGTH_4 (BIT(10))
59#define BUS_MODE_DMA_BURST_LENGTH_8 (BIT(11))
60#define BUS_MODE_DMA_BURST_LENGTH_16 (BIT(12))
61#define BUS_MODE_DMA_BURST_LENGTH_32 (BIT(13))
62#define BUS_MODE_DBO_ (BIT(20))
63
64#define TX_POLL_DEMAND (0x04)
65
66#define RX_POLL_DEMAND (0x08)
67
68#define RX_BASE_ADDR (0x0C)
69
70#define TX_BASE_ADDR (0x10)
71
72#define DMAC_STATUS (0x14)
73#define DMAC_STS_TS_ (7 << 20)
74#define DMAC_STS_RS_ (7 << 17)
75#define DMAC_STS_NIS_ (BIT(16))
76#define DMAC_STS_AIS_ (BIT(15))
77#define DMAC_STS_RWT_ (BIT(9))
78#define DMAC_STS_RXPS_ (BIT(8))
79#define DMAC_STS_RXBU_ (BIT(7))
80#define DMAC_STS_RX_ (BIT(6))
81#define DMAC_STS_TXUNF_ (BIT(5))
82#define DMAC_STS_TXBU_ (BIT(2))
83#define DMAC_STS_TXPS_ (BIT(1))
84#define DMAC_STS_TX_ (BIT(0))
85
86#define DMAC_CONTROL (0x18)
87#define DMAC_CONTROL_TTM_ (BIT(22))
88#define DMAC_CONTROL_SF_ (BIT(21))
89#define DMAC_CONTROL_ST_ (BIT(13))
90#define DMAC_CONTROL_OSF_ (BIT(2))
91#define DMAC_CONTROL_SR_ (BIT(1))
92
93#define DMAC_INTR_ENA (0x1C)
94#define DMAC_INTR_ENA_NIS_ (BIT(16))
95#define DMAC_INTR_ENA_AIS_ (BIT(15))
96#define DMAC_INTR_ENA_RWT_ (BIT(9))
97#define DMAC_INTR_ENA_RXPS_ (BIT(8))
98#define DMAC_INTR_ENA_RXBU_ (BIT(7))
99#define DMAC_INTR_ENA_RX_ (BIT(6))
100#define DMAC_INTR_ENA_TXBU_ (BIT(2))
101#define DMAC_INTR_ENA_TXPS_ (BIT(1))
102#define DMAC_INTR_ENA_TX_ (BIT(0))
103
104#define MISS_FRAME_CNTR (0x20)
105
106#define TX_BUFF_ADDR (0x50)
107
108#define RX_BUFF_ADDR (0x54)
109
110/* Transmit Descriptor Bit Defs */
111#define TDES0_OWN_ (0x80000000)
112#define TDES0_ERROR_SUMMARY_ (0x00008000)
113#define TDES0_LOSS_OF_CARRIER_ (0x00000800)
114#define TDES0_NO_CARRIER_ (0x00000400)
115#define TDES0_LATE_COLLISION_ (0x00000200)
116#define TDES0_EXCESSIVE_COLLISIONS_ (0x00000100)
117#define TDES0_HEARTBEAT_FAIL_ (0x00000080)
118#define TDES0_COLLISION_COUNT_MASK_ (0x00000078)
119#define TDES0_COLLISION_COUNT_SHFT_ (3)
120#define TDES0_EXCESSIVE_DEFERRAL_ (0x00000004)
121#define TDES0_DEFERRED_ (0x00000001)
122
123#define TDES1_IC_ 0x80000000
124#define TDES1_LS_ 0x40000000
125#define TDES1_FS_ 0x20000000
126#define TDES1_TXCSEN_ 0x08000000
127#define TDES1_TER_ (BIT(25))
128#define TDES1_TCH_ 0x01000000
129
130/* Receive Descriptor 0 Bit Defs */
131#define RDES0_OWN_ (0x80000000)
132#define RDES0_FRAME_LENGTH_MASK_ (0x07FF0000)
133#define RDES0_FRAME_LENGTH_SHFT_ (16)
134#define RDES0_ERROR_SUMMARY_ (0x00008000)
135#define RDES0_DESCRIPTOR_ERROR_ (0x00004000)
136#define RDES0_LENGTH_ERROR_ (0x00001000)
137#define RDES0_RUNT_FRAME_ (0x00000800)
138#define RDES0_MULTICAST_FRAME_ (0x00000400)
139#define RDES0_FIRST_DESCRIPTOR_ (0x00000200)
140#define RDES0_LAST_DESCRIPTOR_ (0x00000100)
141#define RDES0_FRAME_TOO_LONG_ (0x00000080)
142#define RDES0_COLLISION_SEEN_ (0x00000040)
143#define RDES0_FRAME_TYPE_ (0x00000020)
144#define RDES0_WATCHDOG_TIMEOUT_ (0x00000010)
145#define RDES0_MII_ERROR_ (0x00000008)
146#define RDES0_DRIBBLING_BIT_ (0x00000004)
147#define RDES0_CRC_ERROR_ (0x00000002)
148
149/* Receive Descriptor 1 Bit Defs */
150#define RDES1_RER_ (0x02000000)
151
152/***********************************************/
153/* MAC Control and Status Registers */
154/***********************************************/
155#define MAC_CR (0x80)
156#define MAC_CR_RXALL_ (0x80000000)
157#define MAC_CR_DIS_RXOWN_ (0x00800000)
158#define MAC_CR_LOOPBK_ (0x00200000)
159#define MAC_CR_FDPX_ (0x00100000)
160#define MAC_CR_MCPAS_ (0x00080000)
161#define MAC_CR_PRMS_ (0x00040000)
162#define MAC_CR_INVFILT_ (0x00020000)
163#define MAC_CR_PASSBAD_ (0x00010000)
164#define MAC_CR_HFILT_ (0x00008000)
165#define MAC_CR_HPFILT_ (0x00002000)
166#define MAC_CR_LCOLL_ (0x00001000)
167#define MAC_CR_DIS_BCAST_ (0x00000800)
168#define MAC_CR_DIS_RTRY_ (0x00000400)
169#define MAC_CR_PADSTR_ (0x00000100)
170#define MAC_CR_BOLMT_MSK (0x000000C0)
171#define MAC_CR_MFCHK_ (0x00000020)
172#define MAC_CR_TXEN_ (0x00000008)
173#define MAC_CR_RXEN_ (0x00000004)
174
175#define ADDRH (0x84)
176
177#define ADDRL (0x88)
178
179#define HASHH (0x8C)
180
181#define HASHL (0x90)
182
183#define MII_ACCESS (0x94)
184#define MII_ACCESS_MII_BUSY_ (0x00000001)
185#define MII_ACCESS_MII_WRITE_ (0x00000002)
186#define MII_ACCESS_MII_READ_ (0x00000000)
187#define MII_ACCESS_INDX_MSK_ (0x000007C0)
188#define MII_ACCESS_PHYADDR_MSK_ (0x0000F8C0)
189#define MII_ACCESS_INDX_SHFT_CNT (6)
190#define MII_ACCESS_PHYADDR_SHFT_CNT (11)
191
192#define MII_DATA (0x98)
193
194#define FLOW (0x9C)
195
196#define VLAN1 (0xA0)
197
198#define VLAN2 (0xA4)
199
200#define WUFF (0xA8)
201
202#define WUCSR (0xAC)
203
204#define COE_CR (0xB0)
205#define TX_COE_EN (0x00010000)
206#define RX_COE_MODE (0x00000002)
207#define RX_COE_EN (0x00000001)
208
209/***********************************************/
210/* System Control and Status Registers */
211/***********************************************/
212#define ID_REV (0xC0)
213
214#define INT_CTL (0xC4)
215#define INT_CTL_SW_INT_EN_ (0x00008000)
216#define INT_CTL_SBERR_INT_EN_ (1 << 12)
217#define INT_CTL_MBERR_INT_EN_ (1 << 13)
218#define INT_CTL_GPT_INT_EN_ (0x00000008)
219#define INT_CTL_PHY_INT_EN_ (0x00000004)
220#define INT_CTL_WAKE_INT_EN_ (0x00000002)
221
222#define INT_STAT (0xC8)
223#define INT_STAT_SW_INT_ (1 << 15)
224#define INT_STAT_MBERR_INT_ (1 << 13)
225#define INT_STAT_SBERR_INT_ (1 << 12)
226#define INT_STAT_GPT_INT_ (1 << 3)
227#define INT_STAT_PHY_INT_ (0x00000004)
228#define INT_STAT_WAKE_INT_ (0x00000002)
229#define INT_STAT_DMAC_INT_ (0x00000001)
230
231#define INT_CFG (0xCC)
232#define INT_CFG_IRQ_INT_ (0x00080000)
233#define INT_CFG_IRQ_EN_ (0x00040000)
234#define INT_CFG_INT_DEAS_CLR_ (0x00000200)
235#define INT_CFG_INT_DEAS_MASK (0x000000FF)
236
237#define GPIO_CFG (0xD0)
238#define GPIO_CFG_LED_3_ (0x40000000)
239#define GPIO_CFG_LED_2_ (0x20000000)
240#define GPIO_CFG_LED_1_ (0x10000000)
241#define GPIO_CFG_EEPR_EN_ (0x00700000)
242
243#define GPT_CFG (0xD4)
244#define GPT_CFG_TIMER_EN_ (0x20000000)
245
246#define GPT_CNT (0xD8)
247
248#define BUS_CFG (0xDC)
249#define BUS_CFG_RXTXWEIGHT_1_1 (0 << 25)
250#define BUS_CFG_RXTXWEIGHT_2_1 (1 << 25)
251#define BUS_CFG_RXTXWEIGHT_3_1 (2 << 25)
252#define BUS_CFG_RXTXWEIGHT_4_1 (3 << 25)
253
254#define PMT_CTRL (0xE0)
255
256#define FREE_RUN (0xF4)
257
258#define E2P_CMD (0xF8)
259#define E2P_CMD_EPC_BUSY_ (0x80000000)
260#define E2P_CMD_EPC_CMD_ (0x70000000)
261#define E2P_CMD_EPC_CMD_READ_ (0x00000000)
262#define E2P_CMD_EPC_CMD_EWDS_ (0x10000000)
263#define E2P_CMD_EPC_CMD_EWEN_ (0x20000000)
264#define E2P_CMD_EPC_CMD_WRITE_ (0x30000000)
265#define E2P_CMD_EPC_CMD_WRAL_ (0x40000000)
266#define E2P_CMD_EPC_CMD_ERASE_ (0x50000000)
267#define E2P_CMD_EPC_CMD_ERAL_ (0x60000000)
268#define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000)
269#define E2P_CMD_EPC_TIMEOUT_ (0x00000200)
270#define E2P_CMD_MAC_ADDR_LOADED_ (0x00000100)
271#define E2P_CMD_EPC_ADDR_ (0x000000FF)
272
273#define E2P_DATA (0xFC)
274#define E2P_DATA_EEPROM_DATA_ (0x000000FF)
275
276#endif /* _SMSC9420_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 09:58:07 -0500