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authorJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-05-20 23:43:09 -0400
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-08-12 03:21:56 -0400
commitf2148a472883ddf77626fff52b070655a8a0a788 (patch)
tree4224e4b1f7b7bbec8a5c5ebbd2ed1e2a69a89b9a /drivers/net/ethernet
parent527a626601de6ff89859de90883cc546892bf3ca (diff)
via-*: Move the VIA drivers
Move the VIA drivers into drivers/net/ethernet/via/ and make the necessary Kconfig and Makefile changes. CC: Roger Luethi <rl@hellgate.ch> CC: Francois Romieu <romieu@fr.zoreil.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ethernet')
-rw-r--r--drivers/net/ethernet/Kconfig1
-rw-r--r--drivers/net/ethernet/Makefile1
-rw-r--r--drivers/net/ethernet/via/Kconfig56
-rw-r--r--drivers/net/ethernet/via/Makefile6
-rw-r--r--drivers/net/ethernet/via/via-rhine.c2340
-rw-r--r--drivers/net/ethernet/via/via-velocity.c3592
-rw-r--r--drivers/net/ethernet/via/via-velocity.h1579
7 files changed, 7575 insertions, 0 deletions
diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
index 1c447d96d7e5..bdc0df873daf 100644
--- a/drivers/net/ethernet/Kconfig
+++ b/drivers/net/ethernet/Kconfig
@@ -45,5 +45,6 @@ source "drivers/net/ethernet/smsc/Kconfig"
45source "drivers/net/ethernet/stmicro/Kconfig" 45source "drivers/net/ethernet/stmicro/Kconfig"
46source "drivers/net/ethernet/sun/Kconfig" 46source "drivers/net/ethernet/sun/Kconfig"
47source "drivers/net/ethernet/tehuti/Kconfig" 47source "drivers/net/ethernet/tehuti/Kconfig"
48source "drivers/net/ethernet/via/Kconfig"
48 49
49endif # ETHERNET 50endif # ETHERNET
diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
index 48c8656b96c2..ac60ac9026bb 100644
--- a/drivers/net/ethernet/Makefile
+++ b/drivers/net/ethernet/Makefile
@@ -36,3 +36,4 @@ obj-$(CONFIG_NET_VENDOR_SMSC) += smsc/
36obj-$(CONFIG_NET_VENDOR_STMICRO) += stmicro/ 36obj-$(CONFIG_NET_VENDOR_STMICRO) += stmicro/
37obj-$(CONFIG_NET_VENDOR_SUN) += sun/ 37obj-$(CONFIG_NET_VENDOR_SUN) += sun/
38obj-$(CONFIG_NET_VENDOR_TEHUTI) += tehuti/ 38obj-$(CONFIG_NET_VENDOR_TEHUTI) += tehuti/
39obj-$(CONFIG_NET_VENDOR_VIA) += via/
diff --git a/drivers/net/ethernet/via/Kconfig b/drivers/net/ethernet/via/Kconfig
new file mode 100644
index 000000000000..7199194fa898
--- /dev/null
+++ b/drivers/net/ethernet/via/Kconfig
@@ -0,0 +1,56 @@
1#
2# VIA device configuration
3#
4
5config NET_VENDOR_VIA
6 bool "VIA devices"
7 depends on PCI
8 ---help---
9 If you have a network (Ethernet) card belonging to this class, say Y
10 and read the Ethernet-HOWTO, available from
11 <http://www.tldp.org/docs.html#howto>.
12
13 Note that the answer to this question doesn't directly affect the
14 kernel: saying N will just cause the configurator to skip all
15 the questions about VIA devices. If you say Y, you will be asked for
16 your specific card in the following questions.
17
18if NET_VENDOR_VIA
19
20config VIA_RHINE
21 tristate "VIA Rhine support"
22 depends on PCI
23 select CRC32
24 select MII
25 ---help---
26 If you have a VIA "Rhine" based network card (Rhine-I (VT86C100A),
27 Rhine-II (VT6102), or Rhine-III (VT6105)), say Y here. Rhine-type
28 Ethernet functions can also be found integrated on South Bridges
29 (e.g. VT8235).
30
31 To compile this driver as a module, choose M here. The module
32 will be called via-rhine.
33
34config VIA_RHINE_MMIO
35 bool "Use MMIO instead of PIO"
36 depends on VIA_RHINE
37 ---help---
38 This instructs the driver to use PCI shared memory (MMIO) instead of
39 programmed I/O ports (PIO). Enabling this gives an improvement in
40 processing time in parts of the driver.
41
42 If unsure, say Y.
43
44config VIA_VELOCITY
45 tristate "VIA Velocity support"
46 depends on PCI
47 select CRC32
48 select CRC_CCITT
49 select MII
50 ---help---
51 If you have a VIA "Velocity" based network card say Y here.
52
53 To compile this driver as a module, choose M here. The module
54 will be called via-velocity.
55
56endif # NET_VENDOR_VIA
diff --git a/drivers/net/ethernet/via/Makefile b/drivers/net/ethernet/via/Makefile
new file mode 100644
index 000000000000..46c5d4a3d8f1
--- /dev/null
+++ b/drivers/net/ethernet/via/Makefile
@@ -0,0 +1,6 @@
1#
2# Makefile for the VIA device drivers.
3#
4
5obj-$(CONFIG_VIA_RHINE) += via-rhine.o
6obj-$(CONFIG_VIA_VELOCITY) += via-velocity.o
diff --git a/drivers/net/ethernet/via/via-rhine.c b/drivers/net/ethernet/via/via-rhine.c
new file mode 100644
index 000000000000..7f23ab913fd9
--- /dev/null
+++ b/drivers/net/ethernet/via/via-rhine.c
@@ -0,0 +1,2340 @@
1/* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */
2/*
3 Written 1998-2001 by Donald Becker.
4
5 Current Maintainer: Roger Luethi <rl@hellgate.ch>
6
7 This software may be used and distributed according to the terms of
8 the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on or derived from this code fall under the GPL and must
10 retain the authorship, copyright and license notice. This file is not
11 a complete program and may only be used when the entire operating
12 system is licensed under the GPL.
13
14 This driver is designed for the VIA VT86C100A Rhine-I.
15 It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM
16 and management NIC 6105M).
17
18 The author may be reached as becker@scyld.com, or C/O
19 Scyld Computing Corporation
20 410 Severn Ave., Suite 210
21 Annapolis MD 21403
22
23
24 This driver contains some changes from the original Donald Becker
25 version. He may or may not be interested in bug reports on this
26 code. You can find his versions at:
27 http://www.scyld.com/network/via-rhine.html
28 [link no longer provides useful info -jgarzik]
29
30*/
31
32#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
33
34#define DRV_NAME "via-rhine"
35#define DRV_VERSION "1.5.0"
36#define DRV_RELDATE "2010-10-09"
37
38
39/* A few user-configurable values.
40 These may be modified when a driver module is loaded. */
41
42#define DEBUG
43static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
44static int max_interrupt_work = 20;
45
46/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
47 Setting to > 1518 effectively disables this feature. */
48#if defined(__alpha__) || defined(__arm__) || defined(__hppa__) || \
49 defined(CONFIG_SPARC) || defined(__ia64__) || \
50 defined(__sh__) || defined(__mips__)
51static int rx_copybreak = 1518;
52#else
53static int rx_copybreak;
54#endif
55
56/* Work-around for broken BIOSes: they are unable to get the chip back out of
57 power state D3 so PXE booting fails. bootparam(7): via-rhine.avoid_D3=1 */
58static int avoid_D3;
59
60/*
61 * In case you are looking for 'options[]' or 'full_duplex[]', they
62 * are gone. Use ethtool(8) instead.
63 */
64
65/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
66 The Rhine has a 64 element 8390-like hash table. */
67static const int multicast_filter_limit = 32;
68
69
70/* Operational parameters that are set at compile time. */
71
72/* Keep the ring sizes a power of two for compile efficiency.
73 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
74 Making the Tx ring too large decreases the effectiveness of channel
75 bonding and packet priority.
76 There are no ill effects from too-large receive rings. */
77#define TX_RING_SIZE 16
78#define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
79#define RX_RING_SIZE 64
80
81/* Operational parameters that usually are not changed. */
82
83/* Time in jiffies before concluding the transmitter is hung. */
84#define TX_TIMEOUT (2*HZ)
85
86#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
87
88#include <linux/module.h>
89#include <linux/moduleparam.h>
90#include <linux/kernel.h>
91#include <linux/string.h>
92#include <linux/timer.h>
93#include <linux/errno.h>
94#include <linux/ioport.h>
95#include <linux/interrupt.h>
96#include <linux/pci.h>
97#include <linux/dma-mapping.h>
98#include <linux/netdevice.h>
99#include <linux/etherdevice.h>
100#include <linux/skbuff.h>
101#include <linux/init.h>
102#include <linux/delay.h>
103#include <linux/mii.h>
104#include <linux/ethtool.h>
105#include <linux/crc32.h>
106#include <linux/if_vlan.h>
107#include <linux/bitops.h>
108#include <linux/workqueue.h>
109#include <asm/processor.h> /* Processor type for cache alignment. */
110#include <asm/io.h>
111#include <asm/irq.h>
112#include <asm/uaccess.h>
113#include <linux/dmi.h>
114
115/* These identify the driver base version and may not be removed. */
116static const char version[] __devinitconst =
117 "v1.10-LK" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker";
118
119/* This driver was written to use PCI memory space. Some early versions
120 of the Rhine may only work correctly with I/O space accesses. */
121#ifdef CONFIG_VIA_RHINE_MMIO
122#define USE_MMIO
123#else
124#endif
125
126MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
127MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver");
128MODULE_LICENSE("GPL");
129
130module_param(max_interrupt_work, int, 0);
131module_param(debug, int, 0);
132module_param(rx_copybreak, int, 0);
133module_param(avoid_D3, bool, 0);
134MODULE_PARM_DESC(max_interrupt_work, "VIA Rhine maximum events handled per interrupt");
135MODULE_PARM_DESC(debug, "VIA Rhine debug level (0-7)");
136MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames");
137MODULE_PARM_DESC(avoid_D3, "Avoid power state D3 (work-around for broken BIOSes)");
138
139#define MCAM_SIZE 32
140#define VCAM_SIZE 32
141
142/*
143 Theory of Operation
144
145I. Board Compatibility
146
147This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet
148controller.
149
150II. Board-specific settings
151
152Boards with this chip are functional only in a bus-master PCI slot.
153
154Many operational settings are loaded from the EEPROM to the Config word at
155offset 0x78. For most of these settings, this driver assumes that they are
156correct.
157If this driver is compiled to use PCI memory space operations the EEPROM
158must be configured to enable memory ops.
159
160III. Driver operation
161
162IIIa. Ring buffers
163
164This driver uses two statically allocated fixed-size descriptor lists
165formed into rings by a branch from the final descriptor to the beginning of
166the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
167
168IIIb/c. Transmit/Receive Structure
169
170This driver attempts to use a zero-copy receive and transmit scheme.
171
172Alas, all data buffers are required to start on a 32 bit boundary, so
173the driver must often copy transmit packets into bounce buffers.
174
175The driver allocates full frame size skbuffs for the Rx ring buffers at
176open() time and passes the skb->data field to the chip as receive data
177buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
178a fresh skbuff is allocated and the frame is copied to the new skbuff.
179When the incoming frame is larger, the skbuff is passed directly up the
180protocol stack. Buffers consumed this way are replaced by newly allocated
181skbuffs in the last phase of rhine_rx().
182
183The RX_COPYBREAK value is chosen to trade-off the memory wasted by
184using a full-sized skbuff for small frames vs. the copying costs of larger
185frames. New boards are typically used in generously configured machines
186and the underfilled buffers have negligible impact compared to the benefit of
187a single allocation size, so the default value of zero results in never
188copying packets. When copying is done, the cost is usually mitigated by using
189a combined copy/checksum routine. Copying also preloads the cache, which is
190most useful with small frames.
191
192Since the VIA chips are only able to transfer data to buffers on 32 bit
193boundaries, the IP header at offset 14 in an ethernet frame isn't
194longword aligned for further processing. Copying these unaligned buffers
195has the beneficial effect of 16-byte aligning the IP header.
196
197IIId. Synchronization
198
199The driver runs as two independent, single-threaded flows of control. One
200is the send-packet routine, which enforces single-threaded use by the
201netdev_priv(dev)->lock spinlock. The other thread is the interrupt handler,
202which is single threaded by the hardware and interrupt handling software.
203
204The send packet thread has partial control over the Tx ring. It locks the
205netdev_priv(dev)->lock whenever it's queuing a Tx packet. If the next slot in
206the ring is not available it stops the transmit queue by
207calling netif_stop_queue.
208
209The interrupt handler has exclusive control over the Rx ring and records stats
210from the Tx ring. After reaping the stats, it marks the Tx queue entry as
211empty by incrementing the dirty_tx mark. If at least half of the entries in
212the Rx ring are available the transmit queue is woken up if it was stopped.
213
214IV. Notes
215
216IVb. References
217
218Preliminary VT86C100A manual from http://www.via.com.tw/
219http://www.scyld.com/expert/100mbps.html
220http://www.scyld.com/expert/NWay.html
221ftp://ftp.via.com.tw/public/lan/Products/NIC/VT86C100A/Datasheet/VT86C100A03.pdf
222ftp://ftp.via.com.tw/public/lan/Products/NIC/VT6102/Datasheet/VT6102_021.PDF
223
224
225IVc. Errata
226
227The VT86C100A manual is not reliable information.
228The 3043 chip does not handle unaligned transmit or receive buffers, resulting
229in significant performance degradation for bounce buffer copies on transmit
230and unaligned IP headers on receive.
231The chip does not pad to minimum transmit length.
232
233*/
234
235
236/* This table drives the PCI probe routines. It's mostly boilerplate in all
237 of the drivers, and will likely be provided by some future kernel.
238 Note the matching code -- the first table entry matchs all 56** cards but
239 second only the 1234 card.
240*/
241
242enum rhine_revs {
243 VT86C100A = 0x00,
244 VTunknown0 = 0x20,
245 VT6102 = 0x40,
246 VT8231 = 0x50, /* Integrated MAC */
247 VT8233 = 0x60, /* Integrated MAC */
248 VT8235 = 0x74, /* Integrated MAC */
249 VT8237 = 0x78, /* Integrated MAC */
250 VTunknown1 = 0x7C,
251 VT6105 = 0x80,
252 VT6105_B0 = 0x83,
253 VT6105L = 0x8A,
254 VT6107 = 0x8C,
255 VTunknown2 = 0x8E,
256 VT6105M = 0x90, /* Management adapter */
257};
258
259enum rhine_quirks {
260 rqWOL = 0x0001, /* Wake-On-LAN support */
261 rqForceReset = 0x0002,
262 rq6patterns = 0x0040, /* 6 instead of 4 patterns for WOL */
263 rqStatusWBRace = 0x0080, /* Tx Status Writeback Error possible */
264 rqRhineI = 0x0100, /* See comment below */
265};
266/*
267 * rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable
268 * MMIO as well as for the collision counter and the Tx FIFO underflow
269 * indicator. In addition, Tx and Rx buffers need to 4 byte aligned.
270 */
271
272/* Beware of PCI posted writes */
273#define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0)
274
275static DEFINE_PCI_DEVICE_TABLE(rhine_pci_tbl) = {
276 { 0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, }, /* VT86C100A */
277 { 0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6102 */
278 { 0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, }, /* 6105{,L,LOM} */
279 { 0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6105M */
280 { } /* terminate list */
281};
282MODULE_DEVICE_TABLE(pci, rhine_pci_tbl);
283
284
285/* Offsets to the device registers. */
286enum register_offsets {
287 StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,
288 ChipCmd1=0x09, TQWake=0x0A,
289 IntrStatus=0x0C, IntrEnable=0x0E,
290 MulticastFilter0=0x10, MulticastFilter1=0x14,
291 RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,
292 MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E, PCIBusConfig1=0x6F,
293 MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,
294 ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,
295 RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,
296 StickyHW=0x83, IntrStatus2=0x84,
297 CamMask=0x88, CamCon=0x92, CamAddr=0x93,
298 WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4,
299 WOLcrClr1=0xA6, WOLcgClr=0xA7,
300 PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD,
301};
302
303/* Bits in ConfigD */
304enum backoff_bits {
305 BackOptional=0x01, BackModify=0x02,
306 BackCaptureEffect=0x04, BackRandom=0x08
307};
308
309/* Bits in the TxConfig (TCR) register */
310enum tcr_bits {
311 TCR_PQEN=0x01,
312 TCR_LB0=0x02, /* loopback[0] */
313 TCR_LB1=0x04, /* loopback[1] */
314 TCR_OFSET=0x08,
315 TCR_RTGOPT=0x10,
316 TCR_RTFT0=0x20,
317 TCR_RTFT1=0x40,
318 TCR_RTSF=0x80,
319};
320
321/* Bits in the CamCon (CAMC) register */
322enum camcon_bits {
323 CAMC_CAMEN=0x01,
324 CAMC_VCAMSL=0x02,
325 CAMC_CAMWR=0x04,
326 CAMC_CAMRD=0x08,
327};
328
329/* Bits in the PCIBusConfig1 (BCR1) register */
330enum bcr1_bits {
331 BCR1_POT0=0x01,
332 BCR1_POT1=0x02,
333 BCR1_POT2=0x04,
334 BCR1_CTFT0=0x08,
335 BCR1_CTFT1=0x10,
336 BCR1_CTSF=0x20,
337 BCR1_TXQNOBK=0x40, /* for VT6105 */
338 BCR1_VIDFR=0x80, /* for VT6105 */
339 BCR1_MED0=0x40, /* for VT6102 */
340 BCR1_MED1=0x80, /* for VT6102 */
341};
342
343#ifdef USE_MMIO
344/* Registers we check that mmio and reg are the same. */
345static const int mmio_verify_registers[] = {
346 RxConfig, TxConfig, IntrEnable, ConfigA, ConfigB, ConfigC, ConfigD,
347 0
348};
349#endif
350
351/* Bits in the interrupt status/mask registers. */
352enum intr_status_bits {
353 IntrRxDone=0x0001, IntrRxErr=0x0004, IntrRxEmpty=0x0020,
354 IntrTxDone=0x0002, IntrTxError=0x0008, IntrTxUnderrun=0x0210,
355 IntrPCIErr=0x0040,
356 IntrStatsMax=0x0080, IntrRxEarly=0x0100,
357 IntrRxOverflow=0x0400, IntrRxDropped=0x0800, IntrRxNoBuf=0x1000,
358 IntrTxAborted=0x2000, IntrLinkChange=0x4000,
359 IntrRxWakeUp=0x8000,
360 IntrNormalSummary=0x0003, IntrAbnormalSummary=0xC260,
361 IntrTxDescRace=0x080000, /* mapped from IntrStatus2 */
362 IntrTxErrSummary=0x082218,
363};
364
365/* Bits in WOLcrSet/WOLcrClr and PwrcsrSet/PwrcsrClr */
366enum wol_bits {
367 WOLucast = 0x10,
368 WOLmagic = 0x20,
369 WOLbmcast = 0x30,
370 WOLlnkon = 0x40,
371 WOLlnkoff = 0x80,
372};
373
374/* The Rx and Tx buffer descriptors. */
375struct rx_desc {
376 __le32 rx_status;
377 __le32 desc_length; /* Chain flag, Buffer/frame length */
378 __le32 addr;
379 __le32 next_desc;
380};
381struct tx_desc {
382 __le32 tx_status;
383 __le32 desc_length; /* Chain flag, Tx Config, Frame length */
384 __le32 addr;
385 __le32 next_desc;
386};
387
388/* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */
389#define TXDESC 0x00e08000
390
391enum rx_status_bits {
392 RxOK=0x8000, RxWholePkt=0x0300, RxErr=0x008F
393};
394
395/* Bits in *_desc.*_status */
396enum desc_status_bits {
397 DescOwn=0x80000000
398};
399
400/* Bits in *_desc.*_length */
401enum desc_length_bits {
402 DescTag=0x00010000
403};
404
405/* Bits in ChipCmd. */
406enum chip_cmd_bits {
407 CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08,
408 CmdTxOn=0x10, Cmd1TxDemand=0x20, CmdRxDemand=0x40,
409 Cmd1EarlyRx=0x01, Cmd1EarlyTx=0x02, Cmd1FDuplex=0x04,
410 Cmd1NoTxPoll=0x08, Cmd1Reset=0x80,
411};
412
413struct rhine_private {
414 /* Bit mask for configured VLAN ids */
415 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
416
417 /* Descriptor rings */
418 struct rx_desc *rx_ring;
419 struct tx_desc *tx_ring;
420 dma_addr_t rx_ring_dma;
421 dma_addr_t tx_ring_dma;
422
423 /* The addresses of receive-in-place skbuffs. */
424 struct sk_buff *rx_skbuff[RX_RING_SIZE];
425 dma_addr_t rx_skbuff_dma[RX_RING_SIZE];
426
427 /* The saved address of a sent-in-place packet/buffer, for later free(). */
428 struct sk_buff *tx_skbuff[TX_RING_SIZE];
429 dma_addr_t tx_skbuff_dma[TX_RING_SIZE];
430
431 /* Tx bounce buffers (Rhine-I only) */
432 unsigned char *tx_buf[TX_RING_SIZE];
433 unsigned char *tx_bufs;
434 dma_addr_t tx_bufs_dma;
435
436 struct pci_dev *pdev;
437 long pioaddr;
438 struct net_device *dev;
439 struct napi_struct napi;
440 spinlock_t lock;
441 struct work_struct reset_task;
442
443 /* Frequently used values: keep some adjacent for cache effect. */
444 u32 quirks;
445 struct rx_desc *rx_head_desc;
446 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
447 unsigned int cur_tx, dirty_tx;
448 unsigned int rx_buf_sz; /* Based on MTU+slack. */
449 u8 wolopts;
450
451 u8 tx_thresh, rx_thresh;
452
453 struct mii_if_info mii_if;
454 void __iomem *base;
455};
456
457#define BYTE_REG_BITS_ON(x, p) do { iowrite8((ioread8((p))|(x)), (p)); } while (0)
458#define WORD_REG_BITS_ON(x, p) do { iowrite16((ioread16((p))|(x)), (p)); } while (0)
459#define DWORD_REG_BITS_ON(x, p) do { iowrite32((ioread32((p))|(x)), (p)); } while (0)
460
461#define BYTE_REG_BITS_IS_ON(x, p) (ioread8((p)) & (x))
462#define WORD_REG_BITS_IS_ON(x, p) (ioread16((p)) & (x))
463#define DWORD_REG_BITS_IS_ON(x, p) (ioread32((p)) & (x))
464
465#define BYTE_REG_BITS_OFF(x, p) do { iowrite8(ioread8((p)) & (~(x)), (p)); } while (0)
466#define WORD_REG_BITS_OFF(x, p) do { iowrite16(ioread16((p)) & (~(x)), (p)); } while (0)
467#define DWORD_REG_BITS_OFF(x, p) do { iowrite32(ioread32((p)) & (~(x)), (p)); } while (0)
468
469#define BYTE_REG_BITS_SET(x, m, p) do { iowrite8((ioread8((p)) & (~(m)))|(x), (p)); } while (0)
470#define WORD_REG_BITS_SET(x, m, p) do { iowrite16((ioread16((p)) & (~(m)))|(x), (p)); } while (0)
471#define DWORD_REG_BITS_SET(x, m, p) do { iowrite32((ioread32((p)) & (~(m)))|(x), (p)); } while (0)
472
473
474static int mdio_read(struct net_device *dev, int phy_id, int location);
475static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
476static int rhine_open(struct net_device *dev);
477static void rhine_reset_task(struct work_struct *work);
478static void rhine_tx_timeout(struct net_device *dev);
479static netdev_tx_t rhine_start_tx(struct sk_buff *skb,
480 struct net_device *dev);
481static irqreturn_t rhine_interrupt(int irq, void *dev_instance);
482static void rhine_tx(struct net_device *dev);
483static int rhine_rx(struct net_device *dev, int limit);
484static void rhine_error(struct net_device *dev, int intr_status);
485static void rhine_set_rx_mode(struct net_device *dev);
486static struct net_device_stats *rhine_get_stats(struct net_device *dev);
487static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
488static const struct ethtool_ops netdev_ethtool_ops;
489static int rhine_close(struct net_device *dev);
490static void rhine_shutdown (struct pci_dev *pdev);
491static void rhine_vlan_rx_add_vid(struct net_device *dev, unsigned short vid);
492static void rhine_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid);
493static void rhine_set_cam(void __iomem *ioaddr, int idx, u8 *addr);
494static void rhine_set_vlan_cam(void __iomem *ioaddr, int idx, u8 *addr);
495static void rhine_set_cam_mask(void __iomem *ioaddr, u32 mask);
496static void rhine_set_vlan_cam_mask(void __iomem *ioaddr, u32 mask);
497static void rhine_init_cam_filter(struct net_device *dev);
498static void rhine_update_vcam(struct net_device *dev);
499
500#define RHINE_WAIT_FOR(condition) \
501do { \
502 int i = 1024; \
503 while (!(condition) && --i) \
504 ; \
505 if (debug > 1 && i < 512) \
506 pr_info("%4d cycles used @ %s:%d\n", \
507 1024 - i, __func__, __LINE__); \
508} while (0)
509
510static inline u32 get_intr_status(struct net_device *dev)
511{
512 struct rhine_private *rp = netdev_priv(dev);
513 void __iomem *ioaddr = rp->base;
514 u32 intr_status;
515
516 intr_status = ioread16(ioaddr + IntrStatus);
517 /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
518 if (rp->quirks & rqStatusWBRace)
519 intr_status |= ioread8(ioaddr + IntrStatus2) << 16;
520 return intr_status;
521}
522
523/*
524 * Get power related registers into sane state.
525 * Notify user about past WOL event.
526 */
527static void rhine_power_init(struct net_device *dev)
528{
529 struct rhine_private *rp = netdev_priv(dev);
530 void __iomem *ioaddr = rp->base;
531 u16 wolstat;
532
533 if (rp->quirks & rqWOL) {
534 /* Make sure chip is in power state D0 */
535 iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW);
536
537 /* Disable "force PME-enable" */
538 iowrite8(0x80, ioaddr + WOLcgClr);
539
540 /* Clear power-event config bits (WOL) */
541 iowrite8(0xFF, ioaddr + WOLcrClr);
542 /* More recent cards can manage two additional patterns */
543 if (rp->quirks & rq6patterns)
544 iowrite8(0x03, ioaddr + WOLcrClr1);
545
546 /* Save power-event status bits */
547 wolstat = ioread8(ioaddr + PwrcsrSet);
548 if (rp->quirks & rq6patterns)
549 wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8;
550
551 /* Clear power-event status bits */
552 iowrite8(0xFF, ioaddr + PwrcsrClr);
553 if (rp->quirks & rq6patterns)
554 iowrite8(0x03, ioaddr + PwrcsrClr1);
555
556 if (wolstat) {
557 char *reason;
558 switch (wolstat) {
559 case WOLmagic:
560 reason = "Magic packet";
561 break;
562 case WOLlnkon:
563 reason = "Link went up";
564 break;
565 case WOLlnkoff:
566 reason = "Link went down";
567 break;
568 case WOLucast:
569 reason = "Unicast packet";
570 break;
571 case WOLbmcast:
572 reason = "Multicast/broadcast packet";
573 break;
574 default:
575 reason = "Unknown";
576 }
577 netdev_info(dev, "Woke system up. Reason: %s\n",
578 reason);
579 }
580 }
581}
582
583static void rhine_chip_reset(struct net_device *dev)
584{
585 struct rhine_private *rp = netdev_priv(dev);
586 void __iomem *ioaddr = rp->base;
587
588 iowrite8(Cmd1Reset, ioaddr + ChipCmd1);
589 IOSYNC;
590
591 if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) {
592 netdev_info(dev, "Reset not complete yet. Trying harder.\n");
593
594 /* Force reset */
595 if (rp->quirks & rqForceReset)
596 iowrite8(0x40, ioaddr + MiscCmd);
597
598 /* Reset can take somewhat longer (rare) */
599 RHINE_WAIT_FOR(!(ioread8(ioaddr + ChipCmd1) & Cmd1Reset));
600 }
601
602 if (debug > 1)
603 netdev_info(dev, "Reset %s\n",
604 (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) ?
605 "failed" : "succeeded");
606}
607
608#ifdef USE_MMIO
609static void enable_mmio(long pioaddr, u32 quirks)
610{
611 int n;
612 if (quirks & rqRhineI) {
613 /* More recent docs say that this bit is reserved ... */
614 n = inb(pioaddr + ConfigA) | 0x20;
615 outb(n, pioaddr + ConfigA);
616 } else {
617 n = inb(pioaddr + ConfigD) | 0x80;
618 outb(n, pioaddr + ConfigD);
619 }
620}
621#endif
622
623/*
624 * Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM
625 * (plus 0x6C for Rhine-I/II)
626 */
627static void __devinit rhine_reload_eeprom(long pioaddr, struct net_device *dev)
628{
629 struct rhine_private *rp = netdev_priv(dev);
630 void __iomem *ioaddr = rp->base;
631
632 outb(0x20, pioaddr + MACRegEEcsr);
633 RHINE_WAIT_FOR(!(inb(pioaddr + MACRegEEcsr) & 0x20));
634
635#ifdef USE_MMIO
636 /*
637 * Reloading from EEPROM overwrites ConfigA-D, so we must re-enable
638 * MMIO. If reloading EEPROM was done first this could be avoided, but
639 * it is not known if that still works with the "win98-reboot" problem.
640 */
641 enable_mmio(pioaddr, rp->quirks);
642#endif
643
644 /* Turn off EEPROM-controlled wake-up (magic packet) */
645 if (rp->quirks & rqWOL)
646 iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA);
647
648}
649
650#ifdef CONFIG_NET_POLL_CONTROLLER
651static void rhine_poll(struct net_device *dev)
652{
653 disable_irq(dev->irq);
654 rhine_interrupt(dev->irq, (void *)dev);
655 enable_irq(dev->irq);
656}
657#endif
658
659static int rhine_napipoll(struct napi_struct *napi, int budget)
660{
661 struct rhine_private *rp = container_of(napi, struct rhine_private, napi);
662 struct net_device *dev = rp->dev;
663 void __iomem *ioaddr = rp->base;
664 int work_done;
665
666 work_done = rhine_rx(dev, budget);
667
668 if (work_done < budget) {
669 napi_complete(napi);
670
671 iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |
672 IntrRxDropped | IntrRxNoBuf | IntrTxAborted |
673 IntrTxDone | IntrTxError | IntrTxUnderrun |
674 IntrPCIErr | IntrStatsMax | IntrLinkChange,
675 ioaddr + IntrEnable);
676 }
677 return work_done;
678}
679
680static void __devinit rhine_hw_init(struct net_device *dev, long pioaddr)
681{
682 struct rhine_private *rp = netdev_priv(dev);
683
684 /* Reset the chip to erase previous misconfiguration. */
685 rhine_chip_reset(dev);
686
687 /* Rhine-I needs extra time to recuperate before EEPROM reload */
688 if (rp->quirks & rqRhineI)
689 msleep(5);
690
691 /* Reload EEPROM controlled bytes cleared by soft reset */
692 rhine_reload_eeprom(pioaddr, dev);
693}
694
695static const struct net_device_ops rhine_netdev_ops = {
696 .ndo_open = rhine_open,
697 .ndo_stop = rhine_close,
698 .ndo_start_xmit = rhine_start_tx,
699 .ndo_get_stats = rhine_get_stats,
700 .ndo_set_multicast_list = rhine_set_rx_mode,
701 .ndo_change_mtu = eth_change_mtu,
702 .ndo_validate_addr = eth_validate_addr,
703 .ndo_set_mac_address = eth_mac_addr,
704 .ndo_do_ioctl = netdev_ioctl,
705 .ndo_tx_timeout = rhine_tx_timeout,
706 .ndo_vlan_rx_add_vid = rhine_vlan_rx_add_vid,
707 .ndo_vlan_rx_kill_vid = rhine_vlan_rx_kill_vid,
708#ifdef CONFIG_NET_POLL_CONTROLLER
709 .ndo_poll_controller = rhine_poll,
710#endif
711};
712
713static int __devinit rhine_init_one(struct pci_dev *pdev,
714 const struct pci_device_id *ent)
715{
716 struct net_device *dev;
717 struct rhine_private *rp;
718 int i, rc;
719 u32 quirks;
720 long pioaddr;
721 long memaddr;
722 void __iomem *ioaddr;
723 int io_size, phy_id;
724 const char *name;
725#ifdef USE_MMIO
726 int bar = 1;
727#else
728 int bar = 0;
729#endif
730
731/* when built into the kernel, we only print version if device is found */
732#ifndef MODULE
733 pr_info_once("%s\n", version);
734#endif
735
736 io_size = 256;
737 phy_id = 0;
738 quirks = 0;
739 name = "Rhine";
740 if (pdev->revision < VTunknown0) {
741 quirks = rqRhineI;
742 io_size = 128;
743 }
744 else if (pdev->revision >= VT6102) {
745 quirks = rqWOL | rqForceReset;
746 if (pdev->revision < VT6105) {
747 name = "Rhine II";
748 quirks |= rqStatusWBRace; /* Rhine-II exclusive */
749 }
750 else {
751 phy_id = 1; /* Integrated PHY, phy_id fixed to 1 */
752 if (pdev->revision >= VT6105_B0)
753 quirks |= rq6patterns;
754 if (pdev->revision < VT6105M)
755 name = "Rhine III";
756 else
757 name = "Rhine III (Management Adapter)";
758 }
759 }
760
761 rc = pci_enable_device(pdev);
762 if (rc)
763 goto err_out;
764
765 /* this should always be supported */
766 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
767 if (rc) {
768 dev_err(&pdev->dev,
769 "32-bit PCI DMA addresses not supported by the card!?\n");
770 goto err_out;
771 }
772
773 /* sanity check */
774 if ((pci_resource_len(pdev, 0) < io_size) ||
775 (pci_resource_len(pdev, 1) < io_size)) {
776 rc = -EIO;
777 dev_err(&pdev->dev, "Insufficient PCI resources, aborting\n");
778 goto err_out;
779 }
780
781 pioaddr = pci_resource_start(pdev, 0);
782 memaddr = pci_resource_start(pdev, 1);
783
784 pci_set_master(pdev);
785
786 dev = alloc_etherdev(sizeof(struct rhine_private));
787 if (!dev) {
788 rc = -ENOMEM;
789 dev_err(&pdev->dev, "alloc_etherdev failed\n");
790 goto err_out;
791 }
792 SET_NETDEV_DEV(dev, &pdev->dev);
793
794 rp = netdev_priv(dev);
795 rp->dev = dev;
796 rp->quirks = quirks;
797 rp->pioaddr = pioaddr;
798 rp->pdev = pdev;
799
800 rc = pci_request_regions(pdev, DRV_NAME);
801 if (rc)
802 goto err_out_free_netdev;
803
804 ioaddr = pci_iomap(pdev, bar, io_size);
805 if (!ioaddr) {
806 rc = -EIO;
807 dev_err(&pdev->dev,
808 "ioremap failed for device %s, region 0x%X @ 0x%lX\n",
809 pci_name(pdev), io_size, memaddr);
810 goto err_out_free_res;
811 }
812
813#ifdef USE_MMIO
814 enable_mmio(pioaddr, quirks);
815
816 /* Check that selected MMIO registers match the PIO ones */
817 i = 0;
818 while (mmio_verify_registers[i]) {
819 int reg = mmio_verify_registers[i++];
820 unsigned char a = inb(pioaddr+reg);
821 unsigned char b = readb(ioaddr+reg);
822 if (a != b) {
823 rc = -EIO;
824 dev_err(&pdev->dev,
825 "MMIO do not match PIO [%02x] (%02x != %02x)\n",
826 reg, a, b);
827 goto err_out_unmap;
828 }
829 }
830#endif /* USE_MMIO */
831
832 dev->base_addr = (unsigned long)ioaddr;
833 rp->base = ioaddr;
834
835 /* Get chip registers into a sane state */
836 rhine_power_init(dev);
837 rhine_hw_init(dev, pioaddr);
838
839 for (i = 0; i < 6; i++)
840 dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i);
841
842 if (!is_valid_ether_addr(dev->dev_addr)) {
843 /* Report it and use a random ethernet address instead */
844 netdev_err(dev, "Invalid MAC address: %pM\n", dev->dev_addr);
845 random_ether_addr(dev->dev_addr);
846 netdev_info(dev, "Using random MAC address: %pM\n",
847 dev->dev_addr);
848 }
849 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
850
851 /* For Rhine-I/II, phy_id is loaded from EEPROM */
852 if (!phy_id)
853 phy_id = ioread8(ioaddr + 0x6C);
854
855 dev->irq = pdev->irq;
856
857 spin_lock_init(&rp->lock);
858 INIT_WORK(&rp->reset_task, rhine_reset_task);
859
860 rp->mii_if.dev = dev;
861 rp->mii_if.mdio_read = mdio_read;
862 rp->mii_if.mdio_write = mdio_write;
863 rp->mii_if.phy_id_mask = 0x1f;
864 rp->mii_if.reg_num_mask = 0x1f;
865
866 /* The chip-specific entries in the device structure. */
867 dev->netdev_ops = &rhine_netdev_ops;
868 dev->ethtool_ops = &netdev_ethtool_ops,
869 dev->watchdog_timeo = TX_TIMEOUT;
870
871 netif_napi_add(dev, &rp->napi, rhine_napipoll, 64);
872
873 if (rp->quirks & rqRhineI)
874 dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;
875
876 if (pdev->revision >= VT6105M)
877 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX |
878 NETIF_F_HW_VLAN_FILTER;
879
880 /* dev->name not defined before register_netdev()! */
881 rc = register_netdev(dev);
882 if (rc)
883 goto err_out_unmap;
884
885 netdev_info(dev, "VIA %s at 0x%lx, %pM, IRQ %d\n",
886 name,
887#ifdef USE_MMIO
888 memaddr,
889#else
890 (long)ioaddr,
891#endif
892 dev->dev_addr, pdev->irq);
893
894 pci_set_drvdata(pdev, dev);
895
896 {
897 u16 mii_cmd;
898 int mii_status = mdio_read(dev, phy_id, 1);
899 mii_cmd = mdio_read(dev, phy_id, MII_BMCR) & ~BMCR_ISOLATE;
900 mdio_write(dev, phy_id, MII_BMCR, mii_cmd);
901 if (mii_status != 0xffff && mii_status != 0x0000) {
902 rp->mii_if.advertising = mdio_read(dev, phy_id, 4);
903 netdev_info(dev,
904 "MII PHY found at address %d, status 0x%04x advertising %04x Link %04x\n",
905 phy_id,
906 mii_status, rp->mii_if.advertising,
907 mdio_read(dev, phy_id, 5));
908
909 /* set IFF_RUNNING */
910 if (mii_status & BMSR_LSTATUS)
911 netif_carrier_on(dev);
912 else
913 netif_carrier_off(dev);
914
915 }
916 }
917 rp->mii_if.phy_id = phy_id;
918 if (debug > 1 && avoid_D3)
919 netdev_info(dev, "No D3 power state at shutdown\n");
920
921 return 0;
922
923err_out_unmap:
924 pci_iounmap(pdev, ioaddr);
925err_out_free_res:
926 pci_release_regions(pdev);
927err_out_free_netdev:
928 free_netdev(dev);
929err_out:
930 return rc;
931}
932
933static int alloc_ring(struct net_device* dev)
934{
935 struct rhine_private *rp = netdev_priv(dev);
936 void *ring;
937 dma_addr_t ring_dma;
938
939 ring = pci_alloc_consistent(rp->pdev,
940 RX_RING_SIZE * sizeof(struct rx_desc) +
941 TX_RING_SIZE * sizeof(struct tx_desc),
942 &ring_dma);
943 if (!ring) {
944 netdev_err(dev, "Could not allocate DMA memory\n");
945 return -ENOMEM;
946 }
947 if (rp->quirks & rqRhineI) {
948 rp->tx_bufs = pci_alloc_consistent(rp->pdev,
949 PKT_BUF_SZ * TX_RING_SIZE,
950 &rp->tx_bufs_dma);
951 if (rp->tx_bufs == NULL) {
952 pci_free_consistent(rp->pdev,
953 RX_RING_SIZE * sizeof(struct rx_desc) +
954 TX_RING_SIZE * sizeof(struct tx_desc),
955 ring, ring_dma);
956 return -ENOMEM;
957 }
958 }
959
960 rp->rx_ring = ring;
961 rp->tx_ring = ring + RX_RING_SIZE * sizeof(struct rx_desc);
962 rp->rx_ring_dma = ring_dma;
963 rp->tx_ring_dma = ring_dma + RX_RING_SIZE * sizeof(struct rx_desc);
964
965 return 0;
966}
967
968static void free_ring(struct net_device* dev)
969{
970 struct rhine_private *rp = netdev_priv(dev);
971
972 pci_free_consistent(rp->pdev,
973 RX_RING_SIZE * sizeof(struct rx_desc) +
974 TX_RING_SIZE * sizeof(struct tx_desc),
975 rp->rx_ring, rp->rx_ring_dma);
976 rp->tx_ring = NULL;
977
978 if (rp->tx_bufs)
979 pci_free_consistent(rp->pdev, PKT_BUF_SZ * TX_RING_SIZE,
980 rp->tx_bufs, rp->tx_bufs_dma);
981
982 rp->tx_bufs = NULL;
983
984}
985
986static void alloc_rbufs(struct net_device *dev)
987{
988 struct rhine_private *rp = netdev_priv(dev);
989 dma_addr_t next;
990 int i;
991
992 rp->dirty_rx = rp->cur_rx = 0;
993
994 rp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
995 rp->rx_head_desc = &rp->rx_ring[0];
996 next = rp->rx_ring_dma;
997
998 /* Init the ring entries */
999 for (i = 0; i < RX_RING_SIZE; i++) {
1000 rp->rx_ring[i].rx_status = 0;
1001 rp->rx_ring[i].desc_length = cpu_to_le32(rp->rx_buf_sz);
1002 next += sizeof(struct rx_desc);
1003 rp->rx_ring[i].next_desc = cpu_to_le32(next);
1004 rp->rx_skbuff[i] = NULL;
1005 }
1006 /* Mark the last entry as wrapping the ring. */
1007 rp->rx_ring[i-1].next_desc = cpu_to_le32(rp->rx_ring_dma);
1008
1009 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1010 for (i = 0; i < RX_RING_SIZE; i++) {
1011 struct sk_buff *skb = netdev_alloc_skb(dev, rp->rx_buf_sz);
1012 rp->rx_skbuff[i] = skb;
1013 if (skb == NULL)
1014 break;
1015 skb->dev = dev; /* Mark as being used by this device. */
1016
1017 rp->rx_skbuff_dma[i] =
1018 pci_map_single(rp->pdev, skb->data, rp->rx_buf_sz,
1019 PCI_DMA_FROMDEVICE);
1020
1021 rp->rx_ring[i].addr = cpu_to_le32(rp->rx_skbuff_dma[i]);
1022 rp->rx_ring[i].rx_status = cpu_to_le32(DescOwn);
1023 }
1024 rp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1025}
1026
1027static void free_rbufs(struct net_device* dev)
1028{
1029 struct rhine_private *rp = netdev_priv(dev);
1030 int i;
1031
1032 /* Free all the skbuffs in the Rx queue. */
1033 for (i = 0; i < RX_RING_SIZE; i++) {
1034 rp->rx_ring[i].rx_status = 0;
1035 rp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1036 if (rp->rx_skbuff[i]) {
1037 pci_unmap_single(rp->pdev,
1038 rp->rx_skbuff_dma[i],
1039 rp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1040 dev_kfree_skb(rp->rx_skbuff[i]);
1041 }
1042 rp->rx_skbuff[i] = NULL;
1043 }
1044}
1045
1046static void alloc_tbufs(struct net_device* dev)
1047{
1048 struct rhine_private *rp = netdev_priv(dev);
1049 dma_addr_t next;
1050 int i;
1051
1052 rp->dirty_tx = rp->cur_tx = 0;
1053 next = rp->tx_ring_dma;
1054 for (i = 0; i < TX_RING_SIZE; i++) {
1055 rp->tx_skbuff[i] = NULL;
1056 rp->tx_ring[i].tx_status = 0;
1057 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
1058 next += sizeof(struct tx_desc);
1059 rp->tx_ring[i].next_desc = cpu_to_le32(next);
1060 if (rp->quirks & rqRhineI)
1061 rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ];
1062 }
1063 rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma);
1064
1065}
1066
1067static void free_tbufs(struct net_device* dev)
1068{
1069 struct rhine_private *rp = netdev_priv(dev);
1070 int i;
1071
1072 for (i = 0; i < TX_RING_SIZE; i++) {
1073 rp->tx_ring[i].tx_status = 0;
1074 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
1075 rp->tx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1076 if (rp->tx_skbuff[i]) {
1077 if (rp->tx_skbuff_dma[i]) {
1078 pci_unmap_single(rp->pdev,
1079 rp->tx_skbuff_dma[i],
1080 rp->tx_skbuff[i]->len,
1081 PCI_DMA_TODEVICE);
1082 }
1083 dev_kfree_skb(rp->tx_skbuff[i]);
1084 }
1085 rp->tx_skbuff[i] = NULL;
1086 rp->tx_buf[i] = NULL;
1087 }
1088}
1089
1090static void rhine_check_media(struct net_device *dev, unsigned int init_media)
1091{
1092 struct rhine_private *rp = netdev_priv(dev);
1093 void __iomem *ioaddr = rp->base;
1094
1095 mii_check_media(&rp->mii_if, debug, init_media);
1096
1097 if (rp->mii_if.full_duplex)
1098 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex,
1099 ioaddr + ChipCmd1);
1100 else
1101 iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex,
1102 ioaddr + ChipCmd1);
1103 if (debug > 1)
1104 netdev_info(dev, "force_media %d, carrier %d\n",
1105 rp->mii_if.force_media, netif_carrier_ok(dev));
1106}
1107
1108/* Called after status of force_media possibly changed */
1109static void rhine_set_carrier(struct mii_if_info *mii)
1110{
1111 if (mii->force_media) {
1112 /* autoneg is off: Link is always assumed to be up */
1113 if (!netif_carrier_ok(mii->dev))
1114 netif_carrier_on(mii->dev);
1115 }
1116 else /* Let MMI library update carrier status */
1117 rhine_check_media(mii->dev, 0);
1118 if (debug > 1)
1119 netdev_info(mii->dev, "force_media %d, carrier %d\n",
1120 mii->force_media, netif_carrier_ok(mii->dev));
1121}
1122
1123/**
1124 * rhine_set_cam - set CAM multicast filters
1125 * @ioaddr: register block of this Rhine
1126 * @idx: multicast CAM index [0..MCAM_SIZE-1]
1127 * @addr: multicast address (6 bytes)
1128 *
1129 * Load addresses into multicast filters.
1130 */
1131static void rhine_set_cam(void __iomem *ioaddr, int idx, u8 *addr)
1132{
1133 int i;
1134
1135 iowrite8(CAMC_CAMEN, ioaddr + CamCon);
1136 wmb();
1137
1138 /* Paranoid -- idx out of range should never happen */
1139 idx &= (MCAM_SIZE - 1);
1140
1141 iowrite8((u8) idx, ioaddr + CamAddr);
1142
1143 for (i = 0; i < 6; i++, addr++)
1144 iowrite8(*addr, ioaddr + MulticastFilter0 + i);
1145 udelay(10);
1146 wmb();
1147
1148 iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon);
1149 udelay(10);
1150
1151 iowrite8(0, ioaddr + CamCon);
1152}
1153
1154/**
1155 * rhine_set_vlan_cam - set CAM VLAN filters
1156 * @ioaddr: register block of this Rhine
1157 * @idx: VLAN CAM index [0..VCAM_SIZE-1]
1158 * @addr: VLAN ID (2 bytes)
1159 *
1160 * Load addresses into VLAN filters.
1161 */
1162static void rhine_set_vlan_cam(void __iomem *ioaddr, int idx, u8 *addr)
1163{
1164 iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon);
1165 wmb();
1166
1167 /* Paranoid -- idx out of range should never happen */
1168 idx &= (VCAM_SIZE - 1);
1169
1170 iowrite8((u8) idx, ioaddr + CamAddr);
1171
1172 iowrite16(*((u16 *) addr), ioaddr + MulticastFilter0 + 6);
1173 udelay(10);
1174 wmb();
1175
1176 iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon);
1177 udelay(10);
1178
1179 iowrite8(0, ioaddr + CamCon);
1180}
1181
1182/**
1183 * rhine_set_cam_mask - set multicast CAM mask
1184 * @ioaddr: register block of this Rhine
1185 * @mask: multicast CAM mask
1186 *
1187 * Mask sets multicast filters active/inactive.
1188 */
1189static void rhine_set_cam_mask(void __iomem *ioaddr, u32 mask)
1190{
1191 iowrite8(CAMC_CAMEN, ioaddr + CamCon);
1192 wmb();
1193
1194 /* write mask */
1195 iowrite32(mask, ioaddr + CamMask);
1196
1197 /* disable CAMEN */
1198 iowrite8(0, ioaddr + CamCon);
1199}
1200
1201/**
1202 * rhine_set_vlan_cam_mask - set VLAN CAM mask
1203 * @ioaddr: register block of this Rhine
1204 * @mask: VLAN CAM mask
1205 *
1206 * Mask sets VLAN filters active/inactive.
1207 */
1208static void rhine_set_vlan_cam_mask(void __iomem *ioaddr, u32 mask)
1209{
1210 iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon);
1211 wmb();
1212
1213 /* write mask */
1214 iowrite32(mask, ioaddr + CamMask);
1215
1216 /* disable CAMEN */
1217 iowrite8(0, ioaddr + CamCon);
1218}
1219
1220/**
1221 * rhine_init_cam_filter - initialize CAM filters
1222 * @dev: network device
1223 *
1224 * Initialize (disable) hardware VLAN and multicast support on this
1225 * Rhine.
1226 */
1227static void rhine_init_cam_filter(struct net_device *dev)
1228{
1229 struct rhine_private *rp = netdev_priv(dev);
1230 void __iomem *ioaddr = rp->base;
1231
1232 /* Disable all CAMs */
1233 rhine_set_vlan_cam_mask(ioaddr, 0);
1234 rhine_set_cam_mask(ioaddr, 0);
1235
1236 /* disable hardware VLAN support */
1237 BYTE_REG_BITS_ON(TCR_PQEN, ioaddr + TxConfig);
1238 BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1);
1239}
1240
1241/**
1242 * rhine_update_vcam - update VLAN CAM filters
1243 * @rp: rhine_private data of this Rhine
1244 *
1245 * Update VLAN CAM filters to match configuration change.
1246 */
1247static void rhine_update_vcam(struct net_device *dev)
1248{
1249 struct rhine_private *rp = netdev_priv(dev);
1250 void __iomem *ioaddr = rp->base;
1251 u16 vid;
1252 u32 vCAMmask = 0; /* 32 vCAMs (6105M and better) */
1253 unsigned int i = 0;
1254
1255 for_each_set_bit(vid, rp->active_vlans, VLAN_N_VID) {
1256 rhine_set_vlan_cam(ioaddr, i, (u8 *)&vid);
1257 vCAMmask |= 1 << i;
1258 if (++i >= VCAM_SIZE)
1259 break;
1260 }
1261 rhine_set_vlan_cam_mask(ioaddr, vCAMmask);
1262}
1263
1264static void rhine_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)
1265{
1266 struct rhine_private *rp = netdev_priv(dev);
1267
1268 spin_lock_irq(&rp->lock);
1269 set_bit(vid, rp->active_vlans);
1270 rhine_update_vcam(dev);
1271 spin_unlock_irq(&rp->lock);
1272}
1273
1274static void rhine_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
1275{
1276 struct rhine_private *rp = netdev_priv(dev);
1277
1278 spin_lock_irq(&rp->lock);
1279 clear_bit(vid, rp->active_vlans);
1280 rhine_update_vcam(dev);
1281 spin_unlock_irq(&rp->lock);
1282}
1283
1284static void init_registers(struct net_device *dev)
1285{
1286 struct rhine_private *rp = netdev_priv(dev);
1287 void __iomem *ioaddr = rp->base;
1288 int i;
1289
1290 for (i = 0; i < 6; i++)
1291 iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
1292
1293 /* Initialize other registers. */
1294 iowrite16(0x0006, ioaddr + PCIBusConfig); /* Tune configuration??? */
1295 /* Configure initial FIFO thresholds. */
1296 iowrite8(0x20, ioaddr + TxConfig);
1297 rp->tx_thresh = 0x20;
1298 rp->rx_thresh = 0x60; /* Written in rhine_set_rx_mode(). */
1299
1300 iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr);
1301 iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr);
1302
1303 rhine_set_rx_mode(dev);
1304
1305 if (rp->pdev->revision >= VT6105M)
1306 rhine_init_cam_filter(dev);
1307
1308 napi_enable(&rp->napi);
1309
1310 /* Enable interrupts by setting the interrupt mask. */
1311 iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |
1312 IntrRxDropped | IntrRxNoBuf | IntrTxAborted |
1313 IntrTxDone | IntrTxError | IntrTxUnderrun |
1314 IntrPCIErr | IntrStatsMax | IntrLinkChange,
1315 ioaddr + IntrEnable);
1316
1317 iowrite16(CmdStart | CmdTxOn | CmdRxOn | (Cmd1NoTxPoll << 8),
1318 ioaddr + ChipCmd);
1319 rhine_check_media(dev, 1);
1320}
1321
1322/* Enable MII link status auto-polling (required for IntrLinkChange) */
1323static void rhine_enable_linkmon(void __iomem *ioaddr)
1324{
1325 iowrite8(0, ioaddr + MIICmd);
1326 iowrite8(MII_BMSR, ioaddr + MIIRegAddr);
1327 iowrite8(0x80, ioaddr + MIICmd);
1328
1329 RHINE_WAIT_FOR((ioread8(ioaddr + MIIRegAddr) & 0x20));
1330
1331 iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr);
1332}
1333
1334/* Disable MII link status auto-polling (required for MDIO access) */
1335static void rhine_disable_linkmon(void __iomem *ioaddr, u32 quirks)
1336{
1337 iowrite8(0, ioaddr + MIICmd);
1338
1339 if (quirks & rqRhineI) {
1340 iowrite8(0x01, ioaddr + MIIRegAddr); // MII_BMSR
1341
1342 /* Can be called from ISR. Evil. */
1343 mdelay(1);
1344
1345 /* 0x80 must be set immediately before turning it off */
1346 iowrite8(0x80, ioaddr + MIICmd);
1347
1348 RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x20);
1349
1350 /* Heh. Now clear 0x80 again. */
1351 iowrite8(0, ioaddr + MIICmd);
1352 }
1353 else
1354 RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x80);
1355}
1356
1357/* Read and write over the MII Management Data I/O (MDIO) interface. */
1358
1359static int mdio_read(struct net_device *dev, int phy_id, int regnum)
1360{
1361 struct rhine_private *rp = netdev_priv(dev);
1362 void __iomem *ioaddr = rp->base;
1363 int result;
1364
1365 rhine_disable_linkmon(ioaddr, rp->quirks);
1366
1367 /* rhine_disable_linkmon already cleared MIICmd */
1368 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1369 iowrite8(regnum, ioaddr + MIIRegAddr);
1370 iowrite8(0x40, ioaddr + MIICmd); /* Trigger read */
1371 RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x40));
1372 result = ioread16(ioaddr + MIIData);
1373
1374 rhine_enable_linkmon(ioaddr);
1375 return result;
1376}
1377
1378static void mdio_write(struct net_device *dev, int phy_id, int regnum, int value)
1379{
1380 struct rhine_private *rp = netdev_priv(dev);
1381 void __iomem *ioaddr = rp->base;
1382
1383 rhine_disable_linkmon(ioaddr, rp->quirks);
1384
1385 /* rhine_disable_linkmon already cleared MIICmd */
1386 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1387 iowrite8(regnum, ioaddr + MIIRegAddr);
1388 iowrite16(value, ioaddr + MIIData);
1389 iowrite8(0x20, ioaddr + MIICmd); /* Trigger write */
1390 RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x20));
1391
1392 rhine_enable_linkmon(ioaddr);
1393}
1394
1395static int rhine_open(struct net_device *dev)
1396{
1397 struct rhine_private *rp = netdev_priv(dev);
1398 void __iomem *ioaddr = rp->base;
1399 int rc;
1400
1401 rc = request_irq(rp->pdev->irq, rhine_interrupt, IRQF_SHARED, dev->name,
1402 dev);
1403 if (rc)
1404 return rc;
1405
1406 if (debug > 1)
1407 netdev_dbg(dev, "%s() irq %d\n", __func__, rp->pdev->irq);
1408
1409 rc = alloc_ring(dev);
1410 if (rc) {
1411 free_irq(rp->pdev->irq, dev);
1412 return rc;
1413 }
1414 alloc_rbufs(dev);
1415 alloc_tbufs(dev);
1416 rhine_chip_reset(dev);
1417 init_registers(dev);
1418 if (debug > 2)
1419 netdev_dbg(dev, "%s() Done - status %04x MII status: %04x\n",
1420 __func__, ioread16(ioaddr + ChipCmd),
1421 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1422
1423 netif_start_queue(dev);
1424
1425 return 0;
1426}
1427
1428static void rhine_reset_task(struct work_struct *work)
1429{
1430 struct rhine_private *rp = container_of(work, struct rhine_private,
1431 reset_task);
1432 struct net_device *dev = rp->dev;
1433
1434 /* protect against concurrent rx interrupts */
1435 disable_irq(rp->pdev->irq);
1436
1437 napi_disable(&rp->napi);
1438
1439 spin_lock_bh(&rp->lock);
1440
1441 /* clear all descriptors */
1442 free_tbufs(dev);
1443 free_rbufs(dev);
1444 alloc_tbufs(dev);
1445 alloc_rbufs(dev);
1446
1447 /* Reinitialize the hardware. */
1448 rhine_chip_reset(dev);
1449 init_registers(dev);
1450
1451 spin_unlock_bh(&rp->lock);
1452 enable_irq(rp->pdev->irq);
1453
1454 dev->trans_start = jiffies; /* prevent tx timeout */
1455 dev->stats.tx_errors++;
1456 netif_wake_queue(dev);
1457}
1458
1459static void rhine_tx_timeout(struct net_device *dev)
1460{
1461 struct rhine_private *rp = netdev_priv(dev);
1462 void __iomem *ioaddr = rp->base;
1463
1464 netdev_warn(dev, "Transmit timed out, status %04x, PHY status %04x, resetting...\n",
1465 ioread16(ioaddr + IntrStatus),
1466 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1467
1468 schedule_work(&rp->reset_task);
1469}
1470
1471static netdev_tx_t rhine_start_tx(struct sk_buff *skb,
1472 struct net_device *dev)
1473{
1474 struct rhine_private *rp = netdev_priv(dev);
1475 void __iomem *ioaddr = rp->base;
1476 unsigned entry;
1477 unsigned long flags;
1478
1479 /* Caution: the write order is important here, set the field
1480 with the "ownership" bits last. */
1481
1482 /* Calculate the next Tx descriptor entry. */
1483 entry = rp->cur_tx % TX_RING_SIZE;
1484
1485 if (skb_padto(skb, ETH_ZLEN))
1486 return NETDEV_TX_OK;
1487
1488 rp->tx_skbuff[entry] = skb;
1489
1490 if ((rp->quirks & rqRhineI) &&
1491 (((unsigned long)skb->data & 3) || skb_shinfo(skb)->nr_frags != 0 || skb->ip_summed == CHECKSUM_PARTIAL)) {
1492 /* Must use alignment buffer. */
1493 if (skb->len > PKT_BUF_SZ) {
1494 /* packet too long, drop it */
1495 dev_kfree_skb(skb);
1496 rp->tx_skbuff[entry] = NULL;
1497 dev->stats.tx_dropped++;
1498 return NETDEV_TX_OK;
1499 }
1500
1501 /* Padding is not copied and so must be redone. */
1502 skb_copy_and_csum_dev(skb, rp->tx_buf[entry]);
1503 if (skb->len < ETH_ZLEN)
1504 memset(rp->tx_buf[entry] + skb->len, 0,
1505 ETH_ZLEN - skb->len);
1506 rp->tx_skbuff_dma[entry] = 0;
1507 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma +
1508 (rp->tx_buf[entry] -
1509 rp->tx_bufs));
1510 } else {
1511 rp->tx_skbuff_dma[entry] =
1512 pci_map_single(rp->pdev, skb->data, skb->len,
1513 PCI_DMA_TODEVICE);
1514 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_skbuff_dma[entry]);
1515 }
1516
1517 rp->tx_ring[entry].desc_length =
1518 cpu_to_le32(TXDESC | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1519
1520 if (unlikely(vlan_tx_tag_present(skb))) {
1521 rp->tx_ring[entry].tx_status = cpu_to_le32((vlan_tx_tag_get(skb)) << 16);
1522 /* request tagging */
1523 rp->tx_ring[entry].desc_length |= cpu_to_le32(0x020000);
1524 }
1525 else
1526 rp->tx_ring[entry].tx_status = 0;
1527
1528 /* lock eth irq */
1529 spin_lock_irqsave(&rp->lock, flags);
1530 wmb();
1531 rp->tx_ring[entry].tx_status |= cpu_to_le32(DescOwn);
1532 wmb();
1533
1534 rp->cur_tx++;
1535
1536 /* Non-x86 Todo: explicitly flush cache lines here. */
1537
1538 if (vlan_tx_tag_present(skb))
1539 /* Tx queues are bits 7-0 (first Tx queue: bit 7) */
1540 BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake);
1541
1542 /* Wake the potentially-idle transmit channel */
1543 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1544 ioaddr + ChipCmd1);
1545 IOSYNC;
1546
1547 if (rp->cur_tx == rp->dirty_tx + TX_QUEUE_LEN)
1548 netif_stop_queue(dev);
1549
1550 spin_unlock_irqrestore(&rp->lock, flags);
1551
1552 if (debug > 4) {
1553 netdev_dbg(dev, "Transmit frame #%d queued in slot %d\n",
1554 rp->cur_tx-1, entry);
1555 }
1556 return NETDEV_TX_OK;
1557}
1558
1559/* The interrupt handler does all of the Rx thread work and cleans up
1560 after the Tx thread. */
1561static irqreturn_t rhine_interrupt(int irq, void *dev_instance)
1562{
1563 struct net_device *dev = dev_instance;
1564 struct rhine_private *rp = netdev_priv(dev);
1565 void __iomem *ioaddr = rp->base;
1566 u32 intr_status;
1567 int boguscnt = max_interrupt_work;
1568 int handled = 0;
1569
1570 while ((intr_status = get_intr_status(dev))) {
1571 handled = 1;
1572
1573 /* Acknowledge all of the current interrupt sources ASAP. */
1574 if (intr_status & IntrTxDescRace)
1575 iowrite8(0x08, ioaddr + IntrStatus2);
1576 iowrite16(intr_status & 0xffff, ioaddr + IntrStatus);
1577 IOSYNC;
1578
1579 if (debug > 4)
1580 netdev_dbg(dev, "Interrupt, status %08x\n",
1581 intr_status);
1582
1583 if (intr_status & (IntrRxDone | IntrRxErr | IntrRxDropped |
1584 IntrRxWakeUp | IntrRxEmpty | IntrRxNoBuf)) {
1585 iowrite16(IntrTxAborted |
1586 IntrTxDone | IntrTxError | IntrTxUnderrun |
1587 IntrPCIErr | IntrStatsMax | IntrLinkChange,
1588 ioaddr + IntrEnable);
1589
1590 napi_schedule(&rp->napi);
1591 }
1592
1593 if (intr_status & (IntrTxErrSummary | IntrTxDone)) {
1594 if (intr_status & IntrTxErrSummary) {
1595 /* Avoid scavenging before Tx engine turned off */
1596 RHINE_WAIT_FOR(!(ioread8(ioaddr+ChipCmd) & CmdTxOn));
1597 if (debug > 2 &&
1598 ioread8(ioaddr+ChipCmd) & CmdTxOn)
1599 netdev_warn(dev,
1600 "%s: Tx engine still on\n",
1601 __func__);
1602 }
1603 rhine_tx(dev);
1604 }
1605
1606 /* Abnormal error summary/uncommon events handlers. */
1607 if (intr_status & (IntrPCIErr | IntrLinkChange |
1608 IntrStatsMax | IntrTxError | IntrTxAborted |
1609 IntrTxUnderrun | IntrTxDescRace))
1610 rhine_error(dev, intr_status);
1611
1612 if (--boguscnt < 0) {
1613 netdev_warn(dev, "Too much work at interrupt, status=%#08x\n",
1614 intr_status);
1615 break;
1616 }
1617 }
1618
1619 if (debug > 3)
1620 netdev_dbg(dev, "exiting interrupt, status=%08x\n",
1621 ioread16(ioaddr + IntrStatus));
1622 return IRQ_RETVAL(handled);
1623}
1624
1625/* This routine is logically part of the interrupt handler, but isolated
1626 for clarity. */
1627static void rhine_tx(struct net_device *dev)
1628{
1629 struct rhine_private *rp = netdev_priv(dev);
1630 int txstatus = 0, entry = rp->dirty_tx % TX_RING_SIZE;
1631
1632 spin_lock(&rp->lock);
1633
1634 /* find and cleanup dirty tx descriptors */
1635 while (rp->dirty_tx != rp->cur_tx) {
1636 txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status);
1637 if (debug > 6)
1638 netdev_dbg(dev, "Tx scavenge %d status %08x\n",
1639 entry, txstatus);
1640 if (txstatus & DescOwn)
1641 break;
1642 if (txstatus & 0x8000) {
1643 if (debug > 1)
1644 netdev_dbg(dev, "Transmit error, Tx status %08x\n",
1645 txstatus);
1646 dev->stats.tx_errors++;
1647 if (txstatus & 0x0400)
1648 dev->stats.tx_carrier_errors++;
1649 if (txstatus & 0x0200)
1650 dev->stats.tx_window_errors++;
1651 if (txstatus & 0x0100)
1652 dev->stats.tx_aborted_errors++;
1653 if (txstatus & 0x0080)
1654 dev->stats.tx_heartbeat_errors++;
1655 if (((rp->quirks & rqRhineI) && txstatus & 0x0002) ||
1656 (txstatus & 0x0800) || (txstatus & 0x1000)) {
1657 dev->stats.tx_fifo_errors++;
1658 rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
1659 break; /* Keep the skb - we try again */
1660 }
1661 /* Transmitter restarted in 'abnormal' handler. */
1662 } else {
1663 if (rp->quirks & rqRhineI)
1664 dev->stats.collisions += (txstatus >> 3) & 0x0F;
1665 else
1666 dev->stats.collisions += txstatus & 0x0F;
1667 if (debug > 6)
1668 netdev_dbg(dev, "collisions: %1.1x:%1.1x\n",
1669 (txstatus >> 3) & 0xF,
1670 txstatus & 0xF);
1671 dev->stats.tx_bytes += rp->tx_skbuff[entry]->len;
1672 dev->stats.tx_packets++;
1673 }
1674 /* Free the original skb. */
1675 if (rp->tx_skbuff_dma[entry]) {
1676 pci_unmap_single(rp->pdev,
1677 rp->tx_skbuff_dma[entry],
1678 rp->tx_skbuff[entry]->len,
1679 PCI_DMA_TODEVICE);
1680 }
1681 dev_kfree_skb_irq(rp->tx_skbuff[entry]);
1682 rp->tx_skbuff[entry] = NULL;
1683 entry = (++rp->dirty_tx) % TX_RING_SIZE;
1684 }
1685 if ((rp->cur_tx - rp->dirty_tx) < TX_QUEUE_LEN - 4)
1686 netif_wake_queue(dev);
1687
1688 spin_unlock(&rp->lock);
1689}
1690
1691/**
1692 * rhine_get_vlan_tci - extract TCI from Rx data buffer
1693 * @skb: pointer to sk_buff
1694 * @data_size: used data area of the buffer including CRC
1695 *
1696 * If hardware VLAN tag extraction is enabled and the chip indicates a 802.1Q
1697 * packet, the extracted 802.1Q header (2 bytes TPID + 2 bytes TCI) is 4-byte
1698 * aligned following the CRC.
1699 */
1700static inline u16 rhine_get_vlan_tci(struct sk_buff *skb, int data_size)
1701{
1702 u8 *trailer = (u8 *)skb->data + ((data_size + 3) & ~3) + 2;
1703 return be16_to_cpup((__be16 *)trailer);
1704}
1705
1706/* Process up to limit frames from receive ring */
1707static int rhine_rx(struct net_device *dev, int limit)
1708{
1709 struct rhine_private *rp = netdev_priv(dev);
1710 int count;
1711 int entry = rp->cur_rx % RX_RING_SIZE;
1712
1713 if (debug > 4) {
1714 netdev_dbg(dev, "%s(), entry %d status %08x\n",
1715 __func__, entry,
1716 le32_to_cpu(rp->rx_head_desc->rx_status));
1717 }
1718
1719 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1720 for (count = 0; count < limit; ++count) {
1721 struct rx_desc *desc = rp->rx_head_desc;
1722 u32 desc_status = le32_to_cpu(desc->rx_status);
1723 u32 desc_length = le32_to_cpu(desc->desc_length);
1724 int data_size = desc_status >> 16;
1725
1726 if (desc_status & DescOwn)
1727 break;
1728
1729 if (debug > 4)
1730 netdev_dbg(dev, "%s() status is %08x\n",
1731 __func__, desc_status);
1732
1733 if ((desc_status & (RxWholePkt | RxErr)) != RxWholePkt) {
1734 if ((desc_status & RxWholePkt) != RxWholePkt) {
1735 netdev_warn(dev,
1736 "Oversized Ethernet frame spanned multiple buffers, "
1737 "entry %#x length %d status %08x!\n",
1738 entry, data_size,
1739 desc_status);
1740 netdev_warn(dev,
1741 "Oversized Ethernet frame %p vs %p\n",
1742 rp->rx_head_desc,
1743 &rp->rx_ring[entry]);
1744 dev->stats.rx_length_errors++;
1745 } else if (desc_status & RxErr) {
1746 /* There was a error. */
1747 if (debug > 2)
1748 netdev_dbg(dev, "%s() Rx error was %08x\n",
1749 __func__, desc_status);
1750 dev->stats.rx_errors++;
1751 if (desc_status & 0x0030)
1752 dev->stats.rx_length_errors++;
1753 if (desc_status & 0x0048)
1754 dev->stats.rx_fifo_errors++;
1755 if (desc_status & 0x0004)
1756 dev->stats.rx_frame_errors++;
1757 if (desc_status & 0x0002) {
1758 /* this can also be updated outside the interrupt handler */
1759 spin_lock(&rp->lock);
1760 dev->stats.rx_crc_errors++;
1761 spin_unlock(&rp->lock);
1762 }
1763 }
1764 } else {
1765 struct sk_buff *skb = NULL;
1766 /* Length should omit the CRC */
1767 int pkt_len = data_size - 4;
1768 u16 vlan_tci = 0;
1769
1770 /* Check if the packet is long enough to accept without
1771 copying to a minimally-sized skbuff. */
1772 if (pkt_len < rx_copybreak)
1773 skb = netdev_alloc_skb_ip_align(dev, pkt_len);
1774 if (skb) {
1775 pci_dma_sync_single_for_cpu(rp->pdev,
1776 rp->rx_skbuff_dma[entry],
1777 rp->rx_buf_sz,
1778 PCI_DMA_FROMDEVICE);
1779
1780 skb_copy_to_linear_data(skb,
1781 rp->rx_skbuff[entry]->data,
1782 pkt_len);
1783 skb_put(skb, pkt_len);
1784 pci_dma_sync_single_for_device(rp->pdev,
1785 rp->rx_skbuff_dma[entry],
1786 rp->rx_buf_sz,
1787 PCI_DMA_FROMDEVICE);
1788 } else {
1789 skb = rp->rx_skbuff[entry];
1790 if (skb == NULL) {
1791 netdev_err(dev, "Inconsistent Rx descriptor chain\n");
1792 break;
1793 }
1794 rp->rx_skbuff[entry] = NULL;
1795 skb_put(skb, pkt_len);
1796 pci_unmap_single(rp->pdev,
1797 rp->rx_skbuff_dma[entry],
1798 rp->rx_buf_sz,
1799 PCI_DMA_FROMDEVICE);
1800 }
1801
1802 if (unlikely(desc_length & DescTag))
1803 vlan_tci = rhine_get_vlan_tci(skb, data_size);
1804
1805 skb->protocol = eth_type_trans(skb, dev);
1806
1807 if (unlikely(desc_length & DescTag))
1808 __vlan_hwaccel_put_tag(skb, vlan_tci);
1809 netif_receive_skb(skb);
1810 dev->stats.rx_bytes += pkt_len;
1811 dev->stats.rx_packets++;
1812 }
1813 entry = (++rp->cur_rx) % RX_RING_SIZE;
1814 rp->rx_head_desc = &rp->rx_ring[entry];
1815 }
1816
1817 /* Refill the Rx ring buffers. */
1818 for (; rp->cur_rx - rp->dirty_rx > 0; rp->dirty_rx++) {
1819 struct sk_buff *skb;
1820 entry = rp->dirty_rx % RX_RING_SIZE;
1821 if (rp->rx_skbuff[entry] == NULL) {
1822 skb = netdev_alloc_skb(dev, rp->rx_buf_sz);
1823 rp->rx_skbuff[entry] = skb;
1824 if (skb == NULL)
1825 break; /* Better luck next round. */
1826 skb->dev = dev; /* Mark as being used by this device. */
1827 rp->rx_skbuff_dma[entry] =
1828 pci_map_single(rp->pdev, skb->data,
1829 rp->rx_buf_sz,
1830 PCI_DMA_FROMDEVICE);
1831 rp->rx_ring[entry].addr = cpu_to_le32(rp->rx_skbuff_dma[entry]);
1832 }
1833 rp->rx_ring[entry].rx_status = cpu_to_le32(DescOwn);
1834 }
1835
1836 return count;
1837}
1838
1839/*
1840 * Clears the "tally counters" for CRC errors and missed frames(?).
1841 * It has been reported that some chips need a write of 0 to clear
1842 * these, for others the counters are set to 1 when written to and
1843 * instead cleared when read. So we clear them both ways ...
1844 */
1845static inline void clear_tally_counters(void __iomem *ioaddr)
1846{
1847 iowrite32(0, ioaddr + RxMissed);
1848 ioread16(ioaddr + RxCRCErrs);
1849 ioread16(ioaddr + RxMissed);
1850}
1851
1852static void rhine_restart_tx(struct net_device *dev) {
1853 struct rhine_private *rp = netdev_priv(dev);
1854 void __iomem *ioaddr = rp->base;
1855 int entry = rp->dirty_tx % TX_RING_SIZE;
1856 u32 intr_status;
1857
1858 /*
1859 * If new errors occurred, we need to sort them out before doing Tx.
1860 * In that case the ISR will be back here RSN anyway.
1861 */
1862 intr_status = get_intr_status(dev);
1863
1864 if ((intr_status & IntrTxErrSummary) == 0) {
1865
1866 /* We know better than the chip where it should continue. */
1867 iowrite32(rp->tx_ring_dma + entry * sizeof(struct tx_desc),
1868 ioaddr + TxRingPtr);
1869
1870 iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn,
1871 ioaddr + ChipCmd);
1872
1873 if (rp->tx_ring[entry].desc_length & cpu_to_le32(0x020000))
1874 /* Tx queues are bits 7-0 (first Tx queue: bit 7) */
1875 BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake);
1876
1877 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1878 ioaddr + ChipCmd1);
1879 IOSYNC;
1880 }
1881 else {
1882 /* This should never happen */
1883 if (debug > 1)
1884 netdev_warn(dev, "%s() Another error occurred %08x\n",
1885 __func__, intr_status);
1886 }
1887
1888}
1889
1890static void rhine_error(struct net_device *dev, int intr_status)
1891{
1892 struct rhine_private *rp = netdev_priv(dev);
1893 void __iomem *ioaddr = rp->base;
1894
1895 spin_lock(&rp->lock);
1896
1897 if (intr_status & IntrLinkChange)
1898 rhine_check_media(dev, 0);
1899 if (intr_status & IntrStatsMax) {
1900 dev->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
1901 dev->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
1902 clear_tally_counters(ioaddr);
1903 }
1904 if (intr_status & IntrTxAborted) {
1905 if (debug > 1)
1906 netdev_info(dev, "Abort %08x, frame dropped\n",
1907 intr_status);
1908 }
1909 if (intr_status & IntrTxUnderrun) {
1910 if (rp->tx_thresh < 0xE0)
1911 BYTE_REG_BITS_SET((rp->tx_thresh += 0x20), 0x80, ioaddr + TxConfig);
1912 if (debug > 1)
1913 netdev_info(dev, "Transmitter underrun, Tx threshold now %02x\n",
1914 rp->tx_thresh);
1915 }
1916 if (intr_status & IntrTxDescRace) {
1917 if (debug > 2)
1918 netdev_info(dev, "Tx descriptor write-back race\n");
1919 }
1920 if ((intr_status & IntrTxError) &&
1921 (intr_status & (IntrTxAborted |
1922 IntrTxUnderrun | IntrTxDescRace)) == 0) {
1923 if (rp->tx_thresh < 0xE0) {
1924 BYTE_REG_BITS_SET((rp->tx_thresh += 0x20), 0x80, ioaddr + TxConfig);
1925 }
1926 if (debug > 1)
1927 netdev_info(dev, "Unspecified error. Tx threshold now %02x\n",
1928 rp->tx_thresh);
1929 }
1930 if (intr_status & (IntrTxAborted | IntrTxUnderrun | IntrTxDescRace |
1931 IntrTxError))
1932 rhine_restart_tx(dev);
1933
1934 if (intr_status & ~(IntrLinkChange | IntrStatsMax | IntrTxUnderrun |
1935 IntrTxError | IntrTxAborted | IntrNormalSummary |
1936 IntrTxDescRace)) {
1937 if (debug > 1)
1938 netdev_err(dev, "Something Wicked happened! %08x\n",
1939 intr_status);
1940 }
1941
1942 spin_unlock(&rp->lock);
1943}
1944
1945static struct net_device_stats *rhine_get_stats(struct net_device *dev)
1946{
1947 struct rhine_private *rp = netdev_priv(dev);
1948 void __iomem *ioaddr = rp->base;
1949 unsigned long flags;
1950
1951 spin_lock_irqsave(&rp->lock, flags);
1952 dev->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
1953 dev->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
1954 clear_tally_counters(ioaddr);
1955 spin_unlock_irqrestore(&rp->lock, flags);
1956
1957 return &dev->stats;
1958}
1959
1960static void rhine_set_rx_mode(struct net_device *dev)
1961{
1962 struct rhine_private *rp = netdev_priv(dev);
1963 void __iomem *ioaddr = rp->base;
1964 u32 mc_filter[2]; /* Multicast hash filter */
1965 u8 rx_mode = 0x0C; /* Note: 0x02=accept runt, 0x01=accept errs */
1966 struct netdev_hw_addr *ha;
1967
1968 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1969 rx_mode = 0x1C;
1970 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
1971 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
1972 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
1973 (dev->flags & IFF_ALLMULTI)) {
1974 /* Too many to match, or accept all multicasts. */
1975 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
1976 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
1977 } else if (rp->pdev->revision >= VT6105M) {
1978 int i = 0;
1979 u32 mCAMmask = 0; /* 32 mCAMs (6105M and better) */
1980 netdev_for_each_mc_addr(ha, dev) {
1981 if (i == MCAM_SIZE)
1982 break;
1983 rhine_set_cam(ioaddr, i, ha->addr);
1984 mCAMmask |= 1 << i;
1985 i++;
1986 }
1987 rhine_set_cam_mask(ioaddr, mCAMmask);
1988 } else {
1989 memset(mc_filter, 0, sizeof(mc_filter));
1990 netdev_for_each_mc_addr(ha, dev) {
1991 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1992
1993 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1994 }
1995 iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
1996 iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
1997 }
1998 /* enable/disable VLAN receive filtering */
1999 if (rp->pdev->revision >= VT6105M) {
2000 if (dev->flags & IFF_PROMISC)
2001 BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1);
2002 else
2003 BYTE_REG_BITS_ON(BCR1_VIDFR, ioaddr + PCIBusConfig1);
2004 }
2005 BYTE_REG_BITS_ON(rx_mode, ioaddr + RxConfig);
2006}
2007
2008static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2009{
2010 struct rhine_private *rp = netdev_priv(dev);
2011
2012 strcpy(info->driver, DRV_NAME);
2013 strcpy(info->version, DRV_VERSION);
2014 strcpy(info->bus_info, pci_name(rp->pdev));
2015}
2016
2017static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2018{
2019 struct rhine_private *rp = netdev_priv(dev);
2020 int rc;
2021
2022 spin_lock_irq(&rp->lock);
2023 rc = mii_ethtool_gset(&rp->mii_if, cmd);
2024 spin_unlock_irq(&rp->lock);
2025
2026 return rc;
2027}
2028
2029static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2030{
2031 struct rhine_private *rp = netdev_priv(dev);
2032 int rc;
2033
2034 spin_lock_irq(&rp->lock);
2035 rc = mii_ethtool_sset(&rp->mii_if, cmd);
2036 spin_unlock_irq(&rp->lock);
2037 rhine_set_carrier(&rp->mii_if);
2038
2039 return rc;
2040}
2041
2042static int netdev_nway_reset(struct net_device *dev)
2043{
2044 struct rhine_private *rp = netdev_priv(dev);
2045
2046 return mii_nway_restart(&rp->mii_if);
2047}
2048
2049static u32 netdev_get_link(struct net_device *dev)
2050{
2051 struct rhine_private *rp = netdev_priv(dev);
2052
2053 return mii_link_ok(&rp->mii_if);
2054}
2055
2056static u32 netdev_get_msglevel(struct net_device *dev)
2057{
2058 return debug;
2059}
2060
2061static void netdev_set_msglevel(struct net_device *dev, u32 value)
2062{
2063 debug = value;
2064}
2065
2066static void rhine_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2067{
2068 struct rhine_private *rp = netdev_priv(dev);
2069
2070 if (!(rp->quirks & rqWOL))
2071 return;
2072
2073 spin_lock_irq(&rp->lock);
2074 wol->supported = WAKE_PHY | WAKE_MAGIC |
2075 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
2076 wol->wolopts = rp->wolopts;
2077 spin_unlock_irq(&rp->lock);
2078}
2079
2080static int rhine_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2081{
2082 struct rhine_private *rp = netdev_priv(dev);
2083 u32 support = WAKE_PHY | WAKE_MAGIC |
2084 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
2085
2086 if (!(rp->quirks & rqWOL))
2087 return -EINVAL;
2088
2089 if (wol->wolopts & ~support)
2090 return -EINVAL;
2091
2092 spin_lock_irq(&rp->lock);
2093 rp->wolopts = wol->wolopts;
2094 spin_unlock_irq(&rp->lock);
2095
2096 return 0;
2097}
2098
2099static const struct ethtool_ops netdev_ethtool_ops = {
2100 .get_drvinfo = netdev_get_drvinfo,
2101 .get_settings = netdev_get_settings,
2102 .set_settings = netdev_set_settings,
2103 .nway_reset = netdev_nway_reset,
2104 .get_link = netdev_get_link,
2105 .get_msglevel = netdev_get_msglevel,
2106 .set_msglevel = netdev_set_msglevel,
2107 .get_wol = rhine_get_wol,
2108 .set_wol = rhine_set_wol,
2109};
2110
2111static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2112{
2113 struct rhine_private *rp = netdev_priv(dev);
2114 int rc;
2115
2116 if (!netif_running(dev))
2117 return -EINVAL;
2118
2119 spin_lock_irq(&rp->lock);
2120 rc = generic_mii_ioctl(&rp->mii_if, if_mii(rq), cmd, NULL);
2121 spin_unlock_irq(&rp->lock);
2122 rhine_set_carrier(&rp->mii_if);
2123
2124 return rc;
2125}
2126
2127static int rhine_close(struct net_device *dev)
2128{
2129 struct rhine_private *rp = netdev_priv(dev);
2130 void __iomem *ioaddr = rp->base;
2131
2132 napi_disable(&rp->napi);
2133 cancel_work_sync(&rp->reset_task);
2134 netif_stop_queue(dev);
2135
2136 spin_lock_irq(&rp->lock);
2137
2138 if (debug > 1)
2139 netdev_dbg(dev, "Shutting down ethercard, status was %04x\n",
2140 ioread16(ioaddr + ChipCmd));
2141
2142 /* Switch to loopback mode to avoid hardware races. */
2143 iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig);
2144
2145 /* Disable interrupts by clearing the interrupt mask. */
2146 iowrite16(0x0000, ioaddr + IntrEnable);
2147
2148 /* Stop the chip's Tx and Rx processes. */
2149 iowrite16(CmdStop, ioaddr + ChipCmd);
2150
2151 spin_unlock_irq(&rp->lock);
2152
2153 free_irq(rp->pdev->irq, dev);
2154 free_rbufs(dev);
2155 free_tbufs(dev);
2156 free_ring(dev);
2157
2158 return 0;
2159}
2160
2161
2162static void __devexit rhine_remove_one(struct pci_dev *pdev)
2163{
2164 struct net_device *dev = pci_get_drvdata(pdev);
2165 struct rhine_private *rp = netdev_priv(dev);
2166
2167 unregister_netdev(dev);
2168
2169 pci_iounmap(pdev, rp->base);
2170 pci_release_regions(pdev);
2171
2172 free_netdev(dev);
2173 pci_disable_device(pdev);
2174 pci_set_drvdata(pdev, NULL);
2175}
2176
2177static void rhine_shutdown (struct pci_dev *pdev)
2178{
2179 struct net_device *dev = pci_get_drvdata(pdev);
2180 struct rhine_private *rp = netdev_priv(dev);
2181 void __iomem *ioaddr = rp->base;
2182
2183 if (!(rp->quirks & rqWOL))
2184 return; /* Nothing to do for non-WOL adapters */
2185
2186 rhine_power_init(dev);
2187
2188 /* Make sure we use pattern 0, 1 and not 4, 5 */
2189 if (rp->quirks & rq6patterns)
2190 iowrite8(0x04, ioaddr + WOLcgClr);
2191
2192 if (rp->wolopts & WAKE_MAGIC) {
2193 iowrite8(WOLmagic, ioaddr + WOLcrSet);
2194 /*
2195 * Turn EEPROM-controlled wake-up back on -- some hardware may
2196 * not cooperate otherwise.
2197 */
2198 iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA);
2199 }
2200
2201 if (rp->wolopts & (WAKE_BCAST|WAKE_MCAST))
2202 iowrite8(WOLbmcast, ioaddr + WOLcgSet);
2203
2204 if (rp->wolopts & WAKE_PHY)
2205 iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet);
2206
2207 if (rp->wolopts & WAKE_UCAST)
2208 iowrite8(WOLucast, ioaddr + WOLcrSet);
2209
2210 if (rp->wolopts) {
2211 /* Enable legacy WOL (for old motherboards) */
2212 iowrite8(0x01, ioaddr + PwcfgSet);
2213 iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW);
2214 }
2215
2216 /* Hit power state D3 (sleep) */
2217 if (!avoid_D3)
2218 iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW);
2219
2220 /* TODO: Check use of pci_enable_wake() */
2221
2222}
2223
2224#ifdef CONFIG_PM
2225static int rhine_suspend(struct pci_dev *pdev, pm_message_t state)
2226{
2227 struct net_device *dev = pci_get_drvdata(pdev);
2228 struct rhine_private *rp = netdev_priv(dev);
2229 unsigned long flags;
2230
2231 if (!netif_running(dev))
2232 return 0;
2233
2234 napi_disable(&rp->napi);
2235
2236 netif_device_detach(dev);
2237 pci_save_state(pdev);
2238
2239 spin_lock_irqsave(&rp->lock, flags);
2240 rhine_shutdown(pdev);
2241 spin_unlock_irqrestore(&rp->lock, flags);
2242
2243 free_irq(dev->irq, dev);
2244 return 0;
2245}
2246
2247static int rhine_resume(struct pci_dev *pdev)
2248{
2249 struct net_device *dev = pci_get_drvdata(pdev);
2250 struct rhine_private *rp = netdev_priv(dev);
2251 unsigned long flags;
2252 int ret;
2253
2254 if (!netif_running(dev))
2255 return 0;
2256
2257 if (request_irq(dev->irq, rhine_interrupt, IRQF_SHARED, dev->name, dev))
2258 netdev_err(dev, "request_irq failed\n");
2259
2260 ret = pci_set_power_state(pdev, PCI_D0);
2261 if (debug > 1)
2262 netdev_info(dev, "Entering power state D0 %s (%d)\n",
2263 ret ? "failed" : "succeeded", ret);
2264
2265 pci_restore_state(pdev);
2266
2267 spin_lock_irqsave(&rp->lock, flags);
2268#ifdef USE_MMIO
2269 enable_mmio(rp->pioaddr, rp->quirks);
2270#endif
2271 rhine_power_init(dev);
2272 free_tbufs(dev);
2273 free_rbufs(dev);
2274 alloc_tbufs(dev);
2275 alloc_rbufs(dev);
2276 init_registers(dev);
2277 spin_unlock_irqrestore(&rp->lock, flags);
2278
2279 netif_device_attach(dev);
2280
2281 return 0;
2282}
2283#endif /* CONFIG_PM */
2284
2285static struct pci_driver rhine_driver = {
2286 .name = DRV_NAME,
2287 .id_table = rhine_pci_tbl,
2288 .probe = rhine_init_one,
2289 .remove = __devexit_p(rhine_remove_one),
2290#ifdef CONFIG_PM
2291 .suspend = rhine_suspend,
2292 .resume = rhine_resume,
2293#endif /* CONFIG_PM */
2294 .shutdown = rhine_shutdown,
2295};
2296
2297static struct dmi_system_id __initdata rhine_dmi_table[] = {
2298 {
2299 .ident = "EPIA-M",
2300 .matches = {
2301 DMI_MATCH(DMI_BIOS_VENDOR, "Award Software International, Inc."),
2302 DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
2303 },
2304 },
2305 {
2306 .ident = "KV7",
2307 .matches = {
2308 DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies, LTD"),
2309 DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
2310 },
2311 },
2312 { NULL }
2313};
2314
2315static int __init rhine_init(void)
2316{
2317/* when a module, this is printed whether or not devices are found in probe */
2318#ifdef MODULE
2319 pr_info("%s\n", version);
2320#endif
2321 if (dmi_check_system(rhine_dmi_table)) {
2322 /* these BIOSes fail at PXE boot if chip is in D3 */
2323 avoid_D3 = 1;
2324 pr_warn("Broken BIOS detected, avoid_D3 enabled\n");
2325 }
2326 else if (avoid_D3)
2327 pr_info("avoid_D3 set\n");
2328
2329 return pci_register_driver(&rhine_driver);
2330}
2331
2332
2333static void __exit rhine_cleanup(void)
2334{
2335 pci_unregister_driver(&rhine_driver);
2336}
2337
2338
2339module_init(rhine_init);
2340module_exit(rhine_cleanup);
diff --git a/drivers/net/ethernet/via/via-velocity.c b/drivers/net/ethernet/via/via-velocity.c
new file mode 100644
index 000000000000..490ec5b2775a
--- /dev/null
+++ b/drivers/net/ethernet/via/via-velocity.c
@@ -0,0 +1,3592 @@
1/*
2 * This code is derived from the VIA reference driver (copyright message
3 * below) provided to Red Hat by VIA Networking Technologies, Inc. for
4 * addition to the Linux kernel.
5 *
6 * The code has been merged into one source file, cleaned up to follow
7 * Linux coding style, ported to the Linux 2.6 kernel tree and cleaned
8 * for 64bit hardware platforms.
9 *
10 * TODO
11 * rx_copybreak/alignment
12 * More testing
13 *
14 * The changes are (c) Copyright 2004, Red Hat Inc. <alan@lxorguk.ukuu.org.uk>
15 * Additional fixes and clean up: Francois Romieu
16 *
17 * This source has not been verified for use in safety critical systems.
18 *
19 * Please direct queries about the revamped driver to the linux-kernel
20 * list not VIA.
21 *
22 * Original code:
23 *
24 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
25 * All rights reserved.
26 *
27 * This software may be redistributed and/or modified under
28 * the terms of the GNU General Public License as published by the Free
29 * Software Foundation; either version 2 of the License, or
30 * any later version.
31 *
32 * This program is distributed in the hope that it will be useful, but
33 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
34 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
35 * for more details.
36 *
37 * Author: Chuang Liang-Shing, AJ Jiang
38 *
39 * Date: Jan 24, 2003
40 *
41 * MODULE_LICENSE("GPL");
42 *
43 */
44
45#include <linux/module.h>
46#include <linux/types.h>
47#include <linux/bitops.h>
48#include <linux/init.h>
49#include <linux/mm.h>
50#include <linux/errno.h>
51#include <linux/ioport.h>
52#include <linux/pci.h>
53#include <linux/kernel.h>
54#include <linux/netdevice.h>
55#include <linux/etherdevice.h>
56#include <linux/skbuff.h>
57#include <linux/delay.h>
58#include <linux/timer.h>
59#include <linux/slab.h>
60#include <linux/interrupt.h>
61#include <linux/string.h>
62#include <linux/wait.h>
63#include <linux/io.h>
64#include <linux/if.h>
65#include <linux/uaccess.h>
66#include <linux/proc_fs.h>
67#include <linux/inetdevice.h>
68#include <linux/reboot.h>
69#include <linux/ethtool.h>
70#include <linux/mii.h>
71#include <linux/in.h>
72#include <linux/if_arp.h>
73#include <linux/if_vlan.h>
74#include <linux/ip.h>
75#include <linux/tcp.h>
76#include <linux/udp.h>
77#include <linux/crc-ccitt.h>
78#include <linux/crc32.h>
79
80#include "via-velocity.h"
81
82
83static int velocity_nics;
84static int msglevel = MSG_LEVEL_INFO;
85
86/**
87 * mac_get_cam_mask - Read a CAM mask
88 * @regs: register block for this velocity
89 * @mask: buffer to store mask
90 *
91 * Fetch the mask bits of the selected CAM and store them into the
92 * provided mask buffer.
93 */
94static void mac_get_cam_mask(struct mac_regs __iomem *regs, u8 *mask)
95{
96 int i;
97
98 /* Select CAM mask */
99 BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
100
101 writeb(0, &regs->CAMADDR);
102
103 /* read mask */
104 for (i = 0; i < 8; i++)
105 *mask++ = readb(&(regs->MARCAM[i]));
106
107 /* disable CAMEN */
108 writeb(0, &regs->CAMADDR);
109
110 /* Select mar */
111 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
112}
113
114/**
115 * mac_set_cam_mask - Set a CAM mask
116 * @regs: register block for this velocity
117 * @mask: CAM mask to load
118 *
119 * Store a new mask into a CAM
120 */
121static void mac_set_cam_mask(struct mac_regs __iomem *regs, u8 *mask)
122{
123 int i;
124 /* Select CAM mask */
125 BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
126
127 writeb(CAMADDR_CAMEN, &regs->CAMADDR);
128
129 for (i = 0; i < 8; i++)
130 writeb(*mask++, &(regs->MARCAM[i]));
131
132 /* disable CAMEN */
133 writeb(0, &regs->CAMADDR);
134
135 /* Select mar */
136 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
137}
138
139static void mac_set_vlan_cam_mask(struct mac_regs __iomem *regs, u8 *mask)
140{
141 int i;
142 /* Select CAM mask */
143 BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
144
145 writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL, &regs->CAMADDR);
146
147 for (i = 0; i < 8; i++)
148 writeb(*mask++, &(regs->MARCAM[i]));
149
150 /* disable CAMEN */
151 writeb(0, &regs->CAMADDR);
152
153 /* Select mar */
154 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
155}
156
157/**
158 * mac_set_cam - set CAM data
159 * @regs: register block of this velocity
160 * @idx: Cam index
161 * @addr: 2 or 6 bytes of CAM data
162 *
163 * Load an address or vlan tag into a CAM
164 */
165static void mac_set_cam(struct mac_regs __iomem *regs, int idx, const u8 *addr)
166{
167 int i;
168
169 /* Select CAM mask */
170 BYTE_REG_BITS_SET(CAMCR_PS_CAM_DATA, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
171
172 idx &= (64 - 1);
173
174 writeb(CAMADDR_CAMEN | idx, &regs->CAMADDR);
175
176 for (i = 0; i < 6; i++)
177 writeb(*addr++, &(regs->MARCAM[i]));
178
179 BYTE_REG_BITS_ON(CAMCR_CAMWR, &regs->CAMCR);
180
181 udelay(10);
182
183 writeb(0, &regs->CAMADDR);
184
185 /* Select mar */
186 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
187}
188
189static void mac_set_vlan_cam(struct mac_regs __iomem *regs, int idx,
190 const u8 *addr)
191{
192
193 /* Select CAM mask */
194 BYTE_REG_BITS_SET(CAMCR_PS_CAM_DATA, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
195
196 idx &= (64 - 1);
197
198 writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL | idx, &regs->CAMADDR);
199 writew(*((u16 *) addr), &regs->MARCAM[0]);
200
201 BYTE_REG_BITS_ON(CAMCR_CAMWR, &regs->CAMCR);
202
203 udelay(10);
204
205 writeb(0, &regs->CAMADDR);
206
207 /* Select mar */
208 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, &regs->CAMCR);
209}
210
211
212/**
213 * mac_wol_reset - reset WOL after exiting low power
214 * @regs: register block of this velocity
215 *
216 * Called after we drop out of wake on lan mode in order to
217 * reset the Wake on lan features. This function doesn't restore
218 * the rest of the logic from the result of sleep/wakeup
219 */
220static void mac_wol_reset(struct mac_regs __iomem *regs)
221{
222
223 /* Turn off SWPTAG right after leaving power mode */
224 BYTE_REG_BITS_OFF(STICKHW_SWPTAG, &regs->STICKHW);
225 /* clear sticky bits */
226 BYTE_REG_BITS_OFF((STICKHW_DS1 | STICKHW_DS0), &regs->STICKHW);
227
228 BYTE_REG_BITS_OFF(CHIPGCR_FCGMII, &regs->CHIPGCR);
229 BYTE_REG_BITS_OFF(CHIPGCR_FCMODE, &regs->CHIPGCR);
230 /* disable force PME-enable */
231 writeb(WOLCFG_PMEOVR, &regs->WOLCFGClr);
232 /* disable power-event config bit */
233 writew(0xFFFF, &regs->WOLCRClr);
234 /* clear power status */
235 writew(0xFFFF, &regs->WOLSRClr);
236}
237
238static const struct ethtool_ops velocity_ethtool_ops;
239
240/*
241 Define module options
242*/
243
244MODULE_AUTHOR("VIA Networking Technologies, Inc.");
245MODULE_LICENSE("GPL");
246MODULE_DESCRIPTION("VIA Networking Velocity Family Gigabit Ethernet Adapter Driver");
247
248#define VELOCITY_PARAM(N, D) \
249 static int N[MAX_UNITS] = OPTION_DEFAULT;\
250 module_param_array(N, int, NULL, 0); \
251 MODULE_PARM_DESC(N, D);
252
253#define RX_DESC_MIN 64
254#define RX_DESC_MAX 255
255#define RX_DESC_DEF 64
256VELOCITY_PARAM(RxDescriptors, "Number of receive descriptors");
257
258#define TX_DESC_MIN 16
259#define TX_DESC_MAX 256
260#define TX_DESC_DEF 64
261VELOCITY_PARAM(TxDescriptors, "Number of transmit descriptors");
262
263#define RX_THRESH_MIN 0
264#define RX_THRESH_MAX 3
265#define RX_THRESH_DEF 0
266/* rx_thresh[] is used for controlling the receive fifo threshold.
267 0: indicate the rxfifo threshold is 128 bytes.
268 1: indicate the rxfifo threshold is 512 bytes.
269 2: indicate the rxfifo threshold is 1024 bytes.
270 3: indicate the rxfifo threshold is store & forward.
271*/
272VELOCITY_PARAM(rx_thresh, "Receive fifo threshold");
273
274#define DMA_LENGTH_MIN 0
275#define DMA_LENGTH_MAX 7
276#define DMA_LENGTH_DEF 6
277
278/* DMA_length[] is used for controlling the DMA length
279 0: 8 DWORDs
280 1: 16 DWORDs
281 2: 32 DWORDs
282 3: 64 DWORDs
283 4: 128 DWORDs
284 5: 256 DWORDs
285 6: SF(flush till emply)
286 7: SF(flush till emply)
287*/
288VELOCITY_PARAM(DMA_length, "DMA length");
289
290#define IP_ALIG_DEF 0
291/* IP_byte_align[] is used for IP header DWORD byte aligned
292 0: indicate the IP header won't be DWORD byte aligned.(Default) .
293 1: indicate the IP header will be DWORD byte aligned.
294 In some environment, the IP header should be DWORD byte aligned,
295 or the packet will be droped when we receive it. (eg: IPVS)
296*/
297VELOCITY_PARAM(IP_byte_align, "Enable IP header dword aligned");
298
299#define FLOW_CNTL_DEF 1
300#define FLOW_CNTL_MIN 1
301#define FLOW_CNTL_MAX 5
302
303/* flow_control[] is used for setting the flow control ability of NIC.
304 1: hardware deafult - AUTO (default). Use Hardware default value in ANAR.
305 2: enable TX flow control.
306 3: enable RX flow control.
307 4: enable RX/TX flow control.
308 5: disable
309*/
310VELOCITY_PARAM(flow_control, "Enable flow control ability");
311
312#define MED_LNK_DEF 0
313#define MED_LNK_MIN 0
314#define MED_LNK_MAX 5
315/* speed_duplex[] is used for setting the speed and duplex mode of NIC.
316 0: indicate autonegotiation for both speed and duplex mode
317 1: indicate 100Mbps half duplex mode
318 2: indicate 100Mbps full duplex mode
319 3: indicate 10Mbps half duplex mode
320 4: indicate 10Mbps full duplex mode
321 5: indicate 1000Mbps full duplex mode
322
323 Note:
324 if EEPROM have been set to the force mode, this option is ignored
325 by driver.
326*/
327VELOCITY_PARAM(speed_duplex, "Setting the speed and duplex mode");
328
329#define VAL_PKT_LEN_DEF 0
330/* ValPktLen[] is used for setting the checksum offload ability of NIC.
331 0: Receive frame with invalid layer 2 length (Default)
332 1: Drop frame with invalid layer 2 length
333*/
334VELOCITY_PARAM(ValPktLen, "Receiving or Drop invalid 802.3 frame");
335
336#define WOL_OPT_DEF 0
337#define WOL_OPT_MIN 0
338#define WOL_OPT_MAX 7
339/* wol_opts[] is used for controlling wake on lan behavior.
340 0: Wake up if recevied a magic packet. (Default)
341 1: Wake up if link status is on/off.
342 2: Wake up if recevied an arp packet.
343 4: Wake up if recevied any unicast packet.
344 Those value can be sumed up to support more than one option.
345*/
346VELOCITY_PARAM(wol_opts, "Wake On Lan options");
347
348static int rx_copybreak = 200;
349module_param(rx_copybreak, int, 0644);
350MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
351
352/*
353 * Internal board variants. At the moment we have only one
354 */
355static struct velocity_info_tbl chip_info_table[] = {
356 {CHIP_TYPE_VT6110, "VIA Networking Velocity Family Gigabit Ethernet Adapter", 1, 0x00FFFFFFUL},
357 { }
358};
359
360/*
361 * Describe the PCI device identifiers that we support in this
362 * device driver. Used for hotplug autoloading.
363 */
364static DEFINE_PCI_DEVICE_TABLE(velocity_id_table) = {
365 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_612X) },
366 { }
367};
368
369MODULE_DEVICE_TABLE(pci, velocity_id_table);
370
371/**
372 * get_chip_name - identifier to name
373 * @id: chip identifier
374 *
375 * Given a chip identifier return a suitable description. Returns
376 * a pointer a static string valid while the driver is loaded.
377 */
378static const char __devinit *get_chip_name(enum chip_type chip_id)
379{
380 int i;
381 for (i = 0; chip_info_table[i].name != NULL; i++)
382 if (chip_info_table[i].chip_id == chip_id)
383 break;
384 return chip_info_table[i].name;
385}
386
387/**
388 * velocity_remove1 - device unplug
389 * @pdev: PCI device being removed
390 *
391 * Device unload callback. Called on an unplug or on module
392 * unload for each active device that is present. Disconnects
393 * the device from the network layer and frees all the resources
394 */
395static void __devexit velocity_remove1(struct pci_dev *pdev)
396{
397 struct net_device *dev = pci_get_drvdata(pdev);
398 struct velocity_info *vptr = netdev_priv(dev);
399
400 unregister_netdev(dev);
401 iounmap(vptr->mac_regs);
402 pci_release_regions(pdev);
403 pci_disable_device(pdev);
404 pci_set_drvdata(pdev, NULL);
405 free_netdev(dev);
406
407 velocity_nics--;
408}
409
410/**
411 * velocity_set_int_opt - parser for integer options
412 * @opt: pointer to option value
413 * @val: value the user requested (or -1 for default)
414 * @min: lowest value allowed
415 * @max: highest value allowed
416 * @def: default value
417 * @name: property name
418 * @dev: device name
419 *
420 * Set an integer property in the module options. This function does
421 * all the verification and checking as well as reporting so that
422 * we don't duplicate code for each option.
423 */
424static void __devinit velocity_set_int_opt(int *opt, int val, int min, int max, int def, char *name, const char *devname)
425{
426 if (val == -1)
427 *opt = def;
428 else if (val < min || val > max) {
429 VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: the value of parameter %s is invalid, the valid range is (%d-%d)\n",
430 devname, name, min, max);
431 *opt = def;
432 } else {
433 VELOCITY_PRT(MSG_LEVEL_INFO, KERN_INFO "%s: set value of parameter %s to %d\n",
434 devname, name, val);
435 *opt = val;
436 }
437}
438
439/**
440 * velocity_set_bool_opt - parser for boolean options
441 * @opt: pointer to option value
442 * @val: value the user requested (or -1 for default)
443 * @def: default value (yes/no)
444 * @flag: numeric value to set for true.
445 * @name: property name
446 * @dev: device name
447 *
448 * Set a boolean property in the module options. This function does
449 * all the verification and checking as well as reporting so that
450 * we don't duplicate code for each option.
451 */
452static void __devinit velocity_set_bool_opt(u32 *opt, int val, int def, u32 flag, char *name, const char *devname)
453{
454 (*opt) &= (~flag);
455 if (val == -1)
456 *opt |= (def ? flag : 0);
457 else if (val < 0 || val > 1) {
458 printk(KERN_NOTICE "%s: the value of parameter %s is invalid, the valid range is (0-1)\n",
459 devname, name);
460 *opt |= (def ? flag : 0);
461 } else {
462 printk(KERN_INFO "%s: set parameter %s to %s\n",
463 devname, name, val ? "TRUE" : "FALSE");
464 *opt |= (val ? flag : 0);
465 }
466}
467
468/**
469 * velocity_get_options - set options on device
470 * @opts: option structure for the device
471 * @index: index of option to use in module options array
472 * @devname: device name
473 *
474 * Turn the module and command options into a single structure
475 * for the current device
476 */
477static void __devinit velocity_get_options(struct velocity_opt *opts, int index, const char *devname)
478{
479
480 velocity_set_int_opt(&opts->rx_thresh, rx_thresh[index], RX_THRESH_MIN, RX_THRESH_MAX, RX_THRESH_DEF, "rx_thresh", devname);
481 velocity_set_int_opt(&opts->DMA_length, DMA_length[index], DMA_LENGTH_MIN, DMA_LENGTH_MAX, DMA_LENGTH_DEF, "DMA_length", devname);
482 velocity_set_int_opt(&opts->numrx, RxDescriptors[index], RX_DESC_MIN, RX_DESC_MAX, RX_DESC_DEF, "RxDescriptors", devname);
483 velocity_set_int_opt(&opts->numtx, TxDescriptors[index], TX_DESC_MIN, TX_DESC_MAX, TX_DESC_DEF, "TxDescriptors", devname);
484
485 velocity_set_int_opt(&opts->flow_cntl, flow_control[index], FLOW_CNTL_MIN, FLOW_CNTL_MAX, FLOW_CNTL_DEF, "flow_control", devname);
486 velocity_set_bool_opt(&opts->flags, IP_byte_align[index], IP_ALIG_DEF, VELOCITY_FLAGS_IP_ALIGN, "IP_byte_align", devname);
487 velocity_set_bool_opt(&opts->flags, ValPktLen[index], VAL_PKT_LEN_DEF, VELOCITY_FLAGS_VAL_PKT_LEN, "ValPktLen", devname);
488 velocity_set_int_opt((int *) &opts->spd_dpx, speed_duplex[index], MED_LNK_MIN, MED_LNK_MAX, MED_LNK_DEF, "Media link mode", devname);
489 velocity_set_int_opt((int *) &opts->wol_opts, wol_opts[index], WOL_OPT_MIN, WOL_OPT_MAX, WOL_OPT_DEF, "Wake On Lan options", devname);
490 opts->numrx = (opts->numrx & ~3);
491}
492
493/**
494 * velocity_init_cam_filter - initialise CAM
495 * @vptr: velocity to program
496 *
497 * Initialize the content addressable memory used for filters. Load
498 * appropriately according to the presence of VLAN
499 */
500static void velocity_init_cam_filter(struct velocity_info *vptr)
501{
502 struct mac_regs __iomem *regs = vptr->mac_regs;
503 unsigned int vid, i = 0;
504
505 /* Turn on MCFG_PQEN, turn off MCFG_RTGOPT */
506 WORD_REG_BITS_SET(MCFG_PQEN, MCFG_RTGOPT, &regs->MCFG);
507 WORD_REG_BITS_ON(MCFG_VIDFR, &regs->MCFG);
508
509 /* Disable all CAMs */
510 memset(vptr->vCAMmask, 0, sizeof(u8) * 8);
511 memset(vptr->mCAMmask, 0, sizeof(u8) * 8);
512 mac_set_vlan_cam_mask(regs, vptr->vCAMmask);
513 mac_set_cam_mask(regs, vptr->mCAMmask);
514
515 /* Enable VCAMs */
516
517 if (test_bit(0, vptr->active_vlans))
518 WORD_REG_BITS_ON(MCFG_RTGOPT, &regs->MCFG);
519
520 for_each_set_bit(vid, vptr->active_vlans, VLAN_N_VID) {
521 mac_set_vlan_cam(regs, i, (u8 *) &vid);
522 vptr->vCAMmask[i / 8] |= 0x1 << (i % 8);
523 if (++i >= VCAM_SIZE)
524 break;
525 }
526 mac_set_vlan_cam_mask(regs, vptr->vCAMmask);
527}
528
529static void velocity_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)
530{
531 struct velocity_info *vptr = netdev_priv(dev);
532
533 spin_lock_irq(&vptr->lock);
534 set_bit(vid, vptr->active_vlans);
535 velocity_init_cam_filter(vptr);
536 spin_unlock_irq(&vptr->lock);
537}
538
539static void velocity_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
540{
541 struct velocity_info *vptr = netdev_priv(dev);
542
543 spin_lock_irq(&vptr->lock);
544 clear_bit(vid, vptr->active_vlans);
545 velocity_init_cam_filter(vptr);
546 spin_unlock_irq(&vptr->lock);
547}
548
549static void velocity_init_rx_ring_indexes(struct velocity_info *vptr)
550{
551 vptr->rx.dirty = vptr->rx.filled = vptr->rx.curr = 0;
552}
553
554/**
555 * velocity_rx_reset - handle a receive reset
556 * @vptr: velocity we are resetting
557 *
558 * Reset the ownership and status for the receive ring side.
559 * Hand all the receive queue to the NIC.
560 */
561static void velocity_rx_reset(struct velocity_info *vptr)
562{
563
564 struct mac_regs __iomem *regs = vptr->mac_regs;
565 int i;
566
567 velocity_init_rx_ring_indexes(vptr);
568
569 /*
570 * Init state, all RD entries belong to the NIC
571 */
572 for (i = 0; i < vptr->options.numrx; ++i)
573 vptr->rx.ring[i].rdesc0.len |= OWNED_BY_NIC;
574
575 writew(vptr->options.numrx, &regs->RBRDU);
576 writel(vptr->rx.pool_dma, &regs->RDBaseLo);
577 writew(0, &regs->RDIdx);
578 writew(vptr->options.numrx - 1, &regs->RDCSize);
579}
580
581/**
582 * velocity_get_opt_media_mode - get media selection
583 * @vptr: velocity adapter
584 *
585 * Get the media mode stored in EEPROM or module options and load
586 * mii_status accordingly. The requested link state information
587 * is also returned.
588 */
589static u32 velocity_get_opt_media_mode(struct velocity_info *vptr)
590{
591 u32 status = 0;
592
593 switch (vptr->options.spd_dpx) {
594 case SPD_DPX_AUTO:
595 status = VELOCITY_AUTONEG_ENABLE;
596 break;
597 case SPD_DPX_100_FULL:
598 status = VELOCITY_SPEED_100 | VELOCITY_DUPLEX_FULL;
599 break;
600 case SPD_DPX_10_FULL:
601 status = VELOCITY_SPEED_10 | VELOCITY_DUPLEX_FULL;
602 break;
603 case SPD_DPX_100_HALF:
604 status = VELOCITY_SPEED_100;
605 break;
606 case SPD_DPX_10_HALF:
607 status = VELOCITY_SPEED_10;
608 break;
609 case SPD_DPX_1000_FULL:
610 status = VELOCITY_SPEED_1000 | VELOCITY_DUPLEX_FULL;
611 break;
612 }
613 vptr->mii_status = status;
614 return status;
615}
616
617/**
618 * safe_disable_mii_autopoll - autopoll off
619 * @regs: velocity registers
620 *
621 * Turn off the autopoll and wait for it to disable on the chip
622 */
623static void safe_disable_mii_autopoll(struct mac_regs __iomem *regs)
624{
625 u16 ww;
626
627 /* turn off MAUTO */
628 writeb(0, &regs->MIICR);
629 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
630 udelay(1);
631 if (BYTE_REG_BITS_IS_ON(MIISR_MIDLE, &regs->MIISR))
632 break;
633 }
634}
635
636/**
637 * enable_mii_autopoll - turn on autopolling
638 * @regs: velocity registers
639 *
640 * Enable the MII link status autopoll feature on the Velocity
641 * hardware. Wait for it to enable.
642 */
643static void enable_mii_autopoll(struct mac_regs __iomem *regs)
644{
645 int ii;
646
647 writeb(0, &(regs->MIICR));
648 writeb(MIIADR_SWMPL, &regs->MIIADR);
649
650 for (ii = 0; ii < W_MAX_TIMEOUT; ii++) {
651 udelay(1);
652 if (BYTE_REG_BITS_IS_ON(MIISR_MIDLE, &regs->MIISR))
653 break;
654 }
655
656 writeb(MIICR_MAUTO, &regs->MIICR);
657
658 for (ii = 0; ii < W_MAX_TIMEOUT; ii++) {
659 udelay(1);
660 if (!BYTE_REG_BITS_IS_ON(MIISR_MIDLE, &regs->MIISR))
661 break;
662 }
663
664}
665
666/**
667 * velocity_mii_read - read MII data
668 * @regs: velocity registers
669 * @index: MII register index
670 * @data: buffer for received data
671 *
672 * Perform a single read of an MII 16bit register. Returns zero
673 * on success or -ETIMEDOUT if the PHY did not respond.
674 */
675static int velocity_mii_read(struct mac_regs __iomem *regs, u8 index, u16 *data)
676{
677 u16 ww;
678
679 /*
680 * Disable MIICR_MAUTO, so that mii addr can be set normally
681 */
682 safe_disable_mii_autopoll(regs);
683
684 writeb(index, &regs->MIIADR);
685
686 BYTE_REG_BITS_ON(MIICR_RCMD, &regs->MIICR);
687
688 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
689 if (!(readb(&regs->MIICR) & MIICR_RCMD))
690 break;
691 }
692
693 *data = readw(&regs->MIIDATA);
694
695 enable_mii_autopoll(regs);
696 if (ww == W_MAX_TIMEOUT)
697 return -ETIMEDOUT;
698 return 0;
699}
700
701/**
702 * mii_check_media_mode - check media state
703 * @regs: velocity registers
704 *
705 * Check the current MII status and determine the link status
706 * accordingly
707 */
708static u32 mii_check_media_mode(struct mac_regs __iomem *regs)
709{
710 u32 status = 0;
711 u16 ANAR;
712
713 if (!MII_REG_BITS_IS_ON(BMSR_LSTATUS, MII_BMSR, regs))
714 status |= VELOCITY_LINK_FAIL;
715
716 if (MII_REG_BITS_IS_ON(ADVERTISE_1000FULL, MII_CTRL1000, regs))
717 status |= VELOCITY_SPEED_1000 | VELOCITY_DUPLEX_FULL;
718 else if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF, MII_CTRL1000, regs))
719 status |= (VELOCITY_SPEED_1000);
720 else {
721 velocity_mii_read(regs, MII_ADVERTISE, &ANAR);
722 if (ANAR & ADVERTISE_100FULL)
723 status |= (VELOCITY_SPEED_100 | VELOCITY_DUPLEX_FULL);
724 else if (ANAR & ADVERTISE_100HALF)
725 status |= VELOCITY_SPEED_100;
726 else if (ANAR & ADVERTISE_10FULL)
727 status |= (VELOCITY_SPEED_10 | VELOCITY_DUPLEX_FULL);
728 else
729 status |= (VELOCITY_SPEED_10);
730 }
731
732 if (MII_REG_BITS_IS_ON(BMCR_ANENABLE, MII_BMCR, regs)) {
733 velocity_mii_read(regs, MII_ADVERTISE, &ANAR);
734 if ((ANAR & (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF))
735 == (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF)) {
736 if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF | ADVERTISE_1000FULL, MII_CTRL1000, regs))
737 status |= VELOCITY_AUTONEG_ENABLE;
738 }
739 }
740
741 return status;
742}
743
744/**
745 * velocity_mii_write - write MII data
746 * @regs: velocity registers
747 * @index: MII register index
748 * @data: 16bit data for the MII register
749 *
750 * Perform a single write to an MII 16bit register. Returns zero
751 * on success or -ETIMEDOUT if the PHY did not respond.
752 */
753static int velocity_mii_write(struct mac_regs __iomem *regs, u8 mii_addr, u16 data)
754{
755 u16 ww;
756
757 /*
758 * Disable MIICR_MAUTO, so that mii addr can be set normally
759 */
760 safe_disable_mii_autopoll(regs);
761
762 /* MII reg offset */
763 writeb(mii_addr, &regs->MIIADR);
764 /* set MII data */
765 writew(data, &regs->MIIDATA);
766
767 /* turn on MIICR_WCMD */
768 BYTE_REG_BITS_ON(MIICR_WCMD, &regs->MIICR);
769
770 /* W_MAX_TIMEOUT is the timeout period */
771 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
772 udelay(5);
773 if (!(readb(&regs->MIICR) & MIICR_WCMD))
774 break;
775 }
776 enable_mii_autopoll(regs);
777
778 if (ww == W_MAX_TIMEOUT)
779 return -ETIMEDOUT;
780 return 0;
781}
782
783/**
784 * set_mii_flow_control - flow control setup
785 * @vptr: velocity interface
786 *
787 * Set up the flow control on this interface according to
788 * the supplied user/eeprom options.
789 */
790static void set_mii_flow_control(struct velocity_info *vptr)
791{
792 /*Enable or Disable PAUSE in ANAR */
793 switch (vptr->options.flow_cntl) {
794 case FLOW_CNTL_TX:
795 MII_REG_BITS_OFF(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs);
796 MII_REG_BITS_ON(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs);
797 break;
798
799 case FLOW_CNTL_RX:
800 MII_REG_BITS_ON(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs);
801 MII_REG_BITS_ON(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs);
802 break;
803
804 case FLOW_CNTL_TX_RX:
805 MII_REG_BITS_ON(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs);
806 MII_REG_BITS_OFF(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs);
807 break;
808
809 case FLOW_CNTL_DISABLE:
810 MII_REG_BITS_OFF(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs);
811 MII_REG_BITS_OFF(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs);
812 break;
813 default:
814 break;
815 }
816}
817
818/**
819 * mii_set_auto_on - autonegotiate on
820 * @vptr: velocity
821 *
822 * Enable autonegotation on this interface
823 */
824static void mii_set_auto_on(struct velocity_info *vptr)
825{
826 if (MII_REG_BITS_IS_ON(BMCR_ANENABLE, MII_BMCR, vptr->mac_regs))
827 MII_REG_BITS_ON(BMCR_ANRESTART, MII_BMCR, vptr->mac_regs);
828 else
829 MII_REG_BITS_ON(BMCR_ANENABLE, MII_BMCR, vptr->mac_regs);
830}
831
832static u32 check_connection_type(struct mac_regs __iomem *regs)
833{
834 u32 status = 0;
835 u8 PHYSR0;
836 u16 ANAR;
837 PHYSR0 = readb(&regs->PHYSR0);
838
839 /*
840 if (!(PHYSR0 & PHYSR0_LINKGD))
841 status|=VELOCITY_LINK_FAIL;
842 */
843
844 if (PHYSR0 & PHYSR0_FDPX)
845 status |= VELOCITY_DUPLEX_FULL;
846
847 if (PHYSR0 & PHYSR0_SPDG)
848 status |= VELOCITY_SPEED_1000;
849 else if (PHYSR0 & PHYSR0_SPD10)
850 status |= VELOCITY_SPEED_10;
851 else
852 status |= VELOCITY_SPEED_100;
853
854 if (MII_REG_BITS_IS_ON(BMCR_ANENABLE, MII_BMCR, regs)) {
855 velocity_mii_read(regs, MII_ADVERTISE, &ANAR);
856 if ((ANAR & (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF))
857 == (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF)) {
858 if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF | ADVERTISE_1000FULL, MII_CTRL1000, regs))
859 status |= VELOCITY_AUTONEG_ENABLE;
860 }
861 }
862
863 return status;
864}
865
866/**
867 * velocity_set_media_mode - set media mode
868 * @mii_status: old MII link state
869 *
870 * Check the media link state and configure the flow control
871 * PHY and also velocity hardware setup accordingly. In particular
872 * we need to set up CD polling and frame bursting.
873 */
874static int velocity_set_media_mode(struct velocity_info *vptr, u32 mii_status)
875{
876 u32 curr_status;
877 struct mac_regs __iomem *regs = vptr->mac_regs;
878
879 vptr->mii_status = mii_check_media_mode(vptr->mac_regs);
880 curr_status = vptr->mii_status & (~VELOCITY_LINK_FAIL);
881
882 /* Set mii link status */
883 set_mii_flow_control(vptr);
884
885 /*
886 Check if new status is consistent with current status
887 if (((mii_status & curr_status) & VELOCITY_AUTONEG_ENABLE) ||
888 (mii_status==curr_status)) {
889 vptr->mii_status=mii_check_media_mode(vptr->mac_regs);
890 vptr->mii_status=check_connection_type(vptr->mac_regs);
891 VELOCITY_PRT(MSG_LEVEL_INFO, "Velocity link no change\n");
892 return 0;
893 }
894 */
895
896 if (PHYID_GET_PHY_ID(vptr->phy_id) == PHYID_CICADA_CS8201)
897 MII_REG_BITS_ON(AUXCR_MDPPS, MII_NCONFIG, vptr->mac_regs);
898
899 /*
900 * If connection type is AUTO
901 */
902 if (mii_status & VELOCITY_AUTONEG_ENABLE) {
903 VELOCITY_PRT(MSG_LEVEL_INFO, "Velocity is AUTO mode\n");
904 /* clear force MAC mode bit */
905 BYTE_REG_BITS_OFF(CHIPGCR_FCMODE, &regs->CHIPGCR);
906 /* set duplex mode of MAC according to duplex mode of MII */
907 MII_REG_BITS_ON(ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF, MII_ADVERTISE, vptr->mac_regs);
908 MII_REG_BITS_ON(ADVERTISE_1000FULL | ADVERTISE_1000HALF, MII_CTRL1000, vptr->mac_regs);
909 MII_REG_BITS_ON(BMCR_SPEED1000, MII_BMCR, vptr->mac_regs);
910
911 /* enable AUTO-NEGO mode */
912 mii_set_auto_on(vptr);
913 } else {
914 u16 CTRL1000;
915 u16 ANAR;
916 u8 CHIPGCR;
917
918 /*
919 * 1. if it's 3119, disable frame bursting in halfduplex mode
920 * and enable it in fullduplex mode
921 * 2. set correct MII/GMII and half/full duplex mode in CHIPGCR
922 * 3. only enable CD heart beat counter in 10HD mode
923 */
924
925 /* set force MAC mode bit */
926 BYTE_REG_BITS_ON(CHIPGCR_FCMODE, &regs->CHIPGCR);
927
928 CHIPGCR = readb(&regs->CHIPGCR);
929
930 if (mii_status & VELOCITY_SPEED_1000)
931 CHIPGCR |= CHIPGCR_FCGMII;
932 else
933 CHIPGCR &= ~CHIPGCR_FCGMII;
934
935 if (mii_status & VELOCITY_DUPLEX_FULL) {
936 CHIPGCR |= CHIPGCR_FCFDX;
937 writeb(CHIPGCR, &regs->CHIPGCR);
938 VELOCITY_PRT(MSG_LEVEL_INFO, "set Velocity to forced full mode\n");
939 if (vptr->rev_id < REV_ID_VT3216_A0)
940 BYTE_REG_BITS_OFF(TCR_TB2BDIS, &regs->TCR);
941 } else {
942 CHIPGCR &= ~CHIPGCR_FCFDX;
943 VELOCITY_PRT(MSG_LEVEL_INFO, "set Velocity to forced half mode\n");
944 writeb(CHIPGCR, &regs->CHIPGCR);
945 if (vptr->rev_id < REV_ID_VT3216_A0)
946 BYTE_REG_BITS_ON(TCR_TB2BDIS, &regs->TCR);
947 }
948
949 velocity_mii_read(vptr->mac_regs, MII_CTRL1000, &CTRL1000);
950 CTRL1000 &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
951 if ((mii_status & VELOCITY_SPEED_1000) &&
952 (mii_status & VELOCITY_DUPLEX_FULL)) {
953 CTRL1000 |= ADVERTISE_1000FULL;
954 }
955 velocity_mii_write(vptr->mac_regs, MII_CTRL1000, CTRL1000);
956
957 if (!(mii_status & VELOCITY_DUPLEX_FULL) && (mii_status & VELOCITY_SPEED_10))
958 BYTE_REG_BITS_OFF(TESTCFG_HBDIS, &regs->TESTCFG);
959 else
960 BYTE_REG_BITS_ON(TESTCFG_HBDIS, &regs->TESTCFG);
961
962 /* MII_REG_BITS_OFF(BMCR_SPEED1000, MII_BMCR, vptr->mac_regs); */
963 velocity_mii_read(vptr->mac_regs, MII_ADVERTISE, &ANAR);
964 ANAR &= (~(ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF));
965 if (mii_status & VELOCITY_SPEED_100) {
966 if (mii_status & VELOCITY_DUPLEX_FULL)
967 ANAR |= ADVERTISE_100FULL;
968 else
969 ANAR |= ADVERTISE_100HALF;
970 } else if (mii_status & VELOCITY_SPEED_10) {
971 if (mii_status & VELOCITY_DUPLEX_FULL)
972 ANAR |= ADVERTISE_10FULL;
973 else
974 ANAR |= ADVERTISE_10HALF;
975 }
976 velocity_mii_write(vptr->mac_regs, MII_ADVERTISE, ANAR);
977 /* enable AUTO-NEGO mode */
978 mii_set_auto_on(vptr);
979 /* MII_REG_BITS_ON(BMCR_ANENABLE, MII_BMCR, vptr->mac_regs); */
980 }
981 /* vptr->mii_status=mii_check_media_mode(vptr->mac_regs); */
982 /* vptr->mii_status=check_connection_type(vptr->mac_regs); */
983 return VELOCITY_LINK_CHANGE;
984}
985
986/**
987 * velocity_print_link_status - link status reporting
988 * @vptr: velocity to report on
989 *
990 * Turn the link status of the velocity card into a kernel log
991 * description of the new link state, detailing speed and duplex
992 * status
993 */
994static void velocity_print_link_status(struct velocity_info *vptr)
995{
996
997 if (vptr->mii_status & VELOCITY_LINK_FAIL) {
998 VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: failed to detect cable link\n", vptr->dev->name);
999 } else if (vptr->options.spd_dpx == SPD_DPX_AUTO) {
1000 VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link auto-negotiation", vptr->dev->name);
1001
1002 if (vptr->mii_status & VELOCITY_SPEED_1000)
1003 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 1000M bps");
1004 else if (vptr->mii_status & VELOCITY_SPEED_100)
1005 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 100M bps");
1006 else
1007 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 10M bps");
1008
1009 if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
1010 VELOCITY_PRT(MSG_LEVEL_INFO, " full duplex\n");
1011 else
1012 VELOCITY_PRT(MSG_LEVEL_INFO, " half duplex\n");
1013 } else {
1014 VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link forced", vptr->dev->name);
1015 switch (vptr->options.spd_dpx) {
1016 case SPD_DPX_1000_FULL:
1017 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 1000M bps full duplex\n");
1018 break;
1019 case SPD_DPX_100_HALF:
1020 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 100M bps half duplex\n");
1021 break;
1022 case SPD_DPX_100_FULL:
1023 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 100M bps full duplex\n");
1024 break;
1025 case SPD_DPX_10_HALF:
1026 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 10M bps half duplex\n");
1027 break;
1028 case SPD_DPX_10_FULL:
1029 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 10M bps full duplex\n");
1030 break;
1031 default:
1032 break;
1033 }
1034 }
1035}
1036
1037/**
1038 * enable_flow_control_ability - flow control
1039 * @vptr: veloity to configure
1040 *
1041 * Set up flow control according to the flow control options
1042 * determined by the eeprom/configuration.
1043 */
1044static void enable_flow_control_ability(struct velocity_info *vptr)
1045{
1046
1047 struct mac_regs __iomem *regs = vptr->mac_regs;
1048
1049 switch (vptr->options.flow_cntl) {
1050
1051 case FLOW_CNTL_DEFAULT:
1052 if (BYTE_REG_BITS_IS_ON(PHYSR0_RXFLC, &regs->PHYSR0))
1053 writel(CR0_FDXRFCEN, &regs->CR0Set);
1054 else
1055 writel(CR0_FDXRFCEN, &regs->CR0Clr);
1056
1057 if (BYTE_REG_BITS_IS_ON(PHYSR0_TXFLC, &regs->PHYSR0))
1058 writel(CR0_FDXTFCEN, &regs->CR0Set);
1059 else
1060 writel(CR0_FDXTFCEN, &regs->CR0Clr);
1061 break;
1062
1063 case FLOW_CNTL_TX:
1064 writel(CR0_FDXTFCEN, &regs->CR0Set);
1065 writel(CR0_FDXRFCEN, &regs->CR0Clr);
1066 break;
1067
1068 case FLOW_CNTL_RX:
1069 writel(CR0_FDXRFCEN, &regs->CR0Set);
1070 writel(CR0_FDXTFCEN, &regs->CR0Clr);
1071 break;
1072
1073 case FLOW_CNTL_TX_RX:
1074 writel(CR0_FDXTFCEN, &regs->CR0Set);
1075 writel(CR0_FDXRFCEN, &regs->CR0Set);
1076 break;
1077
1078 case FLOW_CNTL_DISABLE:
1079 writel(CR0_FDXRFCEN, &regs->CR0Clr);
1080 writel(CR0_FDXTFCEN, &regs->CR0Clr);
1081 break;
1082
1083 default:
1084 break;
1085 }
1086
1087}
1088
1089/**
1090 * velocity_soft_reset - soft reset
1091 * @vptr: velocity to reset
1092 *
1093 * Kick off a soft reset of the velocity adapter and then poll
1094 * until the reset sequence has completed before returning.
1095 */
1096static int velocity_soft_reset(struct velocity_info *vptr)
1097{
1098 struct mac_regs __iomem *regs = vptr->mac_regs;
1099 int i = 0;
1100
1101 writel(CR0_SFRST, &regs->CR0Set);
1102
1103 for (i = 0; i < W_MAX_TIMEOUT; i++) {
1104 udelay(5);
1105 if (!DWORD_REG_BITS_IS_ON(CR0_SFRST, &regs->CR0Set))
1106 break;
1107 }
1108
1109 if (i == W_MAX_TIMEOUT) {
1110 writel(CR0_FORSRST, &regs->CR0Set);
1111 /* FIXME: PCI POSTING */
1112 /* delay 2ms */
1113 mdelay(2);
1114 }
1115 return 0;
1116}
1117
1118/**
1119 * velocity_set_multi - filter list change callback
1120 * @dev: network device
1121 *
1122 * Called by the network layer when the filter lists need to change
1123 * for a velocity adapter. Reload the CAMs with the new address
1124 * filter ruleset.
1125 */
1126static void velocity_set_multi(struct net_device *dev)
1127{
1128 struct velocity_info *vptr = netdev_priv(dev);
1129 struct mac_regs __iomem *regs = vptr->mac_regs;
1130 u8 rx_mode;
1131 int i;
1132 struct netdev_hw_addr *ha;
1133
1134 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1135 writel(0xffffffff, &regs->MARCAM[0]);
1136 writel(0xffffffff, &regs->MARCAM[4]);
1137 rx_mode = (RCR_AM | RCR_AB | RCR_PROM);
1138 } else if ((netdev_mc_count(dev) > vptr->multicast_limit) ||
1139 (dev->flags & IFF_ALLMULTI)) {
1140 writel(0xffffffff, &regs->MARCAM[0]);
1141 writel(0xffffffff, &regs->MARCAM[4]);
1142 rx_mode = (RCR_AM | RCR_AB);
1143 } else {
1144 int offset = MCAM_SIZE - vptr->multicast_limit;
1145 mac_get_cam_mask(regs, vptr->mCAMmask);
1146
1147 i = 0;
1148 netdev_for_each_mc_addr(ha, dev) {
1149 mac_set_cam(regs, i + offset, ha->addr);
1150 vptr->mCAMmask[(offset + i) / 8] |= 1 << ((offset + i) & 7);
1151 i++;
1152 }
1153
1154 mac_set_cam_mask(regs, vptr->mCAMmask);
1155 rx_mode = RCR_AM | RCR_AB | RCR_AP;
1156 }
1157 if (dev->mtu > 1500)
1158 rx_mode |= RCR_AL;
1159
1160 BYTE_REG_BITS_ON(rx_mode, &regs->RCR);
1161
1162}
1163
1164/*
1165 * MII access , media link mode setting functions
1166 */
1167
1168/**
1169 * mii_init - set up MII
1170 * @vptr: velocity adapter
1171 * @mii_status: links tatus
1172 *
1173 * Set up the PHY for the current link state.
1174 */
1175static void mii_init(struct velocity_info *vptr, u32 mii_status)
1176{
1177 u16 BMCR;
1178
1179 switch (PHYID_GET_PHY_ID(vptr->phy_id)) {
1180 case PHYID_CICADA_CS8201:
1181 /*
1182 * Reset to hardware default
1183 */
1184 MII_REG_BITS_OFF((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP), MII_ADVERTISE, vptr->mac_regs);
1185 /*
1186 * Turn on ECHODIS bit in NWay-forced full mode and turn it
1187 * off it in NWay-forced half mode for NWay-forced v.s.
1188 * legacy-forced issue.
1189 */
1190 if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
1191 MII_REG_BITS_ON(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs);
1192 else
1193 MII_REG_BITS_OFF(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs);
1194 /*
1195 * Turn on Link/Activity LED enable bit for CIS8201
1196 */
1197 MII_REG_BITS_ON(PLED_LALBE, MII_TPISTATUS, vptr->mac_regs);
1198 break;
1199 case PHYID_VT3216_32BIT:
1200 case PHYID_VT3216_64BIT:
1201 /*
1202 * Reset to hardware default
1203 */
1204 MII_REG_BITS_ON((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP), MII_ADVERTISE, vptr->mac_regs);
1205 /*
1206 * Turn on ECHODIS bit in NWay-forced full mode and turn it
1207 * off it in NWay-forced half mode for NWay-forced v.s.
1208 * legacy-forced issue
1209 */
1210 if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
1211 MII_REG_BITS_ON(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs);
1212 else
1213 MII_REG_BITS_OFF(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs);
1214 break;
1215
1216 case PHYID_MARVELL_1000:
1217 case PHYID_MARVELL_1000S:
1218 /*
1219 * Assert CRS on Transmit
1220 */
1221 MII_REG_BITS_ON(PSCR_ACRSTX, MII_REG_PSCR, vptr->mac_regs);
1222 /*
1223 * Reset to hardware default
1224 */
1225 MII_REG_BITS_ON((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP), MII_ADVERTISE, vptr->mac_regs);
1226 break;
1227 default:
1228 ;
1229 }
1230 velocity_mii_read(vptr->mac_regs, MII_BMCR, &BMCR);
1231 if (BMCR & BMCR_ISOLATE) {
1232 BMCR &= ~BMCR_ISOLATE;
1233 velocity_mii_write(vptr->mac_regs, MII_BMCR, BMCR);
1234 }
1235}
1236
1237/**
1238 * setup_queue_timers - Setup interrupt timers
1239 *
1240 * Setup interrupt frequency during suppression (timeout if the frame
1241 * count isn't filled).
1242 */
1243static void setup_queue_timers(struct velocity_info *vptr)
1244{
1245 /* Only for newer revisions */
1246 if (vptr->rev_id >= REV_ID_VT3216_A0) {
1247 u8 txqueue_timer = 0;
1248 u8 rxqueue_timer = 0;
1249
1250 if (vptr->mii_status & (VELOCITY_SPEED_1000 |
1251 VELOCITY_SPEED_100)) {
1252 txqueue_timer = vptr->options.txqueue_timer;
1253 rxqueue_timer = vptr->options.rxqueue_timer;
1254 }
1255
1256 writeb(txqueue_timer, &vptr->mac_regs->TQETMR);
1257 writeb(rxqueue_timer, &vptr->mac_regs->RQETMR);
1258 }
1259}
1260
1261/**
1262 * setup_adaptive_interrupts - Setup interrupt suppression
1263 *
1264 * @vptr velocity adapter
1265 *
1266 * The velocity is able to suppress interrupt during high interrupt load.
1267 * This function turns on that feature.
1268 */
1269static void setup_adaptive_interrupts(struct velocity_info *vptr)
1270{
1271 struct mac_regs __iomem *regs = vptr->mac_regs;
1272 u16 tx_intsup = vptr->options.tx_intsup;
1273 u16 rx_intsup = vptr->options.rx_intsup;
1274
1275 /* Setup default interrupt mask (will be changed below) */
1276 vptr->int_mask = INT_MASK_DEF;
1277
1278 /* Set Tx Interrupt Suppression Threshold */
1279 writeb(CAMCR_PS0, &regs->CAMCR);
1280 if (tx_intsup != 0) {
1281 vptr->int_mask &= ~(ISR_PTXI | ISR_PTX0I | ISR_PTX1I |
1282 ISR_PTX2I | ISR_PTX3I);
1283 writew(tx_intsup, &regs->ISRCTL);
1284 } else
1285 writew(ISRCTL_TSUPDIS, &regs->ISRCTL);
1286
1287 /* Set Rx Interrupt Suppression Threshold */
1288 writeb(CAMCR_PS1, &regs->CAMCR);
1289 if (rx_intsup != 0) {
1290 vptr->int_mask &= ~ISR_PRXI;
1291 writew(rx_intsup, &regs->ISRCTL);
1292 } else
1293 writew(ISRCTL_RSUPDIS, &regs->ISRCTL);
1294
1295 /* Select page to interrupt hold timer */
1296 writeb(0, &regs->CAMCR);
1297}
1298
1299/**
1300 * velocity_init_registers - initialise MAC registers
1301 * @vptr: velocity to init
1302 * @type: type of initialisation (hot or cold)
1303 *
1304 * Initialise the MAC on a reset or on first set up on the
1305 * hardware.
1306 */
1307static void velocity_init_registers(struct velocity_info *vptr,
1308 enum velocity_init_type type)
1309{
1310 struct mac_regs __iomem *regs = vptr->mac_regs;
1311 int i, mii_status;
1312
1313 mac_wol_reset(regs);
1314
1315 switch (type) {
1316 case VELOCITY_INIT_RESET:
1317 case VELOCITY_INIT_WOL:
1318
1319 netif_stop_queue(vptr->dev);
1320
1321 /*
1322 * Reset RX to prevent RX pointer not on the 4X location
1323 */
1324 velocity_rx_reset(vptr);
1325 mac_rx_queue_run(regs);
1326 mac_rx_queue_wake(regs);
1327
1328 mii_status = velocity_get_opt_media_mode(vptr);
1329 if (velocity_set_media_mode(vptr, mii_status) != VELOCITY_LINK_CHANGE) {
1330 velocity_print_link_status(vptr);
1331 if (!(vptr->mii_status & VELOCITY_LINK_FAIL))
1332 netif_wake_queue(vptr->dev);
1333 }
1334
1335 enable_flow_control_ability(vptr);
1336
1337 mac_clear_isr(regs);
1338 writel(CR0_STOP, &regs->CR0Clr);
1339 writel((CR0_DPOLL | CR0_TXON | CR0_RXON | CR0_STRT),
1340 &regs->CR0Set);
1341
1342 break;
1343
1344 case VELOCITY_INIT_COLD:
1345 default:
1346 /*
1347 * Do reset
1348 */
1349 velocity_soft_reset(vptr);
1350 mdelay(5);
1351
1352 mac_eeprom_reload(regs);
1353 for (i = 0; i < 6; i++)
1354 writeb(vptr->dev->dev_addr[i], &(regs->PAR[i]));
1355
1356 /*
1357 * clear Pre_ACPI bit.
1358 */
1359 BYTE_REG_BITS_OFF(CFGA_PACPI, &(regs->CFGA));
1360 mac_set_rx_thresh(regs, vptr->options.rx_thresh);
1361 mac_set_dma_length(regs, vptr->options.DMA_length);
1362
1363 writeb(WOLCFG_SAM | WOLCFG_SAB, &regs->WOLCFGSet);
1364 /*
1365 * Back off algorithm use original IEEE standard
1366 */
1367 BYTE_REG_BITS_SET(CFGB_OFSET, (CFGB_CRANDOM | CFGB_CAP | CFGB_MBA | CFGB_BAKOPT), &regs->CFGB);
1368
1369 /*
1370 * Init CAM filter
1371 */
1372 velocity_init_cam_filter(vptr);
1373
1374 /*
1375 * Set packet filter: Receive directed and broadcast address
1376 */
1377 velocity_set_multi(vptr->dev);
1378
1379 /*
1380 * Enable MII auto-polling
1381 */
1382 enable_mii_autopoll(regs);
1383
1384 setup_adaptive_interrupts(vptr);
1385
1386 writel(vptr->rx.pool_dma, &regs->RDBaseLo);
1387 writew(vptr->options.numrx - 1, &regs->RDCSize);
1388 mac_rx_queue_run(regs);
1389 mac_rx_queue_wake(regs);
1390
1391 writew(vptr->options.numtx - 1, &regs->TDCSize);
1392
1393 for (i = 0; i < vptr->tx.numq; i++) {
1394 writel(vptr->tx.pool_dma[i], &regs->TDBaseLo[i]);
1395 mac_tx_queue_run(regs, i);
1396 }
1397
1398 init_flow_control_register(vptr);
1399
1400 writel(CR0_STOP, &regs->CR0Clr);
1401 writel((CR0_DPOLL | CR0_TXON | CR0_RXON | CR0_STRT), &regs->CR0Set);
1402
1403 mii_status = velocity_get_opt_media_mode(vptr);
1404 netif_stop_queue(vptr->dev);
1405
1406 mii_init(vptr, mii_status);
1407
1408 if (velocity_set_media_mode(vptr, mii_status) != VELOCITY_LINK_CHANGE) {
1409 velocity_print_link_status(vptr);
1410 if (!(vptr->mii_status & VELOCITY_LINK_FAIL))
1411 netif_wake_queue(vptr->dev);
1412 }
1413
1414 enable_flow_control_ability(vptr);
1415 mac_hw_mibs_init(regs);
1416 mac_write_int_mask(vptr->int_mask, regs);
1417 mac_clear_isr(regs);
1418
1419 }
1420}
1421
1422static void velocity_give_many_rx_descs(struct velocity_info *vptr)
1423{
1424 struct mac_regs __iomem *regs = vptr->mac_regs;
1425 int avail, dirty, unusable;
1426
1427 /*
1428 * RD number must be equal to 4X per hardware spec
1429 * (programming guide rev 1.20, p.13)
1430 */
1431 if (vptr->rx.filled < 4)
1432 return;
1433
1434 wmb();
1435
1436 unusable = vptr->rx.filled & 0x0003;
1437 dirty = vptr->rx.dirty - unusable;
1438 for (avail = vptr->rx.filled & 0xfffc; avail; avail--) {
1439 dirty = (dirty > 0) ? dirty - 1 : vptr->options.numrx - 1;
1440 vptr->rx.ring[dirty].rdesc0.len |= OWNED_BY_NIC;
1441 }
1442
1443 writew(vptr->rx.filled & 0xfffc, &regs->RBRDU);
1444 vptr->rx.filled = unusable;
1445}
1446
1447/**
1448 * velocity_init_dma_rings - set up DMA rings
1449 * @vptr: Velocity to set up
1450 *
1451 * Allocate PCI mapped DMA rings for the receive and transmit layer
1452 * to use.
1453 */
1454static int velocity_init_dma_rings(struct velocity_info *vptr)
1455{
1456 struct velocity_opt *opt = &vptr->options;
1457 const unsigned int rx_ring_size = opt->numrx * sizeof(struct rx_desc);
1458 const unsigned int tx_ring_size = opt->numtx * sizeof(struct tx_desc);
1459 struct pci_dev *pdev = vptr->pdev;
1460 dma_addr_t pool_dma;
1461 void *pool;
1462 unsigned int i;
1463
1464 /*
1465 * Allocate all RD/TD rings a single pool.
1466 *
1467 * pci_alloc_consistent() fulfills the requirement for 64 bytes
1468 * alignment
1469 */
1470 pool = pci_alloc_consistent(pdev, tx_ring_size * vptr->tx.numq +
1471 rx_ring_size, &pool_dma);
1472 if (!pool) {
1473 dev_err(&pdev->dev, "%s : DMA memory allocation failed.\n",
1474 vptr->dev->name);
1475 return -ENOMEM;
1476 }
1477
1478 vptr->rx.ring = pool;
1479 vptr->rx.pool_dma = pool_dma;
1480
1481 pool += rx_ring_size;
1482 pool_dma += rx_ring_size;
1483
1484 for (i = 0; i < vptr->tx.numq; i++) {
1485 vptr->tx.rings[i] = pool;
1486 vptr->tx.pool_dma[i] = pool_dma;
1487 pool += tx_ring_size;
1488 pool_dma += tx_ring_size;
1489 }
1490
1491 return 0;
1492}
1493
1494static void velocity_set_rxbufsize(struct velocity_info *vptr, int mtu)
1495{
1496 vptr->rx.buf_sz = (mtu <= ETH_DATA_LEN) ? PKT_BUF_SZ : mtu + 32;
1497}
1498
1499/**
1500 * velocity_alloc_rx_buf - allocate aligned receive buffer
1501 * @vptr: velocity
1502 * @idx: ring index
1503 *
1504 * Allocate a new full sized buffer for the reception of a frame and
1505 * map it into PCI space for the hardware to use. The hardware
1506 * requires *64* byte alignment of the buffer which makes life
1507 * less fun than would be ideal.
1508 */
1509static int velocity_alloc_rx_buf(struct velocity_info *vptr, int idx)
1510{
1511 struct rx_desc *rd = &(vptr->rx.ring[idx]);
1512 struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]);
1513
1514 rd_info->skb = dev_alloc_skb(vptr->rx.buf_sz + 64);
1515 if (rd_info->skb == NULL)
1516 return -ENOMEM;
1517
1518 /*
1519 * Do the gymnastics to get the buffer head for data at
1520 * 64byte alignment.
1521 */
1522 skb_reserve(rd_info->skb,
1523 64 - ((unsigned long) rd_info->skb->data & 63));
1524 rd_info->skb_dma = pci_map_single(vptr->pdev, rd_info->skb->data,
1525 vptr->rx.buf_sz, PCI_DMA_FROMDEVICE);
1526
1527 /*
1528 * Fill in the descriptor to match
1529 */
1530
1531 *((u32 *) & (rd->rdesc0)) = 0;
1532 rd->size = cpu_to_le16(vptr->rx.buf_sz) | RX_INTEN;
1533 rd->pa_low = cpu_to_le32(rd_info->skb_dma);
1534 rd->pa_high = 0;
1535 return 0;
1536}
1537
1538
1539static int velocity_rx_refill(struct velocity_info *vptr)
1540{
1541 int dirty = vptr->rx.dirty, done = 0;
1542
1543 do {
1544 struct rx_desc *rd = vptr->rx.ring + dirty;
1545
1546 /* Fine for an all zero Rx desc at init time as well */
1547 if (rd->rdesc0.len & OWNED_BY_NIC)
1548 break;
1549
1550 if (!vptr->rx.info[dirty].skb) {
1551 if (velocity_alloc_rx_buf(vptr, dirty) < 0)
1552 break;
1553 }
1554 done++;
1555 dirty = (dirty < vptr->options.numrx - 1) ? dirty + 1 : 0;
1556 } while (dirty != vptr->rx.curr);
1557
1558 if (done) {
1559 vptr->rx.dirty = dirty;
1560 vptr->rx.filled += done;
1561 }
1562
1563 return done;
1564}
1565
1566/**
1567 * velocity_free_rd_ring - free receive ring
1568 * @vptr: velocity to clean up
1569 *
1570 * Free the receive buffers for each ring slot and any
1571 * attached socket buffers that need to go away.
1572 */
1573static void velocity_free_rd_ring(struct velocity_info *vptr)
1574{
1575 int i;
1576
1577 if (vptr->rx.info == NULL)
1578 return;
1579
1580 for (i = 0; i < vptr->options.numrx; i++) {
1581 struct velocity_rd_info *rd_info = &(vptr->rx.info[i]);
1582 struct rx_desc *rd = vptr->rx.ring + i;
1583
1584 memset(rd, 0, sizeof(*rd));
1585
1586 if (!rd_info->skb)
1587 continue;
1588 pci_unmap_single(vptr->pdev, rd_info->skb_dma, vptr->rx.buf_sz,
1589 PCI_DMA_FROMDEVICE);
1590 rd_info->skb_dma = 0;
1591
1592 dev_kfree_skb(rd_info->skb);
1593 rd_info->skb = NULL;
1594 }
1595
1596 kfree(vptr->rx.info);
1597 vptr->rx.info = NULL;
1598}
1599
1600/**
1601 * velocity_init_rd_ring - set up receive ring
1602 * @vptr: velocity to configure
1603 *
1604 * Allocate and set up the receive buffers for each ring slot and
1605 * assign them to the network adapter.
1606 */
1607static int velocity_init_rd_ring(struct velocity_info *vptr)
1608{
1609 int ret = -ENOMEM;
1610
1611 vptr->rx.info = kcalloc(vptr->options.numrx,
1612 sizeof(struct velocity_rd_info), GFP_KERNEL);
1613 if (!vptr->rx.info)
1614 goto out;
1615
1616 velocity_init_rx_ring_indexes(vptr);
1617
1618 if (velocity_rx_refill(vptr) != vptr->options.numrx) {
1619 VELOCITY_PRT(MSG_LEVEL_ERR, KERN_ERR
1620 "%s: failed to allocate RX buffer.\n", vptr->dev->name);
1621 velocity_free_rd_ring(vptr);
1622 goto out;
1623 }
1624
1625 ret = 0;
1626out:
1627 return ret;
1628}
1629
1630/**
1631 * velocity_init_td_ring - set up transmit ring
1632 * @vptr: velocity
1633 *
1634 * Set up the transmit ring and chain the ring pointers together.
1635 * Returns zero on success or a negative posix errno code for
1636 * failure.
1637 */
1638static int velocity_init_td_ring(struct velocity_info *vptr)
1639{
1640 int j;
1641
1642 /* Init the TD ring entries */
1643 for (j = 0; j < vptr->tx.numq; j++) {
1644
1645 vptr->tx.infos[j] = kcalloc(vptr->options.numtx,
1646 sizeof(struct velocity_td_info),
1647 GFP_KERNEL);
1648 if (!vptr->tx.infos[j]) {
1649 while (--j >= 0)
1650 kfree(vptr->tx.infos[j]);
1651 return -ENOMEM;
1652 }
1653
1654 vptr->tx.tail[j] = vptr->tx.curr[j] = vptr->tx.used[j] = 0;
1655 }
1656 return 0;
1657}
1658
1659/**
1660 * velocity_free_dma_rings - free PCI ring pointers
1661 * @vptr: Velocity to free from
1662 *
1663 * Clean up the PCI ring buffers allocated to this velocity.
1664 */
1665static void velocity_free_dma_rings(struct velocity_info *vptr)
1666{
1667 const int size = vptr->options.numrx * sizeof(struct rx_desc) +
1668 vptr->options.numtx * sizeof(struct tx_desc) * vptr->tx.numq;
1669
1670 pci_free_consistent(vptr->pdev, size, vptr->rx.ring, vptr->rx.pool_dma);
1671}
1672
1673static int velocity_init_rings(struct velocity_info *vptr, int mtu)
1674{
1675 int ret;
1676
1677 velocity_set_rxbufsize(vptr, mtu);
1678
1679 ret = velocity_init_dma_rings(vptr);
1680 if (ret < 0)
1681 goto out;
1682
1683 ret = velocity_init_rd_ring(vptr);
1684 if (ret < 0)
1685 goto err_free_dma_rings_0;
1686
1687 ret = velocity_init_td_ring(vptr);
1688 if (ret < 0)
1689 goto err_free_rd_ring_1;
1690out:
1691 return ret;
1692
1693err_free_rd_ring_1:
1694 velocity_free_rd_ring(vptr);
1695err_free_dma_rings_0:
1696 velocity_free_dma_rings(vptr);
1697 goto out;
1698}
1699
1700/**
1701 * velocity_free_tx_buf - free transmit buffer
1702 * @vptr: velocity
1703 * @tdinfo: buffer
1704 *
1705 * Release an transmit buffer. If the buffer was preallocated then
1706 * recycle it, if not then unmap the buffer.
1707 */
1708static void velocity_free_tx_buf(struct velocity_info *vptr,
1709 struct velocity_td_info *tdinfo, struct tx_desc *td)
1710{
1711 struct sk_buff *skb = tdinfo->skb;
1712
1713 /*
1714 * Don't unmap the pre-allocated tx_bufs
1715 */
1716 if (tdinfo->skb_dma) {
1717 int i;
1718
1719 for (i = 0; i < tdinfo->nskb_dma; i++) {
1720 size_t pktlen = max_t(size_t, skb->len, ETH_ZLEN);
1721
1722 /* For scatter-gather */
1723 if (skb_shinfo(skb)->nr_frags > 0)
1724 pktlen = max_t(size_t, pktlen,
1725 td->td_buf[i].size & ~TD_QUEUE);
1726
1727 pci_unmap_single(vptr->pdev, tdinfo->skb_dma[i],
1728 le16_to_cpu(pktlen), PCI_DMA_TODEVICE);
1729 }
1730 }
1731 dev_kfree_skb_irq(skb);
1732 tdinfo->skb = NULL;
1733}
1734
1735/*
1736 * FIXME: could we merge this with velocity_free_tx_buf ?
1737 */
1738static void velocity_free_td_ring_entry(struct velocity_info *vptr,
1739 int q, int n)
1740{
1741 struct velocity_td_info *td_info = &(vptr->tx.infos[q][n]);
1742 int i;
1743
1744 if (td_info == NULL)
1745 return;
1746
1747 if (td_info->skb) {
1748 for (i = 0; i < td_info->nskb_dma; i++) {
1749 if (td_info->skb_dma[i]) {
1750 pci_unmap_single(vptr->pdev, td_info->skb_dma[i],
1751 td_info->skb->len, PCI_DMA_TODEVICE);
1752 td_info->skb_dma[i] = 0;
1753 }
1754 }
1755 dev_kfree_skb(td_info->skb);
1756 td_info->skb = NULL;
1757 }
1758}
1759
1760/**
1761 * velocity_free_td_ring - free td ring
1762 * @vptr: velocity
1763 *
1764 * Free up the transmit ring for this particular velocity adapter.
1765 * We free the ring contents but not the ring itself.
1766 */
1767static void velocity_free_td_ring(struct velocity_info *vptr)
1768{
1769 int i, j;
1770
1771 for (j = 0; j < vptr->tx.numq; j++) {
1772 if (vptr->tx.infos[j] == NULL)
1773 continue;
1774 for (i = 0; i < vptr->options.numtx; i++)
1775 velocity_free_td_ring_entry(vptr, j, i);
1776
1777 kfree(vptr->tx.infos[j]);
1778 vptr->tx.infos[j] = NULL;
1779 }
1780}
1781
1782static void velocity_free_rings(struct velocity_info *vptr)
1783{
1784 velocity_free_td_ring(vptr);
1785 velocity_free_rd_ring(vptr);
1786 velocity_free_dma_rings(vptr);
1787}
1788
1789/**
1790 * velocity_error - handle error from controller
1791 * @vptr: velocity
1792 * @status: card status
1793 *
1794 * Process an error report from the hardware and attempt to recover
1795 * the card itself. At the moment we cannot recover from some
1796 * theoretically impossible errors but this could be fixed using
1797 * the pci_device_failed logic to bounce the hardware
1798 *
1799 */
1800static void velocity_error(struct velocity_info *vptr, int status)
1801{
1802
1803 if (status & ISR_TXSTLI) {
1804 struct mac_regs __iomem *regs = vptr->mac_regs;
1805
1806 printk(KERN_ERR "TD structure error TDindex=%hx\n", readw(&regs->TDIdx[0]));
1807 BYTE_REG_BITS_ON(TXESR_TDSTR, &regs->TXESR);
1808 writew(TRDCSR_RUN, &regs->TDCSRClr);
1809 netif_stop_queue(vptr->dev);
1810
1811 /* FIXME: port over the pci_device_failed code and use it
1812 here */
1813 }
1814
1815 if (status & ISR_SRCI) {
1816 struct mac_regs __iomem *regs = vptr->mac_regs;
1817 int linked;
1818
1819 if (vptr->options.spd_dpx == SPD_DPX_AUTO) {
1820 vptr->mii_status = check_connection_type(regs);
1821
1822 /*
1823 * If it is a 3119, disable frame bursting in
1824 * halfduplex mode and enable it in fullduplex
1825 * mode
1826 */
1827 if (vptr->rev_id < REV_ID_VT3216_A0) {
1828 if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
1829 BYTE_REG_BITS_ON(TCR_TB2BDIS, &regs->TCR);
1830 else
1831 BYTE_REG_BITS_OFF(TCR_TB2BDIS, &regs->TCR);
1832 }
1833 /*
1834 * Only enable CD heart beat counter in 10HD mode
1835 */
1836 if (!(vptr->mii_status & VELOCITY_DUPLEX_FULL) && (vptr->mii_status & VELOCITY_SPEED_10))
1837 BYTE_REG_BITS_OFF(TESTCFG_HBDIS, &regs->TESTCFG);
1838 else
1839 BYTE_REG_BITS_ON(TESTCFG_HBDIS, &regs->TESTCFG);
1840
1841 setup_queue_timers(vptr);
1842 }
1843 /*
1844 * Get link status from PHYSR0
1845 */
1846 linked = readb(&regs->PHYSR0) & PHYSR0_LINKGD;
1847
1848 if (linked) {
1849 vptr->mii_status &= ~VELOCITY_LINK_FAIL;
1850 netif_carrier_on(vptr->dev);
1851 } else {
1852 vptr->mii_status |= VELOCITY_LINK_FAIL;
1853 netif_carrier_off(vptr->dev);
1854 }
1855
1856 velocity_print_link_status(vptr);
1857 enable_flow_control_ability(vptr);
1858
1859 /*
1860 * Re-enable auto-polling because SRCI will disable
1861 * auto-polling
1862 */
1863
1864 enable_mii_autopoll(regs);
1865
1866 if (vptr->mii_status & VELOCITY_LINK_FAIL)
1867 netif_stop_queue(vptr->dev);
1868 else
1869 netif_wake_queue(vptr->dev);
1870
1871 }
1872 if (status & ISR_MIBFI)
1873 velocity_update_hw_mibs(vptr);
1874 if (status & ISR_LSTEI)
1875 mac_rx_queue_wake(vptr->mac_regs);
1876}
1877
1878/**
1879 * tx_srv - transmit interrupt service
1880 * @vptr; Velocity
1881 *
1882 * Scan the queues looking for transmitted packets that
1883 * we can complete and clean up. Update any statistics as
1884 * necessary/
1885 */
1886static int velocity_tx_srv(struct velocity_info *vptr)
1887{
1888 struct tx_desc *td;
1889 int qnum;
1890 int full = 0;
1891 int idx;
1892 int works = 0;
1893 struct velocity_td_info *tdinfo;
1894 struct net_device_stats *stats = &vptr->dev->stats;
1895
1896 for (qnum = 0; qnum < vptr->tx.numq; qnum++) {
1897 for (idx = vptr->tx.tail[qnum]; vptr->tx.used[qnum] > 0;
1898 idx = (idx + 1) % vptr->options.numtx) {
1899
1900 /*
1901 * Get Tx Descriptor
1902 */
1903 td = &(vptr->tx.rings[qnum][idx]);
1904 tdinfo = &(vptr->tx.infos[qnum][idx]);
1905
1906 if (td->tdesc0.len & OWNED_BY_NIC)
1907 break;
1908
1909 if ((works++ > 15))
1910 break;
1911
1912 if (td->tdesc0.TSR & TSR0_TERR) {
1913 stats->tx_errors++;
1914 stats->tx_dropped++;
1915 if (td->tdesc0.TSR & TSR0_CDH)
1916 stats->tx_heartbeat_errors++;
1917 if (td->tdesc0.TSR & TSR0_CRS)
1918 stats->tx_carrier_errors++;
1919 if (td->tdesc0.TSR & TSR0_ABT)
1920 stats->tx_aborted_errors++;
1921 if (td->tdesc0.TSR & TSR0_OWC)
1922 stats->tx_window_errors++;
1923 } else {
1924 stats->tx_packets++;
1925 stats->tx_bytes += tdinfo->skb->len;
1926 }
1927 velocity_free_tx_buf(vptr, tdinfo, td);
1928 vptr->tx.used[qnum]--;
1929 }
1930 vptr->tx.tail[qnum] = idx;
1931
1932 if (AVAIL_TD(vptr, qnum) < 1)
1933 full = 1;
1934 }
1935 /*
1936 * Look to see if we should kick the transmit network
1937 * layer for more work.
1938 */
1939 if (netif_queue_stopped(vptr->dev) && (full == 0) &&
1940 (!(vptr->mii_status & VELOCITY_LINK_FAIL))) {
1941 netif_wake_queue(vptr->dev);
1942 }
1943 return works;
1944}
1945
1946/**
1947 * velocity_rx_csum - checksum process
1948 * @rd: receive packet descriptor
1949 * @skb: network layer packet buffer
1950 *
1951 * Process the status bits for the received packet and determine
1952 * if the checksum was computed and verified by the hardware
1953 */
1954static inline void velocity_rx_csum(struct rx_desc *rd, struct sk_buff *skb)
1955{
1956 skb_checksum_none_assert(skb);
1957
1958 if (rd->rdesc1.CSM & CSM_IPKT) {
1959 if (rd->rdesc1.CSM & CSM_IPOK) {
1960 if ((rd->rdesc1.CSM & CSM_TCPKT) ||
1961 (rd->rdesc1.CSM & CSM_UDPKT)) {
1962 if (!(rd->rdesc1.CSM & CSM_TUPOK))
1963 return;
1964 }
1965 skb->ip_summed = CHECKSUM_UNNECESSARY;
1966 }
1967 }
1968}
1969
1970/**
1971 * velocity_rx_copy - in place Rx copy for small packets
1972 * @rx_skb: network layer packet buffer candidate
1973 * @pkt_size: received data size
1974 * @rd: receive packet descriptor
1975 * @dev: network device
1976 *
1977 * Replace the current skb that is scheduled for Rx processing by a
1978 * shorter, immediately allocated skb, if the received packet is small
1979 * enough. This function returns a negative value if the received
1980 * packet is too big or if memory is exhausted.
1981 */
1982static int velocity_rx_copy(struct sk_buff **rx_skb, int pkt_size,
1983 struct velocity_info *vptr)
1984{
1985 int ret = -1;
1986 if (pkt_size < rx_copybreak) {
1987 struct sk_buff *new_skb;
1988
1989 new_skb = netdev_alloc_skb_ip_align(vptr->dev, pkt_size);
1990 if (new_skb) {
1991 new_skb->ip_summed = rx_skb[0]->ip_summed;
1992 skb_copy_from_linear_data(*rx_skb, new_skb->data, pkt_size);
1993 *rx_skb = new_skb;
1994 ret = 0;
1995 }
1996
1997 }
1998 return ret;
1999}
2000
2001/**
2002 * velocity_iph_realign - IP header alignment
2003 * @vptr: velocity we are handling
2004 * @skb: network layer packet buffer
2005 * @pkt_size: received data size
2006 *
2007 * Align IP header on a 2 bytes boundary. This behavior can be
2008 * configured by the user.
2009 */
2010static inline void velocity_iph_realign(struct velocity_info *vptr,
2011 struct sk_buff *skb, int pkt_size)
2012{
2013 if (vptr->flags & VELOCITY_FLAGS_IP_ALIGN) {
2014 memmove(skb->data + 2, skb->data, pkt_size);
2015 skb_reserve(skb, 2);
2016 }
2017}
2018
2019/**
2020 * velocity_receive_frame - received packet processor
2021 * @vptr: velocity we are handling
2022 * @idx: ring index
2023 *
2024 * A packet has arrived. We process the packet and if appropriate
2025 * pass the frame up the network stack
2026 */
2027static int velocity_receive_frame(struct velocity_info *vptr, int idx)
2028{
2029 void (*pci_action)(struct pci_dev *, dma_addr_t, size_t, int);
2030 struct net_device_stats *stats = &vptr->dev->stats;
2031 struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]);
2032 struct rx_desc *rd = &(vptr->rx.ring[idx]);
2033 int pkt_len = le16_to_cpu(rd->rdesc0.len) & 0x3fff;
2034 struct sk_buff *skb;
2035
2036 if (rd->rdesc0.RSR & (RSR_STP | RSR_EDP)) {
2037 VELOCITY_PRT(MSG_LEVEL_VERBOSE, KERN_ERR " %s : the received frame span multple RDs.\n", vptr->dev->name);
2038 stats->rx_length_errors++;
2039 return -EINVAL;
2040 }
2041
2042 if (rd->rdesc0.RSR & RSR_MAR)
2043 stats->multicast++;
2044
2045 skb = rd_info->skb;
2046
2047 pci_dma_sync_single_for_cpu(vptr->pdev, rd_info->skb_dma,
2048 vptr->rx.buf_sz, PCI_DMA_FROMDEVICE);
2049
2050 /*
2051 * Drop frame not meeting IEEE 802.3
2052 */
2053
2054 if (vptr->flags & VELOCITY_FLAGS_VAL_PKT_LEN) {
2055 if (rd->rdesc0.RSR & RSR_RL) {
2056 stats->rx_length_errors++;
2057 return -EINVAL;
2058 }
2059 }
2060
2061 pci_action = pci_dma_sync_single_for_device;
2062
2063 velocity_rx_csum(rd, skb);
2064
2065 if (velocity_rx_copy(&skb, pkt_len, vptr) < 0) {
2066 velocity_iph_realign(vptr, skb, pkt_len);
2067 pci_action = pci_unmap_single;
2068 rd_info->skb = NULL;
2069 }
2070
2071 pci_action(vptr->pdev, rd_info->skb_dma, vptr->rx.buf_sz,
2072 PCI_DMA_FROMDEVICE);
2073
2074 skb_put(skb, pkt_len - 4);
2075 skb->protocol = eth_type_trans(skb, vptr->dev);
2076
2077 if (rd->rdesc0.RSR & RSR_DETAG) {
2078 u16 vid = swab16(le16_to_cpu(rd->rdesc1.PQTAG));
2079
2080 __vlan_hwaccel_put_tag(skb, vid);
2081 }
2082 netif_rx(skb);
2083
2084 stats->rx_bytes += pkt_len;
2085 stats->rx_packets++;
2086
2087 return 0;
2088}
2089
2090/**
2091 * velocity_rx_srv - service RX interrupt
2092 * @vptr: velocity
2093 *
2094 * Walk the receive ring of the velocity adapter and remove
2095 * any received packets from the receive queue. Hand the ring
2096 * slots back to the adapter for reuse.
2097 */
2098static int velocity_rx_srv(struct velocity_info *vptr, int budget_left)
2099{
2100 struct net_device_stats *stats = &vptr->dev->stats;
2101 int rd_curr = vptr->rx.curr;
2102 int works = 0;
2103
2104 while (works < budget_left) {
2105 struct rx_desc *rd = vptr->rx.ring + rd_curr;
2106
2107 if (!vptr->rx.info[rd_curr].skb)
2108 break;
2109
2110 if (rd->rdesc0.len & OWNED_BY_NIC)
2111 break;
2112
2113 rmb();
2114
2115 /*
2116 * Don't drop CE or RL error frame although RXOK is off
2117 */
2118 if (rd->rdesc0.RSR & (RSR_RXOK | RSR_CE | RSR_RL)) {
2119 if (velocity_receive_frame(vptr, rd_curr) < 0)
2120 stats->rx_dropped++;
2121 } else {
2122 if (rd->rdesc0.RSR & RSR_CRC)
2123 stats->rx_crc_errors++;
2124 if (rd->rdesc0.RSR & RSR_FAE)
2125 stats->rx_frame_errors++;
2126
2127 stats->rx_dropped++;
2128 }
2129
2130 rd->size |= RX_INTEN;
2131
2132 rd_curr++;
2133 if (rd_curr >= vptr->options.numrx)
2134 rd_curr = 0;
2135 works++;
2136 }
2137
2138 vptr->rx.curr = rd_curr;
2139
2140 if ((works > 0) && (velocity_rx_refill(vptr) > 0))
2141 velocity_give_many_rx_descs(vptr);
2142
2143 VAR_USED(stats);
2144 return works;
2145}
2146
2147static int velocity_poll(struct napi_struct *napi, int budget)
2148{
2149 struct velocity_info *vptr = container_of(napi,
2150 struct velocity_info, napi);
2151 unsigned int rx_done;
2152 unsigned long flags;
2153
2154 spin_lock_irqsave(&vptr->lock, flags);
2155 /*
2156 * Do rx and tx twice for performance (taken from the VIA
2157 * out-of-tree driver).
2158 */
2159 rx_done = velocity_rx_srv(vptr, budget / 2);
2160 velocity_tx_srv(vptr);
2161 rx_done += velocity_rx_srv(vptr, budget - rx_done);
2162 velocity_tx_srv(vptr);
2163
2164 /* If budget not fully consumed, exit the polling mode */
2165 if (rx_done < budget) {
2166 napi_complete(napi);
2167 mac_enable_int(vptr->mac_regs);
2168 }
2169 spin_unlock_irqrestore(&vptr->lock, flags);
2170
2171 return rx_done;
2172}
2173
2174/**
2175 * velocity_intr - interrupt callback
2176 * @irq: interrupt number
2177 * @dev_instance: interrupting device
2178 *
2179 * Called whenever an interrupt is generated by the velocity
2180 * adapter IRQ line. We may not be the source of the interrupt
2181 * and need to identify initially if we are, and if not exit as
2182 * efficiently as possible.
2183 */
2184static irqreturn_t velocity_intr(int irq, void *dev_instance)
2185{
2186 struct net_device *dev = dev_instance;
2187 struct velocity_info *vptr = netdev_priv(dev);
2188 u32 isr_status;
2189
2190 spin_lock(&vptr->lock);
2191 isr_status = mac_read_isr(vptr->mac_regs);
2192
2193 /* Not us ? */
2194 if (isr_status == 0) {
2195 spin_unlock(&vptr->lock);
2196 return IRQ_NONE;
2197 }
2198
2199 /* Ack the interrupt */
2200 mac_write_isr(vptr->mac_regs, isr_status);
2201
2202 if (likely(napi_schedule_prep(&vptr->napi))) {
2203 mac_disable_int(vptr->mac_regs);
2204 __napi_schedule(&vptr->napi);
2205 }
2206
2207 if (isr_status & (~(ISR_PRXI | ISR_PPRXI | ISR_PTXI | ISR_PPTXI)))
2208 velocity_error(vptr, isr_status);
2209
2210 spin_unlock(&vptr->lock);
2211
2212 return IRQ_HANDLED;
2213}
2214
2215/**
2216 * velocity_open - interface activation callback
2217 * @dev: network layer device to open
2218 *
2219 * Called when the network layer brings the interface up. Returns
2220 * a negative posix error code on failure, or zero on success.
2221 *
2222 * All the ring allocation and set up is done on open for this
2223 * adapter to minimise memory usage when inactive
2224 */
2225static int velocity_open(struct net_device *dev)
2226{
2227 struct velocity_info *vptr = netdev_priv(dev);
2228 int ret;
2229
2230 ret = velocity_init_rings(vptr, dev->mtu);
2231 if (ret < 0)
2232 goto out;
2233
2234 /* Ensure chip is running */
2235 pci_set_power_state(vptr->pdev, PCI_D0);
2236
2237 velocity_init_registers(vptr, VELOCITY_INIT_COLD);
2238
2239 ret = request_irq(vptr->pdev->irq, velocity_intr, IRQF_SHARED,
2240 dev->name, dev);
2241 if (ret < 0) {
2242 /* Power down the chip */
2243 pci_set_power_state(vptr->pdev, PCI_D3hot);
2244 velocity_free_rings(vptr);
2245 goto out;
2246 }
2247
2248 velocity_give_many_rx_descs(vptr);
2249
2250 mac_enable_int(vptr->mac_regs);
2251 netif_start_queue(dev);
2252 napi_enable(&vptr->napi);
2253 vptr->flags |= VELOCITY_FLAGS_OPENED;
2254out:
2255 return ret;
2256}
2257
2258/**
2259 * velocity_shutdown - shut down the chip
2260 * @vptr: velocity to deactivate
2261 *
2262 * Shuts down the internal operations of the velocity and
2263 * disables interrupts, autopolling, transmit and receive
2264 */
2265static void velocity_shutdown(struct velocity_info *vptr)
2266{
2267 struct mac_regs __iomem *regs = vptr->mac_regs;
2268 mac_disable_int(regs);
2269 writel(CR0_STOP, &regs->CR0Set);
2270 writew(0xFFFF, &regs->TDCSRClr);
2271 writeb(0xFF, &regs->RDCSRClr);
2272 safe_disable_mii_autopoll(regs);
2273 mac_clear_isr(regs);
2274}
2275
2276/**
2277 * velocity_change_mtu - MTU change callback
2278 * @dev: network device
2279 * @new_mtu: desired MTU
2280 *
2281 * Handle requests from the networking layer for MTU change on
2282 * this interface. It gets called on a change by the network layer.
2283 * Return zero for success or negative posix error code.
2284 */
2285static int velocity_change_mtu(struct net_device *dev, int new_mtu)
2286{
2287 struct velocity_info *vptr = netdev_priv(dev);
2288 int ret = 0;
2289
2290 if ((new_mtu < VELOCITY_MIN_MTU) || new_mtu > (VELOCITY_MAX_MTU)) {
2291 VELOCITY_PRT(MSG_LEVEL_ERR, KERN_NOTICE "%s: Invalid MTU.\n",
2292 vptr->dev->name);
2293 ret = -EINVAL;
2294 goto out_0;
2295 }
2296
2297 if (!netif_running(dev)) {
2298 dev->mtu = new_mtu;
2299 goto out_0;
2300 }
2301
2302 if (dev->mtu != new_mtu) {
2303 struct velocity_info *tmp_vptr;
2304 unsigned long flags;
2305 struct rx_info rx;
2306 struct tx_info tx;
2307
2308 tmp_vptr = kzalloc(sizeof(*tmp_vptr), GFP_KERNEL);
2309 if (!tmp_vptr) {
2310 ret = -ENOMEM;
2311 goto out_0;
2312 }
2313
2314 tmp_vptr->dev = dev;
2315 tmp_vptr->pdev = vptr->pdev;
2316 tmp_vptr->options = vptr->options;
2317 tmp_vptr->tx.numq = vptr->tx.numq;
2318
2319 ret = velocity_init_rings(tmp_vptr, new_mtu);
2320 if (ret < 0)
2321 goto out_free_tmp_vptr_1;
2322
2323 spin_lock_irqsave(&vptr->lock, flags);
2324
2325 netif_stop_queue(dev);
2326 velocity_shutdown(vptr);
2327
2328 rx = vptr->rx;
2329 tx = vptr->tx;
2330
2331 vptr->rx = tmp_vptr->rx;
2332 vptr->tx = tmp_vptr->tx;
2333
2334 tmp_vptr->rx = rx;
2335 tmp_vptr->tx = tx;
2336
2337 dev->mtu = new_mtu;
2338
2339 velocity_init_registers(vptr, VELOCITY_INIT_COLD);
2340
2341 velocity_give_many_rx_descs(vptr);
2342
2343 mac_enable_int(vptr->mac_regs);
2344 netif_start_queue(dev);
2345
2346 spin_unlock_irqrestore(&vptr->lock, flags);
2347
2348 velocity_free_rings(tmp_vptr);
2349
2350out_free_tmp_vptr_1:
2351 kfree(tmp_vptr);
2352 }
2353out_0:
2354 return ret;
2355}
2356
2357/**
2358 * velocity_mii_ioctl - MII ioctl handler
2359 * @dev: network device
2360 * @ifr: the ifreq block for the ioctl
2361 * @cmd: the command
2362 *
2363 * Process MII requests made via ioctl from the network layer. These
2364 * are used by tools like kudzu to interrogate the link state of the
2365 * hardware
2366 */
2367static int velocity_mii_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2368{
2369 struct velocity_info *vptr = netdev_priv(dev);
2370 struct mac_regs __iomem *regs = vptr->mac_regs;
2371 unsigned long flags;
2372 struct mii_ioctl_data *miidata = if_mii(ifr);
2373 int err;
2374
2375 switch (cmd) {
2376 case SIOCGMIIPHY:
2377 miidata->phy_id = readb(&regs->MIIADR) & 0x1f;
2378 break;
2379 case SIOCGMIIREG:
2380 if (velocity_mii_read(vptr->mac_regs, miidata->reg_num & 0x1f, &(miidata->val_out)) < 0)
2381 return -ETIMEDOUT;
2382 break;
2383 case SIOCSMIIREG:
2384 spin_lock_irqsave(&vptr->lock, flags);
2385 err = velocity_mii_write(vptr->mac_regs, miidata->reg_num & 0x1f, miidata->val_in);
2386 spin_unlock_irqrestore(&vptr->lock, flags);
2387 check_connection_type(vptr->mac_regs);
2388 if (err)
2389 return err;
2390 break;
2391 default:
2392 return -EOPNOTSUPP;
2393 }
2394 return 0;
2395}
2396
2397/**
2398 * velocity_ioctl - ioctl entry point
2399 * @dev: network device
2400 * @rq: interface request ioctl
2401 * @cmd: command code
2402 *
2403 * Called when the user issues an ioctl request to the network
2404 * device in question. The velocity interface supports MII.
2405 */
2406static int velocity_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2407{
2408 struct velocity_info *vptr = netdev_priv(dev);
2409 int ret;
2410
2411 /* If we are asked for information and the device is power
2412 saving then we need to bring the device back up to talk to it */
2413
2414 if (!netif_running(dev))
2415 pci_set_power_state(vptr->pdev, PCI_D0);
2416
2417 switch (cmd) {
2418 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2419 case SIOCGMIIREG: /* Read MII PHY register. */
2420 case SIOCSMIIREG: /* Write to MII PHY register. */
2421 ret = velocity_mii_ioctl(dev, rq, cmd);
2422 break;
2423
2424 default:
2425 ret = -EOPNOTSUPP;
2426 }
2427 if (!netif_running(dev))
2428 pci_set_power_state(vptr->pdev, PCI_D3hot);
2429
2430
2431 return ret;
2432}
2433
2434/**
2435 * velocity_get_status - statistics callback
2436 * @dev: network device
2437 *
2438 * Callback from the network layer to allow driver statistics
2439 * to be resynchronized with hardware collected state. In the
2440 * case of the velocity we need to pull the MIB counters from
2441 * the hardware into the counters before letting the network
2442 * layer display them.
2443 */
2444static struct net_device_stats *velocity_get_stats(struct net_device *dev)
2445{
2446 struct velocity_info *vptr = netdev_priv(dev);
2447
2448 /* If the hardware is down, don't touch MII */
2449 if (!netif_running(dev))
2450 return &dev->stats;
2451
2452 spin_lock_irq(&vptr->lock);
2453 velocity_update_hw_mibs(vptr);
2454 spin_unlock_irq(&vptr->lock);
2455
2456 dev->stats.rx_packets = vptr->mib_counter[HW_MIB_ifRxAllPkts];
2457 dev->stats.rx_errors = vptr->mib_counter[HW_MIB_ifRxErrorPkts];
2458 dev->stats.rx_length_errors = vptr->mib_counter[HW_MIB_ifInRangeLengthErrors];
2459
2460// unsigned long rx_dropped; /* no space in linux buffers */
2461 dev->stats.collisions = vptr->mib_counter[HW_MIB_ifTxEtherCollisions];
2462 /* detailed rx_errors: */
2463// unsigned long rx_length_errors;
2464// unsigned long rx_over_errors; /* receiver ring buff overflow */
2465 dev->stats.rx_crc_errors = vptr->mib_counter[HW_MIB_ifRxPktCRCE];
2466// unsigned long rx_frame_errors; /* recv'd frame alignment error */
2467// unsigned long rx_fifo_errors; /* recv'r fifo overrun */
2468// unsigned long rx_missed_errors; /* receiver missed packet */
2469
2470 /* detailed tx_errors */
2471// unsigned long tx_fifo_errors;
2472
2473 return &dev->stats;
2474}
2475
2476/**
2477 * velocity_close - close adapter callback
2478 * @dev: network device
2479 *
2480 * Callback from the network layer when the velocity is being
2481 * deactivated by the network layer
2482 */
2483static int velocity_close(struct net_device *dev)
2484{
2485 struct velocity_info *vptr = netdev_priv(dev);
2486
2487 napi_disable(&vptr->napi);
2488 netif_stop_queue(dev);
2489 velocity_shutdown(vptr);
2490
2491 if (vptr->flags & VELOCITY_FLAGS_WOL_ENABLED)
2492 velocity_get_ip(vptr);
2493 if (dev->irq != 0)
2494 free_irq(dev->irq, dev);
2495
2496 /* Power down the chip */
2497 pci_set_power_state(vptr->pdev, PCI_D3hot);
2498
2499 velocity_free_rings(vptr);
2500
2501 vptr->flags &= (~VELOCITY_FLAGS_OPENED);
2502 return 0;
2503}
2504
2505/**
2506 * velocity_xmit - transmit packet callback
2507 * @skb: buffer to transmit
2508 * @dev: network device
2509 *
2510 * Called by the networ layer to request a packet is queued to
2511 * the velocity. Returns zero on success.
2512 */
2513static netdev_tx_t velocity_xmit(struct sk_buff *skb,
2514 struct net_device *dev)
2515{
2516 struct velocity_info *vptr = netdev_priv(dev);
2517 int qnum = 0;
2518 struct tx_desc *td_ptr;
2519 struct velocity_td_info *tdinfo;
2520 unsigned long flags;
2521 int pktlen;
2522 int index, prev;
2523 int i = 0;
2524
2525 if (skb_padto(skb, ETH_ZLEN))
2526 goto out;
2527
2528 /* The hardware can handle at most 7 memory segments, so merge
2529 * the skb if there are more */
2530 if (skb_shinfo(skb)->nr_frags > 6 && __skb_linearize(skb)) {
2531 kfree_skb(skb);
2532 return NETDEV_TX_OK;
2533 }
2534
2535 pktlen = skb_shinfo(skb)->nr_frags == 0 ?
2536 max_t(unsigned int, skb->len, ETH_ZLEN) :
2537 skb_headlen(skb);
2538
2539 spin_lock_irqsave(&vptr->lock, flags);
2540
2541 index = vptr->tx.curr[qnum];
2542 td_ptr = &(vptr->tx.rings[qnum][index]);
2543 tdinfo = &(vptr->tx.infos[qnum][index]);
2544
2545 td_ptr->tdesc1.TCR = TCR0_TIC;
2546 td_ptr->td_buf[0].size &= ~TD_QUEUE;
2547
2548 /*
2549 * Map the linear network buffer into PCI space and
2550 * add it to the transmit ring.
2551 */
2552 tdinfo->skb = skb;
2553 tdinfo->skb_dma[0] = pci_map_single(vptr->pdev, skb->data, pktlen, PCI_DMA_TODEVICE);
2554 td_ptr->tdesc0.len = cpu_to_le16(pktlen);
2555 td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]);
2556 td_ptr->td_buf[0].pa_high = 0;
2557 td_ptr->td_buf[0].size = cpu_to_le16(pktlen);
2558
2559 /* Handle fragments */
2560 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2561 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2562
2563 tdinfo->skb_dma[i + 1] = pci_map_page(vptr->pdev, frag->page,
2564 frag->page_offset, frag->size,
2565 PCI_DMA_TODEVICE);
2566
2567 td_ptr->td_buf[i + 1].pa_low = cpu_to_le32(tdinfo->skb_dma[i + 1]);
2568 td_ptr->td_buf[i + 1].pa_high = 0;
2569 td_ptr->td_buf[i + 1].size = cpu_to_le16(frag->size);
2570 }
2571 tdinfo->nskb_dma = i + 1;
2572
2573 td_ptr->tdesc1.cmd = TCPLS_NORMAL + (tdinfo->nskb_dma + 1) * 16;
2574
2575 if (vlan_tx_tag_present(skb)) {
2576 td_ptr->tdesc1.vlan = cpu_to_le16(vlan_tx_tag_get(skb));
2577 td_ptr->tdesc1.TCR |= TCR0_VETAG;
2578 }
2579
2580 /*
2581 * Handle hardware checksum
2582 */
2583 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2584 const struct iphdr *ip = ip_hdr(skb);
2585 if (ip->protocol == IPPROTO_TCP)
2586 td_ptr->tdesc1.TCR |= TCR0_TCPCK;
2587 else if (ip->protocol == IPPROTO_UDP)
2588 td_ptr->tdesc1.TCR |= (TCR0_UDPCK);
2589 td_ptr->tdesc1.TCR |= TCR0_IPCK;
2590 }
2591
2592 prev = index - 1;
2593 if (prev < 0)
2594 prev = vptr->options.numtx - 1;
2595 td_ptr->tdesc0.len |= OWNED_BY_NIC;
2596 vptr->tx.used[qnum]++;
2597 vptr->tx.curr[qnum] = (index + 1) % vptr->options.numtx;
2598
2599 if (AVAIL_TD(vptr, qnum) < 1)
2600 netif_stop_queue(dev);
2601
2602 td_ptr = &(vptr->tx.rings[qnum][prev]);
2603 td_ptr->td_buf[0].size |= TD_QUEUE;
2604 mac_tx_queue_wake(vptr->mac_regs, qnum);
2605
2606 spin_unlock_irqrestore(&vptr->lock, flags);
2607out:
2608 return NETDEV_TX_OK;
2609}
2610
2611static const struct net_device_ops velocity_netdev_ops = {
2612 .ndo_open = velocity_open,
2613 .ndo_stop = velocity_close,
2614 .ndo_start_xmit = velocity_xmit,
2615 .ndo_get_stats = velocity_get_stats,
2616 .ndo_validate_addr = eth_validate_addr,
2617 .ndo_set_mac_address = eth_mac_addr,
2618 .ndo_set_multicast_list = velocity_set_multi,
2619 .ndo_change_mtu = velocity_change_mtu,
2620 .ndo_do_ioctl = velocity_ioctl,
2621 .ndo_vlan_rx_add_vid = velocity_vlan_rx_add_vid,
2622 .ndo_vlan_rx_kill_vid = velocity_vlan_rx_kill_vid,
2623};
2624
2625/**
2626 * velocity_init_info - init private data
2627 * @pdev: PCI device
2628 * @vptr: Velocity info
2629 * @info: Board type
2630 *
2631 * Set up the initial velocity_info struct for the device that has been
2632 * discovered.
2633 */
2634static void __devinit velocity_init_info(struct pci_dev *pdev,
2635 struct velocity_info *vptr,
2636 const struct velocity_info_tbl *info)
2637{
2638 memset(vptr, 0, sizeof(struct velocity_info));
2639
2640 vptr->pdev = pdev;
2641 vptr->chip_id = info->chip_id;
2642 vptr->tx.numq = info->txqueue;
2643 vptr->multicast_limit = MCAM_SIZE;
2644 spin_lock_init(&vptr->lock);
2645}
2646
2647/**
2648 * velocity_get_pci_info - retrieve PCI info for device
2649 * @vptr: velocity device
2650 * @pdev: PCI device it matches
2651 *
2652 * Retrieve the PCI configuration space data that interests us from
2653 * the kernel PCI layer
2654 */
2655static int __devinit velocity_get_pci_info(struct velocity_info *vptr, struct pci_dev *pdev)
2656{
2657 vptr->rev_id = pdev->revision;
2658
2659 pci_set_master(pdev);
2660
2661 vptr->ioaddr = pci_resource_start(pdev, 0);
2662 vptr->memaddr = pci_resource_start(pdev, 1);
2663
2664 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_IO)) {
2665 dev_err(&pdev->dev,
2666 "region #0 is not an I/O resource, aborting.\n");
2667 return -EINVAL;
2668 }
2669
2670 if ((pci_resource_flags(pdev, 1) & IORESOURCE_IO)) {
2671 dev_err(&pdev->dev,
2672 "region #1 is an I/O resource, aborting.\n");
2673 return -EINVAL;
2674 }
2675
2676 if (pci_resource_len(pdev, 1) < VELOCITY_IO_SIZE) {
2677 dev_err(&pdev->dev, "region #1 is too small.\n");
2678 return -EINVAL;
2679 }
2680 vptr->pdev = pdev;
2681
2682 return 0;
2683}
2684
2685/**
2686 * velocity_print_info - per driver data
2687 * @vptr: velocity
2688 *
2689 * Print per driver data as the kernel driver finds Velocity
2690 * hardware
2691 */
2692static void __devinit velocity_print_info(struct velocity_info *vptr)
2693{
2694 struct net_device *dev = vptr->dev;
2695
2696 printk(KERN_INFO "%s: %s\n", dev->name, get_chip_name(vptr->chip_id));
2697 printk(KERN_INFO "%s: Ethernet Address: %pM\n",
2698 dev->name, dev->dev_addr);
2699}
2700
2701static u32 velocity_get_link(struct net_device *dev)
2702{
2703 struct velocity_info *vptr = netdev_priv(dev);
2704 struct mac_regs __iomem *regs = vptr->mac_regs;
2705 return BYTE_REG_BITS_IS_ON(PHYSR0_LINKGD, &regs->PHYSR0) ? 1 : 0;
2706}
2707
2708/**
2709 * velocity_found1 - set up discovered velocity card
2710 * @pdev: PCI device
2711 * @ent: PCI device table entry that matched
2712 *
2713 * Configure a discovered adapter from scratch. Return a negative
2714 * errno error code on failure paths.
2715 */
2716static int __devinit velocity_found1(struct pci_dev *pdev, const struct pci_device_id *ent)
2717{
2718 static int first = 1;
2719 struct net_device *dev;
2720 int i;
2721 const char *drv_string;
2722 const struct velocity_info_tbl *info = &chip_info_table[ent->driver_data];
2723 struct velocity_info *vptr;
2724 struct mac_regs __iomem *regs;
2725 int ret = -ENOMEM;
2726
2727 /* FIXME: this driver, like almost all other ethernet drivers,
2728 * can support more than MAX_UNITS.
2729 */
2730 if (velocity_nics >= MAX_UNITS) {
2731 dev_notice(&pdev->dev, "already found %d NICs.\n",
2732 velocity_nics);
2733 return -ENODEV;
2734 }
2735
2736 dev = alloc_etherdev(sizeof(struct velocity_info));
2737 if (!dev) {
2738 dev_err(&pdev->dev, "allocate net device failed.\n");
2739 goto out;
2740 }
2741
2742 /* Chain it all together */
2743
2744 SET_NETDEV_DEV(dev, &pdev->dev);
2745 vptr = netdev_priv(dev);
2746
2747
2748 if (first) {
2749 printk(KERN_INFO "%s Ver. %s\n",
2750 VELOCITY_FULL_DRV_NAM, VELOCITY_VERSION);
2751 printk(KERN_INFO "Copyright (c) 2002, 2003 VIA Networking Technologies, Inc.\n");
2752 printk(KERN_INFO "Copyright (c) 2004 Red Hat Inc.\n");
2753 first = 0;
2754 }
2755
2756 velocity_init_info(pdev, vptr, info);
2757
2758 vptr->dev = dev;
2759
2760 ret = pci_enable_device(pdev);
2761 if (ret < 0)
2762 goto err_free_dev;
2763
2764 dev->irq = pdev->irq;
2765
2766 ret = velocity_get_pci_info(vptr, pdev);
2767 if (ret < 0) {
2768 /* error message already printed */
2769 goto err_disable;
2770 }
2771
2772 ret = pci_request_regions(pdev, VELOCITY_NAME);
2773 if (ret < 0) {
2774 dev_err(&pdev->dev, "No PCI resources.\n");
2775 goto err_disable;
2776 }
2777
2778 regs = ioremap(vptr->memaddr, VELOCITY_IO_SIZE);
2779 if (regs == NULL) {
2780 ret = -EIO;
2781 goto err_release_res;
2782 }
2783
2784 vptr->mac_regs = regs;
2785
2786 mac_wol_reset(regs);
2787
2788 dev->base_addr = vptr->ioaddr;
2789
2790 for (i = 0; i < 6; i++)
2791 dev->dev_addr[i] = readb(&regs->PAR[i]);
2792
2793
2794 drv_string = dev_driver_string(&pdev->dev);
2795
2796 velocity_get_options(&vptr->options, velocity_nics, drv_string);
2797
2798 /*
2799 * Mask out the options cannot be set to the chip
2800 */
2801
2802 vptr->options.flags &= info->flags;
2803
2804 /*
2805 * Enable the chip specified capbilities
2806 */
2807
2808 vptr->flags = vptr->options.flags | (info->flags & 0xFF000000UL);
2809
2810 vptr->wol_opts = vptr->options.wol_opts;
2811 vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
2812
2813 vptr->phy_id = MII_GET_PHY_ID(vptr->mac_regs);
2814
2815 dev->irq = pdev->irq;
2816 dev->netdev_ops = &velocity_netdev_ops;
2817 dev->ethtool_ops = &velocity_ethtool_ops;
2818 netif_napi_add(dev, &vptr->napi, velocity_poll, VELOCITY_NAPI_WEIGHT);
2819
2820 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HW_VLAN_TX;
2821 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER |
2822 NETIF_F_HW_VLAN_RX | NETIF_F_IP_CSUM;
2823
2824 ret = register_netdev(dev);
2825 if (ret < 0)
2826 goto err_iounmap;
2827
2828 if (!velocity_get_link(dev)) {
2829 netif_carrier_off(dev);
2830 vptr->mii_status |= VELOCITY_LINK_FAIL;
2831 }
2832
2833 velocity_print_info(vptr);
2834 pci_set_drvdata(pdev, dev);
2835
2836 /* and leave the chip powered down */
2837
2838 pci_set_power_state(pdev, PCI_D3hot);
2839 velocity_nics++;
2840out:
2841 return ret;
2842
2843err_iounmap:
2844 iounmap(regs);
2845err_release_res:
2846 pci_release_regions(pdev);
2847err_disable:
2848 pci_disable_device(pdev);
2849err_free_dev:
2850 free_netdev(dev);
2851 goto out;
2852}
2853
2854#ifdef CONFIG_PM
2855/**
2856 * wol_calc_crc - WOL CRC
2857 * @pattern: data pattern
2858 * @mask_pattern: mask
2859 *
2860 * Compute the wake on lan crc hashes for the packet header
2861 * we are interested in.
2862 */
2863static u16 wol_calc_crc(int size, u8 *pattern, u8 *mask_pattern)
2864{
2865 u16 crc = 0xFFFF;
2866 u8 mask;
2867 int i, j;
2868
2869 for (i = 0; i < size; i++) {
2870 mask = mask_pattern[i];
2871
2872 /* Skip this loop if the mask equals to zero */
2873 if (mask == 0x00)
2874 continue;
2875
2876 for (j = 0; j < 8; j++) {
2877 if ((mask & 0x01) == 0) {
2878 mask >>= 1;
2879 continue;
2880 }
2881 mask >>= 1;
2882 crc = crc_ccitt(crc, &(pattern[i * 8 + j]), 1);
2883 }
2884 }
2885 /* Finally, invert the result once to get the correct data */
2886 crc = ~crc;
2887 return bitrev32(crc) >> 16;
2888}
2889
2890/**
2891 * velocity_set_wol - set up for wake on lan
2892 * @vptr: velocity to set WOL status on
2893 *
2894 * Set a card up for wake on lan either by unicast or by
2895 * ARP packet.
2896 *
2897 * FIXME: check static buffer is safe here
2898 */
2899static int velocity_set_wol(struct velocity_info *vptr)
2900{
2901 struct mac_regs __iomem *regs = vptr->mac_regs;
2902 enum speed_opt spd_dpx = vptr->options.spd_dpx;
2903 static u8 buf[256];
2904 int i;
2905
2906 static u32 mask_pattern[2][4] = {
2907 {0x00203000, 0x000003C0, 0x00000000, 0x0000000}, /* ARP */
2908 {0xfffff000, 0xffffffff, 0xffffffff, 0x000ffff} /* Magic Packet */
2909 };
2910
2911 writew(0xFFFF, &regs->WOLCRClr);
2912 writeb(WOLCFG_SAB | WOLCFG_SAM, &regs->WOLCFGSet);
2913 writew(WOLCR_MAGIC_EN, &regs->WOLCRSet);
2914
2915 /*
2916 if (vptr->wol_opts & VELOCITY_WOL_PHY)
2917 writew((WOLCR_LINKON_EN|WOLCR_LINKOFF_EN), &regs->WOLCRSet);
2918 */
2919
2920 if (vptr->wol_opts & VELOCITY_WOL_UCAST)
2921 writew(WOLCR_UNICAST_EN, &regs->WOLCRSet);
2922
2923 if (vptr->wol_opts & VELOCITY_WOL_ARP) {
2924 struct arp_packet *arp = (struct arp_packet *) buf;
2925 u16 crc;
2926 memset(buf, 0, sizeof(struct arp_packet) + 7);
2927
2928 for (i = 0; i < 4; i++)
2929 writel(mask_pattern[0][i], &regs->ByteMask[0][i]);
2930
2931 arp->type = htons(ETH_P_ARP);
2932 arp->ar_op = htons(1);
2933
2934 memcpy(arp->ar_tip, vptr->ip_addr, 4);
2935
2936 crc = wol_calc_crc((sizeof(struct arp_packet) + 7) / 8, buf,
2937 (u8 *) & mask_pattern[0][0]);
2938
2939 writew(crc, &regs->PatternCRC[0]);
2940 writew(WOLCR_ARP_EN, &regs->WOLCRSet);
2941 }
2942
2943 BYTE_REG_BITS_ON(PWCFG_WOLTYPE, &regs->PWCFGSet);
2944 BYTE_REG_BITS_ON(PWCFG_LEGACY_WOLEN, &regs->PWCFGSet);
2945
2946 writew(0x0FFF, &regs->WOLSRClr);
2947
2948 if (spd_dpx == SPD_DPX_1000_FULL)
2949 goto mac_done;
2950
2951 if (spd_dpx != SPD_DPX_AUTO)
2952 goto advertise_done;
2953
2954 if (vptr->mii_status & VELOCITY_AUTONEG_ENABLE) {
2955 if (PHYID_GET_PHY_ID(vptr->phy_id) == PHYID_CICADA_CS8201)
2956 MII_REG_BITS_ON(AUXCR_MDPPS, MII_NCONFIG, vptr->mac_regs);
2957
2958 MII_REG_BITS_OFF(ADVERTISE_1000FULL | ADVERTISE_1000HALF, MII_CTRL1000, vptr->mac_regs);
2959 }
2960
2961 if (vptr->mii_status & VELOCITY_SPEED_1000)
2962 MII_REG_BITS_ON(BMCR_ANRESTART, MII_BMCR, vptr->mac_regs);
2963
2964advertise_done:
2965 BYTE_REG_BITS_ON(CHIPGCR_FCMODE, &regs->CHIPGCR);
2966
2967 {
2968 u8 GCR;
2969 GCR = readb(&regs->CHIPGCR);
2970 GCR = (GCR & ~CHIPGCR_FCGMII) | CHIPGCR_FCFDX;
2971 writeb(GCR, &regs->CHIPGCR);
2972 }
2973
2974mac_done:
2975 BYTE_REG_BITS_OFF(ISR_PWEI, &regs->ISR);
2976 /* Turn on SWPTAG just before entering power mode */
2977 BYTE_REG_BITS_ON(STICKHW_SWPTAG, &regs->STICKHW);
2978 /* Go to bed ..... */
2979 BYTE_REG_BITS_ON((STICKHW_DS1 | STICKHW_DS0), &regs->STICKHW);
2980
2981 return 0;
2982}
2983
2984/**
2985 * velocity_save_context - save registers
2986 * @vptr: velocity
2987 * @context: buffer for stored context
2988 *
2989 * Retrieve the current configuration from the velocity hardware
2990 * and stash it in the context structure, for use by the context
2991 * restore functions. This allows us to save things we need across
2992 * power down states
2993 */
2994static void velocity_save_context(struct velocity_info *vptr, struct velocity_context *context)
2995{
2996 struct mac_regs __iomem *regs = vptr->mac_regs;
2997 u16 i;
2998 u8 __iomem *ptr = (u8 __iomem *)regs;
2999
3000 for (i = MAC_REG_PAR; i < MAC_REG_CR0_CLR; i += 4)
3001 *((u32 *) (context->mac_reg + i)) = readl(ptr + i);
3002
3003 for (i = MAC_REG_MAR; i < MAC_REG_TDCSR_CLR; i += 4)
3004 *((u32 *) (context->mac_reg + i)) = readl(ptr + i);
3005
3006 for (i = MAC_REG_RDBASE_LO; i < MAC_REG_FIFO_TEST0; i += 4)
3007 *((u32 *) (context->mac_reg + i)) = readl(ptr + i);
3008
3009}
3010
3011static int velocity_suspend(struct pci_dev *pdev, pm_message_t state)
3012{
3013 struct net_device *dev = pci_get_drvdata(pdev);
3014 struct velocity_info *vptr = netdev_priv(dev);
3015 unsigned long flags;
3016
3017 if (!netif_running(vptr->dev))
3018 return 0;
3019
3020 netif_device_detach(vptr->dev);
3021
3022 spin_lock_irqsave(&vptr->lock, flags);
3023 pci_save_state(pdev);
3024
3025 if (vptr->flags & VELOCITY_FLAGS_WOL_ENABLED) {
3026 velocity_get_ip(vptr);
3027 velocity_save_context(vptr, &vptr->context);
3028 velocity_shutdown(vptr);
3029 velocity_set_wol(vptr);
3030 pci_enable_wake(pdev, PCI_D3hot, 1);
3031 pci_set_power_state(pdev, PCI_D3hot);
3032 } else {
3033 velocity_save_context(vptr, &vptr->context);
3034 velocity_shutdown(vptr);
3035 pci_disable_device(pdev);
3036 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3037 }
3038
3039 spin_unlock_irqrestore(&vptr->lock, flags);
3040 return 0;
3041}
3042
3043/**
3044 * velocity_restore_context - restore registers
3045 * @vptr: velocity
3046 * @context: buffer for stored context
3047 *
3048 * Reload the register configuration from the velocity context
3049 * created by velocity_save_context.
3050 */
3051static void velocity_restore_context(struct velocity_info *vptr, struct velocity_context *context)
3052{
3053 struct mac_regs __iomem *regs = vptr->mac_regs;
3054 int i;
3055 u8 __iomem *ptr = (u8 __iomem *)regs;
3056
3057 for (i = MAC_REG_PAR; i < MAC_REG_CR0_SET; i += 4)
3058 writel(*((u32 *) (context->mac_reg + i)), ptr + i);
3059
3060 /* Just skip cr0 */
3061 for (i = MAC_REG_CR1_SET; i < MAC_REG_CR0_CLR; i++) {
3062 /* Clear */
3063 writeb(~(*((u8 *) (context->mac_reg + i))), ptr + i + 4);
3064 /* Set */
3065 writeb(*((u8 *) (context->mac_reg + i)), ptr + i);
3066 }
3067
3068 for (i = MAC_REG_MAR; i < MAC_REG_IMR; i += 4)
3069 writel(*((u32 *) (context->mac_reg + i)), ptr + i);
3070
3071 for (i = MAC_REG_RDBASE_LO; i < MAC_REG_FIFO_TEST0; i += 4)
3072 writel(*((u32 *) (context->mac_reg + i)), ptr + i);
3073
3074 for (i = MAC_REG_TDCSR_SET; i <= MAC_REG_RDCSR_SET; i++)
3075 writeb(*((u8 *) (context->mac_reg + i)), ptr + i);
3076}
3077
3078static int velocity_resume(struct pci_dev *pdev)
3079{
3080 struct net_device *dev = pci_get_drvdata(pdev);
3081 struct velocity_info *vptr = netdev_priv(dev);
3082 unsigned long flags;
3083 int i;
3084
3085 if (!netif_running(vptr->dev))
3086 return 0;
3087
3088 pci_set_power_state(pdev, PCI_D0);
3089 pci_enable_wake(pdev, 0, 0);
3090 pci_restore_state(pdev);
3091
3092 mac_wol_reset(vptr->mac_regs);
3093
3094 spin_lock_irqsave(&vptr->lock, flags);
3095 velocity_restore_context(vptr, &vptr->context);
3096 velocity_init_registers(vptr, VELOCITY_INIT_WOL);
3097 mac_disable_int(vptr->mac_regs);
3098
3099 velocity_tx_srv(vptr);
3100
3101 for (i = 0; i < vptr->tx.numq; i++) {
3102 if (vptr->tx.used[i])
3103 mac_tx_queue_wake(vptr->mac_regs, i);
3104 }
3105
3106 mac_enable_int(vptr->mac_regs);
3107 spin_unlock_irqrestore(&vptr->lock, flags);
3108 netif_device_attach(vptr->dev);
3109
3110 return 0;
3111}
3112#endif
3113
3114/*
3115 * Definition for our device driver. The PCI layer interface
3116 * uses this to handle all our card discover and plugging
3117 */
3118static struct pci_driver velocity_driver = {
3119 .name = VELOCITY_NAME,
3120 .id_table = velocity_id_table,
3121 .probe = velocity_found1,
3122 .remove = __devexit_p(velocity_remove1),
3123#ifdef CONFIG_PM
3124 .suspend = velocity_suspend,
3125 .resume = velocity_resume,
3126#endif
3127};
3128
3129
3130/**
3131 * velocity_ethtool_up - pre hook for ethtool
3132 * @dev: network device
3133 *
3134 * Called before an ethtool operation. We need to make sure the
3135 * chip is out of D3 state before we poke at it.
3136 */
3137static int velocity_ethtool_up(struct net_device *dev)
3138{
3139 struct velocity_info *vptr = netdev_priv(dev);
3140 if (!netif_running(dev))
3141 pci_set_power_state(vptr->pdev, PCI_D0);
3142 return 0;
3143}
3144
3145/**
3146 * velocity_ethtool_down - post hook for ethtool
3147 * @dev: network device
3148 *
3149 * Called after an ethtool operation. Restore the chip back to D3
3150 * state if it isn't running.
3151 */
3152static void velocity_ethtool_down(struct net_device *dev)
3153{
3154 struct velocity_info *vptr = netdev_priv(dev);
3155 if (!netif_running(dev))
3156 pci_set_power_state(vptr->pdev, PCI_D3hot);
3157}
3158
3159static int velocity_get_settings(struct net_device *dev,
3160 struct ethtool_cmd *cmd)
3161{
3162 struct velocity_info *vptr = netdev_priv(dev);
3163 struct mac_regs __iomem *regs = vptr->mac_regs;
3164 u32 status;
3165 status = check_connection_type(vptr->mac_regs);
3166
3167 cmd->supported = SUPPORTED_TP |
3168 SUPPORTED_Autoneg |
3169 SUPPORTED_10baseT_Half |
3170 SUPPORTED_10baseT_Full |
3171 SUPPORTED_100baseT_Half |
3172 SUPPORTED_100baseT_Full |
3173 SUPPORTED_1000baseT_Half |
3174 SUPPORTED_1000baseT_Full;
3175
3176 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
3177 if (vptr->options.spd_dpx == SPD_DPX_AUTO) {
3178 cmd->advertising |=
3179 ADVERTISED_10baseT_Half |
3180 ADVERTISED_10baseT_Full |
3181 ADVERTISED_100baseT_Half |
3182 ADVERTISED_100baseT_Full |
3183 ADVERTISED_1000baseT_Half |
3184 ADVERTISED_1000baseT_Full;
3185 } else {
3186 switch (vptr->options.spd_dpx) {
3187 case SPD_DPX_1000_FULL:
3188 cmd->advertising |= ADVERTISED_1000baseT_Full;
3189 break;
3190 case SPD_DPX_100_HALF:
3191 cmd->advertising |= ADVERTISED_100baseT_Half;
3192 break;
3193 case SPD_DPX_100_FULL:
3194 cmd->advertising |= ADVERTISED_100baseT_Full;
3195 break;
3196 case SPD_DPX_10_HALF:
3197 cmd->advertising |= ADVERTISED_10baseT_Half;
3198 break;
3199 case SPD_DPX_10_FULL:
3200 cmd->advertising |= ADVERTISED_10baseT_Full;
3201 break;
3202 default:
3203 break;
3204 }
3205 }
3206
3207 if (status & VELOCITY_SPEED_1000)
3208 ethtool_cmd_speed_set(cmd, SPEED_1000);
3209 else if (status & VELOCITY_SPEED_100)
3210 ethtool_cmd_speed_set(cmd, SPEED_100);
3211 else
3212 ethtool_cmd_speed_set(cmd, SPEED_10);
3213
3214 cmd->autoneg = (status & VELOCITY_AUTONEG_ENABLE) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3215 cmd->port = PORT_TP;
3216 cmd->transceiver = XCVR_INTERNAL;
3217 cmd->phy_address = readb(&regs->MIIADR) & 0x1F;
3218
3219 if (status & VELOCITY_DUPLEX_FULL)
3220 cmd->duplex = DUPLEX_FULL;
3221 else
3222 cmd->duplex = DUPLEX_HALF;
3223
3224 return 0;
3225}
3226
3227static int velocity_set_settings(struct net_device *dev,
3228 struct ethtool_cmd *cmd)
3229{
3230 struct velocity_info *vptr = netdev_priv(dev);
3231 u32 speed = ethtool_cmd_speed(cmd);
3232 u32 curr_status;
3233 u32 new_status = 0;
3234 int ret = 0;
3235
3236 curr_status = check_connection_type(vptr->mac_regs);
3237 curr_status &= (~VELOCITY_LINK_FAIL);
3238
3239 new_status |= ((cmd->autoneg) ? VELOCITY_AUTONEG_ENABLE : 0);
3240 new_status |= ((speed == SPEED_1000) ? VELOCITY_SPEED_1000 : 0);
3241 new_status |= ((speed == SPEED_100) ? VELOCITY_SPEED_100 : 0);
3242 new_status |= ((speed == SPEED_10) ? VELOCITY_SPEED_10 : 0);
3243 new_status |= ((cmd->duplex == DUPLEX_FULL) ? VELOCITY_DUPLEX_FULL : 0);
3244
3245 if ((new_status & VELOCITY_AUTONEG_ENABLE) &&
3246 (new_status != (curr_status | VELOCITY_AUTONEG_ENABLE))) {
3247 ret = -EINVAL;
3248 } else {
3249 enum speed_opt spd_dpx;
3250
3251 if (new_status & VELOCITY_AUTONEG_ENABLE)
3252 spd_dpx = SPD_DPX_AUTO;
3253 else if ((new_status & VELOCITY_SPEED_1000) &&
3254 (new_status & VELOCITY_DUPLEX_FULL)) {
3255 spd_dpx = SPD_DPX_1000_FULL;
3256 } else if (new_status & VELOCITY_SPEED_100)
3257 spd_dpx = (new_status & VELOCITY_DUPLEX_FULL) ?
3258 SPD_DPX_100_FULL : SPD_DPX_100_HALF;
3259 else if (new_status & VELOCITY_SPEED_10)
3260 spd_dpx = (new_status & VELOCITY_DUPLEX_FULL) ?
3261 SPD_DPX_10_FULL : SPD_DPX_10_HALF;
3262 else
3263 return -EOPNOTSUPP;
3264
3265 vptr->options.spd_dpx = spd_dpx;
3266
3267 velocity_set_media_mode(vptr, new_status);
3268 }
3269
3270 return ret;
3271}
3272
3273static void velocity_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3274{
3275 struct velocity_info *vptr = netdev_priv(dev);
3276 strcpy(info->driver, VELOCITY_NAME);
3277 strcpy(info->version, VELOCITY_VERSION);
3278 strcpy(info->bus_info, pci_name(vptr->pdev));
3279}
3280
3281static void velocity_ethtool_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3282{
3283 struct velocity_info *vptr = netdev_priv(dev);
3284 wol->supported = WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_ARP;
3285 wol->wolopts |= WAKE_MAGIC;
3286 /*
3287 if (vptr->wol_opts & VELOCITY_WOL_PHY)
3288 wol.wolopts|=WAKE_PHY;
3289 */
3290 if (vptr->wol_opts & VELOCITY_WOL_UCAST)
3291 wol->wolopts |= WAKE_UCAST;
3292 if (vptr->wol_opts & VELOCITY_WOL_ARP)
3293 wol->wolopts |= WAKE_ARP;
3294 memcpy(&wol->sopass, vptr->wol_passwd, 6);
3295}
3296
3297static int velocity_ethtool_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3298{
3299 struct velocity_info *vptr = netdev_priv(dev);
3300
3301 if (!(wol->wolopts & (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_ARP)))
3302 return -EFAULT;
3303 vptr->wol_opts = VELOCITY_WOL_MAGIC;
3304
3305 /*
3306 if (wol.wolopts & WAKE_PHY) {
3307 vptr->wol_opts|=VELOCITY_WOL_PHY;
3308 vptr->flags |=VELOCITY_FLAGS_WOL_ENABLED;
3309 }
3310 */
3311
3312 if (wol->wolopts & WAKE_MAGIC) {
3313 vptr->wol_opts |= VELOCITY_WOL_MAGIC;
3314 vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
3315 }
3316 if (wol->wolopts & WAKE_UCAST) {
3317 vptr->wol_opts |= VELOCITY_WOL_UCAST;
3318 vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
3319 }
3320 if (wol->wolopts & WAKE_ARP) {
3321 vptr->wol_opts |= VELOCITY_WOL_ARP;
3322 vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
3323 }
3324 memcpy(vptr->wol_passwd, wol->sopass, 6);
3325 return 0;
3326}
3327
3328static u32 velocity_get_msglevel(struct net_device *dev)
3329{
3330 return msglevel;
3331}
3332
3333static void velocity_set_msglevel(struct net_device *dev, u32 value)
3334{
3335 msglevel = value;
3336}
3337
3338static int get_pending_timer_val(int val)
3339{
3340 int mult_bits = val >> 6;
3341 int mult = 1;
3342
3343 switch (mult_bits)
3344 {
3345 case 1:
3346 mult = 4; break;
3347 case 2:
3348 mult = 16; break;
3349 case 3:
3350 mult = 64; break;
3351 case 0:
3352 default:
3353 break;
3354 }
3355
3356 return (val & 0x3f) * mult;
3357}
3358
3359static void set_pending_timer_val(int *val, u32 us)
3360{
3361 u8 mult = 0;
3362 u8 shift = 0;
3363
3364 if (us >= 0x3f) {
3365 mult = 1; /* mult with 4 */
3366 shift = 2;
3367 }
3368 if (us >= 0x3f * 4) {
3369 mult = 2; /* mult with 16 */
3370 shift = 4;
3371 }
3372 if (us >= 0x3f * 16) {
3373 mult = 3; /* mult with 64 */
3374 shift = 6;
3375 }
3376
3377 *val = (mult << 6) | ((us >> shift) & 0x3f);
3378}
3379
3380
3381static int velocity_get_coalesce(struct net_device *dev,
3382 struct ethtool_coalesce *ecmd)
3383{
3384 struct velocity_info *vptr = netdev_priv(dev);
3385
3386 ecmd->tx_max_coalesced_frames = vptr->options.tx_intsup;
3387 ecmd->rx_max_coalesced_frames = vptr->options.rx_intsup;
3388
3389 ecmd->rx_coalesce_usecs = get_pending_timer_val(vptr->options.rxqueue_timer);
3390 ecmd->tx_coalesce_usecs = get_pending_timer_val(vptr->options.txqueue_timer);
3391
3392 return 0;
3393}
3394
3395static int velocity_set_coalesce(struct net_device *dev,
3396 struct ethtool_coalesce *ecmd)
3397{
3398 struct velocity_info *vptr = netdev_priv(dev);
3399 int max_us = 0x3f * 64;
3400 unsigned long flags;
3401
3402 /* 6 bits of */
3403 if (ecmd->tx_coalesce_usecs > max_us)
3404 return -EINVAL;
3405 if (ecmd->rx_coalesce_usecs > max_us)
3406 return -EINVAL;
3407
3408 if (ecmd->tx_max_coalesced_frames > 0xff)
3409 return -EINVAL;
3410 if (ecmd->rx_max_coalesced_frames > 0xff)
3411 return -EINVAL;
3412
3413 vptr->options.rx_intsup = ecmd->rx_max_coalesced_frames;
3414 vptr->options.tx_intsup = ecmd->tx_max_coalesced_frames;
3415
3416 set_pending_timer_val(&vptr->options.rxqueue_timer,
3417 ecmd->rx_coalesce_usecs);
3418 set_pending_timer_val(&vptr->options.txqueue_timer,
3419 ecmd->tx_coalesce_usecs);
3420
3421 /* Setup the interrupt suppression and queue timers */
3422 spin_lock_irqsave(&vptr->lock, flags);
3423 mac_disable_int(vptr->mac_regs);
3424 setup_adaptive_interrupts(vptr);
3425 setup_queue_timers(vptr);
3426
3427 mac_write_int_mask(vptr->int_mask, vptr->mac_regs);
3428 mac_clear_isr(vptr->mac_regs);
3429 mac_enable_int(vptr->mac_regs);
3430 spin_unlock_irqrestore(&vptr->lock, flags);
3431
3432 return 0;
3433}
3434
3435static const char velocity_gstrings[][ETH_GSTRING_LEN] = {
3436 "rx_all",
3437 "rx_ok",
3438 "tx_ok",
3439 "rx_error",
3440 "rx_runt_ok",
3441 "rx_runt_err",
3442 "rx_64",
3443 "tx_64",
3444 "rx_65_to_127",
3445 "tx_65_to_127",
3446 "rx_128_to_255",
3447 "tx_128_to_255",
3448 "rx_256_to_511",
3449 "tx_256_to_511",
3450 "rx_512_to_1023",
3451 "tx_512_to_1023",
3452 "rx_1024_to_1518",
3453 "tx_1024_to_1518",
3454 "tx_ether_collisions",
3455 "rx_crc_errors",
3456 "rx_jumbo",
3457 "tx_jumbo",
3458 "rx_mac_control_frames",
3459 "tx_mac_control_frames",
3460 "rx_frame_alignement_errors",
3461 "rx_long_ok",
3462 "rx_long_err",
3463 "tx_sqe_errors",
3464 "rx_no_buf",
3465 "rx_symbol_errors",
3466 "in_range_length_errors",
3467 "late_collisions"
3468};
3469
3470static void velocity_get_strings(struct net_device *dev, u32 sset, u8 *data)
3471{
3472 switch (sset) {
3473 case ETH_SS_STATS:
3474 memcpy(data, *velocity_gstrings, sizeof(velocity_gstrings));
3475 break;
3476 }
3477}
3478
3479static int velocity_get_sset_count(struct net_device *dev, int sset)
3480{
3481 switch (sset) {
3482 case ETH_SS_STATS:
3483 return ARRAY_SIZE(velocity_gstrings);
3484 default:
3485 return -EOPNOTSUPP;
3486 }
3487}
3488
3489static void velocity_get_ethtool_stats(struct net_device *dev,
3490 struct ethtool_stats *stats, u64 *data)
3491{
3492 if (netif_running(dev)) {
3493 struct velocity_info *vptr = netdev_priv(dev);
3494 u32 *p = vptr->mib_counter;
3495 int i;
3496
3497 spin_lock_irq(&vptr->lock);
3498 velocity_update_hw_mibs(vptr);
3499 spin_unlock_irq(&vptr->lock);
3500
3501 for (i = 0; i < ARRAY_SIZE(velocity_gstrings); i++)
3502 *data++ = *p++;
3503 }
3504}
3505
3506static const struct ethtool_ops velocity_ethtool_ops = {
3507 .get_settings = velocity_get_settings,
3508 .set_settings = velocity_set_settings,
3509 .get_drvinfo = velocity_get_drvinfo,
3510 .get_wol = velocity_ethtool_get_wol,
3511 .set_wol = velocity_ethtool_set_wol,
3512 .get_msglevel = velocity_get_msglevel,
3513 .set_msglevel = velocity_set_msglevel,
3514 .get_link = velocity_get_link,
3515 .get_strings = velocity_get_strings,
3516 .get_sset_count = velocity_get_sset_count,
3517 .get_ethtool_stats = velocity_get_ethtool_stats,
3518 .get_coalesce = velocity_get_coalesce,
3519 .set_coalesce = velocity_set_coalesce,
3520 .begin = velocity_ethtool_up,
3521 .complete = velocity_ethtool_down
3522};
3523
3524#if defined(CONFIG_PM) && defined(CONFIG_INET)
3525static int velocity_netdev_event(struct notifier_block *nb, unsigned long notification, void *ptr)
3526{
3527 struct in_ifaddr *ifa = ptr;
3528 struct net_device *dev = ifa->ifa_dev->dev;
3529
3530 if (dev_net(dev) == &init_net &&
3531 dev->netdev_ops == &velocity_netdev_ops)
3532 velocity_get_ip(netdev_priv(dev));
3533
3534 return NOTIFY_DONE;
3535}
3536
3537static struct notifier_block velocity_inetaddr_notifier = {
3538 .notifier_call = velocity_netdev_event,
3539};
3540
3541static void velocity_register_notifier(void)
3542{
3543 register_inetaddr_notifier(&velocity_inetaddr_notifier);
3544}
3545
3546static void velocity_unregister_notifier(void)
3547{
3548 unregister_inetaddr_notifier(&velocity_inetaddr_notifier);
3549}
3550
3551#else
3552
3553#define velocity_register_notifier() do {} while (0)
3554#define velocity_unregister_notifier() do {} while (0)
3555
3556#endif /* defined(CONFIG_PM) && defined(CONFIG_INET) */
3557
3558/**
3559 * velocity_init_module - load time function
3560 *
3561 * Called when the velocity module is loaded. The PCI driver
3562 * is registered with the PCI layer, and in turn will call
3563 * the probe functions for each velocity adapter installed
3564 * in the system.
3565 */
3566static int __init velocity_init_module(void)
3567{
3568 int ret;
3569
3570 velocity_register_notifier();
3571 ret = pci_register_driver(&velocity_driver);
3572 if (ret < 0)
3573 velocity_unregister_notifier();
3574 return ret;
3575}
3576
3577/**
3578 * velocity_cleanup - module unload
3579 *
3580 * When the velocity hardware is unloaded this function is called.
3581 * It will clean up the notifiers and the unregister the PCI
3582 * driver interface for this hardware. This in turn cleans up
3583 * all discovered interfaces before returning from the function
3584 */
3585static void __exit velocity_cleanup_module(void)
3586{
3587 velocity_unregister_notifier();
3588 pci_unregister_driver(&velocity_driver);
3589}
3590
3591module_init(velocity_init_module);
3592module_exit(velocity_cleanup_module);
diff --git a/drivers/net/ethernet/via/via-velocity.h b/drivers/net/ethernet/via/via-velocity.h
new file mode 100644
index 000000000000..4cb9f13485e9
--- /dev/null
+++ b/drivers/net/ethernet/via/via-velocity.h
@@ -0,0 +1,1579 @@
1/*
2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
3 * All rights reserved.
4 *
5 * This software may be redistributed and/or modified under
6 * the terms of the GNU General Public License as published by the Free
7 * Software Foundation; either version 2 of the License, or
8 * any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * File: via-velocity.h
16 *
17 * Purpose: Header file to define driver's private structures.
18 *
19 * Author: Chuang Liang-Shing, AJ Jiang
20 *
21 * Date: Jan 24, 2003
22 */
23
24
25#ifndef VELOCITY_H
26#define VELOCITY_H
27
28#define VELOCITY_TX_CSUM_SUPPORT
29
30#define VELOCITY_NAME "via-velocity"
31#define VELOCITY_FULL_DRV_NAM "VIA Networking Velocity Family Gigabit Ethernet Adapter Driver"
32#define VELOCITY_VERSION "1.15"
33
34#define VELOCITY_IO_SIZE 256
35#define VELOCITY_NAPI_WEIGHT 64
36
37#define PKT_BUF_SZ 1540
38
39#define MAX_UNITS 8
40#define OPTION_DEFAULT { [0 ... MAX_UNITS-1] = -1}
41
42#define REV_ID_VT6110 (0)
43
44#define BYTE_REG_BITS_ON(x,p) do { writeb(readb((p))|(x),(p));} while (0)
45#define WORD_REG_BITS_ON(x,p) do { writew(readw((p))|(x),(p));} while (0)
46#define DWORD_REG_BITS_ON(x,p) do { writel(readl((p))|(x),(p));} while (0)
47
48#define BYTE_REG_BITS_IS_ON(x,p) (readb((p)) & (x))
49#define WORD_REG_BITS_IS_ON(x,p) (readw((p)) & (x))
50#define DWORD_REG_BITS_IS_ON(x,p) (readl((p)) & (x))
51
52#define BYTE_REG_BITS_OFF(x,p) do { writeb(readb((p)) & (~(x)),(p));} while (0)
53#define WORD_REG_BITS_OFF(x,p) do { writew(readw((p)) & (~(x)),(p));} while (0)
54#define DWORD_REG_BITS_OFF(x,p) do { writel(readl((p)) & (~(x)),(p));} while (0)
55
56#define BYTE_REG_BITS_SET(x,m,p) do { writeb( (readb((p)) & (~(m))) |(x),(p));} while (0)
57#define WORD_REG_BITS_SET(x,m,p) do { writew( (readw((p)) & (~(m))) |(x),(p));} while (0)
58#define DWORD_REG_BITS_SET(x,m,p) do { writel( (readl((p)) & (~(m)))|(x),(p));} while (0)
59
60#define VAR_USED(p) do {(p)=(p);} while (0)
61
62/*
63 * Purpose: Structures for MAX RX/TX descriptors.
64 */
65
66
67#define B_OWNED_BY_CHIP 1
68#define B_OWNED_BY_HOST 0
69
70/*
71 * Bits in the RSR0 register
72 */
73
74#define RSR_DETAG cpu_to_le16(0x0080)
75#define RSR_SNTAG cpu_to_le16(0x0040)
76#define RSR_RXER cpu_to_le16(0x0020)
77#define RSR_RL cpu_to_le16(0x0010)
78#define RSR_CE cpu_to_le16(0x0008)
79#define RSR_FAE cpu_to_le16(0x0004)
80#define RSR_CRC cpu_to_le16(0x0002)
81#define RSR_VIDM cpu_to_le16(0x0001)
82
83/*
84 * Bits in the RSR1 register
85 */
86
87#define RSR_RXOK cpu_to_le16(0x8000) // rx OK
88#define RSR_PFT cpu_to_le16(0x4000) // Perfect filtering address match
89#define RSR_MAR cpu_to_le16(0x2000) // MAC accept multicast address packet
90#define RSR_BAR cpu_to_le16(0x1000) // MAC accept broadcast address packet
91#define RSR_PHY cpu_to_le16(0x0800) // MAC accept physical address packet
92#define RSR_VTAG cpu_to_le16(0x0400) // 802.1p/1q tagging packet indicator
93#define RSR_STP cpu_to_le16(0x0200) // start of packet
94#define RSR_EDP cpu_to_le16(0x0100) // end of packet
95
96/*
97 * Bits in the CSM register
98 */
99
100#define CSM_IPOK 0x40 //IP Checksum validation ok
101#define CSM_TUPOK 0x20 //TCP/UDP Checksum validation ok
102#define CSM_FRAG 0x10 //Fragment IP datagram
103#define CSM_IPKT 0x04 //Received an IP packet
104#define CSM_TCPKT 0x02 //Received a TCP packet
105#define CSM_UDPKT 0x01 //Received a UDP packet
106
107/*
108 * Bits in the TSR0 register
109 */
110
111#define TSR0_ABT cpu_to_le16(0x0080) // Tx abort because of excessive collision
112#define TSR0_OWT cpu_to_le16(0x0040) // Jumbo frame Tx abort
113#define TSR0_OWC cpu_to_le16(0x0020) // Out of window collision
114#define TSR0_COLS cpu_to_le16(0x0010) // experience collision in this transmit event
115#define TSR0_NCR3 cpu_to_le16(0x0008) // collision retry counter[3]
116#define TSR0_NCR2 cpu_to_le16(0x0004) // collision retry counter[2]
117#define TSR0_NCR1 cpu_to_le16(0x0002) // collision retry counter[1]
118#define TSR0_NCR0 cpu_to_le16(0x0001) // collision retry counter[0]
119#define TSR0_TERR cpu_to_le16(0x8000) //
120#define TSR0_FDX cpu_to_le16(0x4000) // current transaction is serviced by full duplex mode
121#define TSR0_GMII cpu_to_le16(0x2000) // current transaction is serviced by GMII mode
122#define TSR0_LNKFL cpu_to_le16(0x1000) // packet serviced during link down
123#define TSR0_SHDN cpu_to_le16(0x0400) // shutdown case
124#define TSR0_CRS cpu_to_le16(0x0200) // carrier sense lost
125#define TSR0_CDH cpu_to_le16(0x0100) // AQE test fail (CD heartbeat)
126
127//
128// Bits in the TCR0 register
129//
130#define TCR0_TIC 0x80 // assert interrupt immediately while descriptor has been send complete
131#define TCR0_PIC 0x40 // priority interrupt request, INA# is issued over adaptive interrupt scheme
132#define TCR0_VETAG 0x20 // enable VLAN tag
133#define TCR0_IPCK 0x10 // request IP checksum calculation.
134#define TCR0_UDPCK 0x08 // request UDP checksum calculation.
135#define TCR0_TCPCK 0x04 // request TCP checksum calculation.
136#define TCR0_JMBO 0x02 // indicate a jumbo packet in GMAC side
137#define TCR0_CRC 0x01 // disable CRC generation
138
139#define TCPLS_NORMAL 3
140#define TCPLS_START 2
141#define TCPLS_END 1
142#define TCPLS_MED 0
143
144
145// max transmit or receive buffer size
146#define CB_RX_BUF_SIZE 2048UL // max buffer size
147 // NOTE: must be multiple of 4
148
149#define CB_MAX_RD_NUM 512 // MAX # of RD
150#define CB_MAX_TD_NUM 256 // MAX # of TD
151
152#define CB_INIT_RD_NUM_3119 128 // init # of RD, for setup VT3119
153#define CB_INIT_TD_NUM_3119 64 // init # of TD, for setup VT3119
154
155#define CB_INIT_RD_NUM 128 // init # of RD, for setup default
156#define CB_INIT_TD_NUM 64 // init # of TD, for setup default
157
158// for 3119
159#define CB_TD_RING_NUM 4 // # of TD rings.
160#define CB_MAX_SEG_PER_PKT 7 // max data seg per packet (Tx)
161
162
163/*
164 * If collisions excess 15 times , tx will abort, and
165 * if tx fifo underflow, tx will fail
166 * we should try to resend it
167 */
168
169#define CB_MAX_TX_ABORT_RETRY 3
170
171/*
172 * Receive descriptor
173 */
174
175struct rdesc0 {
176 __le16 RSR; /* Receive status */
177 __le16 len; /* bits 0--13; bit 15 - owner */
178};
179
180struct rdesc1 {
181 __le16 PQTAG;
182 u8 CSM;
183 u8 IPKT;
184};
185
186enum {
187 RX_INTEN = cpu_to_le16(0x8000)
188};
189
190struct rx_desc {
191 struct rdesc0 rdesc0;
192 struct rdesc1 rdesc1;
193 __le32 pa_low; /* Low 32 bit PCI address */
194 __le16 pa_high; /* Next 16 bit PCI address (48 total) */
195 __le16 size; /* bits 0--14 - frame size, bit 15 - enable int. */
196} __packed;
197
198/*
199 * Transmit descriptor
200 */
201
202struct tdesc0 {
203 __le16 TSR; /* Transmit status register */
204 __le16 len; /* bits 0--13 - size of frame, bit 15 - owner */
205};
206
207struct tdesc1 {
208 __le16 vlan;
209 u8 TCR;
210 u8 cmd; /* bits 0--1 - TCPLS, bits 4--7 - CMDZ */
211} __packed;
212
213enum {
214 TD_QUEUE = cpu_to_le16(0x8000)
215};
216
217struct td_buf {
218 __le32 pa_low;
219 __le16 pa_high;
220 __le16 size; /* bits 0--13 - size, bit 15 - queue */
221} __packed;
222
223struct tx_desc {
224 struct tdesc0 tdesc0;
225 struct tdesc1 tdesc1;
226 struct td_buf td_buf[7];
227};
228
229struct velocity_rd_info {
230 struct sk_buff *skb;
231 dma_addr_t skb_dma;
232};
233
234/*
235 * Used to track transmit side buffers.
236 */
237
238struct velocity_td_info {
239 struct sk_buff *skb;
240 int nskb_dma;
241 dma_addr_t skb_dma[7];
242};
243
244enum velocity_owner {
245 OWNED_BY_HOST = 0,
246 OWNED_BY_NIC = cpu_to_le16(0x8000)
247};
248
249
250/*
251 * MAC registers and macros.
252 */
253
254
255#define MCAM_SIZE 64
256#define VCAM_SIZE 64
257#define TX_QUEUE_NO 4
258
259#define MAX_HW_MIB_COUNTER 32
260#define VELOCITY_MIN_MTU (64)
261#define VELOCITY_MAX_MTU (9000)
262
263/*
264 * Registers in the MAC
265 */
266
267#define MAC_REG_PAR 0x00 // physical address
268#define MAC_REG_RCR 0x06
269#define MAC_REG_TCR 0x07
270#define MAC_REG_CR0_SET 0x08
271#define MAC_REG_CR1_SET 0x09
272#define MAC_REG_CR2_SET 0x0A
273#define MAC_REG_CR3_SET 0x0B
274#define MAC_REG_CR0_CLR 0x0C
275#define MAC_REG_CR1_CLR 0x0D
276#define MAC_REG_CR2_CLR 0x0E
277#define MAC_REG_CR3_CLR 0x0F
278#define MAC_REG_MAR 0x10
279#define MAC_REG_CAM 0x10
280#define MAC_REG_DEC_BASE_HI 0x18
281#define MAC_REG_DBF_BASE_HI 0x1C
282#define MAC_REG_ISR_CTL 0x20
283#define MAC_REG_ISR_HOTMR 0x20
284#define MAC_REG_ISR_TSUPTHR 0x20
285#define MAC_REG_ISR_RSUPTHR 0x20
286#define MAC_REG_ISR_CTL1 0x21
287#define MAC_REG_TXE_SR 0x22
288#define MAC_REG_RXE_SR 0x23
289#define MAC_REG_ISR 0x24
290#define MAC_REG_ISR0 0x24
291#define MAC_REG_ISR1 0x25
292#define MAC_REG_ISR2 0x26
293#define MAC_REG_ISR3 0x27
294#define MAC_REG_IMR 0x28
295#define MAC_REG_IMR0 0x28
296#define MAC_REG_IMR1 0x29
297#define MAC_REG_IMR2 0x2A
298#define MAC_REG_IMR3 0x2B
299#define MAC_REG_TDCSR_SET 0x30
300#define MAC_REG_RDCSR_SET 0x32
301#define MAC_REG_TDCSR_CLR 0x34
302#define MAC_REG_RDCSR_CLR 0x36
303#define MAC_REG_RDBASE_LO 0x38
304#define MAC_REG_RDINDX 0x3C
305#define MAC_REG_TDBASE_LO 0x40
306#define MAC_REG_RDCSIZE 0x50
307#define MAC_REG_TDCSIZE 0x52
308#define MAC_REG_TDINDX 0x54
309#define MAC_REG_TDIDX0 0x54
310#define MAC_REG_TDIDX1 0x56
311#define MAC_REG_TDIDX2 0x58
312#define MAC_REG_TDIDX3 0x5A
313#define MAC_REG_PAUSE_TIMER 0x5C
314#define MAC_REG_RBRDU 0x5E
315#define MAC_REG_FIFO_TEST0 0x60
316#define MAC_REG_FIFO_TEST1 0x64
317#define MAC_REG_CAMADDR 0x68
318#define MAC_REG_CAMCR 0x69
319#define MAC_REG_GFTEST 0x6A
320#define MAC_REG_FTSTCMD 0x6B
321#define MAC_REG_MIICFG 0x6C
322#define MAC_REG_MIISR 0x6D
323#define MAC_REG_PHYSR0 0x6E
324#define MAC_REG_PHYSR1 0x6F
325#define MAC_REG_MIICR 0x70
326#define MAC_REG_MIIADR 0x71
327#define MAC_REG_MIIDATA 0x72
328#define MAC_REG_SOFT_TIMER0 0x74
329#define MAC_REG_SOFT_TIMER1 0x76
330#define MAC_REG_CFGA 0x78
331#define MAC_REG_CFGB 0x79
332#define MAC_REG_CFGC 0x7A
333#define MAC_REG_CFGD 0x7B
334#define MAC_REG_DCFG0 0x7C
335#define MAC_REG_DCFG1 0x7D
336#define MAC_REG_MCFG0 0x7E
337#define MAC_REG_MCFG1 0x7F
338
339#define MAC_REG_TBIST 0x80
340#define MAC_REG_RBIST 0x81
341#define MAC_REG_PMCC 0x82
342#define MAC_REG_STICKHW 0x83
343#define MAC_REG_MIBCR 0x84
344#define MAC_REG_EERSV 0x85
345#define MAC_REG_REVID 0x86
346#define MAC_REG_MIBREAD 0x88
347#define MAC_REG_BPMA 0x8C
348#define MAC_REG_EEWR_DATA 0x8C
349#define MAC_REG_BPMD_WR 0x8F
350#define MAC_REG_BPCMD 0x90
351#define MAC_REG_BPMD_RD 0x91
352#define MAC_REG_EECHKSUM 0x92
353#define MAC_REG_EECSR 0x93
354#define MAC_REG_EERD_DATA 0x94
355#define MAC_REG_EADDR 0x96
356#define MAC_REG_EMBCMD 0x97
357#define MAC_REG_JMPSR0 0x98
358#define MAC_REG_JMPSR1 0x99
359#define MAC_REG_JMPSR2 0x9A
360#define MAC_REG_JMPSR3 0x9B
361#define MAC_REG_CHIPGSR 0x9C
362#define MAC_REG_TESTCFG 0x9D
363#define MAC_REG_DEBUG 0x9E
364#define MAC_REG_CHIPGCR 0x9F /* Chip Operation and Diagnostic Control */
365#define MAC_REG_WOLCR0_SET 0xA0
366#define MAC_REG_WOLCR1_SET 0xA1
367#define MAC_REG_PWCFG_SET 0xA2
368#define MAC_REG_WOLCFG_SET 0xA3
369#define MAC_REG_WOLCR0_CLR 0xA4
370#define MAC_REG_WOLCR1_CLR 0xA5
371#define MAC_REG_PWCFG_CLR 0xA6
372#define MAC_REG_WOLCFG_CLR 0xA7
373#define MAC_REG_WOLSR0_SET 0xA8
374#define MAC_REG_WOLSR1_SET 0xA9
375#define MAC_REG_WOLSR0_CLR 0xAC
376#define MAC_REG_WOLSR1_CLR 0xAD
377#define MAC_REG_PATRN_CRC0 0xB0
378#define MAC_REG_PATRN_CRC1 0xB2
379#define MAC_REG_PATRN_CRC2 0xB4
380#define MAC_REG_PATRN_CRC3 0xB6
381#define MAC_REG_PATRN_CRC4 0xB8
382#define MAC_REG_PATRN_CRC5 0xBA
383#define MAC_REG_PATRN_CRC6 0xBC
384#define MAC_REG_PATRN_CRC7 0xBE
385#define MAC_REG_BYTEMSK0_0 0xC0
386#define MAC_REG_BYTEMSK0_1 0xC4
387#define MAC_REG_BYTEMSK0_2 0xC8
388#define MAC_REG_BYTEMSK0_3 0xCC
389#define MAC_REG_BYTEMSK1_0 0xD0
390#define MAC_REG_BYTEMSK1_1 0xD4
391#define MAC_REG_BYTEMSK1_2 0xD8
392#define MAC_REG_BYTEMSK1_3 0xDC
393#define MAC_REG_BYTEMSK2_0 0xE0
394#define MAC_REG_BYTEMSK2_1 0xE4
395#define MAC_REG_BYTEMSK2_2 0xE8
396#define MAC_REG_BYTEMSK2_3 0xEC
397#define MAC_REG_BYTEMSK3_0 0xF0
398#define MAC_REG_BYTEMSK3_1 0xF4
399#define MAC_REG_BYTEMSK3_2 0xF8
400#define MAC_REG_BYTEMSK3_3 0xFC
401
402/*
403 * Bits in the RCR register
404 */
405
406#define RCR_AS 0x80
407#define RCR_AP 0x40
408#define RCR_AL 0x20
409#define RCR_PROM 0x10
410#define RCR_AB 0x08
411#define RCR_AM 0x04
412#define RCR_AR 0x02
413#define RCR_SEP 0x01
414
415/*
416 * Bits in the TCR register
417 */
418
419#define TCR_TB2BDIS 0x80
420#define TCR_COLTMC1 0x08
421#define TCR_COLTMC0 0x04
422#define TCR_LB1 0x02 /* loopback[1] */
423#define TCR_LB0 0x01 /* loopback[0] */
424
425/*
426 * Bits in the CR0 register
427 */
428
429#define CR0_TXON 0x00000008UL
430#define CR0_RXON 0x00000004UL
431#define CR0_STOP 0x00000002UL /* stop MAC, default = 1 */
432#define CR0_STRT 0x00000001UL /* start MAC */
433#define CR0_SFRST 0x00008000UL /* software reset */
434#define CR0_TM1EN 0x00004000UL
435#define CR0_TM0EN 0x00002000UL
436#define CR0_DPOLL 0x00000800UL /* disable rx/tx auto polling */
437#define CR0_DISAU 0x00000100UL
438#define CR0_XONEN 0x00800000UL
439#define CR0_FDXTFCEN 0x00400000UL /* full-duplex TX flow control enable */
440#define CR0_FDXRFCEN 0x00200000UL /* full-duplex RX flow control enable */
441#define CR0_HDXFCEN 0x00100000UL /* half-duplex flow control enable */
442#define CR0_XHITH1 0x00080000UL /* TX XON high threshold 1 */
443#define CR0_XHITH0 0x00040000UL /* TX XON high threshold 0 */
444#define CR0_XLTH1 0x00020000UL /* TX pause frame low threshold 1 */
445#define CR0_XLTH0 0x00010000UL /* TX pause frame low threshold 0 */
446#define CR0_GSPRST 0x80000000UL
447#define CR0_FORSRST 0x40000000UL
448#define CR0_FPHYRST 0x20000000UL
449#define CR0_DIAG 0x10000000UL
450#define CR0_INTPCTL 0x04000000UL
451#define CR0_GINTMSK1 0x02000000UL
452#define CR0_GINTMSK0 0x01000000UL
453
454/*
455 * Bits in the CR1 register
456 */
457
458#define CR1_SFRST 0x80 /* software reset */
459#define CR1_TM1EN 0x40
460#define CR1_TM0EN 0x20
461#define CR1_DPOLL 0x08 /* disable rx/tx auto polling */
462#define CR1_DISAU 0x01
463
464/*
465 * Bits in the CR2 register
466 */
467
468#define CR2_XONEN 0x80
469#define CR2_FDXTFCEN 0x40 /* full-duplex TX flow control enable */
470#define CR2_FDXRFCEN 0x20 /* full-duplex RX flow control enable */
471#define CR2_HDXFCEN 0x10 /* half-duplex flow control enable */
472#define CR2_XHITH1 0x08 /* TX XON high threshold 1 */
473#define CR2_XHITH0 0x04 /* TX XON high threshold 0 */
474#define CR2_XLTH1 0x02 /* TX pause frame low threshold 1 */
475#define CR2_XLTH0 0x01 /* TX pause frame low threshold 0 */
476
477/*
478 * Bits in the CR3 register
479 */
480
481#define CR3_GSPRST 0x80
482#define CR3_FORSRST 0x40
483#define CR3_FPHYRST 0x20
484#define CR3_DIAG 0x10
485#define CR3_INTPCTL 0x04
486#define CR3_GINTMSK1 0x02
487#define CR3_GINTMSK0 0x01
488
489#define ISRCTL_UDPINT 0x8000
490#define ISRCTL_TSUPDIS 0x4000
491#define ISRCTL_RSUPDIS 0x2000
492#define ISRCTL_PMSK1 0x1000
493#define ISRCTL_PMSK0 0x0800
494#define ISRCTL_INTPD 0x0400
495#define ISRCTL_HCRLD 0x0200
496#define ISRCTL_SCRLD 0x0100
497
498/*
499 * Bits in the ISR_CTL1 register
500 */
501
502#define ISRCTL1_UDPINT 0x80
503#define ISRCTL1_TSUPDIS 0x40
504#define ISRCTL1_RSUPDIS 0x20
505#define ISRCTL1_PMSK1 0x10
506#define ISRCTL1_PMSK0 0x08
507#define ISRCTL1_INTPD 0x04
508#define ISRCTL1_HCRLD 0x02
509#define ISRCTL1_SCRLD 0x01
510
511/*
512 * Bits in the TXE_SR register
513 */
514
515#define TXESR_TFDBS 0x08
516#define TXESR_TDWBS 0x04
517#define TXESR_TDRBS 0x02
518#define TXESR_TDSTR 0x01
519
520/*
521 * Bits in the RXE_SR register
522 */
523
524#define RXESR_RFDBS 0x08
525#define RXESR_RDWBS 0x04
526#define RXESR_RDRBS 0x02
527#define RXESR_RDSTR 0x01
528
529/*
530 * Bits in the ISR register
531 */
532
533#define ISR_ISR3 0x80000000UL
534#define ISR_ISR2 0x40000000UL
535#define ISR_ISR1 0x20000000UL
536#define ISR_ISR0 0x10000000UL
537#define ISR_TXSTLI 0x02000000UL
538#define ISR_RXSTLI 0x01000000UL
539#define ISR_HFLD 0x00800000UL
540#define ISR_UDPI 0x00400000UL
541#define ISR_MIBFI 0x00200000UL
542#define ISR_SHDNI 0x00100000UL
543#define ISR_PHYI 0x00080000UL
544#define ISR_PWEI 0x00040000UL
545#define ISR_TMR1I 0x00020000UL
546#define ISR_TMR0I 0x00010000UL
547#define ISR_SRCI 0x00008000UL
548#define ISR_LSTPEI 0x00004000UL
549#define ISR_LSTEI 0x00002000UL
550#define ISR_OVFI 0x00001000UL
551#define ISR_FLONI 0x00000800UL
552#define ISR_RACEI 0x00000400UL
553#define ISR_TXWB1I 0x00000200UL
554#define ISR_TXWB0I 0x00000100UL
555#define ISR_PTX3I 0x00000080UL
556#define ISR_PTX2I 0x00000040UL
557#define ISR_PTX1I 0x00000020UL
558#define ISR_PTX0I 0x00000010UL
559#define ISR_PTXI 0x00000008UL
560#define ISR_PRXI 0x00000004UL
561#define ISR_PPTXI 0x00000002UL
562#define ISR_PPRXI 0x00000001UL
563
564/*
565 * Bits in the IMR register
566 */
567
568#define IMR_TXSTLM 0x02000000UL
569#define IMR_UDPIM 0x00400000UL
570#define IMR_MIBFIM 0x00200000UL
571#define IMR_SHDNIM 0x00100000UL
572#define IMR_PHYIM 0x00080000UL
573#define IMR_PWEIM 0x00040000UL
574#define IMR_TMR1IM 0x00020000UL
575#define IMR_TMR0IM 0x00010000UL
576
577#define IMR_SRCIM 0x00008000UL
578#define IMR_LSTPEIM 0x00004000UL
579#define IMR_LSTEIM 0x00002000UL
580#define IMR_OVFIM 0x00001000UL
581#define IMR_FLONIM 0x00000800UL
582#define IMR_RACEIM 0x00000400UL
583#define IMR_TXWB1IM 0x00000200UL
584#define IMR_TXWB0IM 0x00000100UL
585
586#define IMR_PTX3IM 0x00000080UL
587#define IMR_PTX2IM 0x00000040UL
588#define IMR_PTX1IM 0x00000020UL
589#define IMR_PTX0IM 0x00000010UL
590#define IMR_PTXIM 0x00000008UL
591#define IMR_PRXIM 0x00000004UL
592#define IMR_PPTXIM 0x00000002UL
593#define IMR_PPRXIM 0x00000001UL
594
595/* 0x0013FB0FUL = initial value of IMR */
596
597#define INT_MASK_DEF (IMR_PPTXIM|IMR_PPRXIM|IMR_PTXIM|IMR_PRXIM|\
598 IMR_PWEIM|IMR_TXWB0IM|IMR_TXWB1IM|IMR_FLONIM|\
599 IMR_OVFIM|IMR_LSTEIM|IMR_LSTPEIM|IMR_SRCIM|IMR_MIBFIM|\
600 IMR_SHDNIM|IMR_TMR1IM|IMR_TMR0IM|IMR_TXSTLM)
601
602/*
603 * Bits in the TDCSR0/1, RDCSR0 register
604 */
605
606#define TRDCSR_DEAD 0x0008
607#define TRDCSR_WAK 0x0004
608#define TRDCSR_ACT 0x0002
609#define TRDCSR_RUN 0x0001
610
611/*
612 * Bits in the CAMADDR register
613 */
614
615#define CAMADDR_CAMEN 0x80
616#define CAMADDR_VCAMSL 0x40
617
618/*
619 * Bits in the CAMCR register
620 */
621
622#define CAMCR_PS1 0x80
623#define CAMCR_PS0 0x40
624#define CAMCR_AITRPKT 0x20
625#define CAMCR_AITR16 0x10
626#define CAMCR_CAMRD 0x08
627#define CAMCR_CAMWR 0x04
628#define CAMCR_PS_CAM_MASK 0x40
629#define CAMCR_PS_CAM_DATA 0x80
630#define CAMCR_PS_MAR 0x00
631
632/*
633 * Bits in the MIICFG register
634 */
635
636#define MIICFG_MPO1 0x80
637#define MIICFG_MPO0 0x40
638#define MIICFG_MFDC 0x20
639
640/*
641 * Bits in the MIISR register
642 */
643
644#define MIISR_MIDLE 0x80
645
646/*
647 * Bits in the PHYSR0 register
648 */
649
650#define PHYSR0_PHYRST 0x80
651#define PHYSR0_LINKGD 0x40
652#define PHYSR0_FDPX 0x10
653#define PHYSR0_SPDG 0x08
654#define PHYSR0_SPD10 0x04
655#define PHYSR0_RXFLC 0x02
656#define PHYSR0_TXFLC 0x01
657
658/*
659 * Bits in the PHYSR1 register
660 */
661
662#define PHYSR1_PHYTBI 0x01
663
664/*
665 * Bits in the MIICR register
666 */
667
668#define MIICR_MAUTO 0x80
669#define MIICR_RCMD 0x40
670#define MIICR_WCMD 0x20
671#define MIICR_MDPM 0x10
672#define MIICR_MOUT 0x08
673#define MIICR_MDO 0x04
674#define MIICR_MDI 0x02
675#define MIICR_MDC 0x01
676
677/*
678 * Bits in the MIIADR register
679 */
680
681#define MIIADR_SWMPL 0x80
682
683/*
684 * Bits in the CFGA register
685 */
686
687#define CFGA_PMHCTG 0x08
688#define CFGA_GPIO1PD 0x04
689#define CFGA_ABSHDN 0x02
690#define CFGA_PACPI 0x01
691
692/*
693 * Bits in the CFGB register
694 */
695
696#define CFGB_GTCKOPT 0x80
697#define CFGB_MIIOPT 0x40
698#define CFGB_CRSEOPT 0x20
699#define CFGB_OFSET 0x10
700#define CFGB_CRANDOM 0x08
701#define CFGB_CAP 0x04
702#define CFGB_MBA 0x02
703#define CFGB_BAKOPT 0x01
704
705/*
706 * Bits in the CFGC register
707 */
708
709#define CFGC_EELOAD 0x80
710#define CFGC_BROPT 0x40
711#define CFGC_DLYEN 0x20
712#define CFGC_DTSEL 0x10
713#define CFGC_BTSEL 0x08
714#define CFGC_BPS2 0x04 /* bootrom select[2] */
715#define CFGC_BPS1 0x02 /* bootrom select[1] */
716#define CFGC_BPS0 0x01 /* bootrom select[0] */
717
718/*
719 * Bits in the CFGD register
720 */
721
722#define CFGD_IODIS 0x80
723#define CFGD_MSLVDACEN 0x40
724#define CFGD_CFGDACEN 0x20
725#define CFGD_PCI64EN 0x10
726#define CFGD_HTMRL4 0x08
727
728/*
729 * Bits in the DCFG1 register
730 */
731
732#define DCFG_XMWI 0x8000
733#define DCFG_XMRM 0x4000
734#define DCFG_XMRL 0x2000
735#define DCFG_PERDIS 0x1000
736#define DCFG_MRWAIT 0x0400
737#define DCFG_MWWAIT 0x0200
738#define DCFG_LATMEN 0x0100
739
740/*
741 * Bits in the MCFG0 register
742 */
743
744#define MCFG_RXARB 0x0080
745#define MCFG_RFT1 0x0020
746#define MCFG_RFT0 0x0010
747#define MCFG_LOWTHOPT 0x0008
748#define MCFG_PQEN 0x0004
749#define MCFG_RTGOPT 0x0002
750#define MCFG_VIDFR 0x0001
751
752/*
753 * Bits in the MCFG1 register
754 */
755
756#define MCFG_TXARB 0x8000
757#define MCFG_TXQBK1 0x0800
758#define MCFG_TXQBK0 0x0400
759#define MCFG_TXQNOBK 0x0200
760#define MCFG_SNAPOPT 0x0100
761
762/*
763 * Bits in the PMCC register
764 */
765
766#define PMCC_DSI 0x80
767#define PMCC_D2_DIS 0x40
768#define PMCC_D1_DIS 0x20
769#define PMCC_D3C_EN 0x10
770#define PMCC_D3H_EN 0x08
771#define PMCC_D2_EN 0x04
772#define PMCC_D1_EN 0x02
773#define PMCC_D0_EN 0x01
774
775/*
776 * Bits in STICKHW
777 */
778
779#define STICKHW_SWPTAG 0x10
780#define STICKHW_WOLSR 0x08
781#define STICKHW_WOLEN 0x04
782#define STICKHW_DS1 0x02 /* R/W by software/cfg cycle */
783#define STICKHW_DS0 0x01 /* suspend well DS write port */
784
785/*
786 * Bits in the MIBCR register
787 */
788
789#define MIBCR_MIBISTOK 0x80
790#define MIBCR_MIBISTGO 0x40
791#define MIBCR_MIBINC 0x20
792#define MIBCR_MIBHI 0x10
793#define MIBCR_MIBFRZ 0x08
794#define MIBCR_MIBFLSH 0x04
795#define MIBCR_MPTRINI 0x02
796#define MIBCR_MIBCLR 0x01
797
798/*
799 * Bits in the EERSV register
800 */
801
802#define EERSV_BOOT_RPL ((u8) 0x01) /* Boot method selection for VT6110 */
803
804#define EERSV_BOOT_MASK ((u8) 0x06)
805#define EERSV_BOOT_INT19 ((u8) 0x00)
806#define EERSV_BOOT_INT18 ((u8) 0x02)
807#define EERSV_BOOT_LOCAL ((u8) 0x04)
808#define EERSV_BOOT_BEV ((u8) 0x06)
809
810
811/*
812 * Bits in BPCMD
813 */
814
815#define BPCMD_BPDNE 0x80
816#define BPCMD_EBPWR 0x02
817#define BPCMD_EBPRD 0x01
818
819/*
820 * Bits in the EECSR register
821 */
822
823#define EECSR_EMBP 0x40 /* eeprom embedded programming */
824#define EECSR_RELOAD 0x20 /* eeprom content reload */
825#define EECSR_DPM 0x10 /* eeprom direct programming */
826#define EECSR_ECS 0x08 /* eeprom CS pin */
827#define EECSR_ECK 0x04 /* eeprom CK pin */
828#define EECSR_EDI 0x02 /* eeprom DI pin */
829#define EECSR_EDO 0x01 /* eeprom DO pin */
830
831/*
832 * Bits in the EMBCMD register
833 */
834
835#define EMBCMD_EDONE 0x80
836#define EMBCMD_EWDIS 0x08
837#define EMBCMD_EWEN 0x04
838#define EMBCMD_EWR 0x02
839#define EMBCMD_ERD 0x01
840
841/*
842 * Bits in TESTCFG register
843 */
844
845#define TESTCFG_HBDIS 0x80
846
847/*
848 * Bits in CHIPGCR register
849 */
850
851#define CHIPGCR_FCGMII 0x80 /* force GMII (else MII only) */
852#define CHIPGCR_FCFDX 0x40 /* force full duplex */
853#define CHIPGCR_FCRESV 0x20
854#define CHIPGCR_FCMODE 0x10 /* enable MAC forced mode */
855#define CHIPGCR_LPSOPT 0x08
856#define CHIPGCR_TM1US 0x04
857#define CHIPGCR_TM0US 0x02
858#define CHIPGCR_PHYINTEN 0x01
859
860/*
861 * Bits in WOLCR0
862 */
863
864#define WOLCR_MSWOLEN7 0x0080 /* enable pattern match filtering */
865#define WOLCR_MSWOLEN6 0x0040
866#define WOLCR_MSWOLEN5 0x0020
867#define WOLCR_MSWOLEN4 0x0010
868#define WOLCR_MSWOLEN3 0x0008
869#define WOLCR_MSWOLEN2 0x0004
870#define WOLCR_MSWOLEN1 0x0002
871#define WOLCR_MSWOLEN0 0x0001
872#define WOLCR_ARP_EN 0x0001
873
874/*
875 * Bits in WOLCR1
876 */
877
878#define WOLCR_LINKOFF_EN 0x0800 /* link off detected enable */
879#define WOLCR_LINKON_EN 0x0400 /* link on detected enable */
880#define WOLCR_MAGIC_EN 0x0200 /* magic packet filter enable */
881#define WOLCR_UNICAST_EN 0x0100 /* unicast filter enable */
882
883
884/*
885 * Bits in PWCFG
886 */
887
888#define PWCFG_PHYPWOPT 0x80 /* internal MII I/F timing */
889#define PWCFG_PCISTICK 0x40 /* PCI sticky R/W enable */
890#define PWCFG_WOLTYPE 0x20 /* pulse(1) or button (0) */
891#define PWCFG_LEGCY_WOL 0x10
892#define PWCFG_PMCSR_PME_SR 0x08
893#define PWCFG_PMCSR_PME_EN 0x04 /* control by PCISTICK */
894#define PWCFG_LEGACY_WOLSR 0x02 /* Legacy WOL_SR shadow */
895#define PWCFG_LEGACY_WOLEN 0x01 /* Legacy WOL_EN shadow */
896
897/*
898 * Bits in WOLCFG
899 */
900
901#define WOLCFG_PMEOVR 0x80 /* for legacy use, force PMEEN always */
902#define WOLCFG_SAM 0x20 /* accept multicast case reset, default=0 */
903#define WOLCFG_SAB 0x10 /* accept broadcast case reset, default=0 */
904#define WOLCFG_SMIIACC 0x08 /* ?? */
905#define WOLCFG_SGENWH 0x02
906#define WOLCFG_PHYINTEN 0x01 /* 0:PHYINT trigger enable, 1:use internal MII
907 to report status change */
908/*
909 * Bits in WOLSR1
910 */
911
912#define WOLSR_LINKOFF_INT 0x0800
913#define WOLSR_LINKON_INT 0x0400
914#define WOLSR_MAGIC_INT 0x0200
915#define WOLSR_UNICAST_INT 0x0100
916
917/*
918 * Ethernet address filter type
919 */
920
921#define PKT_TYPE_NONE 0x0000 /* Turn off receiver */
922#define PKT_TYPE_DIRECTED 0x0001 /* obselete, directed address is always accepted */
923#define PKT_TYPE_MULTICAST 0x0002
924#define PKT_TYPE_ALL_MULTICAST 0x0004
925#define PKT_TYPE_BROADCAST 0x0008
926#define PKT_TYPE_PROMISCUOUS 0x0020
927#define PKT_TYPE_LONG 0x2000 /* NOTE.... the definition of LONG is >2048 bytes in our chip */
928#define PKT_TYPE_RUNT 0x4000
929#define PKT_TYPE_ERROR 0x8000 /* Accept error packets, e.g. CRC error */
930
931/*
932 * Loopback mode
933 */
934
935#define MAC_LB_NONE 0x00
936#define MAC_LB_INTERNAL 0x01
937#define MAC_LB_EXTERNAL 0x02
938
939/*
940 * Enabled mask value of irq
941 */
942
943#if defined(_SIM)
944#define IMR_MASK_VALUE 0x0033FF0FUL /* initial value of IMR
945 set IMR0 to 0x0F according to spec */
946
947#else
948#define IMR_MASK_VALUE 0x0013FB0FUL /* initial value of IMR
949 ignore MIBFI,RACEI to
950 reduce intr. frequency
951 NOTE.... do not enable NoBuf int mask at driver driver
952 when (1) NoBuf -> RxThreshold = SF
953 (2) OK -> RxThreshold = original value
954 */
955#endif
956
957/*
958 * Revision id
959 */
960
961#define REV_ID_VT3119_A0 0x00
962#define REV_ID_VT3119_A1 0x01
963#define REV_ID_VT3216_A0 0x10
964
965/*
966 * Max time out delay time
967 */
968
969#define W_MAX_TIMEOUT 0x0FFFU
970
971
972/*
973 * MAC registers as a structure. Cannot be directly accessed this
974 * way but generates offsets for readl/writel() calls
975 */
976
977struct mac_regs {
978 volatile u8 PAR[6]; /* 0x00 */
979 volatile u8 RCR;
980 volatile u8 TCR;
981
982 volatile __le32 CR0Set; /* 0x08 */
983 volatile __le32 CR0Clr; /* 0x0C */
984
985 volatile u8 MARCAM[8]; /* 0x10 */
986
987 volatile __le32 DecBaseHi; /* 0x18 */
988 volatile __le16 DbfBaseHi; /* 0x1C */
989 volatile __le16 reserved_1E;
990
991 volatile __le16 ISRCTL; /* 0x20 */
992 volatile u8 TXESR;
993 volatile u8 RXESR;
994
995 volatile __le32 ISR; /* 0x24 */
996 volatile __le32 IMR;
997
998 volatile __le32 TDStatusPort; /* 0x2C */
999
1000 volatile __le16 TDCSRSet; /* 0x30 */
1001 volatile u8 RDCSRSet;
1002 volatile u8 reserved_33;
1003 volatile __le16 TDCSRClr;
1004 volatile u8 RDCSRClr;
1005 volatile u8 reserved_37;
1006
1007 volatile __le32 RDBaseLo; /* 0x38 */
1008 volatile __le16 RDIdx; /* 0x3C */
1009 volatile u8 TQETMR; /* 0x3E, VT3216 and above only */
1010 volatile u8 RQETMR; /* 0x3F, VT3216 and above only */
1011
1012 volatile __le32 TDBaseLo[4]; /* 0x40 */
1013
1014 volatile __le16 RDCSize; /* 0x50 */
1015 volatile __le16 TDCSize; /* 0x52 */
1016 volatile __le16 TDIdx[4]; /* 0x54 */
1017 volatile __le16 tx_pause_timer; /* 0x5C */
1018 volatile __le16 RBRDU; /* 0x5E */
1019
1020 volatile __le32 FIFOTest0; /* 0x60 */
1021 volatile __le32 FIFOTest1; /* 0x64 */
1022
1023 volatile u8 CAMADDR; /* 0x68 */
1024 volatile u8 CAMCR; /* 0x69 */
1025 volatile u8 GFTEST; /* 0x6A */
1026 volatile u8 FTSTCMD; /* 0x6B */
1027
1028 volatile u8 MIICFG; /* 0x6C */
1029 volatile u8 MIISR;
1030 volatile u8 PHYSR0;
1031 volatile u8 PHYSR1;
1032 volatile u8 MIICR;
1033 volatile u8 MIIADR;
1034 volatile __le16 MIIDATA;
1035
1036 volatile __le16 SoftTimer0; /* 0x74 */
1037 volatile __le16 SoftTimer1;
1038
1039 volatile u8 CFGA; /* 0x78 */
1040 volatile u8 CFGB;
1041 volatile u8 CFGC;
1042 volatile u8 CFGD;
1043
1044 volatile __le16 DCFG; /* 0x7C */
1045 volatile __le16 MCFG;
1046
1047 volatile u8 TBIST; /* 0x80 */
1048 volatile u8 RBIST;
1049 volatile u8 PMCPORT;
1050 volatile u8 STICKHW;
1051
1052 volatile u8 MIBCR; /* 0x84 */
1053 volatile u8 reserved_85;
1054 volatile u8 rev_id;
1055 volatile u8 PORSTS;
1056
1057 volatile __le32 MIBData; /* 0x88 */
1058
1059 volatile __le16 EEWrData;
1060
1061 volatile u8 reserved_8E;
1062 volatile u8 BPMDWr;
1063 volatile u8 BPCMD;
1064 volatile u8 BPMDRd;
1065
1066 volatile u8 EECHKSUM; /* 0x92 */
1067 volatile u8 EECSR;
1068
1069 volatile __le16 EERdData; /* 0x94 */
1070 volatile u8 EADDR;
1071 volatile u8 EMBCMD;
1072
1073
1074 volatile u8 JMPSR0; /* 0x98 */
1075 volatile u8 JMPSR1;
1076 volatile u8 JMPSR2;
1077 volatile u8 JMPSR3;
1078 volatile u8 CHIPGSR; /* 0x9C */
1079 volatile u8 TESTCFG;
1080 volatile u8 DEBUG;
1081 volatile u8 CHIPGCR;
1082
1083 volatile __le16 WOLCRSet; /* 0xA0 */
1084 volatile u8 PWCFGSet;
1085 volatile u8 WOLCFGSet;
1086
1087 volatile __le16 WOLCRClr; /* 0xA4 */
1088 volatile u8 PWCFGCLR;
1089 volatile u8 WOLCFGClr;
1090
1091 volatile __le16 WOLSRSet; /* 0xA8 */
1092 volatile __le16 reserved_AA;
1093
1094 volatile __le16 WOLSRClr; /* 0xAC */
1095 volatile __le16 reserved_AE;
1096
1097 volatile __le16 PatternCRC[8]; /* 0xB0 */
1098 volatile __le32 ByteMask[4][4]; /* 0xC0 */
1099};
1100
1101
1102enum hw_mib {
1103 HW_MIB_ifRxAllPkts = 0,
1104 HW_MIB_ifRxOkPkts,
1105 HW_MIB_ifTxOkPkts,
1106 HW_MIB_ifRxErrorPkts,
1107 HW_MIB_ifRxRuntOkPkt,
1108 HW_MIB_ifRxRuntErrPkt,
1109 HW_MIB_ifRx64Pkts,
1110 HW_MIB_ifTx64Pkts,
1111 HW_MIB_ifRx65To127Pkts,
1112 HW_MIB_ifTx65To127Pkts,
1113 HW_MIB_ifRx128To255Pkts,
1114 HW_MIB_ifTx128To255Pkts,
1115 HW_MIB_ifRx256To511Pkts,
1116 HW_MIB_ifTx256To511Pkts,
1117 HW_MIB_ifRx512To1023Pkts,
1118 HW_MIB_ifTx512To1023Pkts,
1119 HW_MIB_ifRx1024To1518Pkts,
1120 HW_MIB_ifTx1024To1518Pkts,
1121 HW_MIB_ifTxEtherCollisions,
1122 HW_MIB_ifRxPktCRCE,
1123 HW_MIB_ifRxJumboPkts,
1124 HW_MIB_ifTxJumboPkts,
1125 HW_MIB_ifRxMacControlFrames,
1126 HW_MIB_ifTxMacControlFrames,
1127 HW_MIB_ifRxPktFAE,
1128 HW_MIB_ifRxLongOkPkt,
1129 HW_MIB_ifRxLongPktErrPkt,
1130 HW_MIB_ifTXSQEErrors,
1131 HW_MIB_ifRxNobuf,
1132 HW_MIB_ifRxSymbolErrors,
1133 HW_MIB_ifInRangeLengthErrors,
1134 HW_MIB_ifLateCollisions,
1135 HW_MIB_SIZE
1136};
1137
1138enum chip_type {
1139 CHIP_TYPE_VT6110 = 1,
1140};
1141
1142struct velocity_info_tbl {
1143 enum chip_type chip_id;
1144 const char *name;
1145 int txqueue;
1146 u32 flags;
1147};
1148
1149#define mac_hw_mibs_init(regs) {\
1150 BYTE_REG_BITS_ON(MIBCR_MIBFRZ,&((regs)->MIBCR));\
1151 BYTE_REG_BITS_ON(MIBCR_MIBCLR,&((regs)->MIBCR));\
1152 do {}\
1153 while (BYTE_REG_BITS_IS_ON(MIBCR_MIBCLR,&((regs)->MIBCR)));\
1154 BYTE_REG_BITS_OFF(MIBCR_MIBFRZ,&((regs)->MIBCR));\
1155}
1156
1157#define mac_read_isr(regs) readl(&((regs)->ISR))
1158#define mac_write_isr(regs, x) writel((x),&((regs)->ISR))
1159#define mac_clear_isr(regs) writel(0xffffffffL,&((regs)->ISR))
1160
1161#define mac_write_int_mask(mask, regs) writel((mask),&((regs)->IMR));
1162#define mac_disable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Clr))
1163#define mac_enable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Set))
1164
1165#define mac_set_dma_length(regs, n) {\
1166 BYTE_REG_BITS_SET((n),0x07,&((regs)->DCFG));\
1167}
1168
1169#define mac_set_rx_thresh(regs, n) {\
1170 BYTE_REG_BITS_SET((n),(MCFG_RFT0|MCFG_RFT1),&((regs)->MCFG));\
1171}
1172
1173#define mac_rx_queue_run(regs) {\
1174 writeb(TRDCSR_RUN, &((regs)->RDCSRSet));\
1175}
1176
1177#define mac_rx_queue_wake(regs) {\
1178 writeb(TRDCSR_WAK, &((regs)->RDCSRSet));\
1179}
1180
1181#define mac_tx_queue_run(regs, n) {\
1182 writew(TRDCSR_RUN<<((n)*4),&((regs)->TDCSRSet));\
1183}
1184
1185#define mac_tx_queue_wake(regs, n) {\
1186 writew(TRDCSR_WAK<<(n*4),&((regs)->TDCSRSet));\
1187}
1188
1189static inline void mac_eeprom_reload(struct mac_regs __iomem * regs) {
1190 int i=0;
1191
1192 BYTE_REG_BITS_ON(EECSR_RELOAD,&(regs->EECSR));
1193 do {
1194 udelay(10);
1195 if (i++>0x1000)
1196 break;
1197 } while (BYTE_REG_BITS_IS_ON(EECSR_RELOAD,&(regs->EECSR)));
1198}
1199
1200/*
1201 * Header for WOL definitions. Used to compute hashes
1202 */
1203
1204typedef u8 MCAM_ADDR[ETH_ALEN];
1205
1206struct arp_packet {
1207 u8 dest_mac[ETH_ALEN];
1208 u8 src_mac[ETH_ALEN];
1209 __be16 type;
1210 __be16 ar_hrd;
1211 __be16 ar_pro;
1212 u8 ar_hln;
1213 u8 ar_pln;
1214 __be16 ar_op;
1215 u8 ar_sha[ETH_ALEN];
1216 u8 ar_sip[4];
1217 u8 ar_tha[ETH_ALEN];
1218 u8 ar_tip[4];
1219} __packed;
1220
1221struct _magic_packet {
1222 u8 dest_mac[6];
1223 u8 src_mac[6];
1224 __be16 type;
1225 u8 MAC[16][6];
1226 u8 password[6];
1227} __packed;
1228
1229/*
1230 * Store for chip context when saving and restoring status. Not
1231 * all fields are saved/restored currently.
1232 */
1233
1234struct velocity_context {
1235 u8 mac_reg[256];
1236 MCAM_ADDR cam_addr[MCAM_SIZE];
1237 u16 vcam[VCAM_SIZE];
1238 u32 cammask[2];
1239 u32 patcrc[2];
1240 u32 pattern[8];
1241};
1242
1243/*
1244 * Registers in the MII (offset unit is WORD)
1245 */
1246
1247// Marvell 88E1000/88E1000S
1248#define MII_REG_PSCR 0x10 // PHY specific control register
1249
1250//
1251// Bits in the Silicon revision register
1252//
1253
1254#define TCSR_ECHODIS 0x2000 //
1255#define AUXCR_MDPPS 0x0004 //
1256
1257// Bits in the PLED register
1258#define PLED_LALBE 0x0004 //
1259
1260// Marvell 88E1000/88E1000S Bits in the PHY specific control register (10h)
1261#define PSCR_ACRSTX 0x0800 // Assert CRS on Transmit
1262
1263#define PHYID_CICADA_CS8201 0x000FC410UL
1264#define PHYID_VT3216_32BIT 0x000FC610UL
1265#define PHYID_VT3216_64BIT 0x000FC600UL
1266#define PHYID_MARVELL_1000 0x01410C50UL
1267#define PHYID_MARVELL_1000S 0x01410C40UL
1268
1269#define PHYID_REV_ID_MASK 0x0000000FUL
1270
1271#define PHYID_GET_PHY_ID(i) ((i) & ~PHYID_REV_ID_MASK)
1272
1273#define MII_REG_BITS_ON(x,i,p) do {\
1274 u16 w;\
1275 velocity_mii_read((p),(i),&(w));\
1276 (w)|=(x);\
1277 velocity_mii_write((p),(i),(w));\
1278} while (0)
1279
1280#define MII_REG_BITS_OFF(x,i,p) do {\
1281 u16 w;\
1282 velocity_mii_read((p),(i),&(w));\
1283 (w)&=(~(x));\
1284 velocity_mii_write((p),(i),(w));\
1285} while (0)
1286
1287#define MII_REG_BITS_IS_ON(x,i,p) ({\
1288 u16 w;\
1289 velocity_mii_read((p),(i),&(w));\
1290 ((int) ((w) & (x)));})
1291
1292#define MII_GET_PHY_ID(p) ({\
1293 u32 id;\
1294 velocity_mii_read((p),MII_PHYSID2,(u16 *) &id);\
1295 velocity_mii_read((p),MII_PHYSID1,((u16 *) &id)+1);\
1296 (id);})
1297
1298/*
1299 * Inline debug routine
1300 */
1301
1302
1303enum velocity_msg_level {
1304 MSG_LEVEL_ERR = 0, //Errors that will cause abnormal operation.
1305 MSG_LEVEL_NOTICE = 1, //Some errors need users to be notified.
1306 MSG_LEVEL_INFO = 2, //Normal message.
1307 MSG_LEVEL_VERBOSE = 3, //Will report all trival errors.
1308 MSG_LEVEL_DEBUG = 4 //Only for debug purpose.
1309};
1310
1311#ifdef VELOCITY_DEBUG
1312#define ASSERT(x) { \
1313 if (!(x)) { \
1314 printk(KERN_ERR "assertion %s failed: file %s line %d\n", #x,\
1315 __func__, __LINE__);\
1316 BUG(); \
1317 }\
1318}
1319#define VELOCITY_DBG(p,args...) printk(p, ##args)
1320#else
1321#define ASSERT(x)
1322#define VELOCITY_DBG(x)
1323#endif
1324
1325#define VELOCITY_PRT(l, p, args...) do {if (l<=msglevel) printk( p ,##args);} while (0)
1326
1327#define VELOCITY_PRT_CAMMASK(p,t) {\
1328 int i;\
1329 if ((t)==VELOCITY_MULTICAST_CAM) {\
1330 for (i=0;i<(MCAM_SIZE/8);i++)\
1331 printk("%02X",(p)->mCAMmask[i]);\
1332 }\
1333 else {\
1334 for (i=0;i<(VCAM_SIZE/8);i++)\
1335 printk("%02X",(p)->vCAMmask[i]);\
1336 }\
1337 printk("\n");\
1338}
1339
1340
1341
1342#define VELOCITY_WOL_MAGIC 0x00000000UL
1343#define VELOCITY_WOL_PHY 0x00000001UL
1344#define VELOCITY_WOL_ARP 0x00000002UL
1345#define VELOCITY_WOL_UCAST 0x00000004UL
1346#define VELOCITY_WOL_BCAST 0x00000010UL
1347#define VELOCITY_WOL_MCAST 0x00000020UL
1348#define VELOCITY_WOL_MAGIC_SEC 0x00000040UL
1349
1350/*
1351 * Flags for options
1352 */
1353
1354#define VELOCITY_FLAGS_TAGGING 0x00000001UL
1355#define VELOCITY_FLAGS_RX_CSUM 0x00000004UL
1356#define VELOCITY_FLAGS_IP_ALIGN 0x00000008UL
1357#define VELOCITY_FLAGS_VAL_PKT_LEN 0x00000010UL
1358
1359#define VELOCITY_FLAGS_FLOW_CTRL 0x01000000UL
1360
1361/*
1362 * Flags for driver status
1363 */
1364
1365#define VELOCITY_FLAGS_OPENED 0x00010000UL
1366#define VELOCITY_FLAGS_VMNS_CONNECTED 0x00020000UL
1367#define VELOCITY_FLAGS_VMNS_COMMITTED 0x00040000UL
1368#define VELOCITY_FLAGS_WOL_ENABLED 0x00080000UL
1369
1370/*
1371 * Flags for MII status
1372 */
1373
1374#define VELOCITY_LINK_FAIL 0x00000001UL
1375#define VELOCITY_SPEED_10 0x00000002UL
1376#define VELOCITY_SPEED_100 0x00000004UL
1377#define VELOCITY_SPEED_1000 0x00000008UL
1378#define VELOCITY_DUPLEX_FULL 0x00000010UL
1379#define VELOCITY_AUTONEG_ENABLE 0x00000020UL
1380#define VELOCITY_FORCED_BY_EEPROM 0x00000040UL
1381
1382/*
1383 * For velocity_set_media_duplex
1384 */
1385
1386#define VELOCITY_LINK_CHANGE 0x00000001UL
1387
1388enum speed_opt {
1389 SPD_DPX_AUTO = 0,
1390 SPD_DPX_100_HALF = 1,
1391 SPD_DPX_100_FULL = 2,
1392 SPD_DPX_10_HALF = 3,
1393 SPD_DPX_10_FULL = 4,
1394 SPD_DPX_1000_FULL = 5
1395};
1396
1397enum velocity_init_type {
1398 VELOCITY_INIT_COLD = 0,
1399 VELOCITY_INIT_RESET,
1400 VELOCITY_INIT_WOL
1401};
1402
1403enum velocity_flow_cntl_type {
1404 FLOW_CNTL_DEFAULT = 1,
1405 FLOW_CNTL_TX,
1406 FLOW_CNTL_RX,
1407 FLOW_CNTL_TX_RX,
1408 FLOW_CNTL_DISABLE,
1409};
1410
1411struct velocity_opt {
1412 int numrx; /* Number of RX descriptors */
1413 int numtx; /* Number of TX descriptors */
1414 enum speed_opt spd_dpx; /* Media link mode */
1415
1416 int DMA_length; /* DMA length */
1417 int rx_thresh; /* RX_THRESH */
1418 int flow_cntl;
1419 int wol_opts; /* Wake on lan options */
1420 int td_int_count;
1421 int int_works;
1422 int rx_bandwidth_hi;
1423 int rx_bandwidth_lo;
1424 int rx_bandwidth_en;
1425 int rxqueue_timer;
1426 int txqueue_timer;
1427 int tx_intsup;
1428 int rx_intsup;
1429 u32 flags;
1430};
1431
1432#define AVAIL_TD(p,q) ((p)->options.numtx-((p)->tx.used[(q)]))
1433
1434#define GET_RD_BY_IDX(vptr, idx) (vptr->rd_ring[idx])
1435
1436struct velocity_info {
1437 struct pci_dev *pdev;
1438 struct net_device *dev;
1439
1440 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
1441 u8 ip_addr[4];
1442 enum chip_type chip_id;
1443
1444 struct mac_regs __iomem * mac_regs;
1445 unsigned long memaddr;
1446 unsigned long ioaddr;
1447
1448 struct tx_info {
1449 int numq;
1450
1451 /* FIXME: the locality of the data seems rather poor. */
1452 int used[TX_QUEUE_NO];
1453 int curr[TX_QUEUE_NO];
1454 int tail[TX_QUEUE_NO];
1455 struct tx_desc *rings[TX_QUEUE_NO];
1456 struct velocity_td_info *infos[TX_QUEUE_NO];
1457 dma_addr_t pool_dma[TX_QUEUE_NO];
1458 } tx;
1459
1460 struct rx_info {
1461 int buf_sz;
1462
1463 int dirty;
1464 int curr;
1465 u32 filled;
1466 struct rx_desc *ring;
1467 struct velocity_rd_info *info; /* It's an array */
1468 dma_addr_t pool_dma;
1469 } rx;
1470
1471 u32 mib_counter[MAX_HW_MIB_COUNTER];
1472 struct velocity_opt options;
1473
1474 u32 int_mask;
1475
1476 u32 flags;
1477
1478 u32 mii_status;
1479 u32 phy_id;
1480 int multicast_limit;
1481
1482 u8 vCAMmask[(VCAM_SIZE / 8)];
1483 u8 mCAMmask[(MCAM_SIZE / 8)];
1484
1485 spinlock_t lock;
1486
1487 int wol_opts;
1488 u8 wol_passwd[6];
1489
1490 struct velocity_context context;
1491
1492 u32 ticks;
1493
1494 u8 rev_id;
1495
1496 struct napi_struct napi;
1497};
1498
1499/**
1500 * velocity_get_ip - find an IP address for the device
1501 * @vptr: Velocity to query
1502 *
1503 * Dig out an IP address for this interface so that we can
1504 * configure wakeup with WOL for ARP. If there are multiple IP
1505 * addresses on this chain then we use the first - multi-IP WOL is not
1506 * supported.
1507 *
1508 */
1509
1510static inline int velocity_get_ip(struct velocity_info *vptr)
1511{
1512 struct in_device *in_dev;
1513 struct in_ifaddr *ifa;
1514 int res = -ENOENT;
1515
1516 rcu_read_lock();
1517 in_dev = __in_dev_get_rcu(vptr->dev);
1518 if (in_dev != NULL) {
1519 ifa = (struct in_ifaddr *) in_dev->ifa_list;
1520 if (ifa != NULL) {
1521 memcpy(vptr->ip_addr, &ifa->ifa_address, 4);
1522 res = 0;
1523 }
1524 }
1525 rcu_read_unlock();
1526 return res;
1527}
1528
1529/**
1530 * velocity_update_hw_mibs - fetch MIB counters from chip
1531 * @vptr: velocity to update
1532 *
1533 * The velocity hardware keeps certain counters in the hardware
1534 * side. We need to read these when the user asks for statistics
1535 * or when they overflow (causing an interrupt). The read of the
1536 * statistic clears it, so we keep running master counters in user
1537 * space.
1538 */
1539
1540static inline void velocity_update_hw_mibs(struct velocity_info *vptr)
1541{
1542 u32 tmp;
1543 int i;
1544 BYTE_REG_BITS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR));
1545
1546 while (BYTE_REG_BITS_IS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR)));
1547
1548 BYTE_REG_BITS_ON(MIBCR_MPTRINI, &(vptr->mac_regs->MIBCR));
1549 for (i = 0; i < HW_MIB_SIZE; i++) {
1550 tmp = readl(&(vptr->mac_regs->MIBData)) & 0x00FFFFFFUL;
1551 vptr->mib_counter[i] += tmp;
1552 }
1553}
1554
1555/**
1556 * init_flow_control_register - set up flow control
1557 * @vptr: velocity to configure
1558 *
1559 * Configure the flow control registers for this velocity device.
1560 */
1561
1562static inline void init_flow_control_register(struct velocity_info *vptr)
1563{
1564 struct mac_regs __iomem * regs = vptr->mac_regs;
1565
1566 /* Set {XHITH1, XHITH0, XLTH1, XLTH0} in FlowCR1 to {1, 0, 1, 1}
1567 depend on RD=64, and Turn on XNOEN in FlowCR1 */
1568 writel((CR0_XONEN | CR0_XHITH1 | CR0_XLTH1 | CR0_XLTH0), &regs->CR0Set);
1569 writel((CR0_FDXTFCEN | CR0_FDXRFCEN | CR0_HDXFCEN | CR0_XHITH0), &regs->CR0Clr);
1570
1571 /* Set TxPauseTimer to 0xFFFF */
1572 writew(0xFFFF, &regs->tx_pause_timer);
1573
1574 /* Initialize RBRDU to Rx buffer count. */
1575 writew(vptr->options.numrx, &regs->RBRDU);
1576}
1577
1578
1579#endif
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