aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/ethernet/ti
diff options
context:
space:
mode:
authorFelipe Balbi <balbi@ti.com>2015-01-02 17:15:59 -0500
committerDavid S. Miller <davem@davemloft.net>2015-01-04 22:18:34 -0500
commit7ce67a38f799d1fb332f672b117efbadedaa5352 (patch)
tree4cc653c13b1020c73e8b29d82634a8a28c052d1b /drivers/net/ethernet/ti
parent9dac6232e2ee2bc85dc71f464f19f047afc9422c (diff)
net: ethernet: cpsw: fix hangs with interrupts
The CPSW IP implements pulse-signaled interrupts. Due to that we must write a correct, pre-defined value to the CPDMA_MACEOIVECTOR register so the controller generates a pulse on the correct IRQ line to signal the End Of Interrupt. The way the driver is written today, all four IRQ lines are requested using the same IRQ handler and, because of that, we could fall into situations where a TX IRQ fires but we tell the controller that we ended an RX IRQ (or vice-versa). This situation triggers an IRQ storm on the reserved IRQ 127 of INTC which will in turn call ack_bad_irq() which will, then, print a ton of: unexpected IRQ trap at vector 00 In order to fix the problem, we are moving all calls to cpdma_ctlr_eoi() inside the IRQ handler and making sure we *always* write the correct value to the CPDMA_MACEOIVECTOR register. Note that the algorithm assumes that IRQ numbers and value-to-be-written-to-EOI are proportional, meaning that a write of value 0 would trigger an EOI pulse for the RX_THRESHOLD Interrupt and that's the IRQ number sitting in the 0-th index of our irqs_table array. This, however, is safe at least for current implementations of CPSW so we will refrain from making the check smarter (and, as a side-effect, slower) until we actually have a platform where IRQ lines are swapped. This patch has been tested for several days with AM335x- and AM437x-based platforms. AM57x was left out because there are still pending patches to enable ethernet in mainline for that platform. A read of the TRM confirms the statement on previous paragraph. Reported-by: Yegor Yefremov <yegorslists@googlemail.com> Fixes: 510a1e7 (drivers: net: davinci_cpdma: acknowledge interrupt properly) Cc: <stable@vger.kernel.org> # v3.9+ Signed-off-by: Felipe Balbi <balbi@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/ti')
-rw-r--r--drivers/net/ethernet/ti/cpsw.c19
1 files changed, 8 insertions, 11 deletions
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index c560f9aeb55d..e61ee8351272 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -757,6 +757,14 @@ requeue:
757static irqreturn_t cpsw_interrupt(int irq, void *dev_id) 757static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
758{ 758{
759 struct cpsw_priv *priv = dev_id; 759 struct cpsw_priv *priv = dev_id;
760 int value = irq - priv->irqs_table[0];
761
762 /* NOTICE: Ending IRQ here. The trick with the 'value' variable above
763 * is to make sure we will always write the correct value to the EOI
764 * register. Namely 0 for RX_THRESH Interrupt, 1 for RX Interrupt, 2
765 * for TX Interrupt and 3 for MISC Interrupt.
766 */
767 cpdma_ctlr_eoi(priv->dma, value);
760 768
761 cpsw_intr_disable(priv); 769 cpsw_intr_disable(priv);
762 if (priv->irq_enabled == true) { 770 if (priv->irq_enabled == true) {
@@ -786,8 +794,6 @@ static int cpsw_poll(struct napi_struct *napi, int budget)
786 int num_tx, num_rx; 794 int num_tx, num_rx;
787 795
788 num_tx = cpdma_chan_process(priv->txch, 128); 796 num_tx = cpdma_chan_process(priv->txch, 128);
789 if (num_tx)
790 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
791 797
792 num_rx = cpdma_chan_process(priv->rxch, budget); 798 num_rx = cpdma_chan_process(priv->rxch, budget);
793 if (num_rx < budget) { 799 if (num_rx < budget) {
@@ -795,7 +801,6 @@ static int cpsw_poll(struct napi_struct *napi, int budget)
795 801
796 napi_complete(napi); 802 napi_complete(napi);
797 cpsw_intr_enable(priv); 803 cpsw_intr_enable(priv);
798 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
799 prim_cpsw = cpsw_get_slave_priv(priv, 0); 804 prim_cpsw = cpsw_get_slave_priv(priv, 0);
800 if (prim_cpsw->irq_enabled == false) { 805 if (prim_cpsw->irq_enabled == false) {
801 prim_cpsw->irq_enabled = true; 806 prim_cpsw->irq_enabled = true;
@@ -1310,8 +1315,6 @@ static int cpsw_ndo_open(struct net_device *ndev)
1310 napi_enable(&priv->napi); 1315 napi_enable(&priv->napi);
1311 cpdma_ctlr_start(priv->dma); 1316 cpdma_ctlr_start(priv->dma);
1312 cpsw_intr_enable(priv); 1317 cpsw_intr_enable(priv);
1313 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1314 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1315 1318
1316 prim_cpsw = cpsw_get_slave_priv(priv, 0); 1319 prim_cpsw = cpsw_get_slave_priv(priv, 0);
1317 if (prim_cpsw->irq_enabled == false) { 1320 if (prim_cpsw->irq_enabled == false) {
@@ -1578,9 +1581,6 @@ static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1578 cpdma_chan_start(priv->txch); 1581 cpdma_chan_start(priv->txch);
1579 cpdma_ctlr_int_ctrl(priv->dma, true); 1582 cpdma_ctlr_int_ctrl(priv->dma, true);
1580 cpsw_intr_enable(priv); 1583 cpsw_intr_enable(priv);
1581 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1582 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1583
1584} 1584}
1585 1585
1586static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p) 1586static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
@@ -1620,9 +1620,6 @@ static void cpsw_ndo_poll_controller(struct net_device *ndev)
1620 cpsw_interrupt(ndev->irq, priv); 1620 cpsw_interrupt(ndev->irq, priv);
1621 cpdma_ctlr_int_ctrl(priv->dma, true); 1621 cpdma_ctlr_int_ctrl(priv->dma, true);
1622 cpsw_intr_enable(priv); 1622 cpsw_intr_enable(priv);
1623 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1624 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1625
1626} 1623}
1627#endif 1624#endif
1628 1625