diff options
author | Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> | 2013-06-06 05:51:39 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2013-06-06 19:04:04 -0400 |
commit | dabdde9ea77d4a77094726c82468a3bd767fb29b (patch) | |
tree | 3c941724f7f8511aac176064c5128903650cb598 /drivers/net/ethernet/renesas | |
parent | b7feacf1ee6944fc571802d58dcffaf13b4fb4cc (diff) |
sh_eth: consolidate sh_eth_reset()
This driver has sh_eth_reset() function for each SoC and this function is almost
always the same, except for the several a bit different variations for Gigabit
Ethernet. Consolidate every variation into a single function -- which allows
us to get rid of some more #ifdef'fery.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
[Sergei: moved the new sh_eth_reset() and sh_eth_is_gether() up to decrease the
patch size, fixed function call continuation lines' indentation, reworded the
changelog, reworded the subject, changing the prefix.]
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/renesas')
-rw-r--r-- | drivers/net/ethernet/renesas/sh_eth.c | 176 |
1 files changed, 51 insertions, 125 deletions
diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c index 2234a945ae5b..d190c1e0b0c0 100644 --- a/drivers/net/ethernet/renesas/sh_eth.c +++ b/drivers/net/ethernet/renesas/sh_eth.c | |||
@@ -313,6 +313,14 @@ static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = { | |||
313 | [TSU_ADRL31] = 0x01fc, | 313 | [TSU_ADRL31] = 0x01fc, |
314 | }; | 314 | }; |
315 | 315 | ||
316 | static int sh_eth_is_gether(struct sh_eth_private *mdp) | ||
317 | { | ||
318 | if (mdp->reg_offset == sh_eth_offset_gigabit) | ||
319 | return 1; | ||
320 | else | ||
321 | return 0; | ||
322 | } | ||
323 | |||
316 | static void __maybe_unused sh_eth_select_mii(struct net_device *ndev) | 324 | static void __maybe_unused sh_eth_select_mii(struct net_device *ndev) |
317 | { | 325 | { |
318 | u32 value = 0x0; | 326 | u32 value = 0x0; |
@@ -349,7 +357,6 @@ static void __maybe_unused sh_eth_set_duplex(struct net_device *ndev) | |||
349 | 357 | ||
350 | /* There is CPU dependent code */ | 358 | /* There is CPU dependent code */ |
351 | #if defined(CONFIG_ARCH_R8A7778) || defined(CONFIG_ARCH_R8A7779) | 359 | #if defined(CONFIG_ARCH_R8A7778) || defined(CONFIG_ARCH_R8A7779) |
352 | #define SH_ETH_RESET_DEFAULT 1 | ||
353 | static void sh_eth_set_rate(struct net_device *ndev) | 360 | static void sh_eth_set_rate(struct net_device *ndev) |
354 | { | 361 | { |
355 | struct sh_eth_private *mdp = netdev_priv(ndev); | 362 | struct sh_eth_private *mdp = netdev_priv(ndev); |
@@ -386,7 +393,6 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { | |||
386 | .hw_swap = 1, | 393 | .hw_swap = 1, |
387 | }; | 394 | }; |
388 | #elif defined(CONFIG_CPU_SUBTYPE_SH7724) | 395 | #elif defined(CONFIG_CPU_SUBTYPE_SH7724) |
389 | #define SH_ETH_RESET_DEFAULT 1 | ||
390 | 396 | ||
391 | static void sh_eth_set_rate(struct net_device *ndev) | 397 | static void sh_eth_set_rate(struct net_device *ndev) |
392 | { | 398 | { |
@@ -427,7 +433,6 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { | |||
427 | }; | 433 | }; |
428 | #elif defined(CONFIG_CPU_SUBTYPE_SH7757) | 434 | #elif defined(CONFIG_CPU_SUBTYPE_SH7757) |
429 | #define SH_ETH_HAS_BOTH_MODULES 1 | 435 | #define SH_ETH_HAS_BOTH_MODULES 1 |
430 | static int sh_eth_check_reset(struct net_device *ndev); | ||
431 | 436 | ||
432 | static void sh_eth_set_rate(struct net_device *ndev) | 437 | static void sh_eth_set_rate(struct net_device *ndev) |
433 | { | 438 | { |
@@ -493,42 +498,6 @@ static void sh_eth_chip_reset_giga(struct net_device *ndev) | |||
493 | } | 498 | } |
494 | } | 499 | } |
495 | 500 | ||
496 | static int sh_eth_is_gether(struct sh_eth_private *mdp); | ||
497 | static int sh_eth_reset(struct net_device *ndev) | ||
498 | { | ||
499 | struct sh_eth_private *mdp = netdev_priv(ndev); | ||
500 | int ret = 0; | ||
501 | |||
502 | if (sh_eth_is_gether(mdp)) { | ||
503 | sh_eth_write(ndev, EDSR_ENALL, EDSR); | ||
504 | sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, | ||
505 | EDMR); | ||
506 | |||
507 | ret = sh_eth_check_reset(ndev); | ||
508 | if (ret) | ||
509 | goto out; | ||
510 | |||
511 | /* Table Init */ | ||
512 | sh_eth_write(ndev, 0x0, TDLAR); | ||
513 | sh_eth_write(ndev, 0x0, TDFAR); | ||
514 | sh_eth_write(ndev, 0x0, TDFXR); | ||
515 | sh_eth_write(ndev, 0x0, TDFFR); | ||
516 | sh_eth_write(ndev, 0x0, RDLAR); | ||
517 | sh_eth_write(ndev, 0x0, RDFAR); | ||
518 | sh_eth_write(ndev, 0x0, RDFXR); | ||
519 | sh_eth_write(ndev, 0x0, RDFFR); | ||
520 | } else { | ||
521 | sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, | ||
522 | EDMR); | ||
523 | mdelay(3); | ||
524 | sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, | ||
525 | EDMR); | ||
526 | } | ||
527 | |||
528 | out: | ||
529 | return ret; | ||
530 | } | ||
531 | |||
532 | static void sh_eth_set_rate_giga(struct net_device *ndev) | 501 | static void sh_eth_set_rate_giga(struct net_device *ndev) |
533 | { | 502 | { |
534 | struct sh_eth_private *mdp = netdev_priv(ndev); | 503 | struct sh_eth_private *mdp = netdev_priv(ndev); |
@@ -589,8 +558,6 @@ static struct sh_eth_cpu_data *sh_eth_get_cpu_data(struct sh_eth_private *mdp) | |||
589 | } | 558 | } |
590 | 559 | ||
591 | #elif defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763) | 560 | #elif defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763) |
592 | static int sh_eth_check_reset(struct net_device *ndev); | ||
593 | static void sh_eth_reset_hw_crc(struct net_device *ndev); | ||
594 | 561 | ||
595 | static void sh_eth_chip_reset(struct net_device *ndev) | 562 | static void sh_eth_chip_reset(struct net_device *ndev) |
596 | { | 563 | { |
@@ -653,45 +620,8 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { | |||
653 | #endif | 620 | #endif |
654 | }; | 621 | }; |
655 | 622 | ||
656 | static int sh_eth_reset(struct net_device *ndev) | ||
657 | { | ||
658 | int ret = 0; | ||
659 | |||
660 | sh_eth_write(ndev, EDSR_ENALL, EDSR); | ||
661 | sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR); | ||
662 | |||
663 | ret = sh_eth_check_reset(ndev); | ||
664 | if (ret) | ||
665 | goto out; | ||
666 | |||
667 | /* Table Init */ | ||
668 | sh_eth_write(ndev, 0x0, TDLAR); | ||
669 | sh_eth_write(ndev, 0x0, TDFAR); | ||
670 | sh_eth_write(ndev, 0x0, TDFXR); | ||
671 | sh_eth_write(ndev, 0x0, TDFFR); | ||
672 | sh_eth_write(ndev, 0x0, RDLAR); | ||
673 | sh_eth_write(ndev, 0x0, RDFAR); | ||
674 | sh_eth_write(ndev, 0x0, RDFXR); | ||
675 | sh_eth_write(ndev, 0x0, RDFFR); | ||
676 | |||
677 | /* Reset HW CRC register */ | ||
678 | sh_eth_reset_hw_crc(ndev); | ||
679 | |||
680 | /* Select MII mode */ | ||
681 | if (sh_eth_my_cpu_data.select_mii) | ||
682 | sh_eth_select_mii(ndev); | ||
683 | out: | ||
684 | return ret; | ||
685 | } | ||
686 | |||
687 | static void sh_eth_reset_hw_crc(struct net_device *ndev) | ||
688 | { | ||
689 | if (sh_eth_my_cpu_data.hw_crc) | ||
690 | sh_eth_write(ndev, 0x0, CSMR); | ||
691 | } | ||
692 | 623 | ||
693 | #elif defined(CONFIG_ARCH_R8A7740) | 624 | #elif defined(CONFIG_ARCH_R8A7740) |
694 | static int sh_eth_check_reset(struct net_device *ndev); | ||
695 | 625 | ||
696 | static void sh_eth_chip_reset(struct net_device *ndev) | 626 | static void sh_eth_chip_reset(struct net_device *ndev) |
697 | { | 627 | { |
@@ -704,31 +634,6 @@ static void sh_eth_chip_reset(struct net_device *ndev) | |||
704 | sh_eth_select_mii(ndev); | 634 | sh_eth_select_mii(ndev); |
705 | } | 635 | } |
706 | 636 | ||
707 | static int sh_eth_reset(struct net_device *ndev) | ||
708 | { | ||
709 | int ret = 0; | ||
710 | |||
711 | sh_eth_write(ndev, EDSR_ENALL, EDSR); | ||
712 | sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR); | ||
713 | |||
714 | ret = sh_eth_check_reset(ndev); | ||
715 | if (ret) | ||
716 | goto out; | ||
717 | |||
718 | /* Table Init */ | ||
719 | sh_eth_write(ndev, 0x0, TDLAR); | ||
720 | sh_eth_write(ndev, 0x0, TDFAR); | ||
721 | sh_eth_write(ndev, 0x0, TDFXR); | ||
722 | sh_eth_write(ndev, 0x0, TDFFR); | ||
723 | sh_eth_write(ndev, 0x0, RDLAR); | ||
724 | sh_eth_write(ndev, 0x0, RDFAR); | ||
725 | sh_eth_write(ndev, 0x0, RDFXR); | ||
726 | sh_eth_write(ndev, 0x0, RDFFR); | ||
727 | |||
728 | out: | ||
729 | return ret; | ||
730 | } | ||
731 | |||
732 | static void sh_eth_set_rate(struct net_device *ndev) | 637 | static void sh_eth_set_rate(struct net_device *ndev) |
733 | { | 638 | { |
734 | struct sh_eth_private *mdp = netdev_priv(ndev); | 639 | struct sh_eth_private *mdp = netdev_priv(ndev); |
@@ -777,7 +682,6 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { | |||
777 | }; | 682 | }; |
778 | 683 | ||
779 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) | 684 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) |
780 | #define SH_ETH_RESET_DEFAULT 1 | ||
781 | static struct sh_eth_cpu_data sh_eth_my_cpu_data = { | 685 | static struct sh_eth_cpu_data sh_eth_my_cpu_data = { |
782 | .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, | 686 | .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, |
783 | 687 | ||
@@ -787,7 +691,6 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { | |||
787 | .hw_swap = 1, | 691 | .hw_swap = 1, |
788 | }; | 692 | }; |
789 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) | 693 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
790 | #define SH_ETH_RESET_DEFAULT 1 | ||
791 | static struct sh_eth_cpu_data sh_eth_my_cpu_data = { | 694 | static struct sh_eth_cpu_data sh_eth_my_cpu_data = { |
792 | .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, | 695 | .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, |
793 | .tsu = 1, | 696 | .tsu = 1, |
@@ -822,17 +725,6 @@ static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) | |||
822 | cd->tx_error_check = DEFAULT_TX_ERROR_CHECK; | 725 | cd->tx_error_check = DEFAULT_TX_ERROR_CHECK; |
823 | } | 726 | } |
824 | 727 | ||
825 | #if defined(SH_ETH_RESET_DEFAULT) | ||
826 | /* Chip Reset */ | ||
827 | static int sh_eth_reset(struct net_device *ndev) | ||
828 | { | ||
829 | sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, EDMR); | ||
830 | mdelay(3); | ||
831 | sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, EDMR); | ||
832 | |||
833 | return 0; | ||
834 | } | ||
835 | #else | ||
836 | static int sh_eth_check_reset(struct net_device *ndev) | 728 | static int sh_eth_check_reset(struct net_device *ndev) |
837 | { | 729 | { |
838 | int ret = 0; | 730 | int ret = 0; |
@@ -850,7 +742,49 @@ static int sh_eth_check_reset(struct net_device *ndev) | |||
850 | } | 742 | } |
851 | return ret; | 743 | return ret; |
852 | } | 744 | } |
853 | #endif | 745 | |
746 | static int sh_eth_reset(struct net_device *ndev) | ||
747 | { | ||
748 | struct sh_eth_private *mdp = netdev_priv(ndev); | ||
749 | int ret = 0; | ||
750 | |||
751 | if (sh_eth_is_gether(mdp)) { | ||
752 | sh_eth_write(ndev, EDSR_ENALL, EDSR); | ||
753 | sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, | ||
754 | EDMR); | ||
755 | |||
756 | ret = sh_eth_check_reset(ndev); | ||
757 | if (ret) | ||
758 | goto out; | ||
759 | |||
760 | /* Table Init */ | ||
761 | sh_eth_write(ndev, 0x0, TDLAR); | ||
762 | sh_eth_write(ndev, 0x0, TDFAR); | ||
763 | sh_eth_write(ndev, 0x0, TDFXR); | ||
764 | sh_eth_write(ndev, 0x0, TDFFR); | ||
765 | sh_eth_write(ndev, 0x0, RDLAR); | ||
766 | sh_eth_write(ndev, 0x0, RDFAR); | ||
767 | sh_eth_write(ndev, 0x0, RDFXR); | ||
768 | sh_eth_write(ndev, 0x0, RDFFR); | ||
769 | |||
770 | /* Reset HW CRC register */ | ||
771 | if (mdp->cd->hw_crc) | ||
772 | sh_eth_write(ndev, 0x0, CSMR); | ||
773 | |||
774 | /* Select MII mode */ | ||
775 | if (mdp->cd->select_mii) | ||
776 | sh_eth_select_mii(ndev); | ||
777 | } else { | ||
778 | sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, | ||
779 | EDMR); | ||
780 | mdelay(3); | ||
781 | sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, | ||
782 | EDMR); | ||
783 | } | ||
784 | |||
785 | out: | ||
786 | return ret; | ||
787 | } | ||
854 | 788 | ||
855 | #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) | 789 | #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) |
856 | static void sh_eth_set_receive_align(struct sk_buff *skb) | 790 | static void sh_eth_set_receive_align(struct sk_buff *skb) |
@@ -926,14 +860,6 @@ static void read_mac_address(struct net_device *ndev, unsigned char *mac) | |||
926 | } | 860 | } |
927 | } | 861 | } |
928 | 862 | ||
929 | static int sh_eth_is_gether(struct sh_eth_private *mdp) | ||
930 | { | ||
931 | if (mdp->reg_offset == sh_eth_offset_gigabit) | ||
932 | return 1; | ||
933 | else | ||
934 | return 0; | ||
935 | } | ||
936 | |||
937 | static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp) | 863 | static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp) |
938 | { | 864 | { |
939 | if (sh_eth_is_gether(mdp)) | 865 | if (sh_eth_is_gether(mdp)) |