diff options
author | Chun-Hao Lin <hau@realtek.com> | 2014-10-01 11:17:18 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2014-10-01 15:33:18 -0400 |
commit | 706123d06c18b55da5e9da21e2d138ee789bf8f4 (patch) | |
tree | be352b0484cd4460f0afd689cb9fee0cea28719e /drivers/net/ethernet/realtek | |
parent | 7656442824f6174b56a19c664fe560972df56ad4 (diff) |
r8169:change the name of function"rtl_w1w0_eri"
Change the name of function "rtl_w1w0_eri" to "rtl_w0w1_eri".
In this function, the local variable "val" is "write zeros then write ones".
Please see below code.
(val & ~m) | p
In this patch, change the function name from "xx_w1w0_xx" to "xx_w0w1_xx".
The changed function name is more suitable for it's behavior.
Signed-off-by: Chun-Hao Lin <hau@realtek.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/realtek')
-rw-r--r-- | drivers/net/ethernet/realtek/r8169.c | 58 |
1 files changed, 29 insertions, 29 deletions
diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c index cdfad3524e6c..5884b6d9a717 100644 --- a/drivers/net/ethernet/realtek/r8169.c +++ b/drivers/net/ethernet/realtek/r8169.c | |||
@@ -1320,7 +1320,7 @@ static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type) | |||
1320 | RTL_R32(ERIDR) : ~0; | 1320 | RTL_R32(ERIDR) : ~0; |
1321 | } | 1321 | } |
1322 | 1322 | ||
1323 | static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p, | 1323 | static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p, |
1324 | u32 m, int type) | 1324 | u32 m, int type) |
1325 | { | 1325 | { |
1326 | u32 val; | 1326 | u32 val; |
@@ -1473,9 +1473,9 @@ static void rtl_link_chg_patch(struct rtl8169_private *tp) | |||
1473 | ERIAR_EXGMAC); | 1473 | ERIAR_EXGMAC); |
1474 | } | 1474 | } |
1475 | /* Reset packet filter */ | 1475 | /* Reset packet filter */ |
1476 | rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, | 1476 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, |
1477 | ERIAR_EXGMAC); | 1477 | ERIAR_EXGMAC); |
1478 | rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, | 1478 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, |
1479 | ERIAR_EXGMAC); | 1479 | ERIAR_EXGMAC); |
1480 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || | 1480 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || |
1481 | tp->mac_version == RTL_GIGA_MAC_VER_36) { | 1481 | tp->mac_version == RTL_GIGA_MAC_VER_36) { |
@@ -1629,14 +1629,14 @@ static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) | |||
1629 | case RTL_GIGA_MAC_VER_48: | 1629 | case RTL_GIGA_MAC_VER_48: |
1630 | tmp = ARRAY_SIZE(cfg) - 1; | 1630 | tmp = ARRAY_SIZE(cfg) - 1; |
1631 | if (wolopts & WAKE_MAGIC) | 1631 | if (wolopts & WAKE_MAGIC) |
1632 | rtl_w1w0_eri(tp, | 1632 | rtl_w0w1_eri(tp, |
1633 | 0x0dc, | 1633 | 0x0dc, |
1634 | ERIAR_MASK_0100, | 1634 | ERIAR_MASK_0100, |
1635 | MagicPacket_v2, | 1635 | MagicPacket_v2, |
1636 | 0x0000, | 1636 | 0x0000, |
1637 | ERIAR_EXGMAC); | 1637 | ERIAR_EXGMAC); |
1638 | else | 1638 | else |
1639 | rtl_w1w0_eri(tp, | 1639 | rtl_w0w1_eri(tp, |
1640 | 0x0dc, | 1640 | 0x0dc, |
1641 | ERIAR_MASK_0100, | 1641 | ERIAR_MASK_0100, |
1642 | 0x0000, | 1642 | 0x0000, |
@@ -3292,7 +3292,7 @@ static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp) | |||
3292 | rtl_writephy(tp, 0x1f, 0x0000); | 3292 | rtl_writephy(tp, 0x1f, 0x0000); |
3293 | 3293 | ||
3294 | /* EEE setting */ | 3294 | /* EEE setting */ |
3295 | rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC); | 3295 | rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC); |
3296 | rtl_writephy(tp, 0x1f, 0x0005); | 3296 | rtl_writephy(tp, 0x1f, 0x0005); |
3297 | rtl_writephy(tp, 0x05, 0x8b85); | 3297 | rtl_writephy(tp, 0x05, 0x8b85); |
3298 | rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000); | 3298 | rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000); |
@@ -3472,7 +3472,7 @@ static void rtl8411_hw_phy_config(struct rtl8169_private *tp) | |||
3472 | rtl_writephy(tp, 0x1f, 0x0000); | 3472 | rtl_writephy(tp, 0x1f, 0x0000); |
3473 | 3473 | ||
3474 | /* eee setting */ | 3474 | /* eee setting */ |
3475 | rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC); | 3475 | rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC); |
3476 | rtl_writephy(tp, 0x1f, 0x0005); | 3476 | rtl_writephy(tp, 0x1f, 0x0005); |
3477 | rtl_writephy(tp, 0x05, 0x8b85); | 3477 | rtl_writephy(tp, 0x05, 0x8b85); |
3478 | rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000); | 3478 | rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000); |
@@ -4398,7 +4398,7 @@ static void r8168_pll_power_down(struct rtl8169_private *tp) | |||
4398 | break; | 4398 | break; |
4399 | case RTL_GIGA_MAC_VER_40: | 4399 | case RTL_GIGA_MAC_VER_40: |
4400 | case RTL_GIGA_MAC_VER_41: | 4400 | case RTL_GIGA_MAC_VER_41: |
4401 | rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000, | 4401 | rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000, |
4402 | 0xfc000000, ERIAR_EXGMAC); | 4402 | 0xfc000000, ERIAR_EXGMAC); |
4403 | RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80); | 4403 | RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80); |
4404 | break; | 4404 | break; |
@@ -4427,7 +4427,7 @@ static void r8168_pll_power_up(struct rtl8169_private *tp) | |||
4427 | case RTL_GIGA_MAC_VER_40: | 4427 | case RTL_GIGA_MAC_VER_40: |
4428 | case RTL_GIGA_MAC_VER_41: | 4428 | case RTL_GIGA_MAC_VER_41: |
4429 | RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0); | 4429 | RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0); |
4430 | rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000, | 4430 | rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000, |
4431 | 0x00000000, ERIAR_EXGMAC); | 4431 | 0x00000000, ERIAR_EXGMAC); |
4432 | break; | 4432 | break; |
4433 | } | 4433 | } |
@@ -5501,8 +5501,8 @@ static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) | |||
5501 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); | 5501 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); |
5502 | rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); | 5502 | rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); |
5503 | rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC); | 5503 | rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC); |
5504 | rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); | 5504 | rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); |
5505 | rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC); | 5505 | rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC); |
5506 | 5506 | ||
5507 | RTL_W8(MaxTxPacketSize, EarlySize); | 5507 | RTL_W8(MaxTxPacketSize, EarlySize); |
5508 | 5508 | ||
@@ -5532,10 +5532,10 @@ static void rtl_hw_start_8168f(struct rtl8169_private *tp) | |||
5532 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | 5532 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
5533 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC); | 5533 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC); |
5534 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); | 5534 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); |
5535 | rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); | 5535 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); |
5536 | rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); | 5536 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); |
5537 | rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); | 5537 | rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); |
5538 | rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); | 5538 | rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); |
5539 | rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); | 5539 | rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); |
5540 | rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC); | 5540 | rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC); |
5541 | 5541 | ||
@@ -5564,7 +5564,7 @@ static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) | |||
5564 | 5564 | ||
5565 | rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1)); | 5565 | rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1)); |
5566 | 5566 | ||
5567 | rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC); | 5567 | rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC); |
5568 | 5568 | ||
5569 | /* Adjust EEE LED frequency */ | 5569 | /* Adjust EEE LED frequency */ |
5570 | RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); | 5570 | RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); |
@@ -5584,7 +5584,7 @@ static void rtl_hw_start_8411(struct rtl8169_private *tp) | |||
5584 | 5584 | ||
5585 | rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1)); | 5585 | rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1)); |
5586 | 5586 | ||
5587 | rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC); | 5587 | rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC); |
5588 | } | 5588 | } |
5589 | 5589 | ||
5590 | static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) | 5590 | static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) |
@@ -5603,8 +5603,8 @@ static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) | |||
5603 | 5603 | ||
5604 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | 5604 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
5605 | 5605 | ||
5606 | rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); | 5606 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); |
5607 | rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); | 5607 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); |
5608 | rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC); | 5608 | rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC); |
5609 | 5609 | ||
5610 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); | 5610 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
@@ -5617,8 +5617,8 @@ static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) | |||
5617 | /* Adjust EEE LED frequency */ | 5617 | /* Adjust EEE LED frequency */ |
5618 | RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); | 5618 | RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); |
5619 | 5619 | ||
5620 | rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC); | 5620 | rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC); |
5621 | rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC); | 5621 | rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC); |
5622 | 5622 | ||
5623 | rtl_pcie_state_l2l3_enable(tp, false); | 5623 | rtl_pcie_state_l2l3_enable(tp, false); |
5624 | } | 5624 | } |
@@ -5691,12 +5691,12 @@ static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) | |||
5691 | 5691 | ||
5692 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | 5692 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
5693 | 5693 | ||
5694 | rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); | 5694 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); |
5695 | rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); | 5695 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); |
5696 | 5696 | ||
5697 | rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC); | 5697 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC); |
5698 | 5698 | ||
5699 | rtl_w1w0_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC); | 5699 | rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC); |
5700 | 5700 | ||
5701 | rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC); | 5701 | rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC); |
5702 | 5702 | ||
@@ -5715,7 +5715,7 @@ static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) | |||
5715 | 5715 | ||
5716 | RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN); | 5716 | RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN); |
5717 | 5717 | ||
5718 | rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC); | 5718 | rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC); |
5719 | 5719 | ||
5720 | rtl_pcie_state_l2l3_enable(tp, false); | 5720 | rtl_pcie_state_l2l3_enable(tp, false); |
5721 | 5721 | ||
@@ -6009,11 +6009,11 @@ static void rtl_hw_start_8402(struct rtl8169_private *tp) | |||
6009 | 6009 | ||
6010 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC); | 6010 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC); |
6011 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC); | 6011 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC); |
6012 | rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); | 6012 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); |
6013 | rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); | 6013 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); |
6014 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | 6014 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
6015 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | 6015 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
6016 | rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC); | 6016 | rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC); |
6017 | 6017 | ||
6018 | rtl_pcie_state_l2l3_enable(tp, false); | 6018 | rtl_pcie_state_l2l3_enable(tp, false); |
6019 | } | 6019 | } |