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authorChun-Hao Lin <hau@realtek.com>2014-10-01 11:17:17 -0400
committerDavid S. Miller <davem@davemloft.net>2014-10-01 15:33:17 -0400
commit7656442824f6174b56a19c664fe560972df56ad4 (patch)
tree6938d75fe49b89a43cd9b7fd4e7147ec6b83cba8 /drivers/net/ethernet/realtek/r8169.c
parentac85bcdbc0ffd3903d6db4abcd769ecacf98605b (diff)
r8169:for function "rtl_w1w0_phy" change its name and behavior
Change function name from "rtl_w1w0_phy" to "rtl_w0w1_phy". And its behavior from "write ones then write zeros" to "write zeros then write ones". In Realtek internal driver, bitwise operations are almost "write zeros then write ones". For easy to port hardware parameters from Realtek internal driver to Linux kernal driver "r8169", we would like to change this function's behavior and its name. Signed-off-by: Chun-Hao Lin <hau@realtek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/realtek/r8169.c')
-rw-r--r--drivers/net/ethernet/realtek/r8169.c176
1 files changed, 88 insertions, 88 deletions
diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
index 070724c12b75..cdfad3524e6c 100644
--- a/drivers/net/ethernet/realtek/r8169.c
+++ b/drivers/net/ethernet/realtek/r8169.c
@@ -1246,12 +1246,12 @@ static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1246 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value); 1246 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1247} 1247}
1248 1248
1249static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m) 1249static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1250{ 1250{
1251 int val; 1251 int val;
1252 1252
1253 val = rtl_readphy(tp, reg_addr); 1253 val = rtl_readphy(tp, reg_addr);
1254 rtl_writephy(tp, reg_addr, (val | p) & ~m); 1254 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1255} 1255}
1256 1256
1257static void rtl_mdio_write(struct net_device *dev, int phy_id, int location, 1257static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
@@ -2901,8 +2901,8 @@ static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2901 * Fine Tune Switching regulator parameter 2901 * Fine Tune Switching regulator parameter
2902 */ 2902 */
2903 rtl_writephy(tp, 0x1f, 0x0002); 2903 rtl_writephy(tp, 0x1f, 0x0002);
2904 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef); 2904 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2905 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00); 2905 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2906 2906
2907 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { 2907 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2908 static const struct phy_reg phy_reg_init[] = { 2908 static const struct phy_reg phy_reg_init[] = {
@@ -2951,8 +2951,8 @@ static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2951 2951
2952 /* Fine tune PLL performance */ 2952 /* Fine tune PLL performance */
2953 rtl_writephy(tp, 0x1f, 0x0002); 2953 rtl_writephy(tp, 0x1f, 0x0002);
2954 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600); 2954 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2955 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000); 2955 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2956 2956
2957 rtl_writephy(tp, 0x1f, 0x0005); 2957 rtl_writephy(tp, 0x1f, 0x0005);
2958 rtl_writephy(tp, 0x05, 0x001b); 2958 rtl_writephy(tp, 0x05, 0x001b);
@@ -3049,8 +3049,8 @@ static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3049 3049
3050 /* Fine tune PLL performance */ 3050 /* Fine tune PLL performance */
3051 rtl_writephy(tp, 0x1f, 0x0002); 3051 rtl_writephy(tp, 0x1f, 0x0002);
3052 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600); 3052 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3053 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000); 3053 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3054 3054
3055 /* Switching regulator Slew rate */ 3055 /* Switching regulator Slew rate */
3056 rtl_writephy(tp, 0x1f, 0x0002); 3056 rtl_writephy(tp, 0x1f, 0x0002);
@@ -3178,32 +3178,32 @@ static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3178 /* DCO enable for 10M IDLE Power */ 3178 /* DCO enable for 10M IDLE Power */
3179 rtl_writephy(tp, 0x1f, 0x0007); 3179 rtl_writephy(tp, 0x1f, 0x0007);
3180 rtl_writephy(tp, 0x1e, 0x0023); 3180 rtl_writephy(tp, 0x1e, 0x0023);
3181 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000); 3181 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3182 rtl_writephy(tp, 0x1f, 0x0000); 3182 rtl_writephy(tp, 0x1f, 0x0000);
3183 3183
3184 /* For impedance matching */ 3184 /* For impedance matching */
3185 rtl_writephy(tp, 0x1f, 0x0002); 3185 rtl_writephy(tp, 0x1f, 0x0002);
3186 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00); 3186 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3187 rtl_writephy(tp, 0x1f, 0x0000); 3187 rtl_writephy(tp, 0x1f, 0x0000);
3188 3188
3189 /* PHY auto speed down */ 3189 /* PHY auto speed down */
3190 rtl_writephy(tp, 0x1f, 0x0007); 3190 rtl_writephy(tp, 0x1f, 0x0007);
3191 rtl_writephy(tp, 0x1e, 0x002d); 3191 rtl_writephy(tp, 0x1e, 0x002d);
3192 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000); 3192 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3193 rtl_writephy(tp, 0x1f, 0x0000); 3193 rtl_writephy(tp, 0x1f, 0x0000);
3194 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); 3194 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3195 3195
3196 rtl_writephy(tp, 0x1f, 0x0005); 3196 rtl_writephy(tp, 0x1f, 0x0005);
3197 rtl_writephy(tp, 0x05, 0x8b86); 3197 rtl_writephy(tp, 0x05, 0x8b86);
3198 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); 3198 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3199 rtl_writephy(tp, 0x1f, 0x0000); 3199 rtl_writephy(tp, 0x1f, 0x0000);
3200 3200
3201 rtl_writephy(tp, 0x1f, 0x0005); 3201 rtl_writephy(tp, 0x1f, 0x0005);
3202 rtl_writephy(tp, 0x05, 0x8b85); 3202 rtl_writephy(tp, 0x05, 0x8b85);
3203 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); 3203 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3204 rtl_writephy(tp, 0x1f, 0x0007); 3204 rtl_writephy(tp, 0x1f, 0x0007);
3205 rtl_writephy(tp, 0x1e, 0x0020); 3205 rtl_writephy(tp, 0x1e, 0x0020);
3206 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100); 3206 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3207 rtl_writephy(tp, 0x1f, 0x0006); 3207 rtl_writephy(tp, 0x1f, 0x0006);
3208 rtl_writephy(tp, 0x00, 0x5a00); 3208 rtl_writephy(tp, 0x00, 0x5a00);
3209 rtl_writephy(tp, 0x1f, 0x0000); 3209 rtl_writephy(tp, 0x1f, 0x0000);
@@ -3267,39 +3267,39 @@ static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3267 /* For 4-corner performance improve */ 3267 /* For 4-corner performance improve */
3268 rtl_writephy(tp, 0x1f, 0x0005); 3268 rtl_writephy(tp, 0x1f, 0x0005);
3269 rtl_writephy(tp, 0x05, 0x8b80); 3269 rtl_writephy(tp, 0x05, 0x8b80);
3270 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000); 3270 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3271 rtl_writephy(tp, 0x1f, 0x0000); 3271 rtl_writephy(tp, 0x1f, 0x0000);
3272 3272
3273 /* PHY auto speed down */ 3273 /* PHY auto speed down */
3274 rtl_writephy(tp, 0x1f, 0x0004); 3274 rtl_writephy(tp, 0x1f, 0x0004);
3275 rtl_writephy(tp, 0x1f, 0x0007); 3275 rtl_writephy(tp, 0x1f, 0x0007);
3276 rtl_writephy(tp, 0x1e, 0x002d); 3276 rtl_writephy(tp, 0x1e, 0x002d);
3277 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); 3277 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3278 rtl_writephy(tp, 0x1f, 0x0002); 3278 rtl_writephy(tp, 0x1f, 0x0002);
3279 rtl_writephy(tp, 0x1f, 0x0000); 3279 rtl_writephy(tp, 0x1f, 0x0000);
3280 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); 3280 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3281 3281
3282 /* improve 10M EEE waveform */ 3282 /* improve 10M EEE waveform */
3283 rtl_writephy(tp, 0x1f, 0x0005); 3283 rtl_writephy(tp, 0x1f, 0x0005);
3284 rtl_writephy(tp, 0x05, 0x8b86); 3284 rtl_writephy(tp, 0x05, 0x8b86);
3285 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); 3285 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3286 rtl_writephy(tp, 0x1f, 0x0000); 3286 rtl_writephy(tp, 0x1f, 0x0000);
3287 3287
3288 /* Improve 2-pair detection performance */ 3288 /* Improve 2-pair detection performance */
3289 rtl_writephy(tp, 0x1f, 0x0005); 3289 rtl_writephy(tp, 0x1f, 0x0005);
3290 rtl_writephy(tp, 0x05, 0x8b85); 3290 rtl_writephy(tp, 0x05, 0x8b85);
3291 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000); 3291 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3292 rtl_writephy(tp, 0x1f, 0x0000); 3292 rtl_writephy(tp, 0x1f, 0x0000);
3293 3293
3294 /* EEE setting */ 3294 /* EEE setting */
3295 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC); 3295 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3296 rtl_writephy(tp, 0x1f, 0x0005); 3296 rtl_writephy(tp, 0x1f, 0x0005);
3297 rtl_writephy(tp, 0x05, 0x8b85); 3297 rtl_writephy(tp, 0x05, 0x8b85);
3298 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); 3298 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3299 rtl_writephy(tp, 0x1f, 0x0004); 3299 rtl_writephy(tp, 0x1f, 0x0004);
3300 rtl_writephy(tp, 0x1f, 0x0007); 3300 rtl_writephy(tp, 0x1f, 0x0007);
3301 rtl_writephy(tp, 0x1e, 0x0020); 3301 rtl_writephy(tp, 0x1e, 0x0020);
3302 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100); 3302 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3303 rtl_writephy(tp, 0x1f, 0x0002); 3303 rtl_writephy(tp, 0x1f, 0x0002);
3304 rtl_writephy(tp, 0x1f, 0x0000); 3304 rtl_writephy(tp, 0x1f, 0x0000);
3305 rtl_writephy(tp, 0x0d, 0x0007); 3305 rtl_writephy(tp, 0x0d, 0x0007);
@@ -3310,8 +3310,8 @@ static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3310 3310
3311 /* Green feature */ 3311 /* Green feature */
3312 rtl_writephy(tp, 0x1f, 0x0003); 3312 rtl_writephy(tp, 0x1f, 0x0003);
3313 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001); 3313 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3314 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400); 3314 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3315 rtl_writephy(tp, 0x1f, 0x0000); 3315 rtl_writephy(tp, 0x1f, 0x0000);
3316 3316
3317 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */ 3317 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
@@ -3323,20 +3323,20 @@ static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3323 /* For 4-corner performance improve */ 3323 /* For 4-corner performance improve */
3324 rtl_writephy(tp, 0x1f, 0x0005); 3324 rtl_writephy(tp, 0x1f, 0x0005);
3325 rtl_writephy(tp, 0x05, 0x8b80); 3325 rtl_writephy(tp, 0x05, 0x8b80);
3326 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000); 3326 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3327 rtl_writephy(tp, 0x1f, 0x0000); 3327 rtl_writephy(tp, 0x1f, 0x0000);
3328 3328
3329 /* PHY auto speed down */ 3329 /* PHY auto speed down */
3330 rtl_writephy(tp, 0x1f, 0x0007); 3330 rtl_writephy(tp, 0x1f, 0x0007);
3331 rtl_writephy(tp, 0x1e, 0x002d); 3331 rtl_writephy(tp, 0x1e, 0x002d);
3332 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); 3332 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3333 rtl_writephy(tp, 0x1f, 0x0000); 3333 rtl_writephy(tp, 0x1f, 0x0000);
3334 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); 3334 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3335 3335
3336 /* Improve 10M EEE waveform */ 3336 /* Improve 10M EEE waveform */
3337 rtl_writephy(tp, 0x1f, 0x0005); 3337 rtl_writephy(tp, 0x1f, 0x0005);
3338 rtl_writephy(tp, 0x05, 0x8b86); 3338 rtl_writephy(tp, 0x05, 0x8b86);
3339 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); 3339 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3340 rtl_writephy(tp, 0x1f, 0x0000); 3340 rtl_writephy(tp, 0x1f, 0x0000);
3341} 3341}
3342 3342
@@ -3386,7 +3386,7 @@ static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3386 /* Improve 2-pair detection performance */ 3386 /* Improve 2-pair detection performance */
3387 rtl_writephy(tp, 0x1f, 0x0005); 3387 rtl_writephy(tp, 0x1f, 0x0005);
3388 rtl_writephy(tp, 0x05, 0x8b85); 3388 rtl_writephy(tp, 0x05, 0x8b85);
3389 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000); 3389 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3390 rtl_writephy(tp, 0x1f, 0x0000); 3390 rtl_writephy(tp, 0x1f, 0x0000);
3391} 3391}
3392 3392
@@ -3442,7 +3442,7 @@ static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3442 /* Improve 2-pair detection performance */ 3442 /* Improve 2-pair detection performance */
3443 rtl_writephy(tp, 0x1f, 0x0005); 3443 rtl_writephy(tp, 0x1f, 0x0005);
3444 rtl_writephy(tp, 0x05, 0x8b85); 3444 rtl_writephy(tp, 0x05, 0x8b85);
3445 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000); 3445 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3446 rtl_writephy(tp, 0x1f, 0x0000); 3446 rtl_writephy(tp, 0x1f, 0x0000);
3447 3447
3448 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 3448 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
@@ -3450,36 +3450,36 @@ static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3450 /* Modify green table for giga */ 3450 /* Modify green table for giga */
3451 rtl_writephy(tp, 0x1f, 0x0005); 3451 rtl_writephy(tp, 0x1f, 0x0005);
3452 rtl_writephy(tp, 0x05, 0x8b54); 3452 rtl_writephy(tp, 0x05, 0x8b54);
3453 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800); 3453 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3454 rtl_writephy(tp, 0x05, 0x8b5d); 3454 rtl_writephy(tp, 0x05, 0x8b5d);
3455 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800); 3455 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3456 rtl_writephy(tp, 0x05, 0x8a7c); 3456 rtl_writephy(tp, 0x05, 0x8a7c);
3457 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100); 3457 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3458 rtl_writephy(tp, 0x05, 0x8a7f); 3458 rtl_writephy(tp, 0x05, 0x8a7f);
3459 rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000); 3459 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3460 rtl_writephy(tp, 0x05, 0x8a82); 3460 rtl_writephy(tp, 0x05, 0x8a82);
3461 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100); 3461 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3462 rtl_writephy(tp, 0x05, 0x8a85); 3462 rtl_writephy(tp, 0x05, 0x8a85);
3463 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100); 3463 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3464 rtl_writephy(tp, 0x05, 0x8a88); 3464 rtl_writephy(tp, 0x05, 0x8a88);
3465 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100); 3465 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3466 rtl_writephy(tp, 0x1f, 0x0000); 3466 rtl_writephy(tp, 0x1f, 0x0000);
3467 3467
3468 /* uc same-seed solution */ 3468 /* uc same-seed solution */
3469 rtl_writephy(tp, 0x1f, 0x0005); 3469 rtl_writephy(tp, 0x1f, 0x0005);
3470 rtl_writephy(tp, 0x05, 0x8b85); 3470 rtl_writephy(tp, 0x05, 0x8b85);
3471 rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000); 3471 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3472 rtl_writephy(tp, 0x1f, 0x0000); 3472 rtl_writephy(tp, 0x1f, 0x0000);
3473 3473
3474 /* eee setting */ 3474 /* eee setting */
3475 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC); 3475 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3476 rtl_writephy(tp, 0x1f, 0x0005); 3476 rtl_writephy(tp, 0x1f, 0x0005);
3477 rtl_writephy(tp, 0x05, 0x8b85); 3477 rtl_writephy(tp, 0x05, 0x8b85);
3478 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); 3478 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3479 rtl_writephy(tp, 0x1f, 0x0004); 3479 rtl_writephy(tp, 0x1f, 0x0004);
3480 rtl_writephy(tp, 0x1f, 0x0007); 3480 rtl_writephy(tp, 0x1f, 0x0007);
3481 rtl_writephy(tp, 0x1e, 0x0020); 3481 rtl_writephy(tp, 0x1e, 0x0020);
3482 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100); 3482 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3483 rtl_writephy(tp, 0x1f, 0x0000); 3483 rtl_writephy(tp, 0x1f, 0x0000);
3484 rtl_writephy(tp, 0x0d, 0x0007); 3484 rtl_writephy(tp, 0x0d, 0x0007);
3485 rtl_writephy(tp, 0x0e, 0x003c); 3485 rtl_writephy(tp, 0x0e, 0x003c);
@@ -3489,8 +3489,8 @@ static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3489 3489
3490 /* Green feature */ 3490 /* Green feature */
3491 rtl_writephy(tp, 0x1f, 0x0003); 3491 rtl_writephy(tp, 0x1f, 0x0003);
3492 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001); 3492 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3493 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400); 3493 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3494 rtl_writephy(tp, 0x1f, 0x0000); 3494 rtl_writephy(tp, 0x1f, 0x0000);
3495} 3495}
3496 3496
@@ -3501,45 +3501,45 @@ static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3501 rtl_writephy(tp, 0x1f, 0x0a46); 3501 rtl_writephy(tp, 0x1f, 0x0a46);
3502 if (rtl_readphy(tp, 0x10) & 0x0100) { 3502 if (rtl_readphy(tp, 0x10) & 0x0100) {
3503 rtl_writephy(tp, 0x1f, 0x0bcc); 3503 rtl_writephy(tp, 0x1f, 0x0bcc);
3504 rtl_w1w0_phy(tp, 0x12, 0x0000, 0x8000); 3504 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3505 } else { 3505 } else {
3506 rtl_writephy(tp, 0x1f, 0x0bcc); 3506 rtl_writephy(tp, 0x1f, 0x0bcc);
3507 rtl_w1w0_phy(tp, 0x12, 0x8000, 0x0000); 3507 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3508 } 3508 }
3509 3509
3510 rtl_writephy(tp, 0x1f, 0x0a46); 3510 rtl_writephy(tp, 0x1f, 0x0a46);
3511 if (rtl_readphy(tp, 0x13) & 0x0100) { 3511 if (rtl_readphy(tp, 0x13) & 0x0100) {
3512 rtl_writephy(tp, 0x1f, 0x0c41); 3512 rtl_writephy(tp, 0x1f, 0x0c41);
3513 rtl_w1w0_phy(tp, 0x15, 0x0002, 0x0000); 3513 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3514 } else { 3514 } else {
3515 rtl_writephy(tp, 0x1f, 0x0c41); 3515 rtl_writephy(tp, 0x1f, 0x0c41);
3516 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0002); 3516 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3517 } 3517 }
3518 3518
3519 /* Enable PHY auto speed down */ 3519 /* Enable PHY auto speed down */
3520 rtl_writephy(tp, 0x1f, 0x0a44); 3520 rtl_writephy(tp, 0x1f, 0x0a44);
3521 rtl_w1w0_phy(tp, 0x11, 0x000c, 0x0000); 3521 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3522 3522
3523 rtl_writephy(tp, 0x1f, 0x0bcc); 3523 rtl_writephy(tp, 0x1f, 0x0bcc);
3524 rtl_w1w0_phy(tp, 0x14, 0x0100, 0x0000); 3524 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3525 rtl_writephy(tp, 0x1f, 0x0a44); 3525 rtl_writephy(tp, 0x1f, 0x0a44);
3526 rtl_w1w0_phy(tp, 0x11, 0x00c0, 0x0000); 3526 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3527 rtl_writephy(tp, 0x1f, 0x0a43); 3527 rtl_writephy(tp, 0x1f, 0x0a43);
3528 rtl_writephy(tp, 0x13, 0x8084); 3528 rtl_writephy(tp, 0x13, 0x8084);
3529 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x6000); 3529 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3530 rtl_w1w0_phy(tp, 0x10, 0x1003, 0x0000); 3530 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3531 3531
3532 /* EEE auto-fallback function */ 3532 /* EEE auto-fallback function */
3533 rtl_writephy(tp, 0x1f, 0x0a4b); 3533 rtl_writephy(tp, 0x1f, 0x0a4b);
3534 rtl_w1w0_phy(tp, 0x11, 0x0004, 0x0000); 3534 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3535 3535
3536 /* Enable UC LPF tune function */ 3536 /* Enable UC LPF tune function */
3537 rtl_writephy(tp, 0x1f, 0x0a43); 3537 rtl_writephy(tp, 0x1f, 0x0a43);
3538 rtl_writephy(tp, 0x13, 0x8012); 3538 rtl_writephy(tp, 0x13, 0x8012);
3539 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); 3539 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3540 3540
3541 rtl_writephy(tp, 0x1f, 0x0c42); 3541 rtl_writephy(tp, 0x1f, 0x0c42);
3542 rtl_w1w0_phy(tp, 0x11, 0x4000, 0x2000); 3542 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3543 3543
3544 /* Improve SWR Efficiency */ 3544 /* Improve SWR Efficiency */
3545 rtl_writephy(tp, 0x1f, 0x0bcd); 3545 rtl_writephy(tp, 0x1f, 0x0bcd);
@@ -3555,7 +3555,7 @@ static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3555 /* Check ALDPS bit, disable it if enabled */ 3555 /* Check ALDPS bit, disable it if enabled */
3556 rtl_writephy(tp, 0x1f, 0x0a43); 3556 rtl_writephy(tp, 0x1f, 0x0a43);
3557 if (rtl_readphy(tp, 0x10) & 0x0004) 3557 if (rtl_readphy(tp, 0x10) & 0x0004)
3558 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0004); 3558 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3559 3559
3560 rtl_writephy(tp, 0x1f, 0x0000); 3560 rtl_writephy(tp, 0x1f, 0x0000);
3561} 3561}
@@ -3575,33 +3575,33 @@ static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3575 /* CHN EST parameters adjust - giga master */ 3575 /* CHN EST parameters adjust - giga master */
3576 rtl_writephy(tp, 0x1f, 0x0a43); 3576 rtl_writephy(tp, 0x1f, 0x0a43);
3577 rtl_writephy(tp, 0x13, 0x809b); 3577 rtl_writephy(tp, 0x13, 0x809b);
3578 rtl_w1w0_phy(tp, 0x14, 0x8000, 0xf800); 3578 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3579 rtl_writephy(tp, 0x13, 0x80a2); 3579 rtl_writephy(tp, 0x13, 0x80a2);
3580 rtl_w1w0_phy(tp, 0x14, 0x8000, 0xff00); 3580 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3581 rtl_writephy(tp, 0x13, 0x80a4); 3581 rtl_writephy(tp, 0x13, 0x80a4);
3582 rtl_w1w0_phy(tp, 0x14, 0x8500, 0xff00); 3582 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3583 rtl_writephy(tp, 0x13, 0x809c); 3583 rtl_writephy(tp, 0x13, 0x809c);
3584 rtl_w1w0_phy(tp, 0x14, 0xbd00, 0xff00); 3584 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3585 rtl_writephy(tp, 0x1f, 0x0000); 3585 rtl_writephy(tp, 0x1f, 0x0000);
3586 3586
3587 /* CHN EST parameters adjust - giga slave */ 3587 /* CHN EST parameters adjust - giga slave */
3588 rtl_writephy(tp, 0x1f, 0x0a43); 3588 rtl_writephy(tp, 0x1f, 0x0a43);
3589 rtl_writephy(tp, 0x13, 0x80ad); 3589 rtl_writephy(tp, 0x13, 0x80ad);
3590 rtl_w1w0_phy(tp, 0x14, 0x7000, 0xf800); 3590 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3591 rtl_writephy(tp, 0x13, 0x80b4); 3591 rtl_writephy(tp, 0x13, 0x80b4);
3592 rtl_w1w0_phy(tp, 0x14, 0x5000, 0xff00); 3592 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3593 rtl_writephy(tp, 0x13, 0x80ac); 3593 rtl_writephy(tp, 0x13, 0x80ac);
3594 rtl_w1w0_phy(tp, 0x14, 0x4000, 0xff00); 3594 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3595 rtl_writephy(tp, 0x1f, 0x0000); 3595 rtl_writephy(tp, 0x1f, 0x0000);
3596 3596
3597 /* CHN EST parameters adjust - fnet */ 3597 /* CHN EST parameters adjust - fnet */
3598 rtl_writephy(tp, 0x1f, 0x0a43); 3598 rtl_writephy(tp, 0x1f, 0x0a43);
3599 rtl_writephy(tp, 0x13, 0x808e); 3599 rtl_writephy(tp, 0x13, 0x808e);
3600 rtl_w1w0_phy(tp, 0x14, 0x1200, 0xff00); 3600 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3601 rtl_writephy(tp, 0x13, 0x8090); 3601 rtl_writephy(tp, 0x13, 0x8090);
3602 rtl_w1w0_phy(tp, 0x14, 0xe500, 0xff00); 3602 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3603 rtl_writephy(tp, 0x13, 0x8092); 3603 rtl_writephy(tp, 0x13, 0x8092);
3604 rtl_w1w0_phy(tp, 0x14, 0x9f00, 0xff00); 3604 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3605 rtl_writephy(tp, 0x1f, 0x0000); 3605 rtl_writephy(tp, 0x1f, 0x0000);
3606 3606
3607 /* enable R-tune & PGA-retune function */ 3607 /* enable R-tune & PGA-retune function */
@@ -3620,57 +3620,57 @@ static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3620 dout_tapbin &= 0xf000; 3620 dout_tapbin &= 0xf000;
3621 rtl_writephy(tp, 0x1f, 0x0a43); 3621 rtl_writephy(tp, 0x1f, 0x0a43);
3622 rtl_writephy(tp, 0x13, 0x827a); 3622 rtl_writephy(tp, 0x13, 0x827a);
3623 rtl_w1w0_phy(tp, 0x14, dout_tapbin, 0xf000); 3623 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3624 rtl_writephy(tp, 0x13, 0x827b); 3624 rtl_writephy(tp, 0x13, 0x827b);
3625 rtl_w1w0_phy(tp, 0x14, dout_tapbin, 0xf000); 3625 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3626 rtl_writephy(tp, 0x13, 0x827c); 3626 rtl_writephy(tp, 0x13, 0x827c);
3627 rtl_w1w0_phy(tp, 0x14, dout_tapbin, 0xf000); 3627 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3628 rtl_writephy(tp, 0x13, 0x827d); 3628 rtl_writephy(tp, 0x13, 0x827d);
3629 rtl_w1w0_phy(tp, 0x14, dout_tapbin, 0xf000); 3629 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3630 3630
3631 rtl_writephy(tp, 0x1f, 0x0a43); 3631 rtl_writephy(tp, 0x1f, 0x0a43);
3632 rtl_writephy(tp, 0x13, 0x0811); 3632 rtl_writephy(tp, 0x13, 0x0811);
3633 rtl_w1w0_phy(tp, 0x14, 0x0800, 0x0000); 3633 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3634 rtl_writephy(tp, 0x1f, 0x0a42); 3634 rtl_writephy(tp, 0x1f, 0x0a42);
3635 rtl_w1w0_phy(tp, 0x16, 0x0002, 0x0000); 3635 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3636 rtl_writephy(tp, 0x1f, 0x0000); 3636 rtl_writephy(tp, 0x1f, 0x0000);
3637 3637
3638 /* enable GPHY 10M */ 3638 /* enable GPHY 10M */
3639 rtl_writephy(tp, 0x1f, 0x0a44); 3639 rtl_writephy(tp, 0x1f, 0x0a44);
3640 rtl_w1w0_phy(tp, 0x11, 0x0800, 0x0000); 3640 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3641 rtl_writephy(tp, 0x1f, 0x0000); 3641 rtl_writephy(tp, 0x1f, 0x0000);
3642 3642
3643 /* SAR ADC performance */ 3643 /* SAR ADC performance */
3644 rtl_writephy(tp, 0x1f, 0x0bca); 3644 rtl_writephy(tp, 0x1f, 0x0bca);
3645 rtl_w1w0_phy(tp, 0x17, 0x4000, 0x3000); 3645 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3646 rtl_writephy(tp, 0x1f, 0x0000); 3646 rtl_writephy(tp, 0x1f, 0x0000);
3647 3647
3648 rtl_writephy(tp, 0x1f, 0x0a43); 3648 rtl_writephy(tp, 0x1f, 0x0a43);
3649 rtl_writephy(tp, 0x13, 0x803f); 3649 rtl_writephy(tp, 0x13, 0x803f);
3650 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000); 3650 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3651 rtl_writephy(tp, 0x13, 0x8047); 3651 rtl_writephy(tp, 0x13, 0x8047);
3652 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000); 3652 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3653 rtl_writephy(tp, 0x13, 0x804f); 3653 rtl_writephy(tp, 0x13, 0x804f);
3654 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000); 3654 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3655 rtl_writephy(tp, 0x13, 0x8057); 3655 rtl_writephy(tp, 0x13, 0x8057);
3656 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000); 3656 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3657 rtl_writephy(tp, 0x13, 0x805f); 3657 rtl_writephy(tp, 0x13, 0x805f);
3658 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000); 3658 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3659 rtl_writephy(tp, 0x13, 0x8067); 3659 rtl_writephy(tp, 0x13, 0x8067);
3660 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000); 3660 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3661 rtl_writephy(tp, 0x13, 0x806f); 3661 rtl_writephy(tp, 0x13, 0x806f);
3662 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000); 3662 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3663 rtl_writephy(tp, 0x1f, 0x0000); 3663 rtl_writephy(tp, 0x1f, 0x0000);
3664 3664
3665 /* disable phy pfm mode */ 3665 /* disable phy pfm mode */
3666 rtl_writephy(tp, 0x1f, 0x0a44); 3666 rtl_writephy(tp, 0x1f, 0x0a44);
3667 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x0080); 3667 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080);
3668 rtl_writephy(tp, 0x1f, 0x0000); 3668 rtl_writephy(tp, 0x1f, 0x0000);
3669 3669
3670 /* Check ALDPS bit, disable it if enabled */ 3670 /* Check ALDPS bit, disable it if enabled */
3671 rtl_writephy(tp, 0x1f, 0x0a43); 3671 rtl_writephy(tp, 0x1f, 0x0a43);
3672 if (rtl_readphy(tp, 0x10) & 0x0004) 3672 if (rtl_readphy(tp, 0x10) & 0x0004)
3673 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0004); 3673 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3674 3674
3675 rtl_writephy(tp, 0x1f, 0x0000); 3675 rtl_writephy(tp, 0x1f, 0x0000);
3676} 3676}
@@ -3686,20 +3686,20 @@ static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3686 /* CHIN EST parameter update */ 3686 /* CHIN EST parameter update */
3687 rtl_writephy(tp, 0x1f, 0x0a43); 3687 rtl_writephy(tp, 0x1f, 0x0a43);
3688 rtl_writephy(tp, 0x13, 0x808a); 3688 rtl_writephy(tp, 0x13, 0x808a);
3689 rtl_w1w0_phy(tp, 0x14, 0x000a, 0x003f); 3689 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3690 rtl_writephy(tp, 0x1f, 0x0000); 3690 rtl_writephy(tp, 0x1f, 0x0000);
3691 3691
3692 /* enable R-tune & PGA-retune function */ 3692 /* enable R-tune & PGA-retune function */
3693 rtl_writephy(tp, 0x1f, 0x0a43); 3693 rtl_writephy(tp, 0x1f, 0x0a43);
3694 rtl_writephy(tp, 0x13, 0x0811); 3694 rtl_writephy(tp, 0x13, 0x0811);
3695 rtl_w1w0_phy(tp, 0x14, 0x0800, 0x0000); 3695 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3696 rtl_writephy(tp, 0x1f, 0x0a42); 3696 rtl_writephy(tp, 0x1f, 0x0a42);
3697 rtl_w1w0_phy(tp, 0x16, 0x0002, 0x0000); 3697 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3698 rtl_writephy(tp, 0x1f, 0x0000); 3698 rtl_writephy(tp, 0x1f, 0x0000);
3699 3699
3700 /* enable GPHY 10M */ 3700 /* enable GPHY 10M */
3701 rtl_writephy(tp, 0x1f, 0x0a44); 3701 rtl_writephy(tp, 0x1f, 0x0a44);
3702 rtl_w1w0_phy(tp, 0x11, 0x0800, 0x0000); 3702 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3703 rtl_writephy(tp, 0x1f, 0x0000); 3703 rtl_writephy(tp, 0x1f, 0x0000);
3704 3704
3705 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 3705 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
@@ -3737,13 +3737,13 @@ static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3737 3737
3738 /* disable phy pfm mode */ 3738 /* disable phy pfm mode */
3739 rtl_writephy(tp, 0x1f, 0x0a44); 3739 rtl_writephy(tp, 0x1f, 0x0a44);
3740 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x0080); 3740 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080);
3741 rtl_writephy(tp, 0x1f, 0x0000); 3741 rtl_writephy(tp, 0x1f, 0x0000);
3742 3742
3743 /* Check ALDPS bit, disable it if enabled */ 3743 /* Check ALDPS bit, disable it if enabled */
3744 rtl_writephy(tp, 0x1f, 0x0a43); 3744 rtl_writephy(tp, 0x1f, 0x0a43);
3745 if (rtl_readphy(tp, 0x10) & 0x0004) 3745 if (rtl_readphy(tp, 0x10) & 0x0004)
3746 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0004); 3746 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3747 3747
3748 rtl_writephy(tp, 0x1f, 0x0000); 3748 rtl_writephy(tp, 0x1f, 0x0000);
3749} 3749}