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authorChun-Hao Lin <hau@realtek.com>2014-12-02 03:48:31 -0500
committerDavid S. Miller <davem@davemloft.net>2014-12-08 20:43:26 -0500
commit003609da5e270a2f5db6c3b00b82e3c342201f34 (patch)
tree096b4f0fd582e28650ba426a12e88eb0937245ca /drivers/net/ethernet/realtek/r8169.c
parentd6e572911a4cb2b9fcd1c26a38d5317a3971f2fd (diff)
r8169:disable rtl8168ep cmac engine
Cmac engine is the bridge between driver and dash firmware. Other os may not disable cmac when leave. And r8169 did not allocate any resources for cmac engine. Disable it to prevent abnormal system behavior. Signed-off-by: Chunhao Lin <hau@realtek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/realtek/r8169.c')
-rw-r--r--drivers/net/ethernet/realtek/r8169.c30
1 files changed, 22 insertions, 8 deletions
diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
index 7f4515f5a82c..56280c1fc0ed 100644
--- a/drivers/net/ethernet/realtek/r8169.c
+++ b/drivers/net/ethernet/realtek/r8169.c
@@ -1377,6 +1377,16 @@ DECLARE_RTL_COND(rtl_ocp_tx_cond)
1377 return RTL_R8(IBISR0) & 0x02; 1377 return RTL_R8(IBISR0) & 0x02;
1378} 1378}
1379 1379
1380static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1381{
1382 void __iomem *ioaddr = tp->mmio_addr;
1383
1384 RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
1385 rtl_msleep_loop_wait_low(tp, &rtl_ocp_tx_cond, 50, 2000);
1386 RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1387 RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1388}
1389
1380static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1390static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1381{ 1391{
1382 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START); 1392 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
@@ -1417,12 +1427,7 @@ static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1417 1427
1418static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1428static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1419{ 1429{
1420 void __iomem *ioaddr = tp->mmio_addr; 1430 rtl8168ep_stop_cmac(tp);
1421
1422 RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
1423 rtl_msleep_loop_wait_low(tp, &rtl_ocp_tx_cond, 50, 2000);
1424 RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1425 RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1426 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1431 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1427 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01); 1432 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1428 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10); 1433 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
@@ -6089,6 +6094,8 @@ static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6089 void __iomem *ioaddr = tp->mmio_addr; 6094 void __iomem *ioaddr = tp->mmio_addr;
6090 struct pci_dev *pdev = tp->pci_dev; 6095 struct pci_dev *pdev = tp->pci_dev;
6091 6096
6097 rtl8168ep_stop_cmac(tp);
6098
6092 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); 6099 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6093 6100
6094 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC); 6101 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
@@ -8002,6 +8009,12 @@ static void rtl_hw_init_8168g(struct rtl8169_private *tp)
8002 return; 8009 return;
8003} 8010}
8004 8011
8012static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
8013{
8014 rtl8168ep_stop_cmac(tp);
8015 rtl_hw_init_8168g(tp);
8016}
8017
8005static void rtl_hw_initialize(struct rtl8169_private *tp) 8018static void rtl_hw_initialize(struct rtl8169_private *tp)
8006{ 8019{
8007 switch (tp->mac_version) { 8020 switch (tp->mac_version) {
@@ -8014,12 +8027,13 @@ static void rtl_hw_initialize(struct rtl8169_private *tp)
8014 case RTL_GIGA_MAC_VER_46: 8027 case RTL_GIGA_MAC_VER_46:
8015 case RTL_GIGA_MAC_VER_47: 8028 case RTL_GIGA_MAC_VER_47:
8016 case RTL_GIGA_MAC_VER_48: 8029 case RTL_GIGA_MAC_VER_48:
8030 rtl_hw_init_8168g(tp);
8031 break;
8017 case RTL_GIGA_MAC_VER_49: 8032 case RTL_GIGA_MAC_VER_49:
8018 case RTL_GIGA_MAC_VER_50: 8033 case RTL_GIGA_MAC_VER_50:
8019 case RTL_GIGA_MAC_VER_51: 8034 case RTL_GIGA_MAC_VER_51:
8020 rtl_hw_init_8168g(tp); 8035 rtl_hw_init_8168ep(tp);
8021 break; 8036 break;
8022
8023 default: 8037 default:
8024 break; 8038 break;
8025 } 8039 }