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authorSony Chacko <sony.chacko@qlogic.com>2012-11-27 23:34:30 -0500
committerDavid S. Miller <davem@davemloft.net>2012-11-28 11:07:44 -0500
commit58634e74e66dd14407176d8620c76bae299ddb02 (patch)
treea9d9966c4a9b8a94ec1cdfa2784ecfc882221f66 /drivers/net/ethernet/qlogic/qlcnic
parentb66e29c9fda1b7288ec2504a6bc730654bff12b2 (diff)
qlcnic: create file qlcnic_minidump.c for dump utility
Physical refactoring of 82xx adapter register dump utility. Move register dump routines to new file qlcnic_minidump.c Existing register dump routines has coding style issues, the code is moved to the new file without fixing the style issues. There is a seperate patch to fix the style issues in qlcnic_minidump.c Signed-off-by: Sony Chacko <sony.chacko@qlogic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/qlogic/qlcnic')
-rw-r--r--drivers/net/ethernet/qlogic/qlcnic/Makefile2
-rw-r--r--drivers/net/ethernet/qlogic/qlcnic/qlcnic.h143
-rw-r--r--drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c486
-rw-r--r--drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c629
4 files changed, 632 insertions, 628 deletions
diff --git a/drivers/net/ethernet/qlogic/qlcnic/Makefile b/drivers/net/ethernet/qlogic/qlcnic/Makefile
index 34db05366c17..c4b8ced83829 100644
--- a/drivers/net/ethernet/qlogic/qlcnic/Makefile
+++ b/drivers/net/ethernet/qlogic/qlcnic/Makefile
@@ -6,4 +6,4 @@ obj-$(CONFIG_QLCNIC) := qlcnic.o
6 6
7qlcnic-y := qlcnic_hw.o qlcnic_main.o qlcnic_init.o \ 7qlcnic-y := qlcnic_hw.o qlcnic_main.o qlcnic_init.o \
8 qlcnic_ethtool.o qlcnic_ctx.o qlcnic_io.o \ 8 qlcnic_ethtool.o qlcnic_ctx.o qlcnic_io.o \
9 qlcnic_sysfs.o 9 qlcnic_sysfs.o qlcnic_minidump.o
diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic.h b/drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
index 618e5ec5506c..082eecbf4148 100644
--- a/drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
+++ b/drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
@@ -1255,142 +1255,7 @@ struct qlcnic_esw_statistics {
1255 struct __qlcnic_esw_statistics tx; 1255 struct __qlcnic_esw_statistics tx;
1256}; 1256};
1257 1257
1258struct qlcnic_common_entry_hdr {
1259 u32 type;
1260 u32 offset;
1261 u32 cap_size;
1262 u8 mask;
1263 u8 rsvd[2];
1264 u8 flags;
1265} __packed;
1266
1267struct __crb {
1268 u32 addr;
1269 u8 stride;
1270 u8 rsvd1[3];
1271 u32 data_size;
1272 u32 no_ops;
1273 u32 rsvd2[4];
1274} __packed;
1275
1276struct __ctrl {
1277 u32 addr;
1278 u8 stride;
1279 u8 index_a;
1280 u16 timeout;
1281 u32 data_size;
1282 u32 no_ops;
1283 u8 opcode;
1284 u8 index_v;
1285 u8 shl_val;
1286 u8 shr_val;
1287 u32 val1;
1288 u32 val2;
1289 u32 val3;
1290} __packed;
1291
1292struct __cache {
1293 u32 addr;
1294 u16 stride;
1295 u16 init_tag_val;
1296 u32 size;
1297 u32 no_ops;
1298 u32 ctrl_addr;
1299 u32 ctrl_val;
1300 u32 read_addr;
1301 u8 read_addr_stride;
1302 u8 read_addr_num;
1303 u8 rsvd1[2];
1304} __packed;
1305
1306struct __ocm {
1307 u8 rsvd[8];
1308 u32 size;
1309 u32 no_ops;
1310 u8 rsvd1[8];
1311 u32 read_addr;
1312 u32 read_addr_stride;
1313} __packed;
1314
1315struct __mem {
1316 u8 rsvd[24];
1317 u32 addr;
1318 u32 size;
1319} __packed;
1320
1321struct __mux {
1322 u32 addr;
1323 u8 rsvd[4];
1324 u32 size;
1325 u32 no_ops;
1326 u32 val;
1327 u32 val_stride;
1328 u32 read_addr;
1329 u8 rsvd2[4];
1330} __packed;
1331
1332struct __queue {
1333 u32 sel_addr;
1334 u16 stride;
1335 u8 rsvd[2];
1336 u32 size;
1337 u32 no_ops;
1338 u8 rsvd2[8];
1339 u32 read_addr;
1340 u8 read_addr_stride;
1341 u8 read_addr_cnt;
1342 u8 rsvd3[2];
1343} __packed;
1344
1345struct qlcnic_dump_entry {
1346 struct qlcnic_common_entry_hdr hdr;
1347 union {
1348 struct __crb crb;
1349 struct __cache cache;
1350 struct __ocm ocm;
1351 struct __mem mem;
1352 struct __mux mux;
1353 struct __queue que;
1354 struct __ctrl ctrl;
1355 } region;
1356} __packed;
1357
1358enum op_codes {
1359 QLCNIC_DUMP_NOP = 0,
1360 QLCNIC_DUMP_READ_CRB = 1,
1361 QLCNIC_DUMP_READ_MUX = 2,
1362 QLCNIC_DUMP_QUEUE = 3,
1363 QLCNIC_DUMP_BRD_CONFIG = 4,
1364 QLCNIC_DUMP_READ_OCM = 6,
1365 QLCNIC_DUMP_PEG_REG = 7,
1366 QLCNIC_DUMP_L1_DTAG = 8,
1367 QLCNIC_DUMP_L1_ITAG = 9,
1368 QLCNIC_DUMP_L1_DATA = 11,
1369 QLCNIC_DUMP_L1_INST = 12,
1370 QLCNIC_DUMP_L2_DTAG = 21,
1371 QLCNIC_DUMP_L2_ITAG = 22,
1372 QLCNIC_DUMP_L2_DATA = 23,
1373 QLCNIC_DUMP_L2_INST = 24,
1374 QLCNIC_DUMP_READ_ROM = 71,
1375 QLCNIC_DUMP_READ_MEM = 72,
1376 QLCNIC_DUMP_READ_CTRL = 98,
1377 QLCNIC_DUMP_TLHDR = 99,
1378 QLCNIC_DUMP_RDEND = 255
1379};
1380
1381#define QLCNIC_DUMP_WCRB BIT_0
1382#define QLCNIC_DUMP_RWCRB BIT_1
1383#define QLCNIC_DUMP_ANDCRB BIT_2
1384#define QLCNIC_DUMP_ORCRB BIT_3
1385#define QLCNIC_DUMP_POLLCRB BIT_4
1386#define QLCNIC_DUMP_RD_SAVE BIT_5
1387#define QLCNIC_DUMP_WRT_SAVED BIT_6
1388#define QLCNIC_DUMP_MOD_SAVE_ST BIT_7
1389#define QLCNIC_DUMP_SKIP BIT_7
1390
1391#define QLCNIC_DUMP_MASK_MIN 3
1392#define QLCNIC_DUMP_MASK_DEF 0x1f 1258#define QLCNIC_DUMP_MASK_DEF 0x1f
1393#define QLCNIC_DUMP_MASK_MAX 0xff
1394#define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed 1259#define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed
1395#define QLCNIC_ENABLE_FW_DUMP 0xaddfeed 1260#define QLCNIC_ENABLE_FW_DUMP 0xaddfeed
1396#define QLCNIC_DISABLE_FW_DUMP 0xbadfeed 1261#define QLCNIC_DISABLE_FW_DUMP 0xbadfeed
@@ -1398,12 +1263,6 @@ enum op_codes {
1398#define QLCNIC_SET_QUIESCENT 0xadd00010 1263#define QLCNIC_SET_QUIESCENT 0xadd00010
1399#define QLCNIC_RESET_QUIESCENT 0xadd00020 1264#define QLCNIC_RESET_QUIESCENT 0xadd00020
1400 1265
1401struct qlcnic_dump_operations {
1402 enum op_codes opcode;
1403 u32 (*handler)(struct qlcnic_adapter *, struct qlcnic_dump_entry *,
1404 __le32 *);
1405};
1406
1407struct _cdrp_cmd { 1266struct _cdrp_cmd {
1408 u32 cmd; 1267 u32 cmd;
1409 u32 arg1; 1268 u32 arg1;
@@ -1461,6 +1320,8 @@ void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1461#define __QLCNIC_MAX_LED_RATE 0xf 1320#define __QLCNIC_MAX_LED_RATE 0xf
1462#define __QLCNIC_MAX_LED_STATE 0x2 1321#define __QLCNIC_MAX_LED_STATE 0x2
1463 1322
1323#define MAX_CTL_CHECK 1000
1324
1464int qlcnic_get_board_info(struct qlcnic_adapter *adapter); 1325int qlcnic_get_board_info(struct qlcnic_adapter *adapter);
1465int qlcnic_wol_supported(struct qlcnic_adapter *adapter); 1326int qlcnic_wol_supported(struct qlcnic_adapter *adapter);
1466int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate); 1327int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate);
diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c
index aeacf1deea47..ff879cd2925b 100644
--- a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c
+++ b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c
@@ -266,33 +266,6 @@ static const unsigned crb_hub_agt[64] = {
266 0, 266 0,
267}; 267};
268 268
269static void qlcnic_read_dump_reg(u32 addr, void __iomem *bar0, u32 *data)
270{
271 u32 dest;
272 void __iomem *window_reg;
273
274 dest = addr & 0xFFFF0000;
275 window_reg = bar0 + QLCNIC_FW_DUMP_REG1;
276 writel(dest, window_reg);
277 readl(window_reg);
278 window_reg = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
279 *data = readl(window_reg);
280}
281
282static void qlcnic_write_dump_reg(u32 addr, void __iomem *bar0, u32 data)
283{
284 u32 dest;
285 void __iomem *window_reg;
286
287 dest = addr & 0xFFFF0000;
288 window_reg = bar0 + QLCNIC_FW_DUMP_REG1;
289 writel(dest, window_reg);
290 readl(window_reg);
291 window_reg = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
292 writel(data, window_reg);
293 readl(window_reg);
294}
295
296/* PCI Windowing for DDR regions. */ 269/* PCI Windowing for DDR regions. */
297 270
298#define QLCNIC_PCIE_SEM_TIMEOUT 10000 271#define QLCNIC_PCIE_SEM_TIMEOUT 10000
@@ -1088,8 +1061,6 @@ qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
1088 mutex_unlock(&adapter->ahw->mem_lock); 1061 mutex_unlock(&adapter->ahw->mem_lock);
1089} 1062}
1090 1063
1091#define MAX_CTL_CHECK 1000
1092
1093int 1064int
1094qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter, 1065qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter,
1095 u64 off, u64 data) 1066 u64 off, u64 data)
@@ -1347,460 +1318,3 @@ int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
1347 1318
1348 return rv; 1319 return rv;
1349} 1320}
1350
1351/* FW dump related functions */
1352static u32 qlcnic_dump_crb(struct qlcnic_adapter *adapter,
1353 struct qlcnic_dump_entry *entry, __le32 *buffer)
1354{
1355 int i;
1356 u32 addr, data;
1357 struct __crb *crb = &entry->region.crb;
1358 void __iomem *base = adapter->ahw->pci_base0;
1359
1360 addr = crb->addr;
1361
1362 for (i = 0; i < crb->no_ops; i++) {
1363 qlcnic_read_dump_reg(addr, base, &data);
1364 *buffer++ = cpu_to_le32(addr);
1365 *buffer++ = cpu_to_le32(data);
1366 addr += crb->stride;
1367 }
1368 return crb->no_ops * 2 * sizeof(u32);
1369}
1370
1371static u32 qlcnic_dump_ctrl(struct qlcnic_adapter *adapter,
1372 struct qlcnic_dump_entry *entry, __le32 *buffer)
1373{
1374 int i, k, timeout = 0;
1375 void __iomem *base = adapter->ahw->pci_base0;
1376 u32 addr, data;
1377 u8 opcode, no_ops;
1378 struct __ctrl *ctr = &entry->region.ctrl;
1379 struct qlcnic_dump_template_hdr *t_hdr = adapter->ahw->fw_dump.tmpl_hdr;
1380
1381 addr = ctr->addr;
1382 no_ops = ctr->no_ops;
1383
1384 for (i = 0; i < no_ops; i++) {
1385 k = 0;
1386 opcode = 0;
1387 for (k = 0; k < 8; k++) {
1388 if (!(ctr->opcode & (1 << k)))
1389 continue;
1390 switch (1 << k) {
1391 case QLCNIC_DUMP_WCRB:
1392 qlcnic_write_dump_reg(addr, base, ctr->val1);
1393 break;
1394 case QLCNIC_DUMP_RWCRB:
1395 qlcnic_read_dump_reg(addr, base, &data);
1396 qlcnic_write_dump_reg(addr, base, data);
1397 break;
1398 case QLCNIC_DUMP_ANDCRB:
1399 qlcnic_read_dump_reg(addr, base, &data);
1400 qlcnic_write_dump_reg(addr, base,
1401 data & ctr->val2);
1402 break;
1403 case QLCNIC_DUMP_ORCRB:
1404 qlcnic_read_dump_reg(addr, base, &data);
1405 qlcnic_write_dump_reg(addr, base,
1406 data | ctr->val3);
1407 break;
1408 case QLCNIC_DUMP_POLLCRB:
1409 while (timeout <= ctr->timeout) {
1410 qlcnic_read_dump_reg(addr, base, &data);
1411 if ((data & ctr->val2) == ctr->val1)
1412 break;
1413 msleep(1);
1414 timeout++;
1415 }
1416 if (timeout > ctr->timeout) {
1417 dev_info(&adapter->pdev->dev,
1418 "Timed out, aborting poll CRB\n");
1419 return -EINVAL;
1420 }
1421 break;
1422 case QLCNIC_DUMP_RD_SAVE:
1423 if (ctr->index_a)
1424 addr = t_hdr->saved_state[ctr->index_a];
1425 qlcnic_read_dump_reg(addr, base, &data);
1426 t_hdr->saved_state[ctr->index_v] = data;
1427 break;
1428 case QLCNIC_DUMP_WRT_SAVED:
1429 if (ctr->index_v)
1430 data = t_hdr->saved_state[ctr->index_v];
1431 else
1432 data = ctr->val1;
1433 if (ctr->index_a)
1434 addr = t_hdr->saved_state[ctr->index_a];
1435 qlcnic_write_dump_reg(addr, base, data);
1436 break;
1437 case QLCNIC_DUMP_MOD_SAVE_ST:
1438 data = t_hdr->saved_state[ctr->index_v];
1439 data <<= ctr->shl_val;
1440 data >>= ctr->shr_val;
1441 if (ctr->val2)
1442 data &= ctr->val2;
1443 data |= ctr->val3;
1444 data += ctr->val1;
1445 t_hdr->saved_state[ctr->index_v] = data;
1446 break;
1447 default:
1448 dev_info(&adapter->pdev->dev,
1449 "Unknown opcode\n");
1450 break;
1451 }
1452 }
1453 addr += ctr->stride;
1454 }
1455 return 0;
1456}
1457
1458static u32 qlcnic_dump_mux(struct qlcnic_adapter *adapter,
1459 struct qlcnic_dump_entry *entry, __le32 *buffer)
1460{
1461 int loop;
1462 u32 val, data = 0;
1463 struct __mux *mux = &entry->region.mux;
1464 void __iomem *base = adapter->ahw->pci_base0;
1465
1466 val = mux->val;
1467 for (loop = 0; loop < mux->no_ops; loop++) {
1468 qlcnic_write_dump_reg(mux->addr, base, val);
1469 qlcnic_read_dump_reg(mux->read_addr, base, &data);
1470 *buffer++ = cpu_to_le32(val);
1471 *buffer++ = cpu_to_le32(data);
1472 val += mux->val_stride;
1473 }
1474 return 2 * mux->no_ops * sizeof(u32);
1475}
1476
1477static u32 qlcnic_dump_que(struct qlcnic_adapter *adapter,
1478 struct qlcnic_dump_entry *entry, __le32 *buffer)
1479{
1480 int i, loop;
1481 u32 cnt, addr, data, que_id = 0;
1482 void __iomem *base = adapter->ahw->pci_base0;
1483 struct __queue *que = &entry->region.que;
1484
1485 addr = que->read_addr;
1486 cnt = que->read_addr_cnt;
1487
1488 for (loop = 0; loop < que->no_ops; loop++) {
1489 qlcnic_write_dump_reg(que->sel_addr, base, que_id);
1490 addr = que->read_addr;
1491 for (i = 0; i < cnt; i++) {
1492 qlcnic_read_dump_reg(addr, base, &data);
1493 *buffer++ = cpu_to_le32(data);
1494 addr += que->read_addr_stride;
1495 }
1496 que_id += que->stride;
1497 }
1498 return que->no_ops * cnt * sizeof(u32);
1499}
1500
1501static u32 qlcnic_dump_ocm(struct qlcnic_adapter *adapter,
1502 struct qlcnic_dump_entry *entry, __le32 *buffer)
1503{
1504 int i;
1505 u32 data;
1506 void __iomem *addr;
1507 struct __ocm *ocm = &entry->region.ocm;
1508
1509 addr = adapter->ahw->pci_base0 + ocm->read_addr;
1510 for (i = 0; i < ocm->no_ops; i++) {
1511 data = readl(addr);
1512 *buffer++ = cpu_to_le32(data);
1513 addr += ocm->read_addr_stride;
1514 }
1515 return ocm->no_ops * sizeof(u32);
1516}
1517
1518static u32 qlcnic_read_rom(struct qlcnic_adapter *adapter,
1519 struct qlcnic_dump_entry *entry, __le32 *buffer)
1520{
1521 int i, count = 0;
1522 u32 fl_addr, size, val, lck_val, addr;
1523 struct __mem *rom = &entry->region.mem;
1524 void __iomem *base = adapter->ahw->pci_base0;
1525
1526 fl_addr = rom->addr;
1527 size = rom->size/4;
1528lock_try:
1529 lck_val = readl(base + QLCNIC_FLASH_SEM2_LK);
1530 if (!lck_val && count < MAX_CTL_CHECK) {
1531 msleep(10);
1532 count++;
1533 goto lock_try;
1534 }
1535 writel(adapter->ahw->pci_func, (base + QLCNIC_FLASH_LOCK_ID));
1536 for (i = 0; i < size; i++) {
1537 addr = fl_addr & 0xFFFF0000;
1538 qlcnic_write_dump_reg(FLASH_ROM_WINDOW, base, addr);
1539 addr = LSW(fl_addr) + FLASH_ROM_DATA;
1540 qlcnic_read_dump_reg(addr, base, &val);
1541 fl_addr += 4;
1542 *buffer++ = cpu_to_le32(val);
1543 }
1544 readl(base + QLCNIC_FLASH_SEM2_ULK);
1545 return rom->size;
1546}
1547
1548static u32 qlcnic_dump_l1_cache(struct qlcnic_adapter *adapter,
1549 struct qlcnic_dump_entry *entry, __le32 *buffer)
1550{
1551 int i;
1552 u32 cnt, val, data, addr;
1553 void __iomem *base = adapter->ahw->pci_base0;
1554 struct __cache *l1 = &entry->region.cache;
1555
1556 val = l1->init_tag_val;
1557
1558 for (i = 0; i < l1->no_ops; i++) {
1559 qlcnic_write_dump_reg(l1->addr, base, val);
1560 qlcnic_write_dump_reg(l1->ctrl_addr, base, LSW(l1->ctrl_val));
1561 addr = l1->read_addr;
1562 cnt = l1->read_addr_num;
1563 while (cnt) {
1564 qlcnic_read_dump_reg(addr, base, &data);
1565 *buffer++ = cpu_to_le32(data);
1566 addr += l1->read_addr_stride;
1567 cnt--;
1568 }
1569 val += l1->stride;
1570 }
1571 return l1->no_ops * l1->read_addr_num * sizeof(u32);
1572}
1573
1574static u32 qlcnic_dump_l2_cache(struct qlcnic_adapter *adapter,
1575 struct qlcnic_dump_entry *entry, __le32 *buffer)
1576{
1577 int i;
1578 u32 cnt, val, data, addr;
1579 u8 poll_mask, poll_to, time_out = 0;
1580 void __iomem *base = adapter->ahw->pci_base0;
1581 struct __cache *l2 = &entry->region.cache;
1582
1583 val = l2->init_tag_val;
1584 poll_mask = LSB(MSW(l2->ctrl_val));
1585 poll_to = MSB(MSW(l2->ctrl_val));
1586
1587 for (i = 0; i < l2->no_ops; i++) {
1588 qlcnic_write_dump_reg(l2->addr, base, val);
1589 if (LSW(l2->ctrl_val))
1590 qlcnic_write_dump_reg(l2->ctrl_addr, base,
1591 LSW(l2->ctrl_val));
1592 if (!poll_mask)
1593 goto skip_poll;
1594 do {
1595 qlcnic_read_dump_reg(l2->ctrl_addr, base, &data);
1596 if (!(data & poll_mask))
1597 break;
1598 msleep(1);
1599 time_out++;
1600 } while (time_out <= poll_to);
1601
1602 if (time_out > poll_to) {
1603 dev_err(&adapter->pdev->dev,
1604 "Timeout exceeded in %s, aborting dump\n",
1605 __func__);
1606 return -EINVAL;
1607 }
1608skip_poll:
1609 addr = l2->read_addr;
1610 cnt = l2->read_addr_num;
1611 while (cnt) {
1612 qlcnic_read_dump_reg(addr, base, &data);
1613 *buffer++ = cpu_to_le32(data);
1614 addr += l2->read_addr_stride;
1615 cnt--;
1616 }
1617 val += l2->stride;
1618 }
1619 return l2->no_ops * l2->read_addr_num * sizeof(u32);
1620}
1621
1622static u32 qlcnic_read_memory(struct qlcnic_adapter *adapter,
1623 struct qlcnic_dump_entry *entry, __le32 *buffer)
1624{
1625 u32 addr, data, test, ret = 0;
1626 int i, reg_read;
1627 struct __mem *mem = &entry->region.mem;
1628 void __iomem *base = adapter->ahw->pci_base0;
1629
1630 reg_read = mem->size;
1631 addr = mem->addr;
1632 /* check for data size of multiple of 16 and 16 byte alignment */
1633 if ((addr & 0xf) || (reg_read%16)) {
1634 dev_info(&adapter->pdev->dev,
1635 "Unaligned memory addr:0x%x size:0x%x\n",
1636 addr, reg_read);
1637 return -EINVAL;
1638 }
1639
1640 mutex_lock(&adapter->ahw->mem_lock);
1641
1642 while (reg_read != 0) {
1643 qlcnic_write_dump_reg(MIU_TEST_ADDR_LO, base, addr);
1644 qlcnic_write_dump_reg(MIU_TEST_ADDR_HI, base, 0);
1645 qlcnic_write_dump_reg(MIU_TEST_CTR, base,
1646 TA_CTL_ENABLE | TA_CTL_START);
1647
1648 for (i = 0; i < MAX_CTL_CHECK; i++) {
1649 qlcnic_read_dump_reg(MIU_TEST_CTR, base, &test);
1650 if (!(test & TA_CTL_BUSY))
1651 break;
1652 }
1653 if (i == MAX_CTL_CHECK) {
1654 if (printk_ratelimit()) {
1655 dev_err(&adapter->pdev->dev,
1656 "failed to read through agent\n");
1657 ret = -EINVAL;
1658 goto out;
1659 }
1660 }
1661 for (i = 0; i < 4; i++) {
1662 qlcnic_read_dump_reg(MIU_TEST_READ_DATA[i], base,
1663 &data);
1664 *buffer++ = cpu_to_le32(data);
1665 }
1666 addr += 16;
1667 reg_read -= 16;
1668 ret += 16;
1669 }
1670out:
1671 mutex_unlock(&adapter->ahw->mem_lock);
1672 return mem->size;
1673}
1674
1675static u32 qlcnic_dump_nop(struct qlcnic_adapter *adapter,
1676 struct qlcnic_dump_entry *entry, __le32 *buffer)
1677{
1678 entry->hdr.flags |= QLCNIC_DUMP_SKIP;
1679 return 0;
1680}
1681
1682static const struct qlcnic_dump_operations fw_dump_ops[] = {
1683 { QLCNIC_DUMP_NOP, qlcnic_dump_nop },
1684 { QLCNIC_DUMP_READ_CRB, qlcnic_dump_crb },
1685 { QLCNIC_DUMP_READ_MUX, qlcnic_dump_mux },
1686 { QLCNIC_DUMP_QUEUE, qlcnic_dump_que },
1687 { QLCNIC_DUMP_BRD_CONFIG, qlcnic_read_rom },
1688 { QLCNIC_DUMP_READ_OCM, qlcnic_dump_ocm },
1689 { QLCNIC_DUMP_PEG_REG, qlcnic_dump_ctrl },
1690 { QLCNIC_DUMP_L1_DTAG, qlcnic_dump_l1_cache },
1691 { QLCNIC_DUMP_L1_ITAG, qlcnic_dump_l1_cache },
1692 { QLCNIC_DUMP_L1_DATA, qlcnic_dump_l1_cache },
1693 { QLCNIC_DUMP_L1_INST, qlcnic_dump_l1_cache },
1694 { QLCNIC_DUMP_L2_DTAG, qlcnic_dump_l2_cache },
1695 { QLCNIC_DUMP_L2_ITAG, qlcnic_dump_l2_cache },
1696 { QLCNIC_DUMP_L2_DATA, qlcnic_dump_l2_cache },
1697 { QLCNIC_DUMP_L2_INST, qlcnic_dump_l2_cache },
1698 { QLCNIC_DUMP_READ_ROM, qlcnic_read_rom },
1699 { QLCNIC_DUMP_READ_MEM, qlcnic_read_memory },
1700 { QLCNIC_DUMP_READ_CTRL, qlcnic_dump_ctrl },
1701 { QLCNIC_DUMP_TLHDR, qlcnic_dump_nop },
1702 { QLCNIC_DUMP_RDEND, qlcnic_dump_nop },
1703};
1704
1705/* Walk the template and collect dump for each entry in the dump template */
1706static int
1707qlcnic_valid_dump_entry(struct device *dev, struct qlcnic_dump_entry *entry,
1708 u32 size)
1709{
1710 int ret = 1;
1711 if (size != entry->hdr.cap_size) {
1712 dev_info(dev,
1713 "Invalidate dump, Type:%d\tMask:%d\tSize:%dCap_size:%d\n",
1714 entry->hdr.type, entry->hdr.mask, size, entry->hdr.cap_size);
1715 dev_info(dev, "Aborting further dump capture\n");
1716 ret = 0;
1717 }
1718 return ret;
1719}
1720
1721int qlcnic_dump_fw(struct qlcnic_adapter *adapter)
1722{
1723 __le32 *buffer;
1724 char mesg[64];
1725 char *msg[] = {mesg, NULL};
1726 int i, k, ops_cnt, ops_index, dump_size = 0;
1727 u32 entry_offset, dump, no_entries, buf_offset = 0;
1728 struct qlcnic_dump_entry *entry;
1729 struct qlcnic_fw_dump *fw_dump = &adapter->ahw->fw_dump;
1730 struct qlcnic_dump_template_hdr *tmpl_hdr = fw_dump->tmpl_hdr;
1731
1732 if (fw_dump->clr) {
1733 dev_info(&adapter->pdev->dev,
1734 "Previous dump not cleared, not capturing dump\n");
1735 return -EIO;
1736 }
1737 /* Calculate the size for dump data area only */
1738 for (i = 2, k = 1; (i & QLCNIC_DUMP_MASK_MAX); i <<= 1, k++)
1739 if (i & tmpl_hdr->drv_cap_mask)
1740 dump_size += tmpl_hdr->cap_sizes[k];
1741 if (!dump_size)
1742 return -EIO;
1743
1744 fw_dump->data = vzalloc(dump_size);
1745 if (!fw_dump->data) {
1746 dev_info(&adapter->pdev->dev,
1747 "Unable to allocate (%d KB) for fw dump\n",
1748 dump_size/1024);
1749 return -ENOMEM;
1750 }
1751 buffer = fw_dump->data;
1752 fw_dump->size = dump_size;
1753 no_entries = tmpl_hdr->num_entries;
1754 ops_cnt = ARRAY_SIZE(fw_dump_ops);
1755 entry_offset = tmpl_hdr->offset;
1756 tmpl_hdr->sys_info[0] = QLCNIC_DRIVER_VERSION;
1757 tmpl_hdr->sys_info[1] = adapter->fw_version;
1758
1759 for (i = 0; i < no_entries; i++) {
1760 entry = (void *)tmpl_hdr + entry_offset;
1761 if (!(entry->hdr.mask & tmpl_hdr->drv_cap_mask)) {
1762 entry->hdr.flags |= QLCNIC_DUMP_SKIP;
1763 entry_offset += entry->hdr.offset;
1764 continue;
1765 }
1766 /* Find the handler for this entry */
1767 ops_index = 0;
1768 while (ops_index < ops_cnt) {
1769 if (entry->hdr.type == fw_dump_ops[ops_index].opcode)
1770 break;
1771 ops_index++;
1772 }
1773 if (ops_index == ops_cnt) {
1774 dev_info(&adapter->pdev->dev,
1775 "Invalid entry type %d, exiting dump\n",
1776 entry->hdr.type);
1777 goto error;
1778 }
1779 /* Collect dump for this entry */
1780 dump = fw_dump_ops[ops_index].handler(adapter, entry, buffer);
1781 if (dump && !qlcnic_valid_dump_entry(&adapter->pdev->dev, entry,
1782 dump))
1783 entry->hdr.flags |= QLCNIC_DUMP_SKIP;
1784 buf_offset += entry->hdr.cap_size;
1785 entry_offset += entry->hdr.offset;
1786 buffer = fw_dump->data + buf_offset;
1787 }
1788 if (dump_size != buf_offset) {
1789 dev_info(&adapter->pdev->dev,
1790 "Captured(%d) and expected size(%d) do not match\n",
1791 buf_offset, dump_size);
1792 goto error;
1793 } else {
1794 fw_dump->clr = 1;
1795 snprintf(mesg, sizeof(mesg), "FW_DUMP=%s",
1796 adapter->netdev->name);
1797 dev_info(&adapter->pdev->dev, "Dump data, %d bytes captured\n",
1798 fw_dump->size);
1799 /* Send a udev event to notify availability of FW dump */
1800 kobject_uevent_env(&adapter->pdev->dev.kobj, KOBJ_CHANGE, msg);
1801 return 0;
1802 }
1803error:
1804 vfree(fw_dump->data);
1805 return -EINVAL;
1806}
diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c
new file mode 100644
index 000000000000..5e22c62e895d
--- /dev/null
+++ b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c
@@ -0,0 +1,629 @@
1#include "qlcnic.h"
2#include "qlcnic_hdr.h"
3
4#include <net/ip.h>
5
6#define QLCNIC_DUMP_WCRB BIT_0
7#define QLCNIC_DUMP_RWCRB BIT_1
8#define QLCNIC_DUMP_ANDCRB BIT_2
9#define QLCNIC_DUMP_ORCRB BIT_3
10#define QLCNIC_DUMP_POLLCRB BIT_4
11#define QLCNIC_DUMP_RD_SAVE BIT_5
12#define QLCNIC_DUMP_WRT_SAVED BIT_6
13#define QLCNIC_DUMP_MOD_SAVE_ST BIT_7
14#define QLCNIC_DUMP_SKIP BIT_7
15
16#define QLCNIC_DUMP_MASK_MAX 0xff
17
18struct qlcnic_common_entry_hdr {
19 u32 type;
20 u32 offset;
21 u32 cap_size;
22 u8 mask;
23 u8 rsvd[2];
24 u8 flags;
25} __packed;
26
27struct __crb {
28 u32 addr;
29 u8 stride;
30 u8 rsvd1[3];
31 u32 data_size;
32 u32 no_ops;
33 u32 rsvd2[4];
34} __packed;
35
36struct __ctrl {
37 u32 addr;
38 u8 stride;
39 u8 index_a;
40 u16 timeout;
41 u32 data_size;
42 u32 no_ops;
43 u8 opcode;
44 u8 index_v;
45 u8 shl_val;
46 u8 shr_val;
47 u32 val1;
48 u32 val2;
49 u32 val3;
50} __packed;
51
52struct __cache {
53 u32 addr;
54 u16 stride;
55 u16 init_tag_val;
56 u32 size;
57 u32 no_ops;
58 u32 ctrl_addr;
59 u32 ctrl_val;
60 u32 read_addr;
61 u8 read_addr_stride;
62 u8 read_addr_num;
63 u8 rsvd1[2];
64} __packed;
65
66struct __ocm {
67 u8 rsvd[8];
68 u32 size;
69 u32 no_ops;
70 u8 rsvd1[8];
71 u32 read_addr;
72 u32 read_addr_stride;
73} __packed;
74
75struct __mem {
76 u8 rsvd[24];
77 u32 addr;
78 u32 size;
79} __packed;
80
81struct __mux {
82 u32 addr;
83 u8 rsvd[4];
84 u32 size;
85 u32 no_ops;
86 u32 val;
87 u32 val_stride;
88 u32 read_addr;
89 u8 rsvd2[4];
90} __packed;
91
92struct __queue {
93 u32 sel_addr;
94 u16 stride;
95 u8 rsvd[2];
96 u32 size;
97 u32 no_ops;
98 u8 rsvd2[8];
99 u32 read_addr;
100 u8 read_addr_stride;
101 u8 read_addr_cnt;
102 u8 rsvd3[2];
103} __packed;
104
105struct qlcnic_dump_entry {
106 struct qlcnic_common_entry_hdr hdr;
107 union {
108 struct __crb crb;
109 struct __cache cache;
110 struct __ocm ocm;
111 struct __mem mem;
112 struct __mux mux;
113 struct __queue que;
114 struct __ctrl ctrl;
115 } region;
116} __packed;
117
118enum op_codes {
119 QLCNIC_DUMP_NOP = 0,
120 QLCNIC_DUMP_READ_CRB = 1,
121 QLCNIC_DUMP_READ_MUX = 2,
122 QLCNIC_DUMP_QUEUE = 3,
123 QLCNIC_DUMP_BRD_CONFIG = 4,
124 QLCNIC_DUMP_READ_OCM = 6,
125 QLCNIC_DUMP_PEG_REG = 7,
126 QLCNIC_DUMP_L1_DTAG = 8,
127 QLCNIC_DUMP_L1_ITAG = 9,
128 QLCNIC_DUMP_L1_DATA = 11,
129 QLCNIC_DUMP_L1_INST = 12,
130 QLCNIC_DUMP_L2_DTAG = 21,
131 QLCNIC_DUMP_L2_ITAG = 22,
132 QLCNIC_DUMP_L2_DATA = 23,
133 QLCNIC_DUMP_L2_INST = 24,
134 QLCNIC_DUMP_READ_ROM = 71,
135 QLCNIC_DUMP_READ_MEM = 72,
136 QLCNIC_DUMP_READ_CTRL = 98,
137 QLCNIC_DUMP_TLHDR = 99,
138 QLCNIC_DUMP_RDEND = 255
139};
140
141struct qlcnic_dump_operations {
142 enum op_codes opcode;
143 u32 (*handler)(struct qlcnic_adapter *, struct qlcnic_dump_entry *,
144 __le32 *);
145};
146
147static void qlcnic_read_dump_reg(u32 addr, void __iomem *bar0, u32 *data)
148{
149 u32 dest;
150 void __iomem *window_reg;
151
152 dest = addr & 0xFFFF0000;
153 window_reg = bar0 + QLCNIC_FW_DUMP_REG1;
154 writel(dest, window_reg);
155 readl(window_reg);
156 window_reg = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
157 *data = readl(window_reg);
158}
159
160static void qlcnic_write_dump_reg(u32 addr, void __iomem *bar0, u32 data)
161{
162 u32 dest;
163 void __iomem *window_reg;
164
165 dest = addr & 0xFFFF0000;
166 window_reg = bar0 + QLCNIC_FW_DUMP_REG1;
167 writel(dest, window_reg);
168 readl(window_reg);
169 window_reg = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
170 writel(data, window_reg);
171 readl(window_reg);
172}
173
174/* FW dump related functions */
175static u32 qlcnic_dump_crb(struct qlcnic_adapter *adapter,
176 struct qlcnic_dump_entry *entry, __le32 *buffer)
177{
178 int i;
179 u32 addr, data;
180 struct __crb *crb = &entry->region.crb;
181 void __iomem *base = adapter->ahw->pci_base0;
182
183 addr = crb->addr;
184
185 for (i = 0; i < crb->no_ops; i++) {
186 qlcnic_read_dump_reg(addr, base, &data);
187 *buffer++ = cpu_to_le32(addr);
188 *buffer++ = cpu_to_le32(data);
189 addr += crb->stride;
190 }
191 return crb->no_ops * 2 * sizeof(u32);
192}
193
194static u32 qlcnic_dump_ctrl(struct qlcnic_adapter *adapter,
195 struct qlcnic_dump_entry *entry, __le32 *buffer)
196{
197 int i, k, timeout = 0;
198 void __iomem *base = adapter->ahw->pci_base0;
199 u32 addr, data;
200 u8 opcode, no_ops;
201 struct __ctrl *ctr = &entry->region.ctrl;
202 struct qlcnic_dump_template_hdr *t_hdr = adapter->ahw->fw_dump.tmpl_hdr;
203
204 addr = ctr->addr;
205 no_ops = ctr->no_ops;
206
207 for (i = 0; i < no_ops; i++) {
208 k = 0;
209 opcode = 0;
210 for (k = 0; k < 8; k++) {
211 if (!(ctr->opcode & (1 << k)))
212 continue;
213 switch (1 << k) {
214 case QLCNIC_DUMP_WCRB:
215 qlcnic_write_dump_reg(addr, base, ctr->val1);
216 break;
217 case QLCNIC_DUMP_RWCRB:
218 qlcnic_read_dump_reg(addr, base, &data);
219 qlcnic_write_dump_reg(addr, base, data);
220 break;
221 case QLCNIC_DUMP_ANDCRB:
222 qlcnic_read_dump_reg(addr, base, &data);
223 qlcnic_write_dump_reg(addr, base,
224 data & ctr->val2);
225 break;
226 case QLCNIC_DUMP_ORCRB:
227 qlcnic_read_dump_reg(addr, base, &data);
228 qlcnic_write_dump_reg(addr, base,
229 data | ctr->val3);
230 break;
231 case QLCNIC_DUMP_POLLCRB:
232 while (timeout <= ctr->timeout) {
233 qlcnic_read_dump_reg(addr, base, &data);
234 if ((data & ctr->val2) == ctr->val1)
235 break;
236 msleep(1);
237 timeout++;
238 }
239 if (timeout > ctr->timeout) {
240 dev_info(&adapter->pdev->dev,
241 "Timed out, aborting poll CRB\n");
242 return -EINVAL;
243 }
244 break;
245 case QLCNIC_DUMP_RD_SAVE:
246 if (ctr->index_a)
247 addr = t_hdr->saved_state[ctr->index_a];
248 qlcnic_read_dump_reg(addr, base, &data);
249 t_hdr->saved_state[ctr->index_v] = data;
250 break;
251 case QLCNIC_DUMP_WRT_SAVED:
252 if (ctr->index_v)
253 data = t_hdr->saved_state[ctr->index_v];
254 else
255 data = ctr->val1;
256 if (ctr->index_a)
257 addr = t_hdr->saved_state[ctr->index_a];
258 qlcnic_write_dump_reg(addr, base, data);
259 break;
260 case QLCNIC_DUMP_MOD_SAVE_ST:
261 data = t_hdr->saved_state[ctr->index_v];
262 data <<= ctr->shl_val;
263 data >>= ctr->shr_val;
264 if (ctr->val2)
265 data &= ctr->val2;
266 data |= ctr->val3;
267 data += ctr->val1;
268 t_hdr->saved_state[ctr->index_v] = data;
269 break;
270 default:
271 dev_info(&adapter->pdev->dev,
272 "Unknown opcode\n");
273 break;
274 }
275 }
276 addr += ctr->stride;
277 }
278 return 0;
279}
280
281static u32 qlcnic_dump_mux(struct qlcnic_adapter *adapter,
282 struct qlcnic_dump_entry *entry, __le32 *buffer)
283{
284 int loop;
285 u32 val, data = 0;
286 struct __mux *mux = &entry->region.mux;
287 void __iomem *base = adapter->ahw->pci_base0;
288
289 val = mux->val;
290 for (loop = 0; loop < mux->no_ops; loop++) {
291 qlcnic_write_dump_reg(mux->addr, base, val);
292 qlcnic_read_dump_reg(mux->read_addr, base, &data);
293 *buffer++ = cpu_to_le32(val);
294 *buffer++ = cpu_to_le32(data);
295 val += mux->val_stride;
296 }
297 return 2 * mux->no_ops * sizeof(u32);
298}
299
300static u32 qlcnic_dump_que(struct qlcnic_adapter *adapter,
301 struct qlcnic_dump_entry *entry, __le32 *buffer)
302{
303 int i, loop;
304 u32 cnt, addr, data, que_id = 0;
305 void __iomem *base = adapter->ahw->pci_base0;
306 struct __queue *que = &entry->region.que;
307
308 addr = que->read_addr;
309 cnt = que->read_addr_cnt;
310
311 for (loop = 0; loop < que->no_ops; loop++) {
312 qlcnic_write_dump_reg(que->sel_addr, base, que_id);
313 addr = que->read_addr;
314 for (i = 0; i < cnt; i++) {
315 qlcnic_read_dump_reg(addr, base, &data);
316 *buffer++ = cpu_to_le32(data);
317 addr += que->read_addr_stride;
318 }
319 que_id += que->stride;
320 }
321 return que->no_ops * cnt * sizeof(u32);
322}
323
324static u32 qlcnic_dump_ocm(struct qlcnic_adapter *adapter,
325 struct qlcnic_dump_entry *entry, __le32 *buffer)
326{
327 int i;
328 u32 data;
329 void __iomem *addr;
330 struct __ocm *ocm = &entry->region.ocm;
331
332 addr = adapter->ahw->pci_base0 + ocm->read_addr;
333 for (i = 0; i < ocm->no_ops; i++) {
334 data = readl(addr);
335 *buffer++ = cpu_to_le32(data);
336 addr += ocm->read_addr_stride;
337 }
338 return ocm->no_ops * sizeof(u32);
339}
340
341static u32 qlcnic_read_rom(struct qlcnic_adapter *adapter,
342 struct qlcnic_dump_entry *entry, __le32 *buffer)
343{
344 int i, count = 0;
345 u32 fl_addr, size, val, lck_val, addr;
346 struct __mem *rom = &entry->region.mem;
347 void __iomem *base = adapter->ahw->pci_base0;
348
349 fl_addr = rom->addr;
350 size = rom->size/4;
351lock_try:
352 lck_val = readl(base + QLCNIC_FLASH_SEM2_LK);
353 if (!lck_val && count < MAX_CTL_CHECK) {
354 msleep(10);
355 count++;
356 goto lock_try;
357 }
358 writel(adapter->ahw->pci_func, (base + QLCNIC_FLASH_LOCK_ID));
359 for (i = 0; i < size; i++) {
360 addr = fl_addr & 0xFFFF0000;
361 qlcnic_write_dump_reg(FLASH_ROM_WINDOW, base, addr);
362 addr = LSW(fl_addr) + FLASH_ROM_DATA;
363 qlcnic_read_dump_reg(addr, base, &val);
364 fl_addr += 4;
365 *buffer++ = cpu_to_le32(val);
366 }
367 readl(base + QLCNIC_FLASH_SEM2_ULK);
368 return rom->size;
369}
370
371static u32 qlcnic_dump_l1_cache(struct qlcnic_adapter *adapter,
372 struct qlcnic_dump_entry *entry, __le32 *buffer)
373{
374 int i;
375 u32 cnt, val, data, addr;
376 void __iomem *base = adapter->ahw->pci_base0;
377 struct __cache *l1 = &entry->region.cache;
378
379 val = l1->init_tag_val;
380
381 for (i = 0; i < l1->no_ops; i++) {
382 qlcnic_write_dump_reg(l1->addr, base, val);
383 qlcnic_write_dump_reg(l1->ctrl_addr, base, LSW(l1->ctrl_val));
384 addr = l1->read_addr;
385 cnt = l1->read_addr_num;
386 while (cnt) {
387 qlcnic_read_dump_reg(addr, base, &data);
388 *buffer++ = cpu_to_le32(data);
389 addr += l1->read_addr_stride;
390 cnt--;
391 }
392 val += l1->stride;
393 }
394 return l1->no_ops * l1->read_addr_num * sizeof(u32);
395}
396
397static u32 qlcnic_dump_l2_cache(struct qlcnic_adapter *adapter,
398 struct qlcnic_dump_entry *entry, __le32 *buffer)
399{
400 int i;
401 u32 cnt, val, data, addr;
402 u8 poll_mask, poll_to, time_out = 0;
403 void __iomem *base = adapter->ahw->pci_base0;
404 struct __cache *l2 = &entry->region.cache;
405
406 val = l2->init_tag_val;
407 poll_mask = LSB(MSW(l2->ctrl_val));
408 poll_to = MSB(MSW(l2->ctrl_val));
409
410 for (i = 0; i < l2->no_ops; i++) {
411 qlcnic_write_dump_reg(l2->addr, base, val);
412 if (LSW(l2->ctrl_val))
413 qlcnic_write_dump_reg(l2->ctrl_addr, base,
414 LSW(l2->ctrl_val));
415 if (!poll_mask)
416 goto skip_poll;
417 do {
418 qlcnic_read_dump_reg(l2->ctrl_addr, base, &data);
419 if (!(data & poll_mask))
420 break;
421 msleep(1);
422 time_out++;
423 } while (time_out <= poll_to);
424
425 if (time_out > poll_to) {
426 dev_err(&adapter->pdev->dev,
427 "Timeout exceeded in %s, aborting dump\n",
428 __func__);
429 return -EINVAL;
430 }
431skip_poll:
432 addr = l2->read_addr;
433 cnt = l2->read_addr_num;
434 while (cnt) {
435 qlcnic_read_dump_reg(addr, base, &data);
436 *buffer++ = cpu_to_le32(data);
437 addr += l2->read_addr_stride;
438 cnt--;
439 }
440 val += l2->stride;
441 }
442 return l2->no_ops * l2->read_addr_num * sizeof(u32);
443}
444
445static u32 qlcnic_read_memory(struct qlcnic_adapter *adapter,
446 struct qlcnic_dump_entry *entry, __le32 *buffer)
447{
448 u32 addr, data, test, ret = 0;
449 int i, reg_read;
450 struct __mem *mem = &entry->region.mem;
451 void __iomem *base = adapter->ahw->pci_base0;
452
453 reg_read = mem->size;
454 addr = mem->addr;
455 /* check for data size of multiple of 16 and 16 byte alignment */
456 if ((addr & 0xf) || (reg_read%16)) {
457 dev_info(&adapter->pdev->dev,
458 "Unaligned memory addr:0x%x size:0x%x\n",
459 addr, reg_read);
460 return -EINVAL;
461 }
462
463 mutex_lock(&adapter->ahw->mem_lock);
464
465 while (reg_read != 0) {
466 qlcnic_write_dump_reg(MIU_TEST_ADDR_LO, base, addr);
467 qlcnic_write_dump_reg(MIU_TEST_ADDR_HI, base, 0);
468 qlcnic_write_dump_reg(MIU_TEST_CTR, base,
469 TA_CTL_ENABLE | TA_CTL_START);
470
471 for (i = 0; i < MAX_CTL_CHECK; i++) {
472 qlcnic_read_dump_reg(MIU_TEST_CTR, base, &test);
473 if (!(test & TA_CTL_BUSY))
474 break;
475 }
476 if (i == MAX_CTL_CHECK) {
477 if (printk_ratelimit()) {
478 dev_err(&adapter->pdev->dev,
479 "failed to read through agent\n");
480 ret = -EINVAL;
481 goto out;
482 }
483 }
484 for (i = 0; i < 4; i++) {
485 qlcnic_read_dump_reg(MIU_TEST_READ_DATA[i], base,
486 &data);
487 *buffer++ = cpu_to_le32(data);
488 }
489 addr += 16;
490 reg_read -= 16;
491 ret += 16;
492 }
493out:
494 mutex_unlock(&adapter->ahw->mem_lock);
495 return mem->size;
496}
497
498static u32 qlcnic_dump_nop(struct qlcnic_adapter *adapter,
499 struct qlcnic_dump_entry *entry, __le32 *buffer)
500{
501 entry->hdr.flags |= QLCNIC_DUMP_SKIP;
502 return 0;
503}
504
505static const struct qlcnic_dump_operations fw_dump_ops[] = {
506 { QLCNIC_DUMP_NOP, qlcnic_dump_nop },
507 { QLCNIC_DUMP_READ_CRB, qlcnic_dump_crb },
508 { QLCNIC_DUMP_READ_MUX, qlcnic_dump_mux },
509 { QLCNIC_DUMP_QUEUE, qlcnic_dump_que },
510 { QLCNIC_DUMP_BRD_CONFIG, qlcnic_read_rom },
511 { QLCNIC_DUMP_READ_OCM, qlcnic_dump_ocm },
512 { QLCNIC_DUMP_PEG_REG, qlcnic_dump_ctrl },
513 { QLCNIC_DUMP_L1_DTAG, qlcnic_dump_l1_cache },
514 { QLCNIC_DUMP_L1_ITAG, qlcnic_dump_l1_cache },
515 { QLCNIC_DUMP_L1_DATA, qlcnic_dump_l1_cache },
516 { QLCNIC_DUMP_L1_INST, qlcnic_dump_l1_cache },
517 { QLCNIC_DUMP_L2_DTAG, qlcnic_dump_l2_cache },
518 { QLCNIC_DUMP_L2_ITAG, qlcnic_dump_l2_cache },
519 { QLCNIC_DUMP_L2_DATA, qlcnic_dump_l2_cache },
520 { QLCNIC_DUMP_L2_INST, qlcnic_dump_l2_cache },
521 { QLCNIC_DUMP_READ_ROM, qlcnic_read_rom },
522 { QLCNIC_DUMP_READ_MEM, qlcnic_read_memory },
523 { QLCNIC_DUMP_READ_CTRL, qlcnic_dump_ctrl },
524 { QLCNIC_DUMP_TLHDR, qlcnic_dump_nop },
525 { QLCNIC_DUMP_RDEND, qlcnic_dump_nop },
526};
527
528/* Walk the template and collect dump for each entry in the dump template */
529static int
530qlcnic_valid_dump_entry(struct device *dev, struct qlcnic_dump_entry *entry,
531 u32 size)
532{
533 int ret = 1;
534 if (size != entry->hdr.cap_size) {
535 dev_info(dev,
536 "Invalidate dump, Type:%d\tMask:%d\tSize:%dCap_size:%d\n",
537 entry->hdr.type, entry->hdr.mask, size, entry->hdr.cap_size);
538 dev_info(dev, "Aborting further dump capture\n");
539 ret = 0;
540 }
541 return ret;
542}
543
544int qlcnic_dump_fw(struct qlcnic_adapter *adapter)
545{
546 __le32 *buffer;
547 char mesg[64];
548 char *msg[] = {mesg, NULL};
549 int i, k, ops_cnt, ops_index, dump_size = 0;
550 u32 entry_offset, dump, no_entries, buf_offset = 0;
551 struct qlcnic_dump_entry *entry;
552 struct qlcnic_fw_dump *fw_dump = &adapter->ahw->fw_dump;
553 struct qlcnic_dump_template_hdr *tmpl_hdr = fw_dump->tmpl_hdr;
554
555 if (fw_dump->clr) {
556 dev_info(&adapter->pdev->dev,
557 "Previous dump not cleared, not capturing dump\n");
558 return -EIO;
559 }
560 /* Calculate the size for dump data area only */
561 for (i = 2, k = 1; (i & QLCNIC_DUMP_MASK_MAX); i <<= 1, k++)
562 if (i & tmpl_hdr->drv_cap_mask)
563 dump_size += tmpl_hdr->cap_sizes[k];
564 if (!dump_size)
565 return -EIO;
566
567 fw_dump->data = vzalloc(dump_size);
568 if (!fw_dump->data) {
569 dev_info(&adapter->pdev->dev,
570 "Unable to allocate (%d KB) for fw dump\n",
571 dump_size/1024);
572 return -ENOMEM;
573 }
574 buffer = fw_dump->data;
575 fw_dump->size = dump_size;
576 no_entries = tmpl_hdr->num_entries;
577 ops_cnt = ARRAY_SIZE(fw_dump_ops);
578 entry_offset = tmpl_hdr->offset;
579 tmpl_hdr->sys_info[0] = QLCNIC_DRIVER_VERSION;
580 tmpl_hdr->sys_info[1] = adapter->fw_version;
581
582 for (i = 0; i < no_entries; i++) {
583 entry = (void *)tmpl_hdr + entry_offset;
584 if (!(entry->hdr.mask & tmpl_hdr->drv_cap_mask)) {
585 entry->hdr.flags |= QLCNIC_DUMP_SKIP;
586 entry_offset += entry->hdr.offset;
587 continue;
588 }
589 /* Find the handler for this entry */
590 ops_index = 0;
591 while (ops_index < ops_cnt) {
592 if (entry->hdr.type == fw_dump_ops[ops_index].opcode)
593 break;
594 ops_index++;
595 }
596 if (ops_index == ops_cnt) {
597 dev_info(&adapter->pdev->dev,
598 "Invalid entry type %d, exiting dump\n",
599 entry->hdr.type);
600 goto error;
601 }
602 /* Collect dump for this entry */
603 dump = fw_dump_ops[ops_index].handler(adapter, entry, buffer);
604 if (dump && !qlcnic_valid_dump_entry(&adapter->pdev->dev, entry,
605 dump))
606 entry->hdr.flags |= QLCNIC_DUMP_SKIP;
607 buf_offset += entry->hdr.cap_size;
608 entry_offset += entry->hdr.offset;
609 buffer = fw_dump->data + buf_offset;
610 }
611 if (dump_size != buf_offset) {
612 dev_info(&adapter->pdev->dev,
613 "Captured(%d) and expected size(%d) do not match\n",
614 buf_offset, dump_size);
615 goto error;
616 } else {
617 fw_dump->clr = 1;
618 snprintf(mesg, sizeof(mesg), "FW_DUMP=%s",
619 adapter->netdev->name);
620 dev_info(&adapter->pdev->dev, "Dump data, %d bytes captured\n",
621 fw_dump->size);
622 /* Send a udev event to notify availability of FW dump */
623 kobject_uevent_env(&adapter->pdev->dev.kobj, KOBJ_CHANGE, msg);
624 return 0;
625 }
626error:
627 vfree(fw_dump->data);
628 return -EINVAL;
629}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-21 12:27:16 -0500