aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/ethernet/packetengines
diff options
context:
space:
mode:
authorJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-06-14 17:02:57 -0400
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-08-12 06:41:14 -0400
commit554f4ffd3b2cd88e42007d069bc519563d0b459f (patch)
tree3701f6d17551bc275d5622721c149521327faaea /drivers/net/ethernet/packetengines
parentb544dbac41218fd015ac79455cfc1e57736e9b0c (diff)
hamachi/yellowfin: Move the packet engine drivers
Move the packet engine drivers to drivers/net/ethernet/packetengines/ and the necessary Kconfig and Makefile changes. CC: Donald Becker <becker@scyld.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ethernet/packetengines')
-rw-r--r--drivers/net/ethernet/packetengines/Kconfig46
-rw-r--r--drivers/net/ethernet/packetengines/Makefile6
-rw-r--r--drivers/net/ethernet/packetengines/hamachi.c1952
-rw-r--r--drivers/net/ethernet/packetengines/yellowfin.c1430
4 files changed, 3434 insertions, 0 deletions
diff --git a/drivers/net/ethernet/packetengines/Kconfig b/drivers/net/ethernet/packetengines/Kconfig
new file mode 100644
index 000000000000..4add1db20f1e
--- /dev/null
+++ b/drivers/net/ethernet/packetengines/Kconfig
@@ -0,0 +1,46 @@
1#
2# Packet engine device configuration
3#
4
5config NET_PACKET_ENGINE
6 bool "Packet Engine devices"
7 depends on PCI
8 ---help---
9 If you have a network (Ethernet) card belonging to this class, say Y
10 and read the Ethernet-HOWTO, available from
11 <http://www.tldp.org/docs.html#howto>.
12
13 Note that the answer to this question doesn't directly affect the
14 kernel: saying N will just cause the configurator to skip all
15 the questions about packet engine devices. If you say Y, you will
16 be asked for your specific card in the following questions.
17
18if NET_PACKET_ENGINE
19
20config HAMACHI
21 tristate "Packet Engines Hamachi GNIC-II support"
22 depends on PCI
23 select MII
24 ---help---
25 If you have a Gigabit Ethernet card of this type, say Y and read
26 the Ethernet-HOWTO, available from
27 <http://www.tldp.org/docs.html#howto>.
28
29 To compile this driver as a module, choose M here. The module will be
30 called hamachi.
31
32config YELLOWFIN
33 tristate "Packet Engines Yellowfin Gigabit-NIC support (EXPERIMENTAL)"
34 depends on PCI && EXPERIMENTAL
35 select CRC32
36 ---help---
37 Say Y here if you have a Packet Engines G-NIC PCI Gigabit Ethernet
38 adapter or the SYM53C885 Ethernet controller. The Gigabit adapter is
39 used by the Beowulf Linux cluster project. See
40 <http://cesdis.gsfc.nasa.gov/linux/drivers/yellowfin.html> for more
41 information about this driver in particular and Beowulf in general.
42
43 To compile this driver as a module, choose M here: the module
44 will be called yellowfin. This is recommended.
45
46endif # NET_PACKET_ENGINE
diff --git a/drivers/net/ethernet/packetengines/Makefile b/drivers/net/ethernet/packetengines/Makefile
new file mode 100644
index 000000000000..995ccd077d0c
--- /dev/null
+++ b/drivers/net/ethernet/packetengines/Makefile
@@ -0,0 +1,6 @@
1#
2# Makefile for the Packet Engine network device drivers.
3#
4
5obj-$(CONFIG_HAMACHI) += hamachi.o
6obj-$(CONFIG_YELLOWFIN) += yellowfin.o
diff --git a/drivers/net/ethernet/packetengines/hamachi.c b/drivers/net/ethernet/packetengines/hamachi.c
new file mode 100644
index 000000000000..c274b3d77eb5
--- /dev/null
+++ b/drivers/net/ethernet/packetengines/hamachi.c
@@ -0,0 +1,1952 @@
1/* hamachi.c: A Packet Engines GNIC-II Gigabit Ethernet driver for Linux. */
2/*
3 Written 1998-2000 by Donald Becker.
4 Updates 2000 by Keith Underwood.
5
6 This software may be used and distributed according to the terms of
7 the GNU General Public License (GPL), incorporated herein by reference.
8 Drivers based on or derived from this code fall under the GPL and must
9 retain the authorship, copyright and license notice. This file is not
10 a complete program and may only be used when the entire operating
11 system is licensed under the GPL.
12
13 The author may be reached as becker@scyld.com, or C/O
14 Scyld Computing Corporation
15 410 Severn Ave., Suite 210
16 Annapolis MD 21403
17
18 This driver is for the Packet Engines GNIC-II PCI Gigabit Ethernet
19 adapter.
20
21 Support and updates available at
22 http://www.scyld.com/network/hamachi.html
23 [link no longer provides useful info -jgarzik]
24 or
25 http://www.parl.clemson.edu/~keithu/hamachi.html
26
27*/
28
29#define DRV_NAME "hamachi"
30#define DRV_VERSION "2.1"
31#define DRV_RELDATE "Sept 11, 2006"
32
33
34/* A few user-configurable values. */
35
36static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
37#define final_version
38#define hamachi_debug debug
39/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
40static int max_interrupt_work = 40;
41static int mtu;
42/* Default values selected by testing on a dual processor PIII-450 */
43/* These six interrupt control parameters may be set directly when loading the
44 * module, or through the rx_params and tx_params variables
45 */
46static int max_rx_latency = 0x11;
47static int max_rx_gap = 0x05;
48static int min_rx_pkt = 0x18;
49static int max_tx_latency = 0x00;
50static int max_tx_gap = 0x00;
51static int min_tx_pkt = 0x30;
52
53/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
54 -Setting to > 1518 causes all frames to be copied
55 -Setting to 0 disables copies
56*/
57static int rx_copybreak;
58
59/* An override for the hardware detection of bus width.
60 Set to 1 to force 32 bit PCI bus detection. Set to 4 to force 64 bit.
61 Add 2 to disable parity detection.
62*/
63static int force32;
64
65
66/* Used to pass the media type, etc.
67 These exist for driver interoperability.
68 No media types are currently defined.
69 - The lower 4 bits are reserved for the media type.
70 - The next three bits may be set to one of the following:
71 0x00000000 : Autodetect PCI bus
72 0x00000010 : Force 32 bit PCI bus
73 0x00000020 : Disable parity detection
74 0x00000040 : Force 64 bit PCI bus
75 Default is autodetect
76 - The next bit can be used to force half-duplex. This is a bad
77 idea since no known implementations implement half-duplex, and,
78 in general, half-duplex for gigabit ethernet is a bad idea.
79 0x00000080 : Force half-duplex
80 Default is full-duplex.
81 - In the original driver, the ninth bit could be used to force
82 full-duplex. Maintain that for compatibility
83 0x00000200 : Force full-duplex
84*/
85#define MAX_UNITS 8 /* More are supported, limit only on options */
86static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
87static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
88/* The Hamachi chipset supports 3 parameters each for Rx and Tx
89 * interruput management. Parameters will be loaded as specified into
90 * the TxIntControl and RxIntControl registers.
91 *
92 * The registers are arranged as follows:
93 * 23 - 16 15 - 8 7 - 0
94 * _________________________________
95 * | min_pkt | max_gap | max_latency |
96 * ---------------------------------
97 * min_pkt : The minimum number of packets processed between
98 * interrupts.
99 * max_gap : The maximum inter-packet gap in units of 8.192 us
100 * max_latency : The absolute time between interrupts in units of 8.192 us
101 *
102 */
103static int rx_params[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
104static int tx_params[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
105
106/* Operational parameters that are set at compile time. */
107
108/* Keep the ring sizes a power of two for compile efficiency.
109 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
110 Making the Tx ring too large decreases the effectiveness of channel
111 bonding and packet priority.
112 There are no ill effects from too-large receive rings, except for
113 excessive memory usage */
114/* Empirically it appears that the Tx ring needs to be a little bigger
115 for these Gbit adapters or you get into an overrun condition really
116 easily. Also, things appear to work a bit better in back-to-back
117 configurations if the Rx ring is 8 times the size of the Tx ring
118*/
119#define TX_RING_SIZE 64
120#define RX_RING_SIZE 512
121#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct hamachi_desc)
122#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct hamachi_desc)
123
124/*
125 * Enable netdev_ioctl. Added interrupt coalescing parameter adjustment.
126 * 2/19/99 Pete Wyckoff <wyckoff@ca.sandia.gov>
127 */
128
129/* play with 64-bit addrlen; seems to be a teensy bit slower --pw */
130/* #define ADDRLEN 64 */
131
132/*
133 * RX_CHECKSUM turns on card-generated receive checksum generation for
134 * TCP and UDP packets. Otherwise the upper layers do the calculation.
135 * 3/10/1999 Pete Wyckoff <wyckoff@ca.sandia.gov>
136 */
137#define RX_CHECKSUM
138
139/* Operational parameters that usually are not changed. */
140/* Time in jiffies before concluding the transmitter is hung. */
141#define TX_TIMEOUT (5*HZ)
142
143#include <linux/capability.h>
144#include <linux/module.h>
145#include <linux/kernel.h>
146#include <linux/string.h>
147#include <linux/timer.h>
148#include <linux/time.h>
149#include <linux/errno.h>
150#include <linux/ioport.h>
151#include <linux/interrupt.h>
152#include <linux/pci.h>
153#include <linux/init.h>
154#include <linux/ethtool.h>
155#include <linux/mii.h>
156#include <linux/netdevice.h>
157#include <linux/etherdevice.h>
158#include <linux/skbuff.h>
159#include <linux/ip.h>
160#include <linux/delay.h>
161#include <linux/bitops.h>
162
163#include <asm/uaccess.h>
164#include <asm/processor.h> /* Processor type for cache alignment. */
165#include <asm/io.h>
166#include <asm/unaligned.h>
167#include <asm/cache.h>
168
169static const char version[] __devinitconst =
170KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker\n"
171" Some modifications by Eric kasten <kasten@nscl.msu.edu>\n"
172" Further modifications by Keith Underwood <keithu@parl.clemson.edu>\n";
173
174
175/* IP_MF appears to be only defined in <netinet/ip.h>, however,
176 we need it for hardware checksumming support. FYI... some of
177 the definitions in <netinet/ip.h> conflict/duplicate those in
178 other linux headers causing many compiler warnings.
179*/
180#ifndef IP_MF
181 #define IP_MF 0x2000 /* IP more frags from <netinet/ip.h> */
182#endif
183
184/* Define IP_OFFSET to be IPOPT_OFFSET */
185#ifndef IP_OFFSET
186 #ifdef IPOPT_OFFSET
187 #define IP_OFFSET IPOPT_OFFSET
188 #else
189 #define IP_OFFSET 2
190 #endif
191#endif
192
193#define RUN_AT(x) (jiffies + (x))
194
195#ifndef ADDRLEN
196#define ADDRLEN 32
197#endif
198
199/* Condensed bus+endian portability operations. */
200#if ADDRLEN == 64
201#define cpu_to_leXX(addr) cpu_to_le64(addr)
202#define leXX_to_cpu(addr) le64_to_cpu(addr)
203#else
204#define cpu_to_leXX(addr) cpu_to_le32(addr)
205#define leXX_to_cpu(addr) le32_to_cpu(addr)
206#endif
207
208
209/*
210 Theory of Operation
211
212I. Board Compatibility
213
214This device driver is designed for the Packet Engines "Hamachi"
215Gigabit Ethernet chip. The only PCA currently supported is the GNIC-II 64-bit
21666Mhz PCI card.
217
218II. Board-specific settings
219
220No jumpers exist on the board. The chip supports software correction of
221various motherboard wiring errors, however this driver does not support
222that feature.
223
224III. Driver operation
225
226IIIa. Ring buffers
227
228The Hamachi uses a typical descriptor based bus-master architecture.
229The descriptor list is similar to that used by the Digital Tulip.
230This driver uses two statically allocated fixed-size descriptor lists
231formed into rings by a branch from the final descriptor to the beginning of
232the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
233
234This driver uses a zero-copy receive and transmit scheme similar my other
235network drivers.
236The driver allocates full frame size skbuffs for the Rx ring buffers at
237open() time and passes the skb->data field to the Hamachi as receive data
238buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
239a fresh skbuff is allocated and the frame is copied to the new skbuff.
240When the incoming frame is larger, the skbuff is passed directly up the
241protocol stack and replaced by a newly allocated skbuff.
242
243The RX_COPYBREAK value is chosen to trade-off the memory wasted by
244using a full-sized skbuff for small frames vs. the copying costs of larger
245frames. Gigabit cards are typically used on generously configured machines
246and the underfilled buffers have negligible impact compared to the benefit of
247a single allocation size, so the default value of zero results in never
248copying packets.
249
250IIIb/c. Transmit/Receive Structure
251
252The Rx and Tx descriptor structure are straight-forward, with no historical
253baggage that must be explained. Unlike the awkward DBDMA structure, there
254are no unused fields or option bits that had only one allowable setting.
255
256Two details should be noted about the descriptors: The chip supports both 32
257bit and 64 bit address structures, and the length field is overwritten on
258the receive descriptors. The descriptor length is set in the control word
259for each channel. The development driver uses 32 bit addresses only, however
26064 bit addresses may be enabled for 64 bit architectures e.g. the Alpha.
261
262IIId. Synchronization
263
264This driver is very similar to my other network drivers.
265The driver runs as two independent, single-threaded flows of control. One
266is the send-packet routine, which enforces single-threaded use by the
267dev->tbusy flag. The other thread is the interrupt handler, which is single
268threaded by the hardware and other software.
269
270The send packet thread has partial control over the Tx ring and 'dev->tbusy'
271flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
272queue slot is empty, it clears the tbusy flag when finished otherwise it sets
273the 'hmp->tx_full' flag.
274
275The interrupt handler has exclusive control over the Rx ring and records stats
276from the Tx ring. After reaping the stats, it marks the Tx queue entry as
277empty by incrementing the dirty_tx mark. Iff the 'hmp->tx_full' flag is set, it
278clears both the tx_full and tbusy flags.
279
280IV. Notes
281
282Thanks to Kim Stearns of Packet Engines for providing a pair of GNIC-II boards.
283
284IVb. References
285
286Hamachi Engineering Design Specification, 5/15/97
287(Note: This version was marked "Confidential".)
288
289IVc. Errata
290
291None noted.
292
293V. Recent Changes
294
29501/15/1999 EPK Enlargement of the TX and RX ring sizes. This appears
296 to help avoid some stall conditions -- this needs further research.
297
29801/15/1999 EPK Creation of the hamachi_tx function. This function cleans
299 the Tx ring and is called from hamachi_start_xmit (this used to be
300 called from hamachi_interrupt but it tends to delay execution of the
301 interrupt handler and thus reduce bandwidth by reducing the latency
302 between hamachi_rx()'s). Notably, some modification has been made so
303 that the cleaning loop checks only to make sure that the DescOwn bit
304 isn't set in the status flag since the card is not required
305 to set the entire flag to zero after processing.
306
30701/15/1999 EPK In the hamachi_start_tx function, the Tx ring full flag is
308 checked before attempting to add a buffer to the ring. If the ring is full
309 an attempt is made to free any dirty buffers and thus find space for
310 the new buffer or the function returns non-zero which should case the
311 scheduler to reschedule the buffer later.
312
31301/15/1999 EPK Some adjustments were made to the chip initialization.
314 End-to-end flow control should now be fully active and the interrupt
315 algorithm vars have been changed. These could probably use further tuning.
316
31701/15/1999 EPK Added the max_{rx,tx}_latency options. These are used to
318 set the rx and tx latencies for the Hamachi interrupts. If you're having
319 problems with network stalls, try setting these to higher values.
320 Valid values are 0x00 through 0xff.
321
32201/15/1999 EPK In general, the overall bandwidth has increased and
323 latencies are better (sometimes by a factor of 2). Stalls are rare at
324 this point, however there still appears to be a bug somewhere between the
325 hardware and driver. TCP checksum errors under load also appear to be
326 eliminated at this point.
327
32801/18/1999 EPK Ensured that the DescEndRing bit was being set on both the
329 Rx and Tx rings. This appears to have been affecting whether a particular
330 peer-to-peer connection would hang under high load. I believe the Rx
331 rings was typically getting set correctly, but the Tx ring wasn't getting
332 the DescEndRing bit set during initialization. ??? Does this mean the
333 hamachi card is using the DescEndRing in processing even if a particular
334 slot isn't in use -- hypothetically, the card might be searching the
335 entire Tx ring for slots with the DescOwn bit set and then processing
336 them. If the DescEndRing bit isn't set, then it might just wander off
337 through memory until it hits a chunk of data with that bit set
338 and then looping back.
339
34002/09/1999 EPK Added Michel Mueller's TxDMA Interrupt and Tx-timeout
341 problem (TxCmd and RxCmd need only to be set when idle or stopped.
342
34302/09/1999 EPK Added code to check/reset dev->tbusy in hamachi_interrupt.
344 (Michel Mueller pointed out the ``permanently busy'' potential
345 problem here).
346
34702/22/1999 EPK Added Pete Wyckoff's ioctl to control the Tx/Rx latencies.
348
34902/23/1999 EPK Verified that the interrupt status field bits for Tx were
350 incorrectly defined and corrected (as per Michel Mueller).
351
35202/23/1999 EPK Corrected the Tx full check to check that at least 4 slots
353 were available before reseting the tbusy and tx_full flags
354 (as per Michel Mueller).
355
35603/11/1999 EPK Added Pete Wyckoff's hardware checksumming support.
357
35812/31/1999 KDU Cleaned up assorted things and added Don's code to force
35932 bit.
360
36102/20/2000 KDU Some of the control was just plain odd. Cleaned up the
362hamachi_start_xmit() and hamachi_interrupt() code. There is still some
363re-structuring I would like to do.
364
36503/01/2000 KDU Experimenting with a WIDE range of interrupt mitigation
366parameters on a dual P3-450 setup yielded the new default interrupt
367mitigation parameters. Tx should interrupt VERY infrequently due to
368Eric's scheme. Rx should be more often...
369
37003/13/2000 KDU Added a patch to make the Rx Checksum code interact
371nicely with non-linux machines.
372
37303/13/2000 KDU Experimented with some of the configuration values:
374
375 -It seems that enabling PCI performance commands for descriptors
376 (changing RxDMACtrl and TxDMACtrl lower nibble from 5 to D) has minimal
377 performance impact for any of my tests. (ttcp, netpipe, netperf) I will
378 leave them that way until I hear further feedback.
379
380 -Increasing the PCI_LATENCY_TIMER to 130
381 (2 + (burst size of 128 * (0 wait states + 1))) seems to slightly
382 degrade performance. Leaving default at 64 pending further information.
383
38403/14/2000 KDU Further tuning:
385
386 -adjusted boguscnt in hamachi_rx() to depend on interrupt
387 mitigation parameters chosen.
388
389 -Selected a set of interrupt parameters based on some extensive testing.
390 These may change with more testing.
391
392TO DO:
393
394-Consider borrowing from the acenic driver code to check PCI_COMMAND for
395PCI_COMMAND_INVALIDATE. Set maximum burst size to cache line size in
396that case.
397
398-fix the reset procedure. It doesn't quite work.
399*/
400
401/* A few values that may be tweaked. */
402/* Size of each temporary Rx buffer, calculated as:
403 * 1518 bytes (ethernet packet) + 2 bytes (to get 8 byte alignment for
404 * the card) + 8 bytes of status info + 8 bytes for the Rx Checksum
405 */
406#define PKT_BUF_SZ 1536
407
408/* For now, this is going to be set to the maximum size of an ethernet
409 * packet. Eventually, we may want to make it a variable that is
410 * related to the MTU
411 */
412#define MAX_FRAME_SIZE 1518
413
414/* The rest of these values should never change. */
415
416static void hamachi_timer(unsigned long data);
417
418enum capability_flags {CanHaveMII=1, };
419static const struct chip_info {
420 u16 vendor_id, device_id, device_id_mask, pad;
421 const char *name;
422 void (*media_timer)(unsigned long data);
423 int flags;
424} chip_tbl[] = {
425 {0x1318, 0x0911, 0xffff, 0, "Hamachi GNIC-II", hamachi_timer, 0},
426 {0,},
427};
428
429/* Offsets to the Hamachi registers. Various sizes. */
430enum hamachi_offsets {
431 TxDMACtrl=0x00, TxCmd=0x04, TxStatus=0x06, TxPtr=0x08, TxCurPtr=0x10,
432 RxDMACtrl=0x20, RxCmd=0x24, RxStatus=0x26, RxPtr=0x28, RxCurPtr=0x30,
433 PCIClkMeas=0x060, MiscStatus=0x066, ChipRev=0x68, ChipReset=0x06B,
434 LEDCtrl=0x06C, VirtualJumpers=0x06D, GPIO=0x6E,
435 TxChecksum=0x074, RxChecksum=0x076,
436 TxIntrCtrl=0x078, RxIntrCtrl=0x07C,
437 InterruptEnable=0x080, InterruptClear=0x084, IntrStatus=0x088,
438 EventStatus=0x08C,
439 MACCnfg=0x0A0, FrameGap0=0x0A2, FrameGap1=0x0A4,
440 /* See enum MII_offsets below. */
441 MACCnfg2=0x0B0, RxDepth=0x0B8, FlowCtrl=0x0BC, MaxFrameSize=0x0CE,
442 AddrMode=0x0D0, StationAddr=0x0D2,
443 /* Gigabit AutoNegotiation. */
444 ANCtrl=0x0E0, ANStatus=0x0E2, ANXchngCtrl=0x0E4, ANAdvertise=0x0E8,
445 ANLinkPartnerAbility=0x0EA,
446 EECmdStatus=0x0F0, EEData=0x0F1, EEAddr=0x0F2,
447 FIFOcfg=0x0F8,
448};
449
450/* Offsets to the MII-mode registers. */
451enum MII_offsets {
452 MII_Cmd=0xA6, MII_Addr=0xA8, MII_Wr_Data=0xAA, MII_Rd_Data=0xAC,
453 MII_Status=0xAE,
454};
455
456/* Bits in the interrupt status/mask registers. */
457enum intr_status_bits {
458 IntrRxDone=0x01, IntrRxPCIFault=0x02, IntrRxPCIErr=0x04,
459 IntrTxDone=0x100, IntrTxPCIFault=0x200, IntrTxPCIErr=0x400,
460 LinkChange=0x10000, NegotiationChange=0x20000, StatsMax=0x40000, };
461
462/* The Hamachi Rx and Tx buffer descriptors. */
463struct hamachi_desc {
464 __le32 status_n_length;
465#if ADDRLEN == 64
466 u32 pad;
467 __le64 addr;
468#else
469 __le32 addr;
470#endif
471};
472
473/* Bits in hamachi_desc.status_n_length */
474enum desc_status_bits {
475 DescOwn=0x80000000, DescEndPacket=0x40000000, DescEndRing=0x20000000,
476 DescIntr=0x10000000,
477};
478
479#define PRIV_ALIGN 15 /* Required alignment mask */
480#define MII_CNT 4
481struct hamachi_private {
482 /* Descriptor rings first for alignment. Tx requires a second descriptor
483 for status. */
484 struct hamachi_desc *rx_ring;
485 struct hamachi_desc *tx_ring;
486 struct sk_buff* rx_skbuff[RX_RING_SIZE];
487 struct sk_buff* tx_skbuff[TX_RING_SIZE];
488 dma_addr_t tx_ring_dma;
489 dma_addr_t rx_ring_dma;
490 struct timer_list timer; /* Media selection timer. */
491 /* Frequently used and paired value: keep adjacent for cache effect. */
492 spinlock_t lock;
493 int chip_id;
494 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
495 unsigned int cur_tx, dirty_tx;
496 unsigned int rx_buf_sz; /* Based on MTU+slack. */
497 unsigned int tx_full:1; /* The Tx queue is full. */
498 unsigned int duplex_lock:1;
499 unsigned int default_port:4; /* Last dev->if_port value. */
500 /* MII transceiver section. */
501 int mii_cnt; /* MII device addresses. */
502 struct mii_if_info mii_if; /* MII lib hooks/info */
503 unsigned char phys[MII_CNT]; /* MII device addresses, only first one used. */
504 u32 rx_int_var, tx_int_var; /* interrupt control variables */
505 u32 option; /* Hold on to a copy of the options */
506 struct pci_dev *pci_dev;
507 void __iomem *base;
508};
509
510MODULE_AUTHOR("Donald Becker <becker@scyld.com>, Eric Kasten <kasten@nscl.msu.edu>, Keith Underwood <keithu@parl.clemson.edu>");
511MODULE_DESCRIPTION("Packet Engines 'Hamachi' GNIC-II Gigabit Ethernet driver");
512MODULE_LICENSE("GPL");
513
514module_param(max_interrupt_work, int, 0);
515module_param(mtu, int, 0);
516module_param(debug, int, 0);
517module_param(min_rx_pkt, int, 0);
518module_param(max_rx_gap, int, 0);
519module_param(max_rx_latency, int, 0);
520module_param(min_tx_pkt, int, 0);
521module_param(max_tx_gap, int, 0);
522module_param(max_tx_latency, int, 0);
523module_param(rx_copybreak, int, 0);
524module_param_array(rx_params, int, NULL, 0);
525module_param_array(tx_params, int, NULL, 0);
526module_param_array(options, int, NULL, 0);
527module_param_array(full_duplex, int, NULL, 0);
528module_param(force32, int, 0);
529MODULE_PARM_DESC(max_interrupt_work, "GNIC-II maximum events handled per interrupt");
530MODULE_PARM_DESC(mtu, "GNIC-II MTU (all boards)");
531MODULE_PARM_DESC(debug, "GNIC-II debug level (0-7)");
532MODULE_PARM_DESC(min_rx_pkt, "GNIC-II minimum Rx packets processed between interrupts");
533MODULE_PARM_DESC(max_rx_gap, "GNIC-II maximum Rx inter-packet gap in 8.192 microsecond units");
534MODULE_PARM_DESC(max_rx_latency, "GNIC-II time between Rx interrupts in 8.192 microsecond units");
535MODULE_PARM_DESC(min_tx_pkt, "GNIC-II minimum Tx packets processed between interrupts");
536MODULE_PARM_DESC(max_tx_gap, "GNIC-II maximum Tx inter-packet gap in 8.192 microsecond units");
537MODULE_PARM_DESC(max_tx_latency, "GNIC-II time between Tx interrupts in 8.192 microsecond units");
538MODULE_PARM_DESC(rx_copybreak, "GNIC-II copy breakpoint for copy-only-tiny-frames");
539MODULE_PARM_DESC(rx_params, "GNIC-II min_rx_pkt+max_rx_gap+max_rx_latency");
540MODULE_PARM_DESC(tx_params, "GNIC-II min_tx_pkt+max_tx_gap+max_tx_latency");
541MODULE_PARM_DESC(options, "GNIC-II Bits 0-3: media type, bits 4-6: as force32, bit 7: half duplex, bit 9 full duplex");
542MODULE_PARM_DESC(full_duplex, "GNIC-II full duplex setting(s) (1)");
543MODULE_PARM_DESC(force32, "GNIC-II: Bit 0: 32 bit PCI, bit 1: disable parity, bit 2: 64 bit PCI (all boards)");
544
545static int read_eeprom(void __iomem *ioaddr, int location);
546static int mdio_read(struct net_device *dev, int phy_id, int location);
547static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
548static int hamachi_open(struct net_device *dev);
549static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
550static void hamachi_timer(unsigned long data);
551static void hamachi_tx_timeout(struct net_device *dev);
552static void hamachi_init_ring(struct net_device *dev);
553static netdev_tx_t hamachi_start_xmit(struct sk_buff *skb,
554 struct net_device *dev);
555static irqreturn_t hamachi_interrupt(int irq, void *dev_instance);
556static int hamachi_rx(struct net_device *dev);
557static inline int hamachi_tx(struct net_device *dev);
558static void hamachi_error(struct net_device *dev, int intr_status);
559static int hamachi_close(struct net_device *dev);
560static struct net_device_stats *hamachi_get_stats(struct net_device *dev);
561static void set_rx_mode(struct net_device *dev);
562static const struct ethtool_ops ethtool_ops;
563static const struct ethtool_ops ethtool_ops_no_mii;
564
565static const struct net_device_ops hamachi_netdev_ops = {
566 .ndo_open = hamachi_open,
567 .ndo_stop = hamachi_close,
568 .ndo_start_xmit = hamachi_start_xmit,
569 .ndo_get_stats = hamachi_get_stats,
570 .ndo_set_multicast_list = set_rx_mode,
571 .ndo_change_mtu = eth_change_mtu,
572 .ndo_validate_addr = eth_validate_addr,
573 .ndo_set_mac_address = eth_mac_addr,
574 .ndo_tx_timeout = hamachi_tx_timeout,
575 .ndo_do_ioctl = netdev_ioctl,
576};
577
578
579static int __devinit hamachi_init_one (struct pci_dev *pdev,
580 const struct pci_device_id *ent)
581{
582 struct hamachi_private *hmp;
583 int option, i, rx_int_var, tx_int_var, boguscnt;
584 int chip_id = ent->driver_data;
585 int irq;
586 void __iomem *ioaddr;
587 unsigned long base;
588 static int card_idx;
589 struct net_device *dev;
590 void *ring_space;
591 dma_addr_t ring_dma;
592 int ret = -ENOMEM;
593
594/* when built into the kernel, we only print version if device is found */
595#ifndef MODULE
596 static int printed_version;
597 if (!printed_version++)
598 printk(version);
599#endif
600
601 if (pci_enable_device(pdev)) {
602 ret = -EIO;
603 goto err_out;
604 }
605
606 base = pci_resource_start(pdev, 0);
607#ifdef __alpha__ /* Really "64 bit addrs" */
608 base |= (pci_resource_start(pdev, 1) << 32);
609#endif
610
611 pci_set_master(pdev);
612
613 i = pci_request_regions(pdev, DRV_NAME);
614 if (i)
615 return i;
616
617 irq = pdev->irq;
618 ioaddr = ioremap(base, 0x400);
619 if (!ioaddr)
620 goto err_out_release;
621
622 dev = alloc_etherdev(sizeof(struct hamachi_private));
623 if (!dev)
624 goto err_out_iounmap;
625
626 SET_NETDEV_DEV(dev, &pdev->dev);
627
628 for (i = 0; i < 6; i++)
629 dev->dev_addr[i] = 1 ? read_eeprom(ioaddr, 4 + i)
630 : readb(ioaddr + StationAddr + i);
631
632#if ! defined(final_version)
633 if (hamachi_debug > 4)
634 for (i = 0; i < 0x10; i++)
635 printk("%2.2x%s",
636 read_eeprom(ioaddr, i), i % 16 != 15 ? " " : "\n");
637#endif
638
639 hmp = netdev_priv(dev);
640 spin_lock_init(&hmp->lock);
641
642 hmp->mii_if.dev = dev;
643 hmp->mii_if.mdio_read = mdio_read;
644 hmp->mii_if.mdio_write = mdio_write;
645 hmp->mii_if.phy_id_mask = 0x1f;
646 hmp->mii_if.reg_num_mask = 0x1f;
647
648 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
649 if (!ring_space)
650 goto err_out_cleardev;
651 hmp->tx_ring = ring_space;
652 hmp->tx_ring_dma = ring_dma;
653
654 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
655 if (!ring_space)
656 goto err_out_unmap_tx;
657 hmp->rx_ring = ring_space;
658 hmp->rx_ring_dma = ring_dma;
659
660 /* Check for options being passed in */
661 option = card_idx < MAX_UNITS ? options[card_idx] : 0;
662 if (dev->mem_start)
663 option = dev->mem_start;
664
665 /* If the bus size is misidentified, do the following. */
666 force32 = force32 ? force32 :
667 ((option >= 0) ? ((option & 0x00000070) >> 4) : 0 );
668 if (force32)
669 writeb(force32, ioaddr + VirtualJumpers);
670
671 /* Hmmm, do we really need to reset the chip???. */
672 writeb(0x01, ioaddr + ChipReset);
673
674 /* After a reset, the clock speed measurement of the PCI bus will not
675 * be valid for a moment. Wait for a little while until it is. If
676 * it takes more than 10ms, forget it.
677 */
678 udelay(10);
679 i = readb(ioaddr + PCIClkMeas);
680 for (boguscnt = 0; (!(i & 0x080)) && boguscnt < 1000; boguscnt++){
681 udelay(10);
682 i = readb(ioaddr + PCIClkMeas);
683 }
684
685 hmp->base = ioaddr;
686 dev->base_addr = (unsigned long)ioaddr;
687 dev->irq = irq;
688 pci_set_drvdata(pdev, dev);
689
690 hmp->chip_id = chip_id;
691 hmp->pci_dev = pdev;
692
693 /* The lower four bits are the media type. */
694 if (option > 0) {
695 hmp->option = option;
696 if (option & 0x200)
697 hmp->mii_if.full_duplex = 1;
698 else if (option & 0x080)
699 hmp->mii_if.full_duplex = 0;
700 hmp->default_port = option & 15;
701 if (hmp->default_port)
702 hmp->mii_if.force_media = 1;
703 }
704 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
705 hmp->mii_if.full_duplex = 1;
706
707 /* lock the duplex mode if someone specified a value */
708 if (hmp->mii_if.full_duplex || (option & 0x080))
709 hmp->duplex_lock = 1;
710
711 /* Set interrupt tuning parameters */
712 max_rx_latency = max_rx_latency & 0x00ff;
713 max_rx_gap = max_rx_gap & 0x00ff;
714 min_rx_pkt = min_rx_pkt & 0x00ff;
715 max_tx_latency = max_tx_latency & 0x00ff;
716 max_tx_gap = max_tx_gap & 0x00ff;
717 min_tx_pkt = min_tx_pkt & 0x00ff;
718
719 rx_int_var = card_idx < MAX_UNITS ? rx_params[card_idx] : -1;
720 tx_int_var = card_idx < MAX_UNITS ? tx_params[card_idx] : -1;
721 hmp->rx_int_var = rx_int_var >= 0 ? rx_int_var :
722 (min_rx_pkt << 16 | max_rx_gap << 8 | max_rx_latency);
723 hmp->tx_int_var = tx_int_var >= 0 ? tx_int_var :
724 (min_tx_pkt << 16 | max_tx_gap << 8 | max_tx_latency);
725
726
727 /* The Hamachi-specific entries in the device structure. */
728 dev->netdev_ops = &hamachi_netdev_ops;
729 if (chip_tbl[hmp->chip_id].flags & CanHaveMII)
730 SET_ETHTOOL_OPS(dev, &ethtool_ops);
731 else
732 SET_ETHTOOL_OPS(dev, &ethtool_ops_no_mii);
733 dev->watchdog_timeo = TX_TIMEOUT;
734 if (mtu)
735 dev->mtu = mtu;
736
737 i = register_netdev(dev);
738 if (i) {
739 ret = i;
740 goto err_out_unmap_rx;
741 }
742
743 printk(KERN_INFO "%s: %s type %x at %p, %pM, IRQ %d.\n",
744 dev->name, chip_tbl[chip_id].name, readl(ioaddr + ChipRev),
745 ioaddr, dev->dev_addr, irq);
746 i = readb(ioaddr + PCIClkMeas);
747 printk(KERN_INFO "%s: %d-bit %d Mhz PCI bus (%d), Virtual Jumpers "
748 "%2.2x, LPA %4.4x.\n",
749 dev->name, readw(ioaddr + MiscStatus) & 1 ? 64 : 32,
750 i ? 2000/(i&0x7f) : 0, i&0x7f, (int)readb(ioaddr + VirtualJumpers),
751 readw(ioaddr + ANLinkPartnerAbility));
752
753 if (chip_tbl[hmp->chip_id].flags & CanHaveMII) {
754 int phy, phy_idx = 0;
755 for (phy = 0; phy < 32 && phy_idx < MII_CNT; phy++) {
756 int mii_status = mdio_read(dev, phy, MII_BMSR);
757 if (mii_status != 0xffff &&
758 mii_status != 0x0000) {
759 hmp->phys[phy_idx++] = phy;
760 hmp->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE);
761 printk(KERN_INFO "%s: MII PHY found at address %d, status "
762 "0x%4.4x advertising %4.4x.\n",
763 dev->name, phy, mii_status, hmp->mii_if.advertising);
764 }
765 }
766 hmp->mii_cnt = phy_idx;
767 if (hmp->mii_cnt > 0)
768 hmp->mii_if.phy_id = hmp->phys[0];
769 else
770 memset(&hmp->mii_if, 0, sizeof(hmp->mii_if));
771 }
772 /* Configure gigabit autonegotiation. */
773 writew(0x0400, ioaddr + ANXchngCtrl); /* Enable legacy links. */
774 writew(0x08e0, ioaddr + ANAdvertise); /* Set our advertise word. */
775 writew(0x1000, ioaddr + ANCtrl); /* Enable negotiation */
776
777 card_idx++;
778 return 0;
779
780err_out_unmap_rx:
781 pci_free_consistent(pdev, RX_TOTAL_SIZE, hmp->rx_ring,
782 hmp->rx_ring_dma);
783err_out_unmap_tx:
784 pci_free_consistent(pdev, TX_TOTAL_SIZE, hmp->tx_ring,
785 hmp->tx_ring_dma);
786err_out_cleardev:
787 free_netdev (dev);
788err_out_iounmap:
789 iounmap(ioaddr);
790err_out_release:
791 pci_release_regions(pdev);
792err_out:
793 return ret;
794}
795
796static int __devinit read_eeprom(void __iomem *ioaddr, int location)
797{
798 int bogus_cnt = 1000;
799
800 /* We should check busy first - per docs -KDU */
801 while ((readb(ioaddr + EECmdStatus) & 0x40) && --bogus_cnt > 0);
802 writew(location, ioaddr + EEAddr);
803 writeb(0x02, ioaddr + EECmdStatus);
804 bogus_cnt = 1000;
805 while ((readb(ioaddr + EECmdStatus) & 0x40) && --bogus_cnt > 0);
806 if (hamachi_debug > 5)
807 printk(" EEPROM status is %2.2x after %d ticks.\n",
808 (int)readb(ioaddr + EECmdStatus), 1000- bogus_cnt);
809 return readb(ioaddr + EEData);
810}
811
812/* MII Managemen Data I/O accesses.
813 These routines assume the MDIO controller is idle, and do not exit until
814 the command is finished. */
815
816static int mdio_read(struct net_device *dev, int phy_id, int location)
817{
818 struct hamachi_private *hmp = netdev_priv(dev);
819 void __iomem *ioaddr = hmp->base;
820 int i;
821
822 /* We should check busy first - per docs -KDU */
823 for (i = 10000; i >= 0; i--)
824 if ((readw(ioaddr + MII_Status) & 1) == 0)
825 break;
826 writew((phy_id<<8) + location, ioaddr + MII_Addr);
827 writew(0x0001, ioaddr + MII_Cmd);
828 for (i = 10000; i >= 0; i--)
829 if ((readw(ioaddr + MII_Status) & 1) == 0)
830 break;
831 return readw(ioaddr + MII_Rd_Data);
832}
833
834static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
835{
836 struct hamachi_private *hmp = netdev_priv(dev);
837 void __iomem *ioaddr = hmp->base;
838 int i;
839
840 /* We should check busy first - per docs -KDU */
841 for (i = 10000; i >= 0; i--)
842 if ((readw(ioaddr + MII_Status) & 1) == 0)
843 break;
844 writew((phy_id<<8) + location, ioaddr + MII_Addr);
845 writew(value, ioaddr + MII_Wr_Data);
846
847 /* Wait for the command to finish. */
848 for (i = 10000; i >= 0; i--)
849 if ((readw(ioaddr + MII_Status) & 1) == 0)
850 break;
851}
852
853
854static int hamachi_open(struct net_device *dev)
855{
856 struct hamachi_private *hmp = netdev_priv(dev);
857 void __iomem *ioaddr = hmp->base;
858 int i;
859 u32 rx_int_var, tx_int_var;
860 u16 fifo_info;
861
862 i = request_irq(dev->irq, hamachi_interrupt, IRQF_SHARED, dev->name, dev);
863 if (i)
864 return i;
865
866 if (hamachi_debug > 1)
867 printk(KERN_DEBUG "%s: hamachi_open() irq %d.\n",
868 dev->name, dev->irq);
869
870 hamachi_init_ring(dev);
871
872#if ADDRLEN == 64
873 /* writellll anyone ? */
874 writel(hmp->rx_ring_dma, ioaddr + RxPtr);
875 writel(hmp->rx_ring_dma >> 32, ioaddr + RxPtr + 4);
876 writel(hmp->tx_ring_dma, ioaddr + TxPtr);
877 writel(hmp->tx_ring_dma >> 32, ioaddr + TxPtr + 4);
878#else
879 writel(hmp->rx_ring_dma, ioaddr + RxPtr);
880 writel(hmp->tx_ring_dma, ioaddr + TxPtr);
881#endif
882
883 /* TODO: It would make sense to organize this as words since the card
884 * documentation does. -KDU
885 */
886 for (i = 0; i < 6; i++)
887 writeb(dev->dev_addr[i], ioaddr + StationAddr + i);
888
889 /* Initialize other registers: with so many this eventually this will
890 converted to an offset/value list. */
891
892 /* Configure the FIFO */
893 fifo_info = (readw(ioaddr + GPIO) & 0x00C0) >> 6;
894 switch (fifo_info){
895 case 0 :
896 /* No FIFO */
897 writew(0x0000, ioaddr + FIFOcfg);
898 break;
899 case 1 :
900 /* Configure the FIFO for 512K external, 16K used for Tx. */
901 writew(0x0028, ioaddr + FIFOcfg);
902 break;
903 case 2 :
904 /* Configure the FIFO for 1024 external, 32K used for Tx. */
905 writew(0x004C, ioaddr + FIFOcfg);
906 break;
907 case 3 :
908 /* Configure the FIFO for 2048 external, 32K used for Tx. */
909 writew(0x006C, ioaddr + FIFOcfg);
910 break;
911 default :
912 printk(KERN_WARNING "%s: Unsupported external memory config!\n",
913 dev->name);
914 /* Default to no FIFO */
915 writew(0x0000, ioaddr + FIFOcfg);
916 break;
917 }
918
919 if (dev->if_port == 0)
920 dev->if_port = hmp->default_port;
921
922
923 /* Setting the Rx mode will start the Rx process. */
924 /* If someone didn't choose a duplex, default to full-duplex */
925 if (hmp->duplex_lock != 1)
926 hmp->mii_if.full_duplex = 1;
927
928 /* always 1, takes no more time to do it */
929 writew(0x0001, ioaddr + RxChecksum);
930 writew(0x0000, ioaddr + TxChecksum);
931 writew(0x8000, ioaddr + MACCnfg); /* Soft reset the MAC */
932 writew(0x215F, ioaddr + MACCnfg);
933 writew(0x000C, ioaddr + FrameGap0);
934 /* WHAT?!?!? Why isn't this documented somewhere? -KDU */
935 writew(0x1018, ioaddr + FrameGap1);
936 /* Why do we enable receives/transmits here? -KDU */
937 writew(0x0780, ioaddr + MACCnfg2); /* Upper 16 bits control LEDs. */
938 /* Enable automatic generation of flow control frames, period 0xffff. */
939 writel(0x0030FFFF, ioaddr + FlowCtrl);
940 writew(MAX_FRAME_SIZE, ioaddr + MaxFrameSize); /* dev->mtu+14 ??? */
941
942 /* Enable legacy links. */
943 writew(0x0400, ioaddr + ANXchngCtrl); /* Enable legacy links. */
944 /* Initial Link LED to blinking red. */
945 writeb(0x03, ioaddr + LEDCtrl);
946
947 /* Configure interrupt mitigation. This has a great effect on
948 performance, so systems tuning should start here!. */
949
950 rx_int_var = hmp->rx_int_var;
951 tx_int_var = hmp->tx_int_var;
952
953 if (hamachi_debug > 1) {
954 printk("max_tx_latency: %d, max_tx_gap: %d, min_tx_pkt: %d\n",
955 tx_int_var & 0x00ff, (tx_int_var & 0x00ff00) >> 8,
956 (tx_int_var & 0x00ff0000) >> 16);
957 printk("max_rx_latency: %d, max_rx_gap: %d, min_rx_pkt: %d\n",
958 rx_int_var & 0x00ff, (rx_int_var & 0x00ff00) >> 8,
959 (rx_int_var & 0x00ff0000) >> 16);
960 printk("rx_int_var: %x, tx_int_var: %x\n", rx_int_var, tx_int_var);
961 }
962
963 writel(tx_int_var, ioaddr + TxIntrCtrl);
964 writel(rx_int_var, ioaddr + RxIntrCtrl);
965
966 set_rx_mode(dev);
967
968 netif_start_queue(dev);
969
970 /* Enable interrupts by setting the interrupt mask. */
971 writel(0x80878787, ioaddr + InterruptEnable);
972 writew(0x0000, ioaddr + EventStatus); /* Clear non-interrupting events */
973
974 /* Configure and start the DMA channels. */
975 /* Burst sizes are in the low three bits: size = 4<<(val&7) */
976#if ADDRLEN == 64
977 writew(0x005D, ioaddr + RxDMACtrl); /* 128 dword bursts */
978 writew(0x005D, ioaddr + TxDMACtrl);
979#else
980 writew(0x001D, ioaddr + RxDMACtrl);
981 writew(0x001D, ioaddr + TxDMACtrl);
982#endif
983 writew(0x0001, ioaddr + RxCmd);
984
985 if (hamachi_debug > 2) {
986 printk(KERN_DEBUG "%s: Done hamachi_open(), status: Rx %x Tx %x.\n",
987 dev->name, readw(ioaddr + RxStatus), readw(ioaddr + TxStatus));
988 }
989 /* Set the timer to check for link beat. */
990 init_timer(&hmp->timer);
991 hmp->timer.expires = RUN_AT((24*HZ)/10); /* 2.4 sec. */
992 hmp->timer.data = (unsigned long)dev;
993 hmp->timer.function = hamachi_timer; /* timer handler */
994 add_timer(&hmp->timer);
995
996 return 0;
997}
998
999static inline int hamachi_tx(struct net_device *dev)
1000{
1001 struct hamachi_private *hmp = netdev_priv(dev);
1002
1003 /* Update the dirty pointer until we find an entry that is
1004 still owned by the card */
1005 for (; hmp->cur_tx - hmp->dirty_tx > 0; hmp->dirty_tx++) {
1006 int entry = hmp->dirty_tx % TX_RING_SIZE;
1007 struct sk_buff *skb;
1008
1009 if (hmp->tx_ring[entry].status_n_length & cpu_to_le32(DescOwn))
1010 break;
1011 /* Free the original skb. */
1012 skb = hmp->tx_skbuff[entry];
1013 if (skb) {
1014 pci_unmap_single(hmp->pci_dev,
1015 leXX_to_cpu(hmp->tx_ring[entry].addr),
1016 skb->len, PCI_DMA_TODEVICE);
1017 dev_kfree_skb(skb);
1018 hmp->tx_skbuff[entry] = NULL;
1019 }
1020 hmp->tx_ring[entry].status_n_length = 0;
1021 if (entry >= TX_RING_SIZE-1)
1022 hmp->tx_ring[TX_RING_SIZE-1].status_n_length |=
1023 cpu_to_le32(DescEndRing);
1024 dev->stats.tx_packets++;
1025 }
1026
1027 return 0;
1028}
1029
1030static void hamachi_timer(unsigned long data)
1031{
1032 struct net_device *dev = (struct net_device *)data;
1033 struct hamachi_private *hmp = netdev_priv(dev);
1034 void __iomem *ioaddr = hmp->base;
1035 int next_tick = 10*HZ;
1036
1037 if (hamachi_debug > 2) {
1038 printk(KERN_INFO "%s: Hamachi Autonegotiation status %4.4x, LPA "
1039 "%4.4x.\n", dev->name, readw(ioaddr + ANStatus),
1040 readw(ioaddr + ANLinkPartnerAbility));
1041 printk(KERN_INFO "%s: Autonegotiation regs %4.4x %4.4x %4.4x "
1042 "%4.4x %4.4x %4.4x.\n", dev->name,
1043 readw(ioaddr + 0x0e0),
1044 readw(ioaddr + 0x0e2),
1045 readw(ioaddr + 0x0e4),
1046 readw(ioaddr + 0x0e6),
1047 readw(ioaddr + 0x0e8),
1048 readw(ioaddr + 0x0eA));
1049 }
1050 /* We could do something here... nah. */
1051 hmp->timer.expires = RUN_AT(next_tick);
1052 add_timer(&hmp->timer);
1053}
1054
1055static void hamachi_tx_timeout(struct net_device *dev)
1056{
1057 int i;
1058 struct hamachi_private *hmp = netdev_priv(dev);
1059 void __iomem *ioaddr = hmp->base;
1060
1061 printk(KERN_WARNING "%s: Hamachi transmit timed out, status %8.8x,"
1062 " resetting...\n", dev->name, (int)readw(ioaddr + TxStatus));
1063
1064 {
1065 printk(KERN_DEBUG " Rx ring %p: ", hmp->rx_ring);
1066 for (i = 0; i < RX_RING_SIZE; i++)
1067 printk(KERN_CONT " %8.8x",
1068 le32_to_cpu(hmp->rx_ring[i].status_n_length));
1069 printk(KERN_CONT "\n");
1070 printk(KERN_DEBUG" Tx ring %p: ", hmp->tx_ring);
1071 for (i = 0; i < TX_RING_SIZE; i++)
1072 printk(KERN_CONT " %4.4x",
1073 le32_to_cpu(hmp->tx_ring[i].status_n_length));
1074 printk(KERN_CONT "\n");
1075 }
1076
1077 /* Reinit the hardware and make sure the Rx and Tx processes
1078 are up and running.
1079 */
1080 dev->if_port = 0;
1081 /* The right way to do Reset. -KDU
1082 * -Clear OWN bit in all Rx/Tx descriptors
1083 * -Wait 50 uS for channels to go idle
1084 * -Turn off MAC receiver
1085 * -Issue Reset
1086 */
1087
1088 for (i = 0; i < RX_RING_SIZE; i++)
1089 hmp->rx_ring[i].status_n_length &= cpu_to_le32(~DescOwn);
1090
1091 /* Presume that all packets in the Tx queue are gone if we have to
1092 * re-init the hardware.
1093 */
1094 for (i = 0; i < TX_RING_SIZE; i++){
1095 struct sk_buff *skb;
1096
1097 if (i >= TX_RING_SIZE - 1)
1098 hmp->tx_ring[i].status_n_length =
1099 cpu_to_le32(DescEndRing) |
1100 (hmp->tx_ring[i].status_n_length &
1101 cpu_to_le32(0x0000ffff));
1102 else
1103 hmp->tx_ring[i].status_n_length &= cpu_to_le32(0x0000ffff);
1104 skb = hmp->tx_skbuff[i];
1105 if (skb){
1106 pci_unmap_single(hmp->pci_dev, leXX_to_cpu(hmp->tx_ring[i].addr),
1107 skb->len, PCI_DMA_TODEVICE);
1108 dev_kfree_skb(skb);
1109 hmp->tx_skbuff[i] = NULL;
1110 }
1111 }
1112
1113 udelay(60); /* Sleep 60 us just for safety sake */
1114 writew(0x0002, ioaddr + RxCmd); /* STOP Rx */
1115
1116 writeb(0x01, ioaddr + ChipReset); /* Reinit the hardware */
1117
1118 hmp->tx_full = 0;
1119 hmp->cur_rx = hmp->cur_tx = 0;
1120 hmp->dirty_rx = hmp->dirty_tx = 0;
1121 /* Rx packets are also presumed lost; however, we need to make sure a
1122 * ring of buffers is in tact. -KDU
1123 */
1124 for (i = 0; i < RX_RING_SIZE; i++){
1125 struct sk_buff *skb = hmp->rx_skbuff[i];
1126
1127 if (skb){
1128 pci_unmap_single(hmp->pci_dev,
1129 leXX_to_cpu(hmp->rx_ring[i].addr),
1130 hmp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1131 dev_kfree_skb(skb);
1132 hmp->rx_skbuff[i] = NULL;
1133 }
1134 }
1135 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1136 for (i = 0; i < RX_RING_SIZE; i++) {
1137 struct sk_buff *skb;
1138
1139 skb = netdev_alloc_skb_ip_align(dev, hmp->rx_buf_sz);
1140 hmp->rx_skbuff[i] = skb;
1141 if (skb == NULL)
1142 break;
1143
1144 hmp->rx_ring[i].addr = cpu_to_leXX(pci_map_single(hmp->pci_dev,
1145 skb->data, hmp->rx_buf_sz, PCI_DMA_FROMDEVICE));
1146 hmp->rx_ring[i].status_n_length = cpu_to_le32(DescOwn |
1147 DescEndPacket | DescIntr | (hmp->rx_buf_sz - 2));
1148 }
1149 hmp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1150 /* Mark the last entry as wrapping the ring. */
1151 hmp->rx_ring[RX_RING_SIZE-1].status_n_length |= cpu_to_le32(DescEndRing);
1152
1153 /* Trigger an immediate transmit demand. */
1154 dev->trans_start = jiffies; /* prevent tx timeout */
1155 dev->stats.tx_errors++;
1156
1157 /* Restart the chip's Tx/Rx processes . */
1158 writew(0x0002, ioaddr + TxCmd); /* STOP Tx */
1159 writew(0x0001, ioaddr + TxCmd); /* START Tx */
1160 writew(0x0001, ioaddr + RxCmd); /* START Rx */
1161
1162 netif_wake_queue(dev);
1163}
1164
1165
1166/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1167static void hamachi_init_ring(struct net_device *dev)
1168{
1169 struct hamachi_private *hmp = netdev_priv(dev);
1170 int i;
1171
1172 hmp->tx_full = 0;
1173 hmp->cur_rx = hmp->cur_tx = 0;
1174 hmp->dirty_rx = hmp->dirty_tx = 0;
1175
1176 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1177 * card needs room to do 8 byte alignment, +2 so we can reserve
1178 * the first 2 bytes, and +16 gets room for the status word from the
1179 * card. -KDU
1180 */
1181 hmp->rx_buf_sz = (dev->mtu <= 1492 ? PKT_BUF_SZ :
1182 (((dev->mtu+26+7) & ~7) + 16));
1183
1184 /* Initialize all Rx descriptors. */
1185 for (i = 0; i < RX_RING_SIZE; i++) {
1186 hmp->rx_ring[i].status_n_length = 0;
1187 hmp->rx_skbuff[i] = NULL;
1188 }
1189 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1190 for (i = 0; i < RX_RING_SIZE; i++) {
1191 struct sk_buff *skb = dev_alloc_skb(hmp->rx_buf_sz + 2);
1192 hmp->rx_skbuff[i] = skb;
1193 if (skb == NULL)
1194 break;
1195 skb->dev = dev; /* Mark as being used by this device. */
1196 skb_reserve(skb, 2); /* 16 byte align the IP header. */
1197 hmp->rx_ring[i].addr = cpu_to_leXX(pci_map_single(hmp->pci_dev,
1198 skb->data, hmp->rx_buf_sz, PCI_DMA_FROMDEVICE));
1199 /* -2 because it doesn't REALLY have that first 2 bytes -KDU */
1200 hmp->rx_ring[i].status_n_length = cpu_to_le32(DescOwn |
1201 DescEndPacket | DescIntr | (hmp->rx_buf_sz -2));
1202 }
1203 hmp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1204 hmp->rx_ring[RX_RING_SIZE-1].status_n_length |= cpu_to_le32(DescEndRing);
1205
1206 for (i = 0; i < TX_RING_SIZE; i++) {
1207 hmp->tx_skbuff[i] = NULL;
1208 hmp->tx_ring[i].status_n_length = 0;
1209 }
1210 /* Mark the last entry of the ring */
1211 hmp->tx_ring[TX_RING_SIZE-1].status_n_length |= cpu_to_le32(DescEndRing);
1212}
1213
1214
1215static netdev_tx_t hamachi_start_xmit(struct sk_buff *skb,
1216 struct net_device *dev)
1217{
1218 struct hamachi_private *hmp = netdev_priv(dev);
1219 unsigned entry;
1220 u16 status;
1221
1222 /* Ok, now make sure that the queue has space before trying to
1223 add another skbuff. if we return non-zero the scheduler
1224 should interpret this as a queue full and requeue the buffer
1225 for later.
1226 */
1227 if (hmp->tx_full) {
1228 /* We should NEVER reach this point -KDU */
1229 printk(KERN_WARNING "%s: Hamachi transmit queue full at slot %d.\n",dev->name, hmp->cur_tx);
1230
1231 /* Wake the potentially-idle transmit channel. */
1232 /* If we don't need to read status, DON'T -KDU */
1233 status=readw(hmp->base + TxStatus);
1234 if( !(status & 0x0001) || (status & 0x0002))
1235 writew(0x0001, hmp->base + TxCmd);
1236 return NETDEV_TX_BUSY;
1237 }
1238
1239 /* Caution: the write order is important here, set the field
1240 with the "ownership" bits last. */
1241
1242 /* Calculate the next Tx descriptor entry. */
1243 entry = hmp->cur_tx % TX_RING_SIZE;
1244
1245 hmp->tx_skbuff[entry] = skb;
1246
1247 hmp->tx_ring[entry].addr = cpu_to_leXX(pci_map_single(hmp->pci_dev,
1248 skb->data, skb->len, PCI_DMA_TODEVICE));
1249
1250 /* Hmmmm, could probably put a DescIntr on these, but the way
1251 the driver is currently coded makes Tx interrupts unnecessary
1252 since the clearing of the Tx ring is handled by the start_xmit
1253 routine. This organization helps mitigate the interrupts a
1254 bit and probably renders the max_tx_latency param useless.
1255
1256 Update: Putting a DescIntr bit on all of the descriptors and
1257 mitigating interrupt frequency with the tx_min_pkt parameter. -KDU
1258 */
1259 if (entry >= TX_RING_SIZE-1) /* Wrap ring */
1260 hmp->tx_ring[entry].status_n_length = cpu_to_le32(DescOwn |
1261 DescEndPacket | DescEndRing | DescIntr | skb->len);
1262 else
1263 hmp->tx_ring[entry].status_n_length = cpu_to_le32(DescOwn |
1264 DescEndPacket | DescIntr | skb->len);
1265 hmp->cur_tx++;
1266
1267 /* Non-x86 Todo: explicitly flush cache lines here. */
1268
1269 /* Wake the potentially-idle transmit channel. */
1270 /* If we don't need to read status, DON'T -KDU */
1271 status=readw(hmp->base + TxStatus);
1272 if( !(status & 0x0001) || (status & 0x0002))
1273 writew(0x0001, hmp->base + TxCmd);
1274
1275 /* Immediately before returning, let's clear as many entries as we can. */
1276 hamachi_tx(dev);
1277
1278 /* We should kick the bottom half here, since we are not accepting
1279 * interrupts with every packet. i.e. realize that Gigabit ethernet
1280 * can transmit faster than ordinary machines can load packets;
1281 * hence, any packet that got put off because we were in the transmit
1282 * routine should IMMEDIATELY get a chance to be re-queued. -KDU
1283 */
1284 if ((hmp->cur_tx - hmp->dirty_tx) < (TX_RING_SIZE - 4))
1285 netif_wake_queue(dev); /* Typical path */
1286 else {
1287 hmp->tx_full = 1;
1288 netif_stop_queue(dev);
1289 }
1290
1291 if (hamachi_debug > 4) {
1292 printk(KERN_DEBUG "%s: Hamachi transmit frame #%d queued in slot %d.\n",
1293 dev->name, hmp->cur_tx, entry);
1294 }
1295 return NETDEV_TX_OK;
1296}
1297
1298/* The interrupt handler does all of the Rx thread work and cleans up
1299 after the Tx thread. */
1300static irqreturn_t hamachi_interrupt(int irq, void *dev_instance)
1301{
1302 struct net_device *dev = dev_instance;
1303 struct hamachi_private *hmp = netdev_priv(dev);
1304 void __iomem *ioaddr = hmp->base;
1305 long boguscnt = max_interrupt_work;
1306 int handled = 0;
1307
1308#ifndef final_version /* Can never occur. */
1309 if (dev == NULL) {
1310 printk (KERN_ERR "hamachi_interrupt(): irq %d for unknown device.\n", irq);
1311 return IRQ_NONE;
1312 }
1313#endif
1314
1315 spin_lock(&hmp->lock);
1316
1317 do {
1318 u32 intr_status = readl(ioaddr + InterruptClear);
1319
1320 if (hamachi_debug > 4)
1321 printk(KERN_DEBUG "%s: Hamachi interrupt, status %4.4x.\n",
1322 dev->name, intr_status);
1323
1324 if (intr_status == 0)
1325 break;
1326
1327 handled = 1;
1328
1329 if (intr_status & IntrRxDone)
1330 hamachi_rx(dev);
1331
1332 if (intr_status & IntrTxDone){
1333 /* This code should RARELY need to execute. After all, this is
1334 * a gigabit link, it should consume packets as fast as we put
1335 * them in AND we clear the Tx ring in hamachi_start_xmit().
1336 */
1337 if (hmp->tx_full){
1338 for (; hmp->cur_tx - hmp->dirty_tx > 0; hmp->dirty_tx++){
1339 int entry = hmp->dirty_tx % TX_RING_SIZE;
1340 struct sk_buff *skb;
1341
1342 if (hmp->tx_ring[entry].status_n_length & cpu_to_le32(DescOwn))
1343 break;
1344 skb = hmp->tx_skbuff[entry];
1345 /* Free the original skb. */
1346 if (skb){
1347 pci_unmap_single(hmp->pci_dev,
1348 leXX_to_cpu(hmp->tx_ring[entry].addr),
1349 skb->len,
1350 PCI_DMA_TODEVICE);
1351 dev_kfree_skb_irq(skb);
1352 hmp->tx_skbuff[entry] = NULL;
1353 }
1354 hmp->tx_ring[entry].status_n_length = 0;
1355 if (entry >= TX_RING_SIZE-1)
1356 hmp->tx_ring[TX_RING_SIZE-1].status_n_length |=
1357 cpu_to_le32(DescEndRing);
1358 dev->stats.tx_packets++;
1359 }
1360 if (hmp->cur_tx - hmp->dirty_tx < TX_RING_SIZE - 4){
1361 /* The ring is no longer full */
1362 hmp->tx_full = 0;
1363 netif_wake_queue(dev);
1364 }
1365 } else {
1366 netif_wake_queue(dev);
1367 }
1368 }
1369
1370
1371 /* Abnormal error summary/uncommon events handlers. */
1372 if (intr_status &
1373 (IntrTxPCIFault | IntrTxPCIErr | IntrRxPCIFault | IntrRxPCIErr |
1374 LinkChange | NegotiationChange | StatsMax))
1375 hamachi_error(dev, intr_status);
1376
1377 if (--boguscnt < 0) {
1378 printk(KERN_WARNING "%s: Too much work at interrupt, status=0x%4.4x.\n",
1379 dev->name, intr_status);
1380 break;
1381 }
1382 } while (1);
1383
1384 if (hamachi_debug > 3)
1385 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1386 dev->name, readl(ioaddr + IntrStatus));
1387
1388#ifndef final_version
1389 /* Code that should never be run! Perhaps remove after testing.. */
1390 {
1391 static int stopit = 10;
1392 if (dev->start == 0 && --stopit < 0) {
1393 printk(KERN_ERR "%s: Emergency stop, looping startup interrupt.\n",
1394 dev->name);
1395 free_irq(irq, dev);
1396 }
1397 }
1398#endif
1399
1400 spin_unlock(&hmp->lock);
1401 return IRQ_RETVAL(handled);
1402}
1403
1404/* This routine is logically part of the interrupt handler, but separated
1405 for clarity and better register allocation. */
1406static int hamachi_rx(struct net_device *dev)
1407{
1408 struct hamachi_private *hmp = netdev_priv(dev);
1409 int entry = hmp->cur_rx % RX_RING_SIZE;
1410 int boguscnt = (hmp->dirty_rx + RX_RING_SIZE) - hmp->cur_rx;
1411
1412 if (hamachi_debug > 4) {
1413 printk(KERN_DEBUG " In hamachi_rx(), entry %d status %4.4x.\n",
1414 entry, hmp->rx_ring[entry].status_n_length);
1415 }
1416
1417 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1418 while (1) {
1419 struct hamachi_desc *desc = &(hmp->rx_ring[entry]);
1420 u32 desc_status = le32_to_cpu(desc->status_n_length);
1421 u16 data_size = desc_status; /* Implicit truncate */
1422 u8 *buf_addr;
1423 s32 frame_status;
1424
1425 if (desc_status & DescOwn)
1426 break;
1427 pci_dma_sync_single_for_cpu(hmp->pci_dev,
1428 leXX_to_cpu(desc->addr),
1429 hmp->rx_buf_sz,
1430 PCI_DMA_FROMDEVICE);
1431 buf_addr = (u8 *) hmp->rx_skbuff[entry]->data;
1432 frame_status = get_unaligned_le32(&(buf_addr[data_size - 12]));
1433 if (hamachi_debug > 4)
1434 printk(KERN_DEBUG " hamachi_rx() status was %8.8x.\n",
1435 frame_status);
1436 if (--boguscnt < 0)
1437 break;
1438 if ( ! (desc_status & DescEndPacket)) {
1439 printk(KERN_WARNING "%s: Oversized Ethernet frame spanned "
1440 "multiple buffers, entry %#x length %d status %4.4x!\n",
1441 dev->name, hmp->cur_rx, data_size, desc_status);
1442 printk(KERN_WARNING "%s: Oversized Ethernet frame %p vs %p.\n",
1443 dev->name, desc, &hmp->rx_ring[hmp->cur_rx % RX_RING_SIZE]);
1444 printk(KERN_WARNING "%s: Oversized Ethernet frame -- next status %x/%x last status %x.\n",
1445 dev->name,
1446 le32_to_cpu(hmp->rx_ring[(hmp->cur_rx+1) % RX_RING_SIZE].status_n_length) & 0xffff0000,
1447 le32_to_cpu(hmp->rx_ring[(hmp->cur_rx+1) % RX_RING_SIZE].status_n_length) & 0x0000ffff,
1448 le32_to_cpu(hmp->rx_ring[(hmp->cur_rx-1) % RX_RING_SIZE].status_n_length));
1449 dev->stats.rx_length_errors++;
1450 } /* else Omit for prototype errata??? */
1451 if (frame_status & 0x00380000) {
1452 /* There was an error. */
1453 if (hamachi_debug > 2)
1454 printk(KERN_DEBUG " hamachi_rx() Rx error was %8.8x.\n",
1455 frame_status);
1456 dev->stats.rx_errors++;
1457 if (frame_status & 0x00600000)
1458 dev->stats.rx_length_errors++;
1459 if (frame_status & 0x00080000)
1460 dev->stats.rx_frame_errors++;
1461 if (frame_status & 0x00100000)
1462 dev->stats.rx_crc_errors++;
1463 if (frame_status < 0)
1464 dev->stats.rx_dropped++;
1465 } else {
1466 struct sk_buff *skb;
1467 /* Omit CRC */
1468 u16 pkt_len = (frame_status & 0x07ff) - 4;
1469#ifdef RX_CHECKSUM
1470 u32 pfck = *(u32 *) &buf_addr[data_size - 8];
1471#endif
1472
1473
1474#ifndef final_version
1475 if (hamachi_debug > 4)
1476 printk(KERN_DEBUG " hamachi_rx() normal Rx pkt length %d"
1477 " of %d, bogus_cnt %d.\n",
1478 pkt_len, data_size, boguscnt);
1479 if (hamachi_debug > 5)
1480 printk(KERN_DEBUG"%s: rx status %8.8x %8.8x %8.8x %8.8x %8.8x.\n",
1481 dev->name,
1482 *(s32*)&(buf_addr[data_size - 20]),
1483 *(s32*)&(buf_addr[data_size - 16]),
1484 *(s32*)&(buf_addr[data_size - 12]),
1485 *(s32*)&(buf_addr[data_size - 8]),
1486 *(s32*)&(buf_addr[data_size - 4]));
1487#endif
1488 /* Check if the packet is long enough to accept without copying
1489 to a minimally-sized skbuff. */
1490 if (pkt_len < rx_copybreak &&
1491 (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1492#ifdef RX_CHECKSUM
1493 printk(KERN_ERR "%s: rx_copybreak non-zero "
1494 "not good with RX_CHECKSUM\n", dev->name);
1495#endif
1496 skb_reserve(skb, 2); /* 16 byte align the IP header */
1497 pci_dma_sync_single_for_cpu(hmp->pci_dev,
1498 leXX_to_cpu(hmp->rx_ring[entry].addr),
1499 hmp->rx_buf_sz,
1500 PCI_DMA_FROMDEVICE);
1501 /* Call copy + cksum if available. */
1502#if 1 || USE_IP_COPYSUM
1503 skb_copy_to_linear_data(skb,
1504 hmp->rx_skbuff[entry]->data, pkt_len);
1505 skb_put(skb, pkt_len);
1506#else
1507 memcpy(skb_put(skb, pkt_len), hmp->rx_ring_dma
1508 + entry*sizeof(*desc), pkt_len);
1509#endif
1510 pci_dma_sync_single_for_device(hmp->pci_dev,
1511 leXX_to_cpu(hmp->rx_ring[entry].addr),
1512 hmp->rx_buf_sz,
1513 PCI_DMA_FROMDEVICE);
1514 } else {
1515 pci_unmap_single(hmp->pci_dev,
1516 leXX_to_cpu(hmp->rx_ring[entry].addr),
1517 hmp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1518 skb_put(skb = hmp->rx_skbuff[entry], pkt_len);
1519 hmp->rx_skbuff[entry] = NULL;
1520 }
1521 skb->protocol = eth_type_trans(skb, dev);
1522
1523
1524#ifdef RX_CHECKSUM
1525 /* TCP or UDP on ipv4, DIX encoding */
1526 if (pfck>>24 == 0x91 || pfck>>24 == 0x51) {
1527 struct iphdr *ih = (struct iphdr *) skb->data;
1528 /* Check that IP packet is at least 46 bytes, otherwise,
1529 * there may be pad bytes included in the hardware checksum.
1530 * This wouldn't happen if everyone padded with 0.
1531 */
1532 if (ntohs(ih->tot_len) >= 46){
1533 /* don't worry about frags */
1534 if (!(ih->frag_off & cpu_to_be16(IP_MF|IP_OFFSET))) {
1535 u32 inv = *(u32 *) &buf_addr[data_size - 16];
1536 u32 *p = (u32 *) &buf_addr[data_size - 20];
1537 register u32 crc, p_r, p_r1;
1538
1539 if (inv & 4) {
1540 inv &= ~4;
1541 --p;
1542 }
1543 p_r = *p;
1544 p_r1 = *(p-1);
1545 switch (inv) {
1546 case 0:
1547 crc = (p_r & 0xffff) + (p_r >> 16);
1548 break;
1549 case 1:
1550 crc = (p_r >> 16) + (p_r & 0xffff)
1551 + (p_r1 >> 16 & 0xff00);
1552 break;
1553 case 2:
1554 crc = p_r + (p_r1 >> 16);
1555 break;
1556 case 3:
1557 crc = p_r + (p_r1 & 0xff00) + (p_r1 >> 16);
1558 break;
1559 default: /*NOTREACHED*/ crc = 0;
1560 }
1561 if (crc & 0xffff0000) {
1562 crc &= 0xffff;
1563 ++crc;
1564 }
1565 /* tcp/udp will add in pseudo */
1566 skb->csum = ntohs(pfck & 0xffff);
1567 if (skb->csum > crc)
1568 skb->csum -= crc;
1569 else
1570 skb->csum += (~crc & 0xffff);
1571 /*
1572 * could do the pseudo myself and return
1573 * CHECKSUM_UNNECESSARY
1574 */
1575 skb->ip_summed = CHECKSUM_COMPLETE;
1576 }
1577 }
1578 }
1579#endif /* RX_CHECKSUM */
1580
1581 netif_rx(skb);
1582 dev->stats.rx_packets++;
1583 }
1584 entry = (++hmp->cur_rx) % RX_RING_SIZE;
1585 }
1586
1587 /* Refill the Rx ring buffers. */
1588 for (; hmp->cur_rx - hmp->dirty_rx > 0; hmp->dirty_rx++) {
1589 struct hamachi_desc *desc;
1590
1591 entry = hmp->dirty_rx % RX_RING_SIZE;
1592 desc = &(hmp->rx_ring[entry]);
1593 if (hmp->rx_skbuff[entry] == NULL) {
1594 struct sk_buff *skb = dev_alloc_skb(hmp->rx_buf_sz + 2);
1595
1596 hmp->rx_skbuff[entry] = skb;
1597 if (skb == NULL)
1598 break; /* Better luck next round. */
1599 skb->dev = dev; /* Mark as being used by this device. */
1600 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1601 desc->addr = cpu_to_leXX(pci_map_single(hmp->pci_dev,
1602 skb->data, hmp->rx_buf_sz, PCI_DMA_FROMDEVICE));
1603 }
1604 desc->status_n_length = cpu_to_le32(hmp->rx_buf_sz);
1605 if (entry >= RX_RING_SIZE-1)
1606 desc->status_n_length |= cpu_to_le32(DescOwn |
1607 DescEndPacket | DescEndRing | DescIntr);
1608 else
1609 desc->status_n_length |= cpu_to_le32(DescOwn |
1610 DescEndPacket | DescIntr);
1611 }
1612
1613 /* Restart Rx engine if stopped. */
1614 /* If we don't need to check status, don't. -KDU */
1615 if (readw(hmp->base + RxStatus) & 0x0002)
1616 writew(0x0001, hmp->base + RxCmd);
1617
1618 return 0;
1619}
1620
1621/* This is more properly named "uncommon interrupt events", as it covers more
1622 than just errors. */
1623static void hamachi_error(struct net_device *dev, int intr_status)
1624{
1625 struct hamachi_private *hmp = netdev_priv(dev);
1626 void __iomem *ioaddr = hmp->base;
1627
1628 if (intr_status & (LinkChange|NegotiationChange)) {
1629 if (hamachi_debug > 1)
1630 printk(KERN_INFO "%s: Link changed: AutoNegotiation Ctrl"
1631 " %4.4x, Status %4.4x %4.4x Intr status %4.4x.\n",
1632 dev->name, readw(ioaddr + 0x0E0), readw(ioaddr + 0x0E2),
1633 readw(ioaddr + ANLinkPartnerAbility),
1634 readl(ioaddr + IntrStatus));
1635 if (readw(ioaddr + ANStatus) & 0x20)
1636 writeb(0x01, ioaddr + LEDCtrl);
1637 else
1638 writeb(0x03, ioaddr + LEDCtrl);
1639 }
1640 if (intr_status & StatsMax) {
1641 hamachi_get_stats(dev);
1642 /* Read the overflow bits to clear. */
1643 readl(ioaddr + 0x370);
1644 readl(ioaddr + 0x3F0);
1645 }
1646 if ((intr_status & ~(LinkChange|StatsMax|NegotiationChange|IntrRxDone|IntrTxDone)) &&
1647 hamachi_debug)
1648 printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n",
1649 dev->name, intr_status);
1650 /* Hmmmmm, it's not clear how to recover from PCI faults. */
1651 if (intr_status & (IntrTxPCIErr | IntrTxPCIFault))
1652 dev->stats.tx_fifo_errors++;
1653 if (intr_status & (IntrRxPCIErr | IntrRxPCIFault))
1654 dev->stats.rx_fifo_errors++;
1655}
1656
1657static int hamachi_close(struct net_device *dev)
1658{
1659 struct hamachi_private *hmp = netdev_priv(dev);
1660 void __iomem *ioaddr = hmp->base;
1661 struct sk_buff *skb;
1662 int i;
1663
1664 netif_stop_queue(dev);
1665
1666 if (hamachi_debug > 1) {
1667 printk(KERN_DEBUG "%s: Shutting down ethercard, status was Tx %4.4x Rx %4.4x Int %2.2x.\n",
1668 dev->name, readw(ioaddr + TxStatus),
1669 readw(ioaddr + RxStatus), readl(ioaddr + IntrStatus));
1670 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1671 dev->name, hmp->cur_tx, hmp->dirty_tx, hmp->cur_rx, hmp->dirty_rx);
1672 }
1673
1674 /* Disable interrupts by clearing the interrupt mask. */
1675 writel(0x0000, ioaddr + InterruptEnable);
1676
1677 /* Stop the chip's Tx and Rx processes. */
1678 writel(2, ioaddr + RxCmd);
1679 writew(2, ioaddr + TxCmd);
1680
1681#ifdef __i386__
1682 if (hamachi_debug > 2) {
1683 printk(KERN_DEBUG " Tx ring at %8.8x:\n",
1684 (int)hmp->tx_ring_dma);
1685 for (i = 0; i < TX_RING_SIZE; i++)
1686 printk(KERN_DEBUG " %c #%d desc. %8.8x %8.8x.\n",
1687 readl(ioaddr + TxCurPtr) == (long)&hmp->tx_ring[i] ? '>' : ' ',
1688 i, hmp->tx_ring[i].status_n_length, hmp->tx_ring[i].addr);
1689 printk(KERN_DEBUG " Rx ring %8.8x:\n",
1690 (int)hmp->rx_ring_dma);
1691 for (i = 0; i < RX_RING_SIZE; i++) {
1692 printk(KERN_DEBUG " %c #%d desc. %4.4x %8.8x\n",
1693 readl(ioaddr + RxCurPtr) == (long)&hmp->rx_ring[i] ? '>' : ' ',
1694 i, hmp->rx_ring[i].status_n_length, hmp->rx_ring[i].addr);
1695 if (hamachi_debug > 6) {
1696 if (*(u8*)hmp->rx_skbuff[i]->data != 0x69) {
1697 u16 *addr = (u16 *)
1698 hmp->rx_skbuff[i]->data;
1699 int j;
1700 printk(KERN_DEBUG "Addr: ");
1701 for (j = 0; j < 0x50; j++)
1702 printk(" %4.4x", addr[j]);
1703 printk("\n");
1704 }
1705 }
1706 }
1707 }
1708#endif /* __i386__ debugging only */
1709
1710 free_irq(dev->irq, dev);
1711
1712 del_timer_sync(&hmp->timer);
1713
1714 /* Free all the skbuffs in the Rx queue. */
1715 for (i = 0; i < RX_RING_SIZE; i++) {
1716 skb = hmp->rx_skbuff[i];
1717 hmp->rx_ring[i].status_n_length = 0;
1718 if (skb) {
1719 pci_unmap_single(hmp->pci_dev,
1720 leXX_to_cpu(hmp->rx_ring[i].addr),
1721 hmp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1722 dev_kfree_skb(skb);
1723 hmp->rx_skbuff[i] = NULL;
1724 }
1725 hmp->rx_ring[i].addr = cpu_to_leXX(0xBADF00D0); /* An invalid address. */
1726 }
1727 for (i = 0; i < TX_RING_SIZE; i++) {
1728 skb = hmp->tx_skbuff[i];
1729 if (skb) {
1730 pci_unmap_single(hmp->pci_dev,
1731 leXX_to_cpu(hmp->tx_ring[i].addr),
1732 skb->len, PCI_DMA_TODEVICE);
1733 dev_kfree_skb(skb);
1734 hmp->tx_skbuff[i] = NULL;
1735 }
1736 }
1737
1738 writeb(0x00, ioaddr + LEDCtrl);
1739
1740 return 0;
1741}
1742
1743static struct net_device_stats *hamachi_get_stats(struct net_device *dev)
1744{
1745 struct hamachi_private *hmp = netdev_priv(dev);
1746 void __iomem *ioaddr = hmp->base;
1747
1748 /* We should lock this segment of code for SMP eventually, although
1749 the vulnerability window is very small and statistics are
1750 non-critical. */
1751 /* Ok, what goes here? This appears to be stuck at 21 packets
1752 according to ifconfig. It does get incremented in hamachi_tx(),
1753 so I think I'll comment it out here and see if better things
1754 happen.
1755 */
1756 /* dev->stats.tx_packets = readl(ioaddr + 0x000); */
1757
1758 /* Total Uni+Brd+Multi */
1759 dev->stats.rx_bytes = readl(ioaddr + 0x330);
1760 /* Total Uni+Brd+Multi */
1761 dev->stats.tx_bytes = readl(ioaddr + 0x3B0);
1762 /* Multicast Rx */
1763 dev->stats.multicast = readl(ioaddr + 0x320);
1764
1765 /* Over+Undersized */
1766 dev->stats.rx_length_errors = readl(ioaddr + 0x368);
1767 /* Jabber */
1768 dev->stats.rx_over_errors = readl(ioaddr + 0x35C);
1769 /* Jabber */
1770 dev->stats.rx_crc_errors = readl(ioaddr + 0x360);
1771 /* Symbol Errs */
1772 dev->stats.rx_frame_errors = readl(ioaddr + 0x364);
1773 /* Dropped */
1774 dev->stats.rx_missed_errors = readl(ioaddr + 0x36C);
1775
1776 return &dev->stats;
1777}
1778
1779static void set_rx_mode(struct net_device *dev)
1780{
1781 struct hamachi_private *hmp = netdev_priv(dev);
1782 void __iomem *ioaddr = hmp->base;
1783
1784 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1785 writew(0x000F, ioaddr + AddrMode);
1786 } else if ((netdev_mc_count(dev) > 63) || (dev->flags & IFF_ALLMULTI)) {
1787 /* Too many to match, or accept all multicasts. */
1788 writew(0x000B, ioaddr + AddrMode);
1789 } else if (!netdev_mc_empty(dev)) { /* Must use the CAM filter. */
1790 struct netdev_hw_addr *ha;
1791 int i = 0;
1792
1793 netdev_for_each_mc_addr(ha, dev) {
1794 writel(*(u32 *)(ha->addr), ioaddr + 0x100 + i*8);
1795 writel(0x20000 | (*(u16 *)&ha->addr[4]),
1796 ioaddr + 0x104 + i*8);
1797 i++;
1798 }
1799 /* Clear remaining entries. */
1800 for (; i < 64; i++)
1801 writel(0, ioaddr + 0x104 + i*8);
1802 writew(0x0003, ioaddr + AddrMode);
1803 } else { /* Normal, unicast/broadcast-only mode. */
1804 writew(0x0001, ioaddr + AddrMode);
1805 }
1806}
1807
1808static int check_if_running(struct net_device *dev)
1809{
1810 if (!netif_running(dev))
1811 return -EINVAL;
1812 return 0;
1813}
1814
1815static void hamachi_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1816{
1817 struct hamachi_private *np = netdev_priv(dev);
1818 strcpy(info->driver, DRV_NAME);
1819 strcpy(info->version, DRV_VERSION);
1820 strcpy(info->bus_info, pci_name(np->pci_dev));
1821}
1822
1823static int hamachi_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1824{
1825 struct hamachi_private *np = netdev_priv(dev);
1826 spin_lock_irq(&np->lock);
1827 mii_ethtool_gset(&np->mii_if, ecmd);
1828 spin_unlock_irq(&np->lock);
1829 return 0;
1830}
1831
1832static int hamachi_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1833{
1834 struct hamachi_private *np = netdev_priv(dev);
1835 int res;
1836 spin_lock_irq(&np->lock);
1837 res = mii_ethtool_sset(&np->mii_if, ecmd);
1838 spin_unlock_irq(&np->lock);
1839 return res;
1840}
1841
1842static int hamachi_nway_reset(struct net_device *dev)
1843{
1844 struct hamachi_private *np = netdev_priv(dev);
1845 return mii_nway_restart(&np->mii_if);
1846}
1847
1848static u32 hamachi_get_link(struct net_device *dev)
1849{
1850 struct hamachi_private *np = netdev_priv(dev);
1851 return mii_link_ok(&np->mii_if);
1852}
1853
1854static const struct ethtool_ops ethtool_ops = {
1855 .begin = check_if_running,
1856 .get_drvinfo = hamachi_get_drvinfo,
1857 .get_settings = hamachi_get_settings,
1858 .set_settings = hamachi_set_settings,
1859 .nway_reset = hamachi_nway_reset,
1860 .get_link = hamachi_get_link,
1861};
1862
1863static const struct ethtool_ops ethtool_ops_no_mii = {
1864 .begin = check_if_running,
1865 .get_drvinfo = hamachi_get_drvinfo,
1866};
1867
1868static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1869{
1870 struct hamachi_private *np = netdev_priv(dev);
1871 struct mii_ioctl_data *data = if_mii(rq);
1872 int rc;
1873
1874 if (!netif_running(dev))
1875 return -EINVAL;
1876
1877 if (cmd == (SIOCDEVPRIVATE+3)) { /* set rx,tx intr params */
1878 u32 *d = (u32 *)&rq->ifr_ifru;
1879 /* Should add this check here or an ordinary user can do nasty
1880 * things. -KDU
1881 *
1882 * TODO: Shut down the Rx and Tx engines while doing this.
1883 */
1884 if (!capable(CAP_NET_ADMIN))
1885 return -EPERM;
1886 writel(d[0], np->base + TxIntrCtrl);
1887 writel(d[1], np->base + RxIntrCtrl);
1888 printk(KERN_NOTICE "%s: tx %08x, rx %08x intr\n", dev->name,
1889 (u32) readl(np->base + TxIntrCtrl),
1890 (u32) readl(np->base + RxIntrCtrl));
1891 rc = 0;
1892 }
1893
1894 else {
1895 spin_lock_irq(&np->lock);
1896 rc = generic_mii_ioctl(&np->mii_if, data, cmd, NULL);
1897 spin_unlock_irq(&np->lock);
1898 }
1899
1900 return rc;
1901}
1902
1903
1904static void __devexit hamachi_remove_one (struct pci_dev *pdev)
1905{
1906 struct net_device *dev = pci_get_drvdata(pdev);
1907
1908 if (dev) {
1909 struct hamachi_private *hmp = netdev_priv(dev);
1910
1911 pci_free_consistent(pdev, RX_TOTAL_SIZE, hmp->rx_ring,
1912 hmp->rx_ring_dma);
1913 pci_free_consistent(pdev, TX_TOTAL_SIZE, hmp->tx_ring,
1914 hmp->tx_ring_dma);
1915 unregister_netdev(dev);
1916 iounmap(hmp->base);
1917 free_netdev(dev);
1918 pci_release_regions(pdev);
1919 pci_set_drvdata(pdev, NULL);
1920 }
1921}
1922
1923static DEFINE_PCI_DEVICE_TABLE(hamachi_pci_tbl) = {
1924 { 0x1318, 0x0911, PCI_ANY_ID, PCI_ANY_ID, },
1925 { 0, }
1926};
1927MODULE_DEVICE_TABLE(pci, hamachi_pci_tbl);
1928
1929static struct pci_driver hamachi_driver = {
1930 .name = DRV_NAME,
1931 .id_table = hamachi_pci_tbl,
1932 .probe = hamachi_init_one,
1933 .remove = __devexit_p(hamachi_remove_one),
1934};
1935
1936static int __init hamachi_init (void)
1937{
1938/* when a module, this is printed whether or not devices are found in probe */
1939#ifdef MODULE
1940 printk(version);
1941#endif
1942 return pci_register_driver(&hamachi_driver);
1943}
1944
1945static void __exit hamachi_exit (void)
1946{
1947 pci_unregister_driver(&hamachi_driver);
1948}
1949
1950
1951module_init(hamachi_init);
1952module_exit(hamachi_exit);
diff --git a/drivers/net/ethernet/packetengines/yellowfin.c b/drivers/net/ethernet/packetengines/yellowfin.c
new file mode 100644
index 000000000000..3e5ac60b89ac
--- /dev/null
+++ b/drivers/net/ethernet/packetengines/yellowfin.c
@@ -0,0 +1,1430 @@
1/* yellowfin.c: A Packet Engines G-NIC ethernet driver for linux. */
2/*
3 Written 1997-2001 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 This driver is for the Packet Engines G-NIC PCI Gigabit Ethernet adapter.
13 It also supports the Symbios Logic version of the same chip core.
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20 Support and updates available at
21 http://www.scyld.com/network/yellowfin.html
22 [link no longer provides useful info -jgarzik]
23
24*/
25
26#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27
28#define DRV_NAME "yellowfin"
29#define DRV_VERSION "2.1"
30#define DRV_RELDATE "Sep 11, 2006"
31
32/* The user-configurable values.
33 These may be modified when a driver module is loaded.*/
34
35static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
36/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
37static int max_interrupt_work = 20;
38static int mtu;
39#ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
40/* System-wide count of bogus-rx frames. */
41static int bogus_rx;
42static int dma_ctrl = 0x004A0263; /* Constrained by errata */
43static int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
44#elif defined(YF_NEW) /* A future perfect board :->. */
45static int dma_ctrl = 0x00CAC277; /* Override when loading module! */
46static int fifo_cfg = 0x0028;
47#else
48static const int dma_ctrl = 0x004A0263; /* Constrained by errata */
49static const int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
50#endif
51
52/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
53 Setting to > 1514 effectively disables this feature. */
54static int rx_copybreak;
55
56/* Used to pass the media type, etc.
57 No media types are currently defined. These exist for driver
58 interoperability.
59*/
60#define MAX_UNITS 8 /* More are supported, limit only on options */
61static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
62static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
63
64/* Do ugly workaround for GX server chipset errata. */
65static int gx_fix;
66
67/* Operational parameters that are set at compile time. */
68
69/* Keep the ring sizes a power of two for efficiency.
70 Making the Tx ring too long decreases the effectiveness of channel
71 bonding and packet priority.
72 There are no ill effects from too-large receive rings. */
73#define TX_RING_SIZE 16
74#define TX_QUEUE_SIZE 12 /* Must be > 4 && <= TX_RING_SIZE */
75#define RX_RING_SIZE 64
76#define STATUS_TOTAL_SIZE TX_RING_SIZE*sizeof(struct tx_status_words)
77#define TX_TOTAL_SIZE 2*TX_RING_SIZE*sizeof(struct yellowfin_desc)
78#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct yellowfin_desc)
79
80/* Operational parameters that usually are not changed. */
81/* Time in jiffies before concluding the transmitter is hung. */
82#define TX_TIMEOUT (2*HZ)
83#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
84
85#define yellowfin_debug debug
86
87#include <linux/module.h>
88#include <linux/kernel.h>
89#include <linux/string.h>
90#include <linux/timer.h>
91#include <linux/errno.h>
92#include <linux/ioport.h>
93#include <linux/interrupt.h>
94#include <linux/pci.h>
95#include <linux/init.h>
96#include <linux/mii.h>
97#include <linux/netdevice.h>
98#include <linux/etherdevice.h>
99#include <linux/skbuff.h>
100#include <linux/ethtool.h>
101#include <linux/crc32.h>
102#include <linux/bitops.h>
103#include <asm/uaccess.h>
104#include <asm/processor.h> /* Processor type for cache alignment. */
105#include <asm/unaligned.h>
106#include <asm/io.h>
107
108/* These identify the driver base version and may not be removed. */
109static const char version[] __devinitconst =
110 KERN_INFO DRV_NAME ".c:v1.05 1/09/2001 Written by Donald Becker <becker@scyld.com>\n"
111 " (unofficial 2.4.x port, " DRV_VERSION ", " DRV_RELDATE ")\n";
112
113MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
114MODULE_DESCRIPTION("Packet Engines Yellowfin G-NIC Gigabit Ethernet driver");
115MODULE_LICENSE("GPL");
116
117module_param(max_interrupt_work, int, 0);
118module_param(mtu, int, 0);
119module_param(debug, int, 0);
120module_param(rx_copybreak, int, 0);
121module_param_array(options, int, NULL, 0);
122module_param_array(full_duplex, int, NULL, 0);
123module_param(gx_fix, int, 0);
124MODULE_PARM_DESC(max_interrupt_work, "G-NIC maximum events handled per interrupt");
125MODULE_PARM_DESC(mtu, "G-NIC MTU (all boards)");
126MODULE_PARM_DESC(debug, "G-NIC debug level (0-7)");
127MODULE_PARM_DESC(rx_copybreak, "G-NIC copy breakpoint for copy-only-tiny-frames");
128MODULE_PARM_DESC(options, "G-NIC: Bits 0-3: media type, bit 17: full duplex");
129MODULE_PARM_DESC(full_duplex, "G-NIC full duplex setting(s) (1)");
130MODULE_PARM_DESC(gx_fix, "G-NIC: enable GX server chipset bug workaround (0-1)");
131
132/*
133 Theory of Operation
134
135I. Board Compatibility
136
137This device driver is designed for the Packet Engines "Yellowfin" Gigabit
138Ethernet adapter. The G-NIC 64-bit PCI card is supported, as well as the
139Symbios 53C885E dual function chip.
140
141II. Board-specific settings
142
143PCI bus devices are configured by the system at boot time, so no jumpers
144need to be set on the board. The system BIOS preferably should assign the
145PCI INTA signal to an otherwise unused system IRQ line.
146Note: Kernel versions earlier than 1.3.73 do not support shared PCI
147interrupt lines.
148
149III. Driver operation
150
151IIIa. Ring buffers
152
153The Yellowfin uses the Descriptor Based DMA Architecture specified by Apple.
154This is a descriptor list scheme similar to that used by the EEPro100 and
155Tulip. This driver uses two statically allocated fixed-size descriptor lists
156formed into rings by a branch from the final descriptor to the beginning of
157the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
158
159The driver allocates full frame size skbuffs for the Rx ring buffers at
160open() time and passes the skb->data field to the Yellowfin as receive data
161buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
162a fresh skbuff is allocated and the frame is copied to the new skbuff.
163When the incoming frame is larger, the skbuff is passed directly up the
164protocol stack and replaced by a newly allocated skbuff.
165
166The RX_COPYBREAK value is chosen to trade-off the memory wasted by
167using a full-sized skbuff for small frames vs. the copying costs of larger
168frames. For small frames the copying cost is negligible (esp. considering
169that we are pre-loading the cache with immediately useful header
170information). For large frames the copying cost is non-trivial, and the
171larger copy might flush the cache of useful data.
172
173IIIC. Synchronization
174
175The driver runs as two independent, single-threaded flows of control. One
176is the send-packet routine, which enforces single-threaded use by the
177dev->tbusy flag. The other thread is the interrupt handler, which is single
178threaded by the hardware and other software.
179
180The send packet thread has partial control over the Tx ring and 'dev->tbusy'
181flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
182queue slot is empty, it clears the tbusy flag when finished otherwise it sets
183the 'yp->tx_full' flag.
184
185The interrupt handler has exclusive control over the Rx ring and records stats
186from the Tx ring. After reaping the stats, it marks the Tx queue entry as
187empty by incrementing the dirty_tx mark. Iff the 'yp->tx_full' flag is set, it
188clears both the tx_full and tbusy flags.
189
190IV. Notes
191
192Thanks to Kim Stearns of Packet Engines for providing a pair of G-NIC boards.
193Thanks to Bruce Faust of Digitalscape for providing both their SYM53C885 board
194and an AlphaStation to verifty the Alpha port!
195
196IVb. References
197
198Yellowfin Engineering Design Specification, 4/23/97 Preliminary/Confidential
199Symbios SYM53C885 PCI-SCSI/Fast Ethernet Multifunction Controller Preliminary
200 Data Manual v3.0
201http://cesdis.gsfc.nasa.gov/linux/misc/NWay.html
202http://cesdis.gsfc.nasa.gov/linux/misc/100mbps.html
203
204IVc. Errata
205
206See Packet Engines confidential appendix (prototype chips only).
207*/
208
209
210
211enum capability_flags {
212 HasMII=1, FullTxStatus=2, IsGigabit=4, HasMulticastBug=8, FullRxStatus=16,
213 HasMACAddrBug=32, /* Only on early revs. */
214 DontUseEeprom=64, /* Don't read the MAC from the EEPROm. */
215};
216
217/* The PCI I/O space extent. */
218enum {
219 YELLOWFIN_SIZE = 0x100,
220};
221
222struct pci_id_info {
223 const char *name;
224 struct match_info {
225 int pci, pci_mask, subsystem, subsystem_mask;
226 int revision, revision_mask; /* Only 8 bits. */
227 } id;
228 int drv_flags; /* Driver use, intended as capability flags. */
229};
230
231static const struct pci_id_info pci_id_tbl[] = {
232 {"Yellowfin G-NIC Gigabit Ethernet", { 0x07021000, 0xffffffff},
233 FullTxStatus | IsGigabit | HasMulticastBug | HasMACAddrBug | DontUseEeprom},
234 {"Symbios SYM83C885", { 0x07011000, 0xffffffff},
235 HasMII | DontUseEeprom },
236 { }
237};
238
239static DEFINE_PCI_DEVICE_TABLE(yellowfin_pci_tbl) = {
240 { 0x1000, 0x0702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
241 { 0x1000, 0x0701, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
242 { }
243};
244MODULE_DEVICE_TABLE (pci, yellowfin_pci_tbl);
245
246
247/* Offsets to the Yellowfin registers. Various sizes and alignments. */
248enum yellowfin_offsets {
249 TxCtrl=0x00, TxStatus=0x04, TxPtr=0x0C,
250 TxIntrSel=0x10, TxBranchSel=0x14, TxWaitSel=0x18,
251 RxCtrl=0x40, RxStatus=0x44, RxPtr=0x4C,
252 RxIntrSel=0x50, RxBranchSel=0x54, RxWaitSel=0x58,
253 EventStatus=0x80, IntrEnb=0x82, IntrClear=0x84, IntrStatus=0x86,
254 ChipRev=0x8C, DMACtrl=0x90, TxThreshold=0x94,
255 Cnfg=0xA0, FrameGap0=0xA2, FrameGap1=0xA4,
256 MII_Cmd=0xA6, MII_Addr=0xA8, MII_Wr_Data=0xAA, MII_Rd_Data=0xAC,
257 MII_Status=0xAE,
258 RxDepth=0xB8, FlowCtrl=0xBC,
259 AddrMode=0xD0, StnAddr=0xD2, HashTbl=0xD8, FIFOcfg=0xF8,
260 EEStatus=0xF0, EECtrl=0xF1, EEAddr=0xF2, EERead=0xF3, EEWrite=0xF4,
261 EEFeature=0xF5,
262};
263
264/* The Yellowfin Rx and Tx buffer descriptors.
265 Elements are written as 32 bit for endian portability. */
266struct yellowfin_desc {
267 __le32 dbdma_cmd;
268 __le32 addr;
269 __le32 branch_addr;
270 __le32 result_status;
271};
272
273struct tx_status_words {
274#ifdef __BIG_ENDIAN
275 u16 tx_errs;
276 u16 tx_cnt;
277 u16 paused;
278 u16 total_tx_cnt;
279#else /* Little endian chips. */
280 u16 tx_cnt;
281 u16 tx_errs;
282 u16 total_tx_cnt;
283 u16 paused;
284#endif /* __BIG_ENDIAN */
285};
286
287/* Bits in yellowfin_desc.cmd */
288enum desc_cmd_bits {
289 CMD_TX_PKT=0x10000000, CMD_RX_BUF=0x20000000, CMD_TXSTATUS=0x30000000,
290 CMD_NOP=0x60000000, CMD_STOP=0x70000000,
291 BRANCH_ALWAYS=0x0C0000, INTR_ALWAYS=0x300000, WAIT_ALWAYS=0x030000,
292 BRANCH_IFTRUE=0x040000,
293};
294
295/* Bits in yellowfin_desc.status */
296enum desc_status_bits { RX_EOP=0x0040, };
297
298/* Bits in the interrupt status/mask registers. */
299enum intr_status_bits {
300 IntrRxDone=0x01, IntrRxInvalid=0x02, IntrRxPCIFault=0x04,IntrRxPCIErr=0x08,
301 IntrTxDone=0x10, IntrTxInvalid=0x20, IntrTxPCIFault=0x40,IntrTxPCIErr=0x80,
302 IntrEarlyRx=0x100, IntrWakeup=0x200, };
303
304#define PRIV_ALIGN 31 /* Required alignment mask */
305#define MII_CNT 4
306struct yellowfin_private {
307 /* Descriptor rings first for alignment.
308 Tx requires a second descriptor for status. */
309 struct yellowfin_desc *rx_ring;
310 struct yellowfin_desc *tx_ring;
311 struct sk_buff* rx_skbuff[RX_RING_SIZE];
312 struct sk_buff* tx_skbuff[TX_RING_SIZE];
313 dma_addr_t rx_ring_dma;
314 dma_addr_t tx_ring_dma;
315
316 struct tx_status_words *tx_status;
317 dma_addr_t tx_status_dma;
318
319 struct timer_list timer; /* Media selection timer. */
320 /* Frequently used and paired value: keep adjacent for cache effect. */
321 int chip_id, drv_flags;
322 struct pci_dev *pci_dev;
323 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
324 unsigned int rx_buf_sz; /* Based on MTU+slack. */
325 struct tx_status_words *tx_tail_desc;
326 unsigned int cur_tx, dirty_tx;
327 int tx_threshold;
328 unsigned int tx_full:1; /* The Tx queue is full. */
329 unsigned int full_duplex:1; /* Full-duplex operation requested. */
330 unsigned int duplex_lock:1;
331 unsigned int medialock:1; /* Do not sense media. */
332 unsigned int default_port:4; /* Last dev->if_port value. */
333 /* MII transceiver section. */
334 int mii_cnt; /* MII device addresses. */
335 u16 advertising; /* NWay media advertisement */
336 unsigned char phys[MII_CNT]; /* MII device addresses, only first one used */
337 spinlock_t lock;
338 void __iomem *base;
339};
340
341static int read_eeprom(void __iomem *ioaddr, int location);
342static int mdio_read(void __iomem *ioaddr, int phy_id, int location);
343static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value);
344static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
345static int yellowfin_open(struct net_device *dev);
346static void yellowfin_timer(unsigned long data);
347static void yellowfin_tx_timeout(struct net_device *dev);
348static int yellowfin_init_ring(struct net_device *dev);
349static netdev_tx_t yellowfin_start_xmit(struct sk_buff *skb,
350 struct net_device *dev);
351static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance);
352static int yellowfin_rx(struct net_device *dev);
353static void yellowfin_error(struct net_device *dev, int intr_status);
354static int yellowfin_close(struct net_device *dev);
355static void set_rx_mode(struct net_device *dev);
356static const struct ethtool_ops ethtool_ops;
357
358static const struct net_device_ops netdev_ops = {
359 .ndo_open = yellowfin_open,
360 .ndo_stop = yellowfin_close,
361 .ndo_start_xmit = yellowfin_start_xmit,
362 .ndo_set_multicast_list = set_rx_mode,
363 .ndo_change_mtu = eth_change_mtu,
364 .ndo_validate_addr = eth_validate_addr,
365 .ndo_set_mac_address = eth_mac_addr,
366 .ndo_do_ioctl = netdev_ioctl,
367 .ndo_tx_timeout = yellowfin_tx_timeout,
368};
369
370static int __devinit yellowfin_init_one(struct pci_dev *pdev,
371 const struct pci_device_id *ent)
372{
373 struct net_device *dev;
374 struct yellowfin_private *np;
375 int irq;
376 int chip_idx = ent->driver_data;
377 static int find_cnt;
378 void __iomem *ioaddr;
379 int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
380 int drv_flags = pci_id_tbl[chip_idx].drv_flags;
381 void *ring_space;
382 dma_addr_t ring_dma;
383#ifdef USE_IO_OPS
384 int bar = 0;
385#else
386 int bar = 1;
387#endif
388
389/* when built into the kernel, we only print version if device is found */
390#ifndef MODULE
391 static int printed_version;
392 if (!printed_version++)
393 printk(version);
394#endif
395
396 i = pci_enable_device(pdev);
397 if (i) return i;
398
399 dev = alloc_etherdev(sizeof(*np));
400 if (!dev) {
401 pr_err("cannot allocate ethernet device\n");
402 return -ENOMEM;
403 }
404 SET_NETDEV_DEV(dev, &pdev->dev);
405
406 np = netdev_priv(dev);
407
408 if (pci_request_regions(pdev, DRV_NAME))
409 goto err_out_free_netdev;
410
411 pci_set_master (pdev);
412
413 ioaddr = pci_iomap(pdev, bar, YELLOWFIN_SIZE);
414 if (!ioaddr)
415 goto err_out_free_res;
416
417 irq = pdev->irq;
418
419 if (drv_flags & DontUseEeprom)
420 for (i = 0; i < 6; i++)
421 dev->dev_addr[i] = ioread8(ioaddr + StnAddr + i);
422 else {
423 int ee_offset = (read_eeprom(ioaddr, 6) == 0xff ? 0x100 : 0);
424 for (i = 0; i < 6; i++)
425 dev->dev_addr[i] = read_eeprom(ioaddr, ee_offset + i);
426 }
427
428 /* Reset the chip. */
429 iowrite32(0x80000000, ioaddr + DMACtrl);
430
431 dev->base_addr = (unsigned long)ioaddr;
432 dev->irq = irq;
433
434 pci_set_drvdata(pdev, dev);
435 spin_lock_init(&np->lock);
436
437 np->pci_dev = pdev;
438 np->chip_id = chip_idx;
439 np->drv_flags = drv_flags;
440 np->base = ioaddr;
441
442 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
443 if (!ring_space)
444 goto err_out_cleardev;
445 np->tx_ring = ring_space;
446 np->tx_ring_dma = ring_dma;
447
448 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
449 if (!ring_space)
450 goto err_out_unmap_tx;
451 np->rx_ring = ring_space;
452 np->rx_ring_dma = ring_dma;
453
454 ring_space = pci_alloc_consistent(pdev, STATUS_TOTAL_SIZE, &ring_dma);
455 if (!ring_space)
456 goto err_out_unmap_rx;
457 np->tx_status = ring_space;
458 np->tx_status_dma = ring_dma;
459
460 if (dev->mem_start)
461 option = dev->mem_start;
462
463 /* The lower four bits are the media type. */
464 if (option > 0) {
465 if (option & 0x200)
466 np->full_duplex = 1;
467 np->default_port = option & 15;
468 if (np->default_port)
469 np->medialock = 1;
470 }
471 if (find_cnt < MAX_UNITS && full_duplex[find_cnt] > 0)
472 np->full_duplex = 1;
473
474 if (np->full_duplex)
475 np->duplex_lock = 1;
476
477 /* The Yellowfin-specific entries in the device structure. */
478 dev->netdev_ops = &netdev_ops;
479 SET_ETHTOOL_OPS(dev, &ethtool_ops);
480 dev->watchdog_timeo = TX_TIMEOUT;
481
482 if (mtu)
483 dev->mtu = mtu;
484
485 i = register_netdev(dev);
486 if (i)
487 goto err_out_unmap_status;
488
489 netdev_info(dev, "%s type %8x at %p, %pM, IRQ %d\n",
490 pci_id_tbl[chip_idx].name,
491 ioread32(ioaddr + ChipRev), ioaddr,
492 dev->dev_addr, irq);
493
494 if (np->drv_flags & HasMII) {
495 int phy, phy_idx = 0;
496 for (phy = 0; phy < 32 && phy_idx < MII_CNT; phy++) {
497 int mii_status = mdio_read(ioaddr, phy, 1);
498 if (mii_status != 0xffff && mii_status != 0x0000) {
499 np->phys[phy_idx++] = phy;
500 np->advertising = mdio_read(ioaddr, phy, 4);
501 netdev_info(dev, "MII PHY found at address %d, status 0x%04x advertising %04x\n",
502 phy, mii_status, np->advertising);
503 }
504 }
505 np->mii_cnt = phy_idx;
506 }
507
508 find_cnt++;
509
510 return 0;
511
512err_out_unmap_status:
513 pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status,
514 np->tx_status_dma);
515err_out_unmap_rx:
516 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
517err_out_unmap_tx:
518 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
519err_out_cleardev:
520 pci_set_drvdata(pdev, NULL);
521 pci_iounmap(pdev, ioaddr);
522err_out_free_res:
523 pci_release_regions(pdev);
524err_out_free_netdev:
525 free_netdev (dev);
526 return -ENODEV;
527}
528
529static int __devinit read_eeprom(void __iomem *ioaddr, int location)
530{
531 int bogus_cnt = 10000; /* Typical 33Mhz: 1050 ticks */
532
533 iowrite8(location, ioaddr + EEAddr);
534 iowrite8(0x30 | ((location >> 8) & 7), ioaddr + EECtrl);
535 while ((ioread8(ioaddr + EEStatus) & 0x80) && --bogus_cnt > 0)
536 ;
537 return ioread8(ioaddr + EERead);
538}
539
540/* MII Managemen Data I/O accesses.
541 These routines assume the MDIO controller is idle, and do not exit until
542 the command is finished. */
543
544static int mdio_read(void __iomem *ioaddr, int phy_id, int location)
545{
546 int i;
547
548 iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);
549 iowrite16(1, ioaddr + MII_Cmd);
550 for (i = 10000; i >= 0; i--)
551 if ((ioread16(ioaddr + MII_Status) & 1) == 0)
552 break;
553 return ioread16(ioaddr + MII_Rd_Data);
554}
555
556static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value)
557{
558 int i;
559
560 iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);
561 iowrite16(value, ioaddr + MII_Wr_Data);
562
563 /* Wait for the command to finish. */
564 for (i = 10000; i >= 0; i--)
565 if ((ioread16(ioaddr + MII_Status) & 1) == 0)
566 break;
567}
568
569
570static int yellowfin_open(struct net_device *dev)
571{
572 struct yellowfin_private *yp = netdev_priv(dev);
573 void __iomem *ioaddr = yp->base;
574 int i, ret;
575
576 /* Reset the chip. */
577 iowrite32(0x80000000, ioaddr + DMACtrl);
578
579 ret = request_irq(dev->irq, yellowfin_interrupt, IRQF_SHARED, dev->name, dev);
580 if (ret)
581 return ret;
582
583 if (yellowfin_debug > 1)
584 netdev_printk(KERN_DEBUG, dev, "%s() irq %d\n",
585 __func__, dev->irq);
586
587 ret = yellowfin_init_ring(dev);
588 if (ret) {
589 free_irq(dev->irq, dev);
590 return ret;
591 }
592
593 iowrite32(yp->rx_ring_dma, ioaddr + RxPtr);
594 iowrite32(yp->tx_ring_dma, ioaddr + TxPtr);
595
596 for (i = 0; i < 6; i++)
597 iowrite8(dev->dev_addr[i], ioaddr + StnAddr + i);
598
599 /* Set up various condition 'select' registers.
600 There are no options here. */
601 iowrite32(0x00800080, ioaddr + TxIntrSel); /* Interrupt on Tx abort */
602 iowrite32(0x00800080, ioaddr + TxBranchSel); /* Branch on Tx abort */
603 iowrite32(0x00400040, ioaddr + TxWaitSel); /* Wait on Tx status */
604 iowrite32(0x00400040, ioaddr + RxIntrSel); /* Interrupt on Rx done */
605 iowrite32(0x00400040, ioaddr + RxBranchSel); /* Branch on Rx error */
606 iowrite32(0x00400040, ioaddr + RxWaitSel); /* Wait on Rx done */
607
608 /* Initialize other registers: with so many this eventually this will
609 converted to an offset/value list. */
610 iowrite32(dma_ctrl, ioaddr + DMACtrl);
611 iowrite16(fifo_cfg, ioaddr + FIFOcfg);
612 /* Enable automatic generation of flow control frames, period 0xffff. */
613 iowrite32(0x0030FFFF, ioaddr + FlowCtrl);
614
615 yp->tx_threshold = 32;
616 iowrite32(yp->tx_threshold, ioaddr + TxThreshold);
617
618 if (dev->if_port == 0)
619 dev->if_port = yp->default_port;
620
621 netif_start_queue(dev);
622
623 /* Setting the Rx mode will start the Rx process. */
624 if (yp->drv_flags & IsGigabit) {
625 /* We are always in full-duplex mode with gigabit! */
626 yp->full_duplex = 1;
627 iowrite16(0x01CF, ioaddr + Cnfg);
628 } else {
629 iowrite16(0x0018, ioaddr + FrameGap0); /* 0060/4060 for non-MII 10baseT */
630 iowrite16(0x1018, ioaddr + FrameGap1);
631 iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
632 }
633 set_rx_mode(dev);
634
635 /* Enable interrupts by setting the interrupt mask. */
636 iowrite16(0x81ff, ioaddr + IntrEnb); /* See enum intr_status_bits */
637 iowrite16(0x0000, ioaddr + EventStatus); /* Clear non-interrupting events */
638 iowrite32(0x80008000, ioaddr + RxCtrl); /* Start Rx and Tx channels. */
639 iowrite32(0x80008000, ioaddr + TxCtrl);
640
641 if (yellowfin_debug > 2) {
642 netdev_printk(KERN_DEBUG, dev, "Done %s()\n", __func__);
643 }
644
645 /* Set the timer to check for link beat. */
646 init_timer(&yp->timer);
647 yp->timer.expires = jiffies + 3*HZ;
648 yp->timer.data = (unsigned long)dev;
649 yp->timer.function = yellowfin_timer; /* timer handler */
650 add_timer(&yp->timer);
651
652 return 0;
653}
654
655static void yellowfin_timer(unsigned long data)
656{
657 struct net_device *dev = (struct net_device *)data;
658 struct yellowfin_private *yp = netdev_priv(dev);
659 void __iomem *ioaddr = yp->base;
660 int next_tick = 60*HZ;
661
662 if (yellowfin_debug > 3) {
663 netdev_printk(KERN_DEBUG, dev, "Yellowfin timer tick, status %08x\n",
664 ioread16(ioaddr + IntrStatus));
665 }
666
667 if (yp->mii_cnt) {
668 int bmsr = mdio_read(ioaddr, yp->phys[0], MII_BMSR);
669 int lpa = mdio_read(ioaddr, yp->phys[0], MII_LPA);
670 int negotiated = lpa & yp->advertising;
671 if (yellowfin_debug > 1)
672 netdev_printk(KERN_DEBUG, dev, "MII #%d status register is %04x, link partner capability %04x\n",
673 yp->phys[0], bmsr, lpa);
674
675 yp->full_duplex = mii_duplex(yp->duplex_lock, negotiated);
676
677 iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
678
679 if (bmsr & BMSR_LSTATUS)
680 next_tick = 60*HZ;
681 else
682 next_tick = 3*HZ;
683 }
684
685 yp->timer.expires = jiffies + next_tick;
686 add_timer(&yp->timer);
687}
688
689static void yellowfin_tx_timeout(struct net_device *dev)
690{
691 struct yellowfin_private *yp = netdev_priv(dev);
692 void __iomem *ioaddr = yp->base;
693
694 netdev_warn(dev, "Yellowfin transmit timed out at %d/%d Tx status %04x, Rx status %04x, resetting...\n",
695 yp->cur_tx, yp->dirty_tx,
696 ioread32(ioaddr + TxStatus),
697 ioread32(ioaddr + RxStatus));
698
699 /* Note: these should be KERN_DEBUG. */
700 if (yellowfin_debug) {
701 int i;
702 pr_warning(" Rx ring %p: ", yp->rx_ring);
703 for (i = 0; i < RX_RING_SIZE; i++)
704 pr_cont(" %08x", yp->rx_ring[i].result_status);
705 pr_cont("\n");
706 pr_warning(" Tx ring %p: ", yp->tx_ring);
707 for (i = 0; i < TX_RING_SIZE; i++)
708 pr_cont(" %04x /%08x",
709 yp->tx_status[i].tx_errs,
710 yp->tx_ring[i].result_status);
711 pr_cont("\n");
712 }
713
714 /* If the hardware is found to hang regularly, we will update the code
715 to reinitialize the chip here. */
716 dev->if_port = 0;
717
718 /* Wake the potentially-idle transmit channel. */
719 iowrite32(0x10001000, yp->base + TxCtrl);
720 if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
721 netif_wake_queue (dev); /* Typical path */
722
723 dev->trans_start = jiffies; /* prevent tx timeout */
724 dev->stats.tx_errors++;
725}
726
727/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
728static int yellowfin_init_ring(struct net_device *dev)
729{
730 struct yellowfin_private *yp = netdev_priv(dev);
731 int i, j;
732
733 yp->tx_full = 0;
734 yp->cur_rx = yp->cur_tx = 0;
735 yp->dirty_tx = 0;
736
737 yp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
738
739 for (i = 0; i < RX_RING_SIZE; i++) {
740 yp->rx_ring[i].dbdma_cmd =
741 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz);
742 yp->rx_ring[i].branch_addr = cpu_to_le32(yp->rx_ring_dma +
743 ((i+1)%RX_RING_SIZE)*sizeof(struct yellowfin_desc));
744 }
745
746 for (i = 0; i < RX_RING_SIZE; i++) {
747 struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz + 2);
748 yp->rx_skbuff[i] = skb;
749 if (skb == NULL)
750 break;
751 skb->dev = dev; /* Mark as being used by this device. */
752 skb_reserve(skb, 2); /* 16 byte align the IP header. */
753 yp->rx_ring[i].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
754 skb->data, yp->rx_buf_sz, PCI_DMA_FROMDEVICE));
755 }
756 if (i != RX_RING_SIZE) {
757 for (j = 0; j < i; j++)
758 dev_kfree_skb(yp->rx_skbuff[j]);
759 return -ENOMEM;
760 }
761 yp->rx_ring[i-1].dbdma_cmd = cpu_to_le32(CMD_STOP);
762 yp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
763
764#define NO_TXSTATS
765#ifdef NO_TXSTATS
766 /* In this mode the Tx ring needs only a single descriptor. */
767 for (i = 0; i < TX_RING_SIZE; i++) {
768 yp->tx_skbuff[i] = NULL;
769 yp->tx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
770 yp->tx_ring[i].branch_addr = cpu_to_le32(yp->tx_ring_dma +
771 ((i+1)%TX_RING_SIZE)*sizeof(struct yellowfin_desc));
772 }
773 /* Wrap ring */
774 yp->tx_ring[--i].dbdma_cmd = cpu_to_le32(CMD_STOP | BRANCH_ALWAYS);
775#else
776{
777 /* Tx ring needs a pair of descriptors, the second for the status. */
778 for (i = 0; i < TX_RING_SIZE; i++) {
779 j = 2*i;
780 yp->tx_skbuff[i] = 0;
781 /* Branch on Tx error. */
782 yp->tx_ring[j].dbdma_cmd = cpu_to_le32(CMD_STOP);
783 yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
784 (j+1)*sizeof(struct yellowfin_desc));
785 j++;
786 if (yp->flags & FullTxStatus) {
787 yp->tx_ring[j].dbdma_cmd =
788 cpu_to_le32(CMD_TXSTATUS | sizeof(*yp->tx_status));
789 yp->tx_ring[j].request_cnt = sizeof(*yp->tx_status);
790 yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
791 i*sizeof(struct tx_status_words));
792 } else {
793 /* Symbios chips write only tx_errs word. */
794 yp->tx_ring[j].dbdma_cmd =
795 cpu_to_le32(CMD_TXSTATUS | INTR_ALWAYS | 2);
796 yp->tx_ring[j].request_cnt = 2;
797 /* Om pade ummmmm... */
798 yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
799 i*sizeof(struct tx_status_words) +
800 &(yp->tx_status[0].tx_errs) -
801 &(yp->tx_status[0]));
802 }
803 yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
804 ((j+1)%(2*TX_RING_SIZE))*sizeof(struct yellowfin_desc));
805 }
806 /* Wrap ring */
807 yp->tx_ring[++j].dbdma_cmd |= cpu_to_le32(BRANCH_ALWAYS | INTR_ALWAYS);
808}
809#endif
810 yp->tx_tail_desc = &yp->tx_status[0];
811 return 0;
812}
813
814static netdev_tx_t yellowfin_start_xmit(struct sk_buff *skb,
815 struct net_device *dev)
816{
817 struct yellowfin_private *yp = netdev_priv(dev);
818 unsigned entry;
819 int len = skb->len;
820
821 netif_stop_queue (dev);
822
823 /* Note: Ordering is important here, set the field with the
824 "ownership" bit last, and only then increment cur_tx. */
825
826 /* Calculate the next Tx descriptor entry. */
827 entry = yp->cur_tx % TX_RING_SIZE;
828
829 if (gx_fix) { /* Note: only works for paddable protocols e.g. IP. */
830 int cacheline_end = ((unsigned long)skb->data + skb->len) % 32;
831 /* Fix GX chipset errata. */
832 if (cacheline_end > 24 || cacheline_end == 0) {
833 len = skb->len + 32 - cacheline_end + 1;
834 if (skb_padto(skb, len)) {
835 yp->tx_skbuff[entry] = NULL;
836 netif_wake_queue(dev);
837 return NETDEV_TX_OK;
838 }
839 }
840 }
841 yp->tx_skbuff[entry] = skb;
842
843#ifdef NO_TXSTATS
844 yp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
845 skb->data, len, PCI_DMA_TODEVICE));
846 yp->tx_ring[entry].result_status = 0;
847 if (entry >= TX_RING_SIZE-1) {
848 /* New stop command. */
849 yp->tx_ring[0].dbdma_cmd = cpu_to_le32(CMD_STOP);
850 yp->tx_ring[TX_RING_SIZE-1].dbdma_cmd =
851 cpu_to_le32(CMD_TX_PKT|BRANCH_ALWAYS | len);
852 } else {
853 yp->tx_ring[entry+1].dbdma_cmd = cpu_to_le32(CMD_STOP);
854 yp->tx_ring[entry].dbdma_cmd =
855 cpu_to_le32(CMD_TX_PKT | BRANCH_IFTRUE | len);
856 }
857 yp->cur_tx++;
858#else
859 yp->tx_ring[entry<<1].request_cnt = len;
860 yp->tx_ring[entry<<1].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
861 skb->data, len, PCI_DMA_TODEVICE));
862 /* The input_last (status-write) command is constant, but we must
863 rewrite the subsequent 'stop' command. */
864
865 yp->cur_tx++;
866 {
867 unsigned next_entry = yp->cur_tx % TX_RING_SIZE;
868 yp->tx_ring[next_entry<<1].dbdma_cmd = cpu_to_le32(CMD_STOP);
869 }
870 /* Final step -- overwrite the old 'stop' command. */
871
872 yp->tx_ring[entry<<1].dbdma_cmd =
873 cpu_to_le32( ((entry % 6) == 0 ? CMD_TX_PKT|INTR_ALWAYS|BRANCH_IFTRUE :
874 CMD_TX_PKT | BRANCH_IFTRUE) | len);
875#endif
876
877 /* Non-x86 Todo: explicitly flush cache lines here. */
878
879 /* Wake the potentially-idle transmit channel. */
880 iowrite32(0x10001000, yp->base + TxCtrl);
881
882 if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
883 netif_start_queue (dev); /* Typical path */
884 else
885 yp->tx_full = 1;
886
887 if (yellowfin_debug > 4) {
888 netdev_printk(KERN_DEBUG, dev, "Yellowfin transmit frame #%d queued in slot %d\n",
889 yp->cur_tx, entry);
890 }
891 return NETDEV_TX_OK;
892}
893
894/* The interrupt handler does all of the Rx thread work and cleans up
895 after the Tx thread. */
896static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance)
897{
898 struct net_device *dev = dev_instance;
899 struct yellowfin_private *yp;
900 void __iomem *ioaddr;
901 int boguscnt = max_interrupt_work;
902 unsigned int handled = 0;
903
904 yp = netdev_priv(dev);
905 ioaddr = yp->base;
906
907 spin_lock (&yp->lock);
908
909 do {
910 u16 intr_status = ioread16(ioaddr + IntrClear);
911
912 if (yellowfin_debug > 4)
913 netdev_printk(KERN_DEBUG, dev, "Yellowfin interrupt, status %04x\n",
914 intr_status);
915
916 if (intr_status == 0)
917 break;
918 handled = 1;
919
920 if (intr_status & (IntrRxDone | IntrEarlyRx)) {
921 yellowfin_rx(dev);
922 iowrite32(0x10001000, ioaddr + RxCtrl); /* Wake Rx engine. */
923 }
924
925#ifdef NO_TXSTATS
926 for (; yp->cur_tx - yp->dirty_tx > 0; yp->dirty_tx++) {
927 int entry = yp->dirty_tx % TX_RING_SIZE;
928 struct sk_buff *skb;
929
930 if (yp->tx_ring[entry].result_status == 0)
931 break;
932 skb = yp->tx_skbuff[entry];
933 dev->stats.tx_packets++;
934 dev->stats.tx_bytes += skb->len;
935 /* Free the original skb. */
936 pci_unmap_single(yp->pci_dev, le32_to_cpu(yp->tx_ring[entry].addr),
937 skb->len, PCI_DMA_TODEVICE);
938 dev_kfree_skb_irq(skb);
939 yp->tx_skbuff[entry] = NULL;
940 }
941 if (yp->tx_full &&
942 yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE - 4) {
943 /* The ring is no longer full, clear tbusy. */
944 yp->tx_full = 0;
945 netif_wake_queue(dev);
946 }
947#else
948 if ((intr_status & IntrTxDone) || (yp->tx_tail_desc->tx_errs)) {
949 unsigned dirty_tx = yp->dirty_tx;
950
951 for (dirty_tx = yp->dirty_tx; yp->cur_tx - dirty_tx > 0;
952 dirty_tx++) {
953 /* Todo: optimize this. */
954 int entry = dirty_tx % TX_RING_SIZE;
955 u16 tx_errs = yp->tx_status[entry].tx_errs;
956 struct sk_buff *skb;
957
958#ifndef final_version
959 if (yellowfin_debug > 5)
960 netdev_printk(KERN_DEBUG, dev, "Tx queue %d check, Tx status %04x %04x %04x %04x\n",
961 entry,
962 yp->tx_status[entry].tx_cnt,
963 yp->tx_status[entry].tx_errs,
964 yp->tx_status[entry].total_tx_cnt,
965 yp->tx_status[entry].paused);
966#endif
967 if (tx_errs == 0)
968 break; /* It still hasn't been Txed */
969 skb = yp->tx_skbuff[entry];
970 if (tx_errs & 0xF810) {
971 /* There was an major error, log it. */
972#ifndef final_version
973 if (yellowfin_debug > 1)
974 netdev_printk(KERN_DEBUG, dev, "Transmit error, Tx status %04x\n",
975 tx_errs);
976#endif
977 dev->stats.tx_errors++;
978 if (tx_errs & 0xF800) dev->stats.tx_aborted_errors++;
979 if (tx_errs & 0x0800) dev->stats.tx_carrier_errors++;
980 if (tx_errs & 0x2000) dev->stats.tx_window_errors++;
981 if (tx_errs & 0x8000) dev->stats.tx_fifo_errors++;
982 } else {
983#ifndef final_version
984 if (yellowfin_debug > 4)
985 netdev_printk(KERN_DEBUG, dev, "Normal transmit, Tx status %04x\n",
986 tx_errs);
987#endif
988 dev->stats.tx_bytes += skb->len;
989 dev->stats.collisions += tx_errs & 15;
990 dev->stats.tx_packets++;
991 }
992 /* Free the original skb. */
993 pci_unmap_single(yp->pci_dev,
994 yp->tx_ring[entry<<1].addr, skb->len,
995 PCI_DMA_TODEVICE);
996 dev_kfree_skb_irq(skb);
997 yp->tx_skbuff[entry] = 0;
998 /* Mark status as empty. */
999 yp->tx_status[entry].tx_errs = 0;
1000 }
1001
1002#ifndef final_version
1003 if (yp->cur_tx - dirty_tx > TX_RING_SIZE) {
1004 netdev_err(dev, "Out-of-sync dirty pointer, %d vs. %d, full=%d\n",
1005 dirty_tx, yp->cur_tx, yp->tx_full);
1006 dirty_tx += TX_RING_SIZE;
1007 }
1008#endif
1009
1010 if (yp->tx_full &&
1011 yp->cur_tx - dirty_tx < TX_QUEUE_SIZE - 2) {
1012 /* The ring is no longer full, clear tbusy. */
1013 yp->tx_full = 0;
1014 netif_wake_queue(dev);
1015 }
1016
1017 yp->dirty_tx = dirty_tx;
1018 yp->tx_tail_desc = &yp->tx_status[dirty_tx % TX_RING_SIZE];
1019 }
1020#endif
1021
1022 /* Log errors and other uncommon events. */
1023 if (intr_status & 0x2ee) /* Abnormal error summary. */
1024 yellowfin_error(dev, intr_status);
1025
1026 if (--boguscnt < 0) {
1027 netdev_warn(dev, "Too much work at interrupt, status=%#04x\n",
1028 intr_status);
1029 break;
1030 }
1031 } while (1);
1032
1033 if (yellowfin_debug > 3)
1034 netdev_printk(KERN_DEBUG, dev, "exiting interrupt, status=%#04x\n",
1035 ioread16(ioaddr + IntrStatus));
1036
1037 spin_unlock (&yp->lock);
1038 return IRQ_RETVAL(handled);
1039}
1040
1041/* This routine is logically part of the interrupt handler, but separated
1042 for clarity and better register allocation. */
1043static int yellowfin_rx(struct net_device *dev)
1044{
1045 struct yellowfin_private *yp = netdev_priv(dev);
1046 int entry = yp->cur_rx % RX_RING_SIZE;
1047 int boguscnt = yp->dirty_rx + RX_RING_SIZE - yp->cur_rx;
1048
1049 if (yellowfin_debug > 4) {
1050 printk(KERN_DEBUG " In yellowfin_rx(), entry %d status %08x\n",
1051 entry, yp->rx_ring[entry].result_status);
1052 printk(KERN_DEBUG " #%d desc. %08x %08x %08x\n",
1053 entry, yp->rx_ring[entry].dbdma_cmd, yp->rx_ring[entry].addr,
1054 yp->rx_ring[entry].result_status);
1055 }
1056
1057 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1058 while (1) {
1059 struct yellowfin_desc *desc = &yp->rx_ring[entry];
1060 struct sk_buff *rx_skb = yp->rx_skbuff[entry];
1061 s16 frame_status;
1062 u16 desc_status;
1063 int data_size;
1064 u8 *buf_addr;
1065
1066 if(!desc->result_status)
1067 break;
1068 pci_dma_sync_single_for_cpu(yp->pci_dev, le32_to_cpu(desc->addr),
1069 yp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1070 desc_status = le32_to_cpu(desc->result_status) >> 16;
1071 buf_addr = rx_skb->data;
1072 data_size = (le32_to_cpu(desc->dbdma_cmd) -
1073 le32_to_cpu(desc->result_status)) & 0xffff;
1074 frame_status = get_unaligned_le16(&(buf_addr[data_size - 2]));
1075 if (yellowfin_debug > 4)
1076 printk(KERN_DEBUG " %s() status was %04x\n",
1077 __func__, frame_status);
1078 if (--boguscnt < 0)
1079 break;
1080 if ( ! (desc_status & RX_EOP)) {
1081 if (data_size != 0)
1082 netdev_warn(dev, "Oversized Ethernet frame spanned multiple buffers, status %04x, data_size %d!\n",
1083 desc_status, data_size);
1084 dev->stats.rx_length_errors++;
1085 } else if ((yp->drv_flags & IsGigabit) && (frame_status & 0x0038)) {
1086 /* There was a error. */
1087 if (yellowfin_debug > 3)
1088 printk(KERN_DEBUG " %s() Rx error was %04x\n",
1089 __func__, frame_status);
1090 dev->stats.rx_errors++;
1091 if (frame_status & 0x0060) dev->stats.rx_length_errors++;
1092 if (frame_status & 0x0008) dev->stats.rx_frame_errors++;
1093 if (frame_status & 0x0010) dev->stats.rx_crc_errors++;
1094 if (frame_status < 0) dev->stats.rx_dropped++;
1095 } else if ( !(yp->drv_flags & IsGigabit) &&
1096 ((buf_addr[data_size-1] & 0x85) || buf_addr[data_size-2] & 0xC0)) {
1097 u8 status1 = buf_addr[data_size-2];
1098 u8 status2 = buf_addr[data_size-1];
1099 dev->stats.rx_errors++;
1100 if (status1 & 0xC0) dev->stats.rx_length_errors++;
1101 if (status2 & 0x03) dev->stats.rx_frame_errors++;
1102 if (status2 & 0x04) dev->stats.rx_crc_errors++;
1103 if (status2 & 0x80) dev->stats.rx_dropped++;
1104#ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
1105 } else if ((yp->flags & HasMACAddrBug) &&
1106 memcmp(le32_to_cpu(yp->rx_ring_dma +
1107 entry*sizeof(struct yellowfin_desc)),
1108 dev->dev_addr, 6) != 0 &&
1109 memcmp(le32_to_cpu(yp->rx_ring_dma +
1110 entry*sizeof(struct yellowfin_desc)),
1111 "\377\377\377\377\377\377", 6) != 0) {
1112 if (bogus_rx++ == 0)
1113 netdev_warn(dev, "Bad frame to %pM\n",
1114 buf_addr);
1115#endif
1116 } else {
1117 struct sk_buff *skb;
1118 int pkt_len = data_size -
1119 (yp->chip_id ? 7 : 8 + buf_addr[data_size - 8]);
1120 /* To verify: Yellowfin Length should omit the CRC! */
1121
1122#ifndef final_version
1123 if (yellowfin_debug > 4)
1124 printk(KERN_DEBUG " %s() normal Rx pkt length %d of %d, bogus_cnt %d\n",
1125 __func__, pkt_len, data_size, boguscnt);
1126#endif
1127 /* Check if the packet is long enough to just pass up the skbuff
1128 without copying to a properly sized skbuff. */
1129 if (pkt_len > rx_copybreak) {
1130 skb_put(skb = rx_skb, pkt_len);
1131 pci_unmap_single(yp->pci_dev,
1132 le32_to_cpu(yp->rx_ring[entry].addr),
1133 yp->rx_buf_sz,
1134 PCI_DMA_FROMDEVICE);
1135 yp->rx_skbuff[entry] = NULL;
1136 } else {
1137 skb = dev_alloc_skb(pkt_len + 2);
1138 if (skb == NULL)
1139 break;
1140 skb_reserve(skb, 2); /* 16 byte align the IP header */
1141 skb_copy_to_linear_data(skb, rx_skb->data, pkt_len);
1142 skb_put(skb, pkt_len);
1143 pci_dma_sync_single_for_device(yp->pci_dev,
1144 le32_to_cpu(desc->addr),
1145 yp->rx_buf_sz,
1146 PCI_DMA_FROMDEVICE);
1147 }
1148 skb->protocol = eth_type_trans(skb, dev);
1149 netif_rx(skb);
1150 dev->stats.rx_packets++;
1151 dev->stats.rx_bytes += pkt_len;
1152 }
1153 entry = (++yp->cur_rx) % RX_RING_SIZE;
1154 }
1155
1156 /* Refill the Rx ring buffers. */
1157 for (; yp->cur_rx - yp->dirty_rx > 0; yp->dirty_rx++) {
1158 entry = yp->dirty_rx % RX_RING_SIZE;
1159 if (yp->rx_skbuff[entry] == NULL) {
1160 struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz + 2);
1161 if (skb == NULL)
1162 break; /* Better luck next round. */
1163 yp->rx_skbuff[entry] = skb;
1164 skb->dev = dev; /* Mark as being used by this device. */
1165 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1166 yp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
1167 skb->data, yp->rx_buf_sz, PCI_DMA_FROMDEVICE));
1168 }
1169 yp->rx_ring[entry].dbdma_cmd = cpu_to_le32(CMD_STOP);
1170 yp->rx_ring[entry].result_status = 0; /* Clear complete bit. */
1171 if (entry != 0)
1172 yp->rx_ring[entry - 1].dbdma_cmd =
1173 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz);
1174 else
1175 yp->rx_ring[RX_RING_SIZE - 1].dbdma_cmd =
1176 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | BRANCH_ALWAYS
1177 | yp->rx_buf_sz);
1178 }
1179
1180 return 0;
1181}
1182
1183static void yellowfin_error(struct net_device *dev, int intr_status)
1184{
1185 netdev_err(dev, "Something Wicked happened! %04x\n", intr_status);
1186 /* Hmmmmm, it's not clear what to do here. */
1187 if (intr_status & (IntrTxPCIErr | IntrTxPCIFault))
1188 dev->stats.tx_errors++;
1189 if (intr_status & (IntrRxPCIErr | IntrRxPCIFault))
1190 dev->stats.rx_errors++;
1191}
1192
1193static int yellowfin_close(struct net_device *dev)
1194{
1195 struct yellowfin_private *yp = netdev_priv(dev);
1196 void __iomem *ioaddr = yp->base;
1197 int i;
1198
1199 netif_stop_queue (dev);
1200
1201 if (yellowfin_debug > 1) {
1202 netdev_printk(KERN_DEBUG, dev, "Shutting down ethercard, status was Tx %04x Rx %04x Int %02x\n",
1203 ioread16(ioaddr + TxStatus),
1204 ioread16(ioaddr + RxStatus),
1205 ioread16(ioaddr + IntrStatus));
1206 netdev_printk(KERN_DEBUG, dev, "Queue pointers were Tx %d / %d, Rx %d / %d\n",
1207 yp->cur_tx, yp->dirty_tx,
1208 yp->cur_rx, yp->dirty_rx);
1209 }
1210
1211 /* Disable interrupts by clearing the interrupt mask. */
1212 iowrite16(0x0000, ioaddr + IntrEnb);
1213
1214 /* Stop the chip's Tx and Rx processes. */
1215 iowrite32(0x80000000, ioaddr + RxCtrl);
1216 iowrite32(0x80000000, ioaddr + TxCtrl);
1217
1218 del_timer(&yp->timer);
1219
1220#if defined(__i386__)
1221 if (yellowfin_debug > 2) {
1222 printk(KERN_DEBUG " Tx ring at %08llx:\n",
1223 (unsigned long long)yp->tx_ring_dma);
1224 for (i = 0; i < TX_RING_SIZE*2; i++)
1225 printk(KERN_DEBUG " %c #%d desc. %08x %08x %08x %08x\n",
1226 ioread32(ioaddr + TxPtr) == (long)&yp->tx_ring[i] ? '>' : ' ',
1227 i, yp->tx_ring[i].dbdma_cmd, yp->tx_ring[i].addr,
1228 yp->tx_ring[i].branch_addr, yp->tx_ring[i].result_status);
1229 printk(KERN_DEBUG " Tx status %p:\n", yp->tx_status);
1230 for (i = 0; i < TX_RING_SIZE; i++)
1231 printk(KERN_DEBUG " #%d status %04x %04x %04x %04x\n",
1232 i, yp->tx_status[i].tx_cnt, yp->tx_status[i].tx_errs,
1233 yp->tx_status[i].total_tx_cnt, yp->tx_status[i].paused);
1234
1235 printk(KERN_DEBUG " Rx ring %08llx:\n",
1236 (unsigned long long)yp->rx_ring_dma);
1237 for (i = 0; i < RX_RING_SIZE; i++) {
1238 printk(KERN_DEBUG " %c #%d desc. %08x %08x %08x\n",
1239 ioread32(ioaddr + RxPtr) == (long)&yp->rx_ring[i] ? '>' : ' ',
1240 i, yp->rx_ring[i].dbdma_cmd, yp->rx_ring[i].addr,
1241 yp->rx_ring[i].result_status);
1242 if (yellowfin_debug > 6) {
1243 if (get_unaligned((u8*)yp->rx_ring[i].addr) != 0x69) {
1244 int j;
1245
1246 printk(KERN_DEBUG);
1247 for (j = 0; j < 0x50; j++)
1248 pr_cont(" %04x",
1249 get_unaligned(((u16*)yp->rx_ring[i].addr) + j));
1250 pr_cont("\n");
1251 }
1252 }
1253 }
1254 }
1255#endif /* __i386__ debugging only */
1256
1257 free_irq(dev->irq, dev);
1258
1259 /* Free all the skbuffs in the Rx queue. */
1260 for (i = 0; i < RX_RING_SIZE; i++) {
1261 yp->rx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
1262 yp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1263 if (yp->rx_skbuff[i]) {
1264 dev_kfree_skb(yp->rx_skbuff[i]);
1265 }
1266 yp->rx_skbuff[i] = NULL;
1267 }
1268 for (i = 0; i < TX_RING_SIZE; i++) {
1269 if (yp->tx_skbuff[i])
1270 dev_kfree_skb(yp->tx_skbuff[i]);
1271 yp->tx_skbuff[i] = NULL;
1272 }
1273
1274#ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
1275 if (yellowfin_debug > 0) {
1276 netdev_printk(KERN_DEBUG, dev, "Received %d frames that we should not have\n",
1277 bogus_rx);
1278 }
1279#endif
1280
1281 return 0;
1282}
1283
1284/* Set or clear the multicast filter for this adaptor. */
1285
1286static void set_rx_mode(struct net_device *dev)
1287{
1288 struct yellowfin_private *yp = netdev_priv(dev);
1289 void __iomem *ioaddr = yp->base;
1290 u16 cfg_value = ioread16(ioaddr + Cnfg);
1291
1292 /* Stop the Rx process to change any value. */
1293 iowrite16(cfg_value & ~0x1000, ioaddr + Cnfg);
1294 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1295 iowrite16(0x000F, ioaddr + AddrMode);
1296 } else if ((netdev_mc_count(dev) > 64) ||
1297 (dev->flags & IFF_ALLMULTI)) {
1298 /* Too many to filter well, or accept all multicasts. */
1299 iowrite16(0x000B, ioaddr + AddrMode);
1300 } else if (!netdev_mc_empty(dev)) { /* Must use the multicast hash table. */
1301 struct netdev_hw_addr *ha;
1302 u16 hash_table[4];
1303 int i;
1304
1305 memset(hash_table, 0, sizeof(hash_table));
1306 netdev_for_each_mc_addr(ha, dev) {
1307 unsigned int bit;
1308
1309 /* Due to a bug in the early chip versions, multiple filter
1310 slots must be set for each address. */
1311 if (yp->drv_flags & HasMulticastBug) {
1312 bit = (ether_crc_le(3, ha->addr) >> 3) & 0x3f;
1313 hash_table[bit >> 4] |= (1 << bit);
1314 bit = (ether_crc_le(4, ha->addr) >> 3) & 0x3f;
1315 hash_table[bit >> 4] |= (1 << bit);
1316 bit = (ether_crc_le(5, ha->addr) >> 3) & 0x3f;
1317 hash_table[bit >> 4] |= (1 << bit);
1318 }
1319 bit = (ether_crc_le(6, ha->addr) >> 3) & 0x3f;
1320 hash_table[bit >> 4] |= (1 << bit);
1321 }
1322 /* Copy the hash table to the chip. */
1323 for (i = 0; i < 4; i++)
1324 iowrite16(hash_table[i], ioaddr + HashTbl + i*2);
1325 iowrite16(0x0003, ioaddr + AddrMode);
1326 } else { /* Normal, unicast/broadcast-only mode. */
1327 iowrite16(0x0001, ioaddr + AddrMode);
1328 }
1329 /* Restart the Rx process. */
1330 iowrite16(cfg_value | 0x1000, ioaddr + Cnfg);
1331}
1332
1333static void yellowfin_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1334{
1335 struct yellowfin_private *np = netdev_priv(dev);
1336 strcpy(info->driver, DRV_NAME);
1337 strcpy(info->version, DRV_VERSION);
1338 strcpy(info->bus_info, pci_name(np->pci_dev));
1339}
1340
1341static const struct ethtool_ops ethtool_ops = {
1342 .get_drvinfo = yellowfin_get_drvinfo
1343};
1344
1345static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1346{
1347 struct yellowfin_private *np = netdev_priv(dev);
1348 void __iomem *ioaddr = np->base;
1349 struct mii_ioctl_data *data = if_mii(rq);
1350
1351 switch(cmd) {
1352 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1353 data->phy_id = np->phys[0] & 0x1f;
1354 /* Fall Through */
1355
1356 case SIOCGMIIREG: /* Read MII PHY register. */
1357 data->val_out = mdio_read(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f);
1358 return 0;
1359
1360 case SIOCSMIIREG: /* Write MII PHY register. */
1361 if (data->phy_id == np->phys[0]) {
1362 u16 value = data->val_in;
1363 switch (data->reg_num) {
1364 case 0:
1365 /* Check for autonegotiation on or reset. */
1366 np->medialock = (value & 0x9000) ? 0 : 1;
1367 if (np->medialock)
1368 np->full_duplex = (value & 0x0100) ? 1 : 0;
1369 break;
1370 case 4: np->advertising = value; break;
1371 }
1372 /* Perhaps check_duplex(dev), depending on chip semantics. */
1373 }
1374 mdio_write(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1375 return 0;
1376 default:
1377 return -EOPNOTSUPP;
1378 }
1379}
1380
1381
1382static void __devexit yellowfin_remove_one (struct pci_dev *pdev)
1383{
1384 struct net_device *dev = pci_get_drvdata(pdev);
1385 struct yellowfin_private *np;
1386
1387 BUG_ON(!dev);
1388 np = netdev_priv(dev);
1389
1390 pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status,
1391 np->tx_status_dma);
1392 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
1393 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
1394 unregister_netdev (dev);
1395
1396 pci_iounmap(pdev, np->base);
1397
1398 pci_release_regions (pdev);
1399
1400 free_netdev (dev);
1401 pci_set_drvdata(pdev, NULL);
1402}
1403
1404
1405static struct pci_driver yellowfin_driver = {
1406 .name = DRV_NAME,
1407 .id_table = yellowfin_pci_tbl,
1408 .probe = yellowfin_init_one,
1409 .remove = __devexit_p(yellowfin_remove_one),
1410};
1411
1412
1413static int __init yellowfin_init (void)
1414{
1415/* when a module, this is printed whether or not devices are found in probe */
1416#ifdef MODULE
1417 printk(version);
1418#endif
1419 return pci_register_driver(&yellowfin_driver);
1420}
1421
1422
1423static void __exit yellowfin_cleanup (void)
1424{
1425 pci_unregister_driver (&yellowfin_driver);
1426}
1427
1428
1429module_init(yellowfin_init);
1430module_exit(yellowfin_cleanup);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-14 12:18:27 -0500