diff options
author | David S. Miller <davem@davemloft.net> | 2011-09-22 03:23:13 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2011-09-22 03:23:13 -0400 |
commit | 8decf868790b48a727d7e7ca164f2bcd3c1389c0 (patch) | |
tree | b759a5f861f842af7ea76f9011b579d06e9d5508 /drivers/net/ethernet/oki-semi | |
parent | 3fc72370186be2f9d4d6ef06d99e1caa5d92c564 (diff) | |
parent | d93dc5c4478c1fd5de85a3e8aece9aad7bbae044 (diff) |
Merge branch 'master' of github.com:davem330/net
Conflicts:
MAINTAINERS
drivers/net/Kconfig
drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
drivers/net/ethernet/broadcom/tg3.c
drivers/net/wireless/iwlwifi/iwl-pci.c
drivers/net/wireless/iwlwifi/iwl-trans-tx-pcie.c
drivers/net/wireless/rt2x00/rt2800usb.c
drivers/net/wireless/wl12xx/main.c
Diffstat (limited to 'drivers/net/ethernet/oki-semi')
-rw-r--r-- | drivers/net/ethernet/oki-semi/pch_gbe/Kconfig | 11 | ||||
-rw-r--r-- | drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h | 12 | ||||
-rw-r--r-- | drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 302 |
3 files changed, 209 insertions, 116 deletions
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig b/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig index 7efa62427235..00bc4fc968c7 100644 --- a/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig +++ b/drivers/net/ethernet/oki-semi/pch_gbe/Kconfig | |||
@@ -3,7 +3,7 @@ | |||
3 | # | 3 | # |
4 | 4 | ||
5 | config PCH_GBE | 5 | config PCH_GBE |
6 | tristate "OKI SEMICONDUCTOR ML7223 IOH GbE (Intel EG20T PCH)" | 6 | tristate "OKI SEMICONDUCTOR IOH(ML7223/ML7831) GbE" |
7 | depends on PCI | 7 | depends on PCI |
8 | select NET_CORE | 8 | select NET_CORE |
9 | select MII | 9 | select MII |
@@ -15,7 +15,8 @@ config PCH_GBE | |||
15 | to Gigabit Ethernet. This driver enables Gigabit Ethernet function. | 15 | to Gigabit Ethernet. This driver enables Gigabit Ethernet function. |
16 | 16 | ||
17 | This driver also can be used for OKI SEMICONDUCTOR IOH(Input/ | 17 | This driver also can be used for OKI SEMICONDUCTOR IOH(Input/ |
18 | Output Hub), ML7223. | 18 | Output Hub), ML7223/ML7831. |
19 | ML7223 IOH is for MP(Media Phone) use. | 19 | ML7223 IOH is for MP(Media Phone) use. ML7831 IOH is for general |
20 | ML7223 is companion chip for Intel Atom E6xx series. | 20 | purpose use. |
21 | ML7223 is completely compatible for Intel EG20T PCH. | 21 | ML7223/ML7831 is companion chip for Intel Atom E6xx series. |
22 | ML7223/ML7831 is completely compatible for Intel EG20T PCH. | ||
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h index 59fac77d0dbb..a09a07197eb5 100644 --- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h +++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h | |||
@@ -127,8 +127,8 @@ struct pch_gbe_regs { | |||
127 | 127 | ||
128 | /* Reset */ | 128 | /* Reset */ |
129 | #define PCH_GBE_ALL_RST 0x80000000 /* All reset */ | 129 | #define PCH_GBE_ALL_RST 0x80000000 /* All reset */ |
130 | #define PCH_GBE_TX_RST 0x40000000 /* TX MAC, TX FIFO, TX DMA reset */ | 130 | #define PCH_GBE_TX_RST 0x00008000 /* TX MAC, TX FIFO, TX DMA reset */ |
131 | #define PCH_GBE_RX_RST 0x04000000 /* RX MAC, RX FIFO, RX DMA reset */ | 131 | #define PCH_GBE_RX_RST 0x00004000 /* RX MAC, RX FIFO, RX DMA reset */ |
132 | 132 | ||
133 | /* TCP/IP Accelerator Control */ | 133 | /* TCP/IP Accelerator Control */ |
134 | #define PCH_GBE_EX_LIST_EN 0x00000008 /* External List Enable */ | 134 | #define PCH_GBE_EX_LIST_EN 0x00000008 /* External List Enable */ |
@@ -276,6 +276,9 @@ struct pch_gbe_regs { | |||
276 | #define PCH_GBE_RX_DMA_EN 0x00000002 /* Enables Receive DMA */ | 276 | #define PCH_GBE_RX_DMA_EN 0x00000002 /* Enables Receive DMA */ |
277 | #define PCH_GBE_TX_DMA_EN 0x00000001 /* Enables Transmission DMA */ | 277 | #define PCH_GBE_TX_DMA_EN 0x00000001 /* Enables Transmission DMA */ |
278 | 278 | ||
279 | /* RX DMA STATUS */ | ||
280 | #define PCH_GBE_IDLE_CHECK 0xFFFFFFFE | ||
281 | |||
279 | /* Wake On LAN Status */ | 282 | /* Wake On LAN Status */ |
280 | #define PCH_GBE_WLS_BR 0x00000008 /* Broadcas Address */ | 283 | #define PCH_GBE_WLS_BR 0x00000008 /* Broadcas Address */ |
281 | #define PCH_GBE_WLS_MLT 0x00000004 /* Multicast Address */ | 284 | #define PCH_GBE_WLS_MLT 0x00000004 /* Multicast Address */ |
@@ -471,6 +474,7 @@ struct pch_gbe_tx_desc { | |||
471 | struct pch_gbe_buffer { | 474 | struct pch_gbe_buffer { |
472 | struct sk_buff *skb; | 475 | struct sk_buff *skb; |
473 | dma_addr_t dma; | 476 | dma_addr_t dma; |
477 | unsigned char *rx_buffer; | ||
474 | unsigned long time_stamp; | 478 | unsigned long time_stamp; |
475 | u16 length; | 479 | u16 length; |
476 | bool mapped; | 480 | bool mapped; |
@@ -511,6 +515,9 @@ struct pch_gbe_tx_ring { | |||
511 | struct pch_gbe_rx_ring { | 515 | struct pch_gbe_rx_ring { |
512 | struct pch_gbe_rx_desc *desc; | 516 | struct pch_gbe_rx_desc *desc; |
513 | dma_addr_t dma; | 517 | dma_addr_t dma; |
518 | unsigned char *rx_buff_pool; | ||
519 | dma_addr_t rx_buff_pool_logic; | ||
520 | unsigned int rx_buff_pool_size; | ||
514 | unsigned int size; | 521 | unsigned int size; |
515 | unsigned int count; | 522 | unsigned int count; |
516 | unsigned int next_to_use; | 523 | unsigned int next_to_use; |
@@ -622,6 +629,7 @@ struct pch_gbe_adapter { | |||
622 | unsigned long rx_buffer_len; | 629 | unsigned long rx_buffer_len; |
623 | unsigned long tx_queue_len; | 630 | unsigned long tx_queue_len; |
624 | bool have_msi; | 631 | bool have_msi; |
632 | bool rx_stop_flag; | ||
625 | }; | 633 | }; |
626 | 634 | ||
627 | extern const char pch_driver_version[]; | 635 | extern const char pch_driver_version[]; |
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c index 72276fe78f8f..35a7c21680b3 100644 --- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c +++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | |||
@@ -20,7 +20,6 @@ | |||
20 | 20 | ||
21 | #include "pch_gbe.h" | 21 | #include "pch_gbe.h" |
22 | #include "pch_gbe_api.h" | 22 | #include "pch_gbe_api.h" |
23 | #include <linux/prefetch.h> | ||
24 | 23 | ||
25 | #define DRV_VERSION "1.00" | 24 | #define DRV_VERSION "1.00" |
26 | const char pch_driver_version[] = DRV_VERSION; | 25 | const char pch_driver_version[] = DRV_VERSION; |
@@ -34,11 +33,15 @@ const char pch_driver_version[] = DRV_VERSION; | |||
34 | #define PCH_GBE_WATCHDOG_PERIOD (1 * HZ) /* watchdog time */ | 33 | #define PCH_GBE_WATCHDOG_PERIOD (1 * HZ) /* watchdog time */ |
35 | #define PCH_GBE_COPYBREAK_DEFAULT 256 | 34 | #define PCH_GBE_COPYBREAK_DEFAULT 256 |
36 | #define PCH_GBE_PCI_BAR 1 | 35 | #define PCH_GBE_PCI_BAR 1 |
36 | #define PCH_GBE_RESERVE_MEMORY 0x200000 /* 2MB */ | ||
37 | 37 | ||
38 | /* Macros for ML7223 */ | 38 | /* Macros for ML7223 */ |
39 | #define PCI_VENDOR_ID_ROHM 0x10db | 39 | #define PCI_VENDOR_ID_ROHM 0x10db |
40 | #define PCI_DEVICE_ID_ROHM_ML7223_GBE 0x8013 | 40 | #define PCI_DEVICE_ID_ROHM_ML7223_GBE 0x8013 |
41 | 41 | ||
42 | /* Macros for ML7831 */ | ||
43 | #define PCI_DEVICE_ID_ROHM_ML7831_GBE 0x8802 | ||
44 | |||
42 | #define PCH_GBE_TX_WEIGHT 64 | 45 | #define PCH_GBE_TX_WEIGHT 64 |
43 | #define PCH_GBE_RX_WEIGHT 64 | 46 | #define PCH_GBE_RX_WEIGHT 64 |
44 | #define PCH_GBE_RX_BUFFER_WRITE 16 | 47 | #define PCH_GBE_RX_BUFFER_WRITE 16 |
@@ -52,6 +55,7 @@ const char pch_driver_version[] = DRV_VERSION; | |||
52 | ) | 55 | ) |
53 | 56 | ||
54 | /* Ethertype field values */ | 57 | /* Ethertype field values */ |
58 | #define PCH_GBE_MAX_RX_BUFFER_SIZE 0x2880 | ||
55 | #define PCH_GBE_MAX_JUMBO_FRAME_SIZE 10318 | 59 | #define PCH_GBE_MAX_JUMBO_FRAME_SIZE 10318 |
56 | #define PCH_GBE_FRAME_SIZE_2048 2048 | 60 | #define PCH_GBE_FRAME_SIZE_2048 2048 |
57 | #define PCH_GBE_FRAME_SIZE_4096 4096 | 61 | #define PCH_GBE_FRAME_SIZE_4096 4096 |
@@ -83,10 +87,12 @@ const char pch_driver_version[] = DRV_VERSION; | |||
83 | #define PCH_GBE_INT_ENABLE_MASK ( \ | 87 | #define PCH_GBE_INT_ENABLE_MASK ( \ |
84 | PCH_GBE_INT_RX_DMA_CMPLT | \ | 88 | PCH_GBE_INT_RX_DMA_CMPLT | \ |
85 | PCH_GBE_INT_RX_DSC_EMP | \ | 89 | PCH_GBE_INT_RX_DSC_EMP | \ |
90 | PCH_GBE_INT_RX_FIFO_ERR | \ | ||
86 | PCH_GBE_INT_WOL_DET | \ | 91 | PCH_GBE_INT_WOL_DET | \ |
87 | PCH_GBE_INT_TX_CMPLT \ | 92 | PCH_GBE_INT_TX_CMPLT \ |
88 | ) | 93 | ) |
89 | 94 | ||
95 | #define PCH_GBE_INT_DISABLE_ALL 0 | ||
90 | 96 | ||
91 | static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT; | 97 | static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT; |
92 | 98 | ||
@@ -138,6 +144,27 @@ static void pch_gbe_wait_clr_bit(void *reg, u32 bit) | |||
138 | if (!tmp) | 144 | if (!tmp) |
139 | pr_err("Error: busy bit is not cleared\n"); | 145 | pr_err("Error: busy bit is not cleared\n"); |
140 | } | 146 | } |
147 | |||
148 | /** | ||
149 | * pch_gbe_wait_clr_bit_irq - Wait to clear a bit for interrupt context | ||
150 | * @reg: Pointer of register | ||
151 | * @busy: Busy bit | ||
152 | */ | ||
153 | static int pch_gbe_wait_clr_bit_irq(void *reg, u32 bit) | ||
154 | { | ||
155 | u32 tmp; | ||
156 | int ret = -1; | ||
157 | /* wait busy */ | ||
158 | tmp = 20; | ||
159 | while ((ioread32(reg) & bit) && --tmp) | ||
160 | udelay(5); | ||
161 | if (!tmp) | ||
162 | pr_err("Error: busy bit is not cleared\n"); | ||
163 | else | ||
164 | ret = 0; | ||
165 | return ret; | ||
166 | } | ||
167 | |||
141 | /** | 168 | /** |
142 | * pch_gbe_mac_mar_set - Set MAC address register | 169 | * pch_gbe_mac_mar_set - Set MAC address register |
143 | * @hw: Pointer to the HW structure | 170 | * @hw: Pointer to the HW structure |
@@ -189,6 +216,17 @@ static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw) | |||
189 | return; | 216 | return; |
190 | } | 217 | } |
191 | 218 | ||
219 | static void pch_gbe_mac_reset_rx(struct pch_gbe_hw *hw) | ||
220 | { | ||
221 | /* Read the MAC address. and store to the private data */ | ||
222 | pch_gbe_mac_read_mac_addr(hw); | ||
223 | iowrite32(PCH_GBE_RX_RST, &hw->reg->RESET); | ||
224 | pch_gbe_wait_clr_bit_irq(&hw->reg->RESET, PCH_GBE_RX_RST); | ||
225 | /* Setup the MAC address */ | ||
226 | pch_gbe_mac_mar_set(hw, hw->mac.addr, 0); | ||
227 | return; | ||
228 | } | ||
229 | |||
192 | /** | 230 | /** |
193 | * pch_gbe_mac_init_rx_addrs - Initialize receive address's | 231 | * pch_gbe_mac_init_rx_addrs - Initialize receive address's |
194 | * @hw: Pointer to the HW structure | 232 | * @hw: Pointer to the HW structure |
@@ -671,13 +709,8 @@ static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter) | |||
671 | 709 | ||
672 | tcpip = ioread32(&hw->reg->TCPIP_ACC); | 710 | tcpip = ioread32(&hw->reg->TCPIP_ACC); |
673 | 711 | ||
674 | if (netdev->features & NETIF_F_RXCSUM) { | 712 | tcpip |= PCH_GBE_RX_TCPIPACC_OFF; |
675 | tcpip &= ~PCH_GBE_RX_TCPIPACC_OFF; | 713 | tcpip &= ~PCH_GBE_RX_TCPIPACC_EN; |
676 | tcpip |= PCH_GBE_RX_TCPIPACC_EN; | ||
677 | } else { | ||
678 | tcpip |= PCH_GBE_RX_TCPIPACC_OFF; | ||
679 | tcpip &= ~PCH_GBE_RX_TCPIPACC_EN; | ||
680 | } | ||
681 | iowrite32(tcpip, &hw->reg->TCPIP_ACC); | 714 | iowrite32(tcpip, &hw->reg->TCPIP_ACC); |
682 | return; | 715 | return; |
683 | } | 716 | } |
@@ -717,13 +750,6 @@ static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter) | |||
717 | iowrite32(rdba, &hw->reg->RX_DSC_BASE); | 750 | iowrite32(rdba, &hw->reg->RX_DSC_BASE); |
718 | iowrite32(rdlen, &hw->reg->RX_DSC_SIZE); | 751 | iowrite32(rdlen, &hw->reg->RX_DSC_SIZE); |
719 | iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P); | 752 | iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P); |
720 | |||
721 | /* Enables Receive DMA */ | ||
722 | rxdma = ioread32(&hw->reg->DMA_CTRL); | ||
723 | rxdma |= PCH_GBE_RX_DMA_EN; | ||
724 | iowrite32(rxdma, &hw->reg->DMA_CTRL); | ||
725 | /* Enables Receive */ | ||
726 | iowrite32(PCH_GBE_MRE_MAC_RX_EN, &hw->reg->MAC_RX_EN); | ||
727 | } | 753 | } |
728 | 754 | ||
729 | /** | 755 | /** |
@@ -1097,6 +1123,48 @@ void pch_gbe_update_stats(struct pch_gbe_adapter *adapter) | |||
1097 | spin_unlock_irqrestore(&adapter->stats_lock, flags); | 1123 | spin_unlock_irqrestore(&adapter->stats_lock, flags); |
1098 | } | 1124 | } |
1099 | 1125 | ||
1126 | static void pch_gbe_stop_receive(struct pch_gbe_adapter *adapter) | ||
1127 | { | ||
1128 | struct pch_gbe_hw *hw = &adapter->hw; | ||
1129 | u32 rxdma; | ||
1130 | u16 value; | ||
1131 | int ret; | ||
1132 | |||
1133 | /* Disable Receive DMA */ | ||
1134 | rxdma = ioread32(&hw->reg->DMA_CTRL); | ||
1135 | rxdma &= ~PCH_GBE_RX_DMA_EN; | ||
1136 | iowrite32(rxdma, &hw->reg->DMA_CTRL); | ||
1137 | /* Wait Rx DMA BUS is IDLE */ | ||
1138 | ret = pch_gbe_wait_clr_bit_irq(&hw->reg->RX_DMA_ST, PCH_GBE_IDLE_CHECK); | ||
1139 | if (ret) { | ||
1140 | /* Disable Bus master */ | ||
1141 | pci_read_config_word(adapter->pdev, PCI_COMMAND, &value); | ||
1142 | value &= ~PCI_COMMAND_MASTER; | ||
1143 | pci_write_config_word(adapter->pdev, PCI_COMMAND, value); | ||
1144 | /* Stop Receive */ | ||
1145 | pch_gbe_mac_reset_rx(hw); | ||
1146 | /* Enable Bus master */ | ||
1147 | value |= PCI_COMMAND_MASTER; | ||
1148 | pci_write_config_word(adapter->pdev, PCI_COMMAND, value); | ||
1149 | } else { | ||
1150 | /* Stop Receive */ | ||
1151 | pch_gbe_mac_reset_rx(hw); | ||
1152 | } | ||
1153 | } | ||
1154 | |||
1155 | static void pch_gbe_start_receive(struct pch_gbe_hw *hw) | ||
1156 | { | ||
1157 | u32 rxdma; | ||
1158 | |||
1159 | /* Enables Receive DMA */ | ||
1160 | rxdma = ioread32(&hw->reg->DMA_CTRL); | ||
1161 | rxdma |= PCH_GBE_RX_DMA_EN; | ||
1162 | iowrite32(rxdma, &hw->reg->DMA_CTRL); | ||
1163 | /* Enables Receive */ | ||
1164 | iowrite32(PCH_GBE_MRE_MAC_RX_EN, &hw->reg->MAC_RX_EN); | ||
1165 | return; | ||
1166 | } | ||
1167 | |||
1100 | /** | 1168 | /** |
1101 | * pch_gbe_intr - Interrupt Handler | 1169 | * pch_gbe_intr - Interrupt Handler |
1102 | * @irq: Interrupt number | 1170 | * @irq: Interrupt number |
@@ -1123,7 +1191,15 @@ static irqreturn_t pch_gbe_intr(int irq, void *data) | |||
1123 | if (int_st & PCH_GBE_INT_RX_FRAME_ERR) | 1191 | if (int_st & PCH_GBE_INT_RX_FRAME_ERR) |
1124 | adapter->stats.intr_rx_frame_err_count++; | 1192 | adapter->stats.intr_rx_frame_err_count++; |
1125 | if (int_st & PCH_GBE_INT_RX_FIFO_ERR) | 1193 | if (int_st & PCH_GBE_INT_RX_FIFO_ERR) |
1126 | adapter->stats.intr_rx_fifo_err_count++; | 1194 | if (!adapter->rx_stop_flag) { |
1195 | adapter->stats.intr_rx_fifo_err_count++; | ||
1196 | pr_debug("Rx fifo over run\n"); | ||
1197 | adapter->rx_stop_flag = true; | ||
1198 | int_en = ioread32(&hw->reg->INT_EN); | ||
1199 | iowrite32((int_en & ~PCH_GBE_INT_RX_FIFO_ERR), | ||
1200 | &hw->reg->INT_EN); | ||
1201 | pch_gbe_stop_receive(adapter); | ||
1202 | } | ||
1127 | if (int_st & PCH_GBE_INT_RX_DMA_ERR) | 1203 | if (int_st & PCH_GBE_INT_RX_DMA_ERR) |
1128 | adapter->stats.intr_rx_dma_err_count++; | 1204 | adapter->stats.intr_rx_dma_err_count++; |
1129 | if (int_st & PCH_GBE_INT_TX_FIFO_ERR) | 1205 | if (int_st & PCH_GBE_INT_TX_FIFO_ERR) |
@@ -1135,7 +1211,7 @@ static irqreturn_t pch_gbe_intr(int irq, void *data) | |||
1135 | /* When Rx descriptor is empty */ | 1211 | /* When Rx descriptor is empty */ |
1136 | if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) { | 1212 | if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) { |
1137 | adapter->stats.intr_rx_dsc_empty_count++; | 1213 | adapter->stats.intr_rx_dsc_empty_count++; |
1138 | pr_err("Rx descriptor is empty\n"); | 1214 | pr_debug("Rx descriptor is empty\n"); |
1139 | int_en = ioread32(&hw->reg->INT_EN); | 1215 | int_en = ioread32(&hw->reg->INT_EN); |
1140 | iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN); | 1216 | iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN); |
1141 | if (hw->mac.tx_fc_enable) { | 1217 | if (hw->mac.tx_fc_enable) { |
@@ -1185,29 +1261,23 @@ pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter, | |||
1185 | unsigned int i; | 1261 | unsigned int i; |
1186 | unsigned int bufsz; | 1262 | unsigned int bufsz; |
1187 | 1263 | ||
1188 | bufsz = adapter->rx_buffer_len + PCH_GBE_DMA_ALIGN; | 1264 | bufsz = adapter->rx_buffer_len + NET_IP_ALIGN; |
1189 | i = rx_ring->next_to_use; | 1265 | i = rx_ring->next_to_use; |
1190 | 1266 | ||
1191 | while ((cleaned_count--)) { | 1267 | while ((cleaned_count--)) { |
1192 | buffer_info = &rx_ring->buffer_info[i]; | 1268 | buffer_info = &rx_ring->buffer_info[i]; |
1193 | skb = buffer_info->skb; | 1269 | skb = netdev_alloc_skb(netdev, bufsz); |
1194 | if (skb) { | 1270 | if (unlikely(!skb)) { |
1195 | skb_trim(skb, 0); | 1271 | /* Better luck next round */ |
1196 | } else { | 1272 | adapter->stats.rx_alloc_buff_failed++; |
1197 | skb = netdev_alloc_skb(netdev, bufsz); | 1273 | break; |
1198 | if (unlikely(!skb)) { | ||
1199 | /* Better luck next round */ | ||
1200 | adapter->stats.rx_alloc_buff_failed++; | ||
1201 | break; | ||
1202 | } | ||
1203 | /* 64byte align */ | ||
1204 | skb_reserve(skb, PCH_GBE_DMA_ALIGN); | ||
1205 | |||
1206 | buffer_info->skb = skb; | ||
1207 | buffer_info->length = adapter->rx_buffer_len; | ||
1208 | } | 1274 | } |
1275 | /* align */ | ||
1276 | skb_reserve(skb, NET_IP_ALIGN); | ||
1277 | buffer_info->skb = skb; | ||
1278 | |||
1209 | buffer_info->dma = dma_map_single(&pdev->dev, | 1279 | buffer_info->dma = dma_map_single(&pdev->dev, |
1210 | skb->data, | 1280 | buffer_info->rx_buffer, |
1211 | buffer_info->length, | 1281 | buffer_info->length, |
1212 | DMA_FROM_DEVICE); | 1282 | DMA_FROM_DEVICE); |
1213 | if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) { | 1283 | if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) { |
@@ -1240,6 +1310,36 @@ pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter, | |||
1240 | return; | 1310 | return; |
1241 | } | 1311 | } |
1242 | 1312 | ||
1313 | static int | ||
1314 | pch_gbe_alloc_rx_buffers_pool(struct pch_gbe_adapter *adapter, | ||
1315 | struct pch_gbe_rx_ring *rx_ring, int cleaned_count) | ||
1316 | { | ||
1317 | struct pci_dev *pdev = adapter->pdev; | ||
1318 | struct pch_gbe_buffer *buffer_info; | ||
1319 | unsigned int i; | ||
1320 | unsigned int bufsz; | ||
1321 | unsigned int size; | ||
1322 | |||
1323 | bufsz = adapter->rx_buffer_len; | ||
1324 | |||
1325 | size = rx_ring->count * bufsz + PCH_GBE_RESERVE_MEMORY; | ||
1326 | rx_ring->rx_buff_pool = dma_alloc_coherent(&pdev->dev, size, | ||
1327 | &rx_ring->rx_buff_pool_logic, | ||
1328 | GFP_KERNEL); | ||
1329 | if (!rx_ring->rx_buff_pool) { | ||
1330 | pr_err("Unable to allocate memory for the receive poll buffer\n"); | ||
1331 | return -ENOMEM; | ||
1332 | } | ||
1333 | memset(rx_ring->rx_buff_pool, 0, size); | ||
1334 | rx_ring->rx_buff_pool_size = size; | ||
1335 | for (i = 0; i < rx_ring->count; i++) { | ||
1336 | buffer_info = &rx_ring->buffer_info[i]; | ||
1337 | buffer_info->rx_buffer = rx_ring->rx_buff_pool + bufsz * i; | ||
1338 | buffer_info->length = bufsz; | ||
1339 | } | ||
1340 | return 0; | ||
1341 | } | ||
1342 | |||
1243 | /** | 1343 | /** |
1244 | * pch_gbe_alloc_tx_buffers - Allocate transmit buffers | 1344 | * pch_gbe_alloc_tx_buffers - Allocate transmit buffers |
1245 | * @adapter: Board private structure | 1345 | * @adapter: Board private structure |
@@ -1380,7 +1480,7 @@ pch_gbe_clean_rx(struct pch_gbe_adapter *adapter, | |||
1380 | unsigned int i; | 1480 | unsigned int i; |
1381 | unsigned int cleaned_count = 0; | 1481 | unsigned int cleaned_count = 0; |
1382 | bool cleaned = false; | 1482 | bool cleaned = false; |
1383 | struct sk_buff *skb, *new_skb; | 1483 | struct sk_buff *skb; |
1384 | u8 dma_status; | 1484 | u8 dma_status; |
1385 | u16 gbec_status; | 1485 | u16 gbec_status; |
1386 | u32 tcp_ip_status; | 1486 | u32 tcp_ip_status; |
@@ -1401,13 +1501,12 @@ pch_gbe_clean_rx(struct pch_gbe_adapter *adapter, | |||
1401 | rx_desc->gbec_status = DSC_INIT16; | 1501 | rx_desc->gbec_status = DSC_INIT16; |
1402 | buffer_info = &rx_ring->buffer_info[i]; | 1502 | buffer_info = &rx_ring->buffer_info[i]; |
1403 | skb = buffer_info->skb; | 1503 | skb = buffer_info->skb; |
1504 | buffer_info->skb = NULL; | ||
1404 | 1505 | ||
1405 | /* unmap dma */ | 1506 | /* unmap dma */ |
1406 | dma_unmap_single(&pdev->dev, buffer_info->dma, | 1507 | dma_unmap_single(&pdev->dev, buffer_info->dma, |
1407 | buffer_info->length, DMA_FROM_DEVICE); | 1508 | buffer_info->length, DMA_FROM_DEVICE); |
1408 | buffer_info->mapped = false; | 1509 | buffer_info->mapped = false; |
1409 | /* Prefetch the packet */ | ||
1410 | prefetch(skb->data); | ||
1411 | 1510 | ||
1412 | pr_debug("RxDecNo = 0x%04x Status[DMA:0x%02x GBE:0x%04x " | 1511 | pr_debug("RxDecNo = 0x%04x Status[DMA:0x%02x GBE:0x%04x " |
1413 | "TCP:0x%08x] BufInf = 0x%p\n", | 1512 | "TCP:0x%08x] BufInf = 0x%p\n", |
@@ -1427,70 +1526,16 @@ pch_gbe_clean_rx(struct pch_gbe_adapter *adapter, | |||
1427 | pr_err("Receive CRC Error\n"); | 1526 | pr_err("Receive CRC Error\n"); |
1428 | } else { | 1527 | } else { |
1429 | /* get receive length */ | 1528 | /* get receive length */ |
1430 | /* length convert[-3] */ | 1529 | /* length convert[-3], length includes FCS length */ |
1431 | length = (rx_desc->rx_words_eob) - 3; | 1530 | length = (rx_desc->rx_words_eob) - 3 - ETH_FCS_LEN; |
1432 | 1531 | if (rx_desc->rx_words_eob & 0x02) | |
1433 | /* Decide the data conversion method */ | 1532 | length = length - 4; |
1434 | if (!(netdev->features & NETIF_F_RXCSUM)) { | 1533 | /* |
1435 | /* [Header:14][payload] */ | 1534 | * buffer_info->rx_buffer: [Header:14][payload] |
1436 | if (NET_IP_ALIGN) { | 1535 | * skb->data: [Reserve:2][Header:14][payload] |
1437 | /* Because alignment differs, | 1536 | */ |
1438 | * the new_skb is newly allocated, | 1537 | memcpy(skb->data, buffer_info->rx_buffer, length); |
1439 | * and data is copied to new_skb.*/ | 1538 | |
1440 | new_skb = netdev_alloc_skb(netdev, | ||
1441 | length + NET_IP_ALIGN); | ||
1442 | if (!new_skb) { | ||
1443 | /* dorrop error */ | ||
1444 | pr_err("New skb allocation " | ||
1445 | "Error\n"); | ||
1446 | goto dorrop; | ||
1447 | } | ||
1448 | skb_reserve(new_skb, NET_IP_ALIGN); | ||
1449 | memcpy(new_skb->data, skb->data, | ||
1450 | length); | ||
1451 | skb = new_skb; | ||
1452 | } else { | ||
1453 | /* DMA buffer is used as SKB as it is.*/ | ||
1454 | buffer_info->skb = NULL; | ||
1455 | } | ||
1456 | } else { | ||
1457 | /* [Header:14][padding:2][payload] */ | ||
1458 | /* The length includes padding length */ | ||
1459 | length = length - PCH_GBE_DMA_PADDING; | ||
1460 | if ((length < copybreak) || | ||
1461 | (NET_IP_ALIGN != PCH_GBE_DMA_PADDING)) { | ||
1462 | /* Because alignment differs, | ||
1463 | * the new_skb is newly allocated, | ||
1464 | * and data is copied to new_skb. | ||
1465 | * Padding data is deleted | ||
1466 | * at the time of a copy.*/ | ||
1467 | new_skb = netdev_alloc_skb(netdev, | ||
1468 | length + NET_IP_ALIGN); | ||
1469 | if (!new_skb) { | ||
1470 | /* dorrop error */ | ||
1471 | pr_err("New skb allocation " | ||
1472 | "Error\n"); | ||
1473 | goto dorrop; | ||
1474 | } | ||
1475 | skb_reserve(new_skb, NET_IP_ALIGN); | ||
1476 | memcpy(new_skb->data, skb->data, | ||
1477 | ETH_HLEN); | ||
1478 | memcpy(&new_skb->data[ETH_HLEN], | ||
1479 | &skb->data[ETH_HLEN + | ||
1480 | PCH_GBE_DMA_PADDING], | ||
1481 | length - ETH_HLEN); | ||
1482 | skb = new_skb; | ||
1483 | } else { | ||
1484 | /* Padding data is deleted | ||
1485 | * by moving header data.*/ | ||
1486 | memmove(&skb->data[PCH_GBE_DMA_PADDING], | ||
1487 | &skb->data[0], ETH_HLEN); | ||
1488 | skb_reserve(skb, NET_IP_ALIGN); | ||
1489 | buffer_info->skb = NULL; | ||
1490 | } | ||
1491 | } | ||
1492 | /* The length includes FCS length */ | ||
1493 | length = length - ETH_FCS_LEN; | ||
1494 | /* update status of driver */ | 1539 | /* update status of driver */ |
1495 | adapter->stats.rx_bytes += length; | 1540 | adapter->stats.rx_bytes += length; |
1496 | adapter->stats.rx_packets++; | 1541 | adapter->stats.rx_packets++; |
@@ -1509,7 +1554,6 @@ pch_gbe_clean_rx(struct pch_gbe_adapter *adapter, | |||
1509 | pr_debug("Receive skb->ip_summed: %d length: %d\n", | 1554 | pr_debug("Receive skb->ip_summed: %d length: %d\n", |
1510 | skb->ip_summed, length); | 1555 | skb->ip_summed, length); |
1511 | } | 1556 | } |
1512 | dorrop: | ||
1513 | /* return some buffers to hardware, one at a time is too slow */ | 1557 | /* return some buffers to hardware, one at a time is too slow */ |
1514 | if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) { | 1558 | if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) { |
1515 | pch_gbe_alloc_rx_buffers(adapter, rx_ring, | 1559 | pch_gbe_alloc_rx_buffers(adapter, rx_ring, |
@@ -1714,9 +1758,15 @@ int pch_gbe_up(struct pch_gbe_adapter *adapter) | |||
1714 | pr_err("Error: can't bring device up\n"); | 1758 | pr_err("Error: can't bring device up\n"); |
1715 | return err; | 1759 | return err; |
1716 | } | 1760 | } |
1761 | err = pch_gbe_alloc_rx_buffers_pool(adapter, rx_ring, rx_ring->count); | ||
1762 | if (err) { | ||
1763 | pr_err("Error: can't bring device up\n"); | ||
1764 | return err; | ||
1765 | } | ||
1717 | pch_gbe_alloc_tx_buffers(adapter, tx_ring); | 1766 | pch_gbe_alloc_tx_buffers(adapter, tx_ring); |
1718 | pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count); | 1767 | pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count); |
1719 | adapter->tx_queue_len = netdev->tx_queue_len; | 1768 | adapter->tx_queue_len = netdev->tx_queue_len; |
1769 | pch_gbe_start_receive(&adapter->hw); | ||
1720 | 1770 | ||
1721 | mod_timer(&adapter->watchdog_timer, jiffies); | 1771 | mod_timer(&adapter->watchdog_timer, jiffies); |
1722 | 1772 | ||
@@ -1734,6 +1784,7 @@ int pch_gbe_up(struct pch_gbe_adapter *adapter) | |||
1734 | void pch_gbe_down(struct pch_gbe_adapter *adapter) | 1784 | void pch_gbe_down(struct pch_gbe_adapter *adapter) |
1735 | { | 1785 | { |
1736 | struct net_device *netdev = adapter->netdev; | 1786 | struct net_device *netdev = adapter->netdev; |
1787 | struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring; | ||
1737 | 1788 | ||
1738 | /* signal that we're down so the interrupt handler does not | 1789 | /* signal that we're down so the interrupt handler does not |
1739 | * reschedule our watchdog timer */ | 1790 | * reschedule our watchdog timer */ |
@@ -1752,6 +1803,12 @@ void pch_gbe_down(struct pch_gbe_adapter *adapter) | |||
1752 | pch_gbe_reset(adapter); | 1803 | pch_gbe_reset(adapter); |
1753 | pch_gbe_clean_tx_ring(adapter, adapter->tx_ring); | 1804 | pch_gbe_clean_tx_ring(adapter, adapter->tx_ring); |
1754 | pch_gbe_clean_rx_ring(adapter, adapter->rx_ring); | 1805 | pch_gbe_clean_rx_ring(adapter, adapter->rx_ring); |
1806 | |||
1807 | pci_free_consistent(adapter->pdev, rx_ring->rx_buff_pool_size, | ||
1808 | rx_ring->rx_buff_pool, rx_ring->rx_buff_pool_logic); | ||
1809 | rx_ring->rx_buff_pool_logic = 0; | ||
1810 | rx_ring->rx_buff_pool_size = 0; | ||
1811 | rx_ring->rx_buff_pool = NULL; | ||
1755 | } | 1812 | } |
1756 | 1813 | ||
1757 | /** | 1814 | /** |
@@ -2004,6 +2061,8 @@ static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu) | |||
2004 | { | 2061 | { |
2005 | struct pch_gbe_adapter *adapter = netdev_priv(netdev); | 2062 | struct pch_gbe_adapter *adapter = netdev_priv(netdev); |
2006 | int max_frame; | 2063 | int max_frame; |
2064 | unsigned long old_rx_buffer_len = adapter->rx_buffer_len; | ||
2065 | int err; | ||
2007 | 2066 | ||
2008 | max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | 2067 | max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; |
2009 | if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) || | 2068 | if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) || |
@@ -2018,14 +2077,24 @@ static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu) | |||
2018 | else if (max_frame <= PCH_GBE_FRAME_SIZE_8192) | 2077 | else if (max_frame <= PCH_GBE_FRAME_SIZE_8192) |
2019 | adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192; | 2078 | adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192; |
2020 | else | 2079 | else |
2021 | adapter->rx_buffer_len = PCH_GBE_MAX_JUMBO_FRAME_SIZE; | 2080 | adapter->rx_buffer_len = PCH_GBE_MAX_RX_BUFFER_SIZE; |
2022 | netdev->mtu = new_mtu; | ||
2023 | adapter->hw.mac.max_frame_size = max_frame; | ||
2024 | 2081 | ||
2025 | if (netif_running(netdev)) | 2082 | if (netif_running(netdev)) { |
2026 | pch_gbe_reinit_locked(adapter); | 2083 | pch_gbe_down(adapter); |
2027 | else | 2084 | err = pch_gbe_up(adapter); |
2085 | if (err) { | ||
2086 | adapter->rx_buffer_len = old_rx_buffer_len; | ||
2087 | pch_gbe_up(adapter); | ||
2088 | return -ENOMEM; | ||
2089 | } else { | ||
2090 | netdev->mtu = new_mtu; | ||
2091 | adapter->hw.mac.max_frame_size = max_frame; | ||
2092 | } | ||
2093 | } else { | ||
2028 | pch_gbe_reset(adapter); | 2094 | pch_gbe_reset(adapter); |
2095 | netdev->mtu = new_mtu; | ||
2096 | adapter->hw.mac.max_frame_size = max_frame; | ||
2097 | } | ||
2029 | 2098 | ||
2030 | pr_debug("max_frame : %d rx_buffer_len : %d mtu : %d max_frame_size : %d\n", | 2099 | pr_debug("max_frame : %d rx_buffer_len : %d mtu : %d max_frame_size : %d\n", |
2031 | max_frame, (u32) adapter->rx_buffer_len, netdev->mtu, | 2100 | max_frame, (u32) adapter->rx_buffer_len, netdev->mtu, |
@@ -2103,6 +2172,7 @@ static int pch_gbe_napi_poll(struct napi_struct *napi, int budget) | |||
2103 | int work_done = 0; | 2172 | int work_done = 0; |
2104 | bool poll_end_flag = false; | 2173 | bool poll_end_flag = false; |
2105 | bool cleaned = false; | 2174 | bool cleaned = false; |
2175 | u32 int_en; | ||
2106 | 2176 | ||
2107 | pr_debug("budget : %d\n", budget); | 2177 | pr_debug("budget : %d\n", budget); |
2108 | 2178 | ||
@@ -2110,8 +2180,15 @@ static int pch_gbe_napi_poll(struct napi_struct *napi, int budget) | |||
2110 | if (!netif_carrier_ok(netdev)) { | 2180 | if (!netif_carrier_ok(netdev)) { |
2111 | poll_end_flag = true; | 2181 | poll_end_flag = true; |
2112 | } else { | 2182 | } else { |
2113 | cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring); | ||
2114 | pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget); | 2183 | pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget); |
2184 | if (adapter->rx_stop_flag) { | ||
2185 | adapter->rx_stop_flag = false; | ||
2186 | pch_gbe_start_receive(&adapter->hw); | ||
2187 | int_en = ioread32(&adapter->hw.reg->INT_EN); | ||
2188 | iowrite32((int_en | PCH_GBE_INT_RX_FIFO_ERR), | ||
2189 | &adapter->hw.reg->INT_EN); | ||
2190 | } | ||
2191 | cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring); | ||
2115 | 2192 | ||
2116 | if (cleaned) | 2193 | if (cleaned) |
2117 | work_done = budget; | 2194 | work_done = budget; |
@@ -2452,6 +2529,13 @@ static DEFINE_PCI_DEVICE_TABLE(pch_gbe_pcidev_id) = { | |||
2452 | .class = (PCI_CLASS_NETWORK_ETHERNET << 8), | 2529 | .class = (PCI_CLASS_NETWORK_ETHERNET << 8), |
2453 | .class_mask = (0xFFFF00) | 2530 | .class_mask = (0xFFFF00) |
2454 | }, | 2531 | }, |
2532 | {.vendor = PCI_VENDOR_ID_ROHM, | ||
2533 | .device = PCI_DEVICE_ID_ROHM_ML7831_GBE, | ||
2534 | .subvendor = PCI_ANY_ID, | ||
2535 | .subdevice = PCI_ANY_ID, | ||
2536 | .class = (PCI_CLASS_NETWORK_ETHERNET << 8), | ||
2537 | .class_mask = (0xFFFF00) | ||
2538 | }, | ||
2455 | /* required last entry */ | 2539 | /* required last entry */ |
2456 | {0} | 2540 | {0} |
2457 | }; | 2541 | }; |