aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/ethernet/marvell/sky2.c
diff options
context:
space:
mode:
authorMirko Lindner <mlindner@marvell.com>2012-07-03 19:38:41 -0400
committerDavid S. Miller <davem@davemloft.net>2012-07-09 03:05:40 -0400
commit0e767324f26fd5e103381d05a65a76ecf50a699a (patch)
treee927f1b5da866d701ef934e1e607dc92f6cacd91 /drivers/net/ethernet/marvell/sky2.c
parent03fc4721cd96753696a988a2ba563f9f08ad4e9f (diff)
sky2: Added support for Optima EEE
This patch adds support for the Optima EEE chipset. Signed-off-by: Mirko Lindner <mlindner@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/marvell/sky2.c')
-rw-r--r--drivers/net/ethernet/marvell/sky2.c14
1 files changed, 13 insertions, 1 deletions
diff --git a/drivers/net/ethernet/marvell/sky2.c b/drivers/net/ethernet/marvell/sky2.c
index 28a54451a3e5..f1163b2aa284 100644
--- a/drivers/net/ethernet/marvell/sky2.c
+++ b/drivers/net/ethernet/marvell/sky2.c
@@ -141,6 +141,7 @@ static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */ 141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */ 142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */ 143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
144 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4382) }, /* 88E8079 */
144 { 0 } 145 { 0 }
145}; 146};
146 147
@@ -3349,6 +3350,17 @@ static void sky2_reset(struct sky2_hw *hw)
3349 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL, 3350 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL,
3350 reg); 3351 reg);
3351 3352
3353 if (hw->chip_id == CHIP_ID_YUKON_PRM &&
3354 hw->chip_rev == CHIP_REV_YU_PRM_A0) {
3355 /* change PHY Interrupt polarity to low active */
3356 reg = sky2_read16(hw, GPHY_CTRL);
3357 sky2_write16(hw, GPHY_CTRL, reg | GPC_INTPOL);
3358
3359 /* adapt HW for low active PHY Interrupt */
3360 reg = sky2_read16(hw, Y2_CFG_SPC + PCI_LDO_CTRL);
3361 sky2_write16(hw, Y2_CFG_SPC + PCI_LDO_CTRL, reg | PHY_M_UNDOC1);
3362 }
3363
3352 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3364 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3353 3365
3354 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */ 3366 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
@@ -4871,7 +4883,7 @@ static const char *sky2_name(u8 chipid, char *buf, int sz)
4871 "UL 2", /* 0xba */ 4883 "UL 2", /* 0xba */
4872 "Unknown", /* 0xbb */ 4884 "Unknown", /* 0xbb */
4873 "Optima", /* 0xbc */ 4885 "Optima", /* 0xbc */
4874 "Optima Prime", /* 0xbd */ 4886 "OptimaEEE", /* 0xbd */
4875 "Optima 2", /* 0xbe */ 4887 "Optima 2", /* 0xbe */
4876 }; 4888 };
4877 4889