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authorAndrew Lunn <andrew@lunn.ch>2012-06-06 02:40:43 -0400
committerDavid S. Miller <davem@davemloft.net>2012-06-06 13:38:38 -0400
commit9a43a02648e8414b2a757437820aa928208fc42f (patch)
tree1b672640c63260e8d1718c24ed213c3a749b4c0f /drivers/net/ethernet/marvell/mv643xx_eth.c
parentba27ec66ffeb78cbf9f85e168b32551a9aaf2a34 (diff)
mv643xx_eth: Fix compile error for architectures without clk.
Commit 452503ebc (ARM: Orion: Eth: Add clk/clkdev support.) broke the building of the driver on architectures which don't have clk support. In particular PPC32 Pegasos which uses this driver. Add #ifdef around the clk API usage. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/marvell/mv643xx_eth.c')
-rw-r--r--drivers/net/ethernet/marvell/mv643xx_eth.c15
1 files changed, 10 insertions, 5 deletions
diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
index 04d901d0ff63..f0f06b2bc28b 100644
--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
@@ -436,7 +436,9 @@ struct mv643xx_eth_private {
436 /* 436 /*
437 * Hardware-specific parameters. 437 * Hardware-specific parameters.
438 */ 438 */
439#if defined(CONFIG_HAVE_CLK)
439 struct clk *clk; 440 struct clk *clk;
441#endif
440 unsigned int t_clk; 442 unsigned int t_clk;
441}; 443};
442 444
@@ -2895,17 +2897,17 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
2895 mp->dev = dev; 2897 mp->dev = dev;
2896 2898
2897 /* 2899 /*
2898 * Get the clk rate, if there is one, otherwise use the default. 2900 * Start with a default rate, and if there is a clock, allow
2901 * it to override the default.
2899 */ 2902 */
2903 mp->t_clk = 133000000;
2904#if defined(CONFIG_HAVE_CLK)
2900 mp->clk = clk_get(&pdev->dev, (pdev->id ? "1" : "0")); 2905 mp->clk = clk_get(&pdev->dev, (pdev->id ? "1" : "0"));
2901 if (!IS_ERR(mp->clk)) { 2906 if (!IS_ERR(mp->clk)) {
2902 clk_prepare_enable(mp->clk); 2907 clk_prepare_enable(mp->clk);
2903 mp->t_clk = clk_get_rate(mp->clk); 2908 mp->t_clk = clk_get_rate(mp->clk);
2904 } else {
2905 mp->t_clk = 133000000;
2906 printk(KERN_WARNING "Unable to get clock");
2907 } 2909 }
2908 2910#endif
2909 set_params(mp, pd); 2911 set_params(mp, pd);
2910 netif_set_real_num_tx_queues(dev, mp->txq_count); 2912 netif_set_real_num_tx_queues(dev, mp->txq_count);
2911 netif_set_real_num_rx_queues(dev, mp->rxq_count); 2913 netif_set_real_num_rx_queues(dev, mp->rxq_count);
@@ -2995,10 +2997,13 @@ static int mv643xx_eth_remove(struct platform_device *pdev)
2995 phy_detach(mp->phy); 2997 phy_detach(mp->phy);
2996 cancel_work_sync(&mp->tx_timeout_task); 2998 cancel_work_sync(&mp->tx_timeout_task);
2997 2999
3000#if defined(CONFIG_HAVE_CLK)
2998 if (!IS_ERR(mp->clk)) { 3001 if (!IS_ERR(mp->clk)) {
2999 clk_disable_unprepare(mp->clk); 3002 clk_disable_unprepare(mp->clk);
3000 clk_put(mp->clk); 3003 clk_put(mp->clk);
3001 } 3004 }
3005#endif
3006
3002 free_netdev(mp->dev); 3007 free_netdev(mp->dev);
3003 3008
3004 platform_set_drvdata(pdev, NULL); 3009 platform_set_drvdata(pdev, NULL);