aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/ethernet/intel
diff options
context:
space:
mode:
authorAlexander Duyck <alexander.h.duyck@intel.com>2012-09-13 02:28:11 -0400
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2012-09-22 06:01:00 -0400
commit797fd4be7b6968ea752ae47367ae95454124a698 (patch)
tree8aa173ed6f531993398581279dbe72e4092d9448 /drivers/net/ethernet/intel
parentf4128785b8f3f1fd7dc81b972661003d639a4676 (diff)
igb: Change how we populate the RSS indirection table
This patch cleans up our RSS indirection table configuration so that we generate the same table regardless of CPU endianness. In addition it changes the table setup so that instead of doing a modulo based setup it is instead a divisor based setup. The advantage to this is that we should be able to take the Rx hash and compute the Rx queue with very little CPU overhead if needed. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel')
-rw-r--r--drivers/net/ethernet/intel/igb/igb_main.c55
1 files changed, 26 insertions, 29 deletions
diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c
index 91f542c50f61..27688d9d2b64 100644
--- a/drivers/net/ethernet/intel/igb/igb_main.c
+++ b/drivers/net/ethernet/intel/igb/igb_main.c
@@ -2834,11 +2834,7 @@ static void igb_setup_mrqc(struct igb_adapter *adapter)
2834{ 2834{
2835 struct e1000_hw *hw = &adapter->hw; 2835 struct e1000_hw *hw = &adapter->hw;
2836 u32 mrqc, rxcsum; 2836 u32 mrqc, rxcsum;
2837 u32 j, num_rx_queues, shift = 0, shift2 = 0; 2837 u32 j, num_rx_queues, shift = 0;
2838 union e1000_reta {
2839 u32 dword;
2840 u8 bytes[4];
2841 } reta;
2842 static const u8 rsshash[40] = { 2838 static const u8 rsshash[40] = {
2843 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, 0x41, 0x67, 2839 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, 0x41, 0x67,
2844 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, 0xd0, 0xca, 0x2b, 0xcb, 2840 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, 0xd0, 0xca, 0x2b, 0xcb,
@@ -2856,35 +2852,36 @@ static void igb_setup_mrqc(struct igb_adapter *adapter)
2856 2852
2857 num_rx_queues = adapter->rss_queues; 2853 num_rx_queues = adapter->rss_queues;
2858 2854
2859 if (adapter->vfs_allocated_count) { 2855 switch (hw->mac.type) {
2860 /* 82575 and 82576 supports 2 RSS queues for VMDq */ 2856 case e1000_82575:
2861 switch (hw->mac.type) { 2857 shift = 6;
2862 case e1000_i350: 2858 break;
2863 case e1000_82580: 2859 case e1000_82576:
2864 num_rx_queues = 1; 2860 /* 82576 supports 2 RSS queues for SR-IOV */
2865 shift = 0; 2861 if (adapter->vfs_allocated_count) {
2866 break;
2867 case e1000_82576:
2868 shift = 3; 2862 shift = 3;
2869 num_rx_queues = 2; 2863 num_rx_queues = 2;
2870 break;
2871 case e1000_82575:
2872 shift = 2;
2873 shift2 = 6;
2874 default:
2875 break;
2876 } 2864 }
2877 } else { 2865 break;
2878 if (hw->mac.type == e1000_82575) 2866 default:
2879 shift = 6; 2867 break;
2880 } 2868 }
2881 2869
2882 for (j = 0; j < (32 * 4); j++) { 2870 /*
2883 reta.bytes[j & 3] = (j % num_rx_queues) << shift; 2871 * Populate the indirection table 4 entries at a time. To do this
2884 if (shift2) 2872 * we are generating the results for n and n+2 and then interleaving
2885 reta.bytes[j & 3] |= num_rx_queues << shift2; 2873 * those with the results with n+1 and n+3.
2886 if ((j & 3) == 3) 2874 */
2887 wr32(E1000_RETA(j >> 2), reta.dword); 2875 for (j = 0; j < 32; j++) {
2876 /* first pass generates n and n+2 */
2877 u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues;
2878 u32 reta = (base & 0x07800780) >> (7 - shift);
2879
2880 /* second pass generates n+1 and n+3 */
2881 base += 0x00010001 * num_rx_queues;
2882 reta |= (base & 0x07800780) << (1 + shift);
2883
2884 wr32(E1000_RETA(j), reta);
2888 } 2885 }
2889 2886
2890 /* 2887 /*