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authorJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-04-07 10:42:33 -0400
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-08-10 23:03:27 -0400
commitdee1ad47f2ee75f5146d83ca757c1b7861c34c3b (patch)
tree47cbdefe3d0f9b729724e378ad6a96eaddfd5fbc /drivers/net/ethernet/intel/e1000
parentf7917c009c28c941ba151ee66f04dc7f6a2e1e0b (diff)
intel: Move the Intel wired LAN drivers
Moves the Intel wired LAN drivers into drivers/net/ethernet/intel/ and the necessary Kconfig and Makefile changes. Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel/e1000')
-rw-r--r--drivers/net/ethernet/intel/e1000/Makefile35
-rw-r--r--drivers/net/ethernet/intel/e1000/e1000.h361
-rw-r--r--drivers/net/ethernet/intel/e1000/e1000_ethtool.c1863
-rw-r--r--drivers/net/ethernet/intel/e1000/e1000_hw.c5824
-rw-r--r--drivers/net/ethernet/intel/e1000/e1000_hw.h3103
-rw-r--r--drivers/net/ethernet/intel/e1000/e1000_main.c4974
-rw-r--r--drivers/net/ethernet/intel/e1000/e1000_osdep.h109
-rw-r--r--drivers/net/ethernet/intel/e1000/e1000_param.c755
8 files changed, 17024 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/e1000/Makefile b/drivers/net/ethernet/intel/e1000/Makefile
new file mode 100644
index 000000000000..4a6ab1522451
--- /dev/null
+++ b/drivers/net/ethernet/intel/e1000/Makefile
@@ -0,0 +1,35 @@
1################################################################################
2#
3# Intel PRO/1000 Linux driver
4# Copyright(c) 1999 - 2006 Intel Corporation.
5#
6# This program is free software; you can redistribute it and/or modify it
7# under the terms and conditions of the GNU General Public License,
8# version 2, as published by the Free Software Foundation.
9#
10# This program is distributed in the hope it will be useful, but WITHOUT
11# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13# more details.
14#
15# You should have received a copy of the GNU General Public License along with
16# this program; if not, write to the Free Software Foundation, Inc.,
17# 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18#
19# The full GNU General Public License is included in this distribution in
20# the file called "COPYING".
21#
22# Contact Information:
23# Linux NICS <linux.nics@intel.com>
24# e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25# Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26#
27################################################################################
28
29#
30# Makefile for the Intel(R) PRO/1000 ethernet driver
31#
32
33obj-$(CONFIG_E1000) += e1000.o
34
35e1000-objs := e1000_main.o e1000_hw.o e1000_ethtool.o e1000_param.o
diff --git a/drivers/net/ethernet/intel/e1000/e1000.h b/drivers/net/ethernet/intel/e1000/e1000.h
new file mode 100644
index 000000000000..24f41da8c4be
--- /dev/null
+++ b/drivers/net/ethernet/intel/e1000/e1000.h
@@ -0,0 +1,361 @@
1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29
30/* Linux PRO/1000 Ethernet Driver main header file */
31
32#ifndef _E1000_H_
33#define _E1000_H_
34
35#include <linux/stddef.h>
36#include <linux/module.h>
37#include <linux/types.h>
38#include <asm/byteorder.h>
39#include <linux/init.h>
40#include <linux/mm.h>
41#include <linux/errno.h>
42#include <linux/ioport.h>
43#include <linux/pci.h>
44#include <linux/kernel.h>
45#include <linux/netdevice.h>
46#include <linux/etherdevice.h>
47#include <linux/skbuff.h>
48#include <linux/delay.h>
49#include <linux/timer.h>
50#include <linux/slab.h>
51#include <linux/vmalloc.h>
52#include <linux/interrupt.h>
53#include <linux/string.h>
54#include <linux/pagemap.h>
55#include <linux/dma-mapping.h>
56#include <linux/bitops.h>
57#include <asm/io.h>
58#include <asm/irq.h>
59#include <linux/capability.h>
60#include <linux/in.h>
61#include <linux/ip.h>
62#include <linux/ipv6.h>
63#include <linux/tcp.h>
64#include <linux/udp.h>
65#include <net/pkt_sched.h>
66#include <linux/list.h>
67#include <linux/reboot.h>
68#include <net/checksum.h>
69#include <linux/mii.h>
70#include <linux/ethtool.h>
71#include <linux/if_vlan.h>
72
73#define BAR_0 0
74#define BAR_1 1
75#define BAR_5 5
76
77#define INTEL_E1000_ETHERNET_DEVICE(device_id) {\
78 PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
79
80struct e1000_adapter;
81
82#include "e1000_hw.h"
83
84#define E1000_MAX_INTR 10
85
86/* TX/RX descriptor defines */
87#define E1000_DEFAULT_TXD 256
88#define E1000_MAX_TXD 256
89#define E1000_MIN_TXD 48
90#define E1000_MAX_82544_TXD 4096
91
92#define E1000_DEFAULT_RXD 256
93#define E1000_MAX_RXD 256
94#define E1000_MIN_RXD 48
95#define E1000_MAX_82544_RXD 4096
96
97#define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
98#define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
99
100/* this is the size past which hardware will drop packets when setting LPE=0 */
101#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
102
103/* Supported Rx Buffer Sizes */
104#define E1000_RXBUFFER_128 128 /* Used for packet split */
105#define E1000_RXBUFFER_256 256 /* Used for packet split */
106#define E1000_RXBUFFER_512 512
107#define E1000_RXBUFFER_1024 1024
108#define E1000_RXBUFFER_2048 2048
109#define E1000_RXBUFFER_4096 4096
110#define E1000_RXBUFFER_8192 8192
111#define E1000_RXBUFFER_16384 16384
112
113/* SmartSpeed delimiters */
114#define E1000_SMARTSPEED_DOWNSHIFT 3
115#define E1000_SMARTSPEED_MAX 15
116
117/* Packet Buffer allocations */
118#define E1000_PBA_BYTES_SHIFT 0xA
119#define E1000_TX_HEAD_ADDR_SHIFT 7
120#define E1000_PBA_TX_MASK 0xFFFF0000
121
122/* Flow Control Watermarks */
123#define E1000_FC_HIGH_DIFF 0x1638 /* High: 5688 bytes below Rx FIFO size */
124#define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */
125
126#define E1000_FC_PAUSE_TIME 0xFFFF /* pause for the max or until send xon */
127
128/* How many Tx Descriptors do we need to call netif_wake_queue ? */
129#define E1000_TX_QUEUE_WAKE 16
130/* How many Rx Buffers do we bundle into one write to the hardware ? */
131#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
132
133#define AUTO_ALL_MODES 0
134#define E1000_EEPROM_82544_APM 0x0004
135#define E1000_EEPROM_APME 0x0400
136
137#ifndef E1000_MASTER_SLAVE
138/* Switch to override PHY master/slave setting */
139#define E1000_MASTER_SLAVE e1000_ms_hw_default
140#endif
141
142#define E1000_MNG_VLAN_NONE (-1)
143
144/* wrapper around a pointer to a socket buffer,
145 * so a DMA handle can be stored along with the buffer */
146struct e1000_buffer {
147 struct sk_buff *skb;
148 dma_addr_t dma;
149 struct page *page;
150 unsigned long time_stamp;
151 u16 length;
152 u16 next_to_watch;
153 u16 mapped_as_page;
154};
155
156struct e1000_tx_ring {
157 /* pointer to the descriptor ring memory */
158 void *desc;
159 /* physical address of the descriptor ring */
160 dma_addr_t dma;
161 /* length of descriptor ring in bytes */
162 unsigned int size;
163 /* number of descriptors in the ring */
164 unsigned int count;
165 /* next descriptor to associate a buffer with */
166 unsigned int next_to_use;
167 /* next descriptor to check for DD status bit */
168 unsigned int next_to_clean;
169 /* array of buffer information structs */
170 struct e1000_buffer *buffer_info;
171
172 u16 tdh;
173 u16 tdt;
174 bool last_tx_tso;
175};
176
177struct e1000_rx_ring {
178 /* pointer to the descriptor ring memory */
179 void *desc;
180 /* physical address of the descriptor ring */
181 dma_addr_t dma;
182 /* length of descriptor ring in bytes */
183 unsigned int size;
184 /* number of descriptors in the ring */
185 unsigned int count;
186 /* next descriptor to associate a buffer with */
187 unsigned int next_to_use;
188 /* next descriptor to check for DD status bit */
189 unsigned int next_to_clean;
190 /* array of buffer information structs */
191 struct e1000_buffer *buffer_info;
192 struct sk_buff *rx_skb_top;
193
194 /* cpu for rx queue */
195 int cpu;
196
197 u16 rdh;
198 u16 rdt;
199};
200
201#define E1000_DESC_UNUSED(R) \
202 ((((R)->next_to_clean > (R)->next_to_use) \
203 ? 0 : (R)->count) + (R)->next_to_clean - (R)->next_to_use - 1)
204
205#define E1000_RX_DESC_EXT(R, i) \
206 (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
207#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
208#define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc)
209#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
210#define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
211
212/* board specific private data structure */
213
214struct e1000_adapter {
215 struct timer_list tx_fifo_stall_timer;
216 struct timer_list watchdog_timer;
217 struct timer_list phy_info_timer;
218 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
219 u16 mng_vlan_id;
220 u32 bd_number;
221 u32 rx_buffer_len;
222 u32 wol;
223 u32 smartspeed;
224 u32 en_mng_pt;
225 u16 link_speed;
226 u16 link_duplex;
227 spinlock_t stats_lock;
228 unsigned int total_tx_bytes;
229 unsigned int total_tx_packets;
230 unsigned int total_rx_bytes;
231 unsigned int total_rx_packets;
232 /* Interrupt Throttle Rate */
233 u32 itr;
234 u32 itr_setting;
235 u16 tx_itr;
236 u16 rx_itr;
237
238 struct work_struct reset_task;
239 u8 fc_autoneg;
240
241 /* TX */
242 struct e1000_tx_ring *tx_ring; /* One per active queue */
243 unsigned int restart_queue;
244 u32 txd_cmd;
245 u32 tx_int_delay;
246 u32 tx_abs_int_delay;
247 u32 gotcl;
248 u64 gotcl_old;
249 u64 tpt_old;
250 u64 colc_old;
251 u32 tx_timeout_count;
252 u32 tx_fifo_head;
253 u32 tx_head_addr;
254 u32 tx_fifo_size;
255 u8 tx_timeout_factor;
256 atomic_t tx_fifo_stall;
257 bool pcix_82544;
258 bool detect_tx_hung;
259
260 /* RX */
261 bool (*clean_rx)(struct e1000_adapter *adapter,
262 struct e1000_rx_ring *rx_ring,
263 int *work_done, int work_to_do);
264 void (*alloc_rx_buf)(struct e1000_adapter *adapter,
265 struct e1000_rx_ring *rx_ring,
266 int cleaned_count);
267 struct e1000_rx_ring *rx_ring; /* One per active queue */
268 struct napi_struct napi;
269
270 int num_tx_queues;
271 int num_rx_queues;
272
273 u64 hw_csum_err;
274 u64 hw_csum_good;
275 u32 alloc_rx_buff_failed;
276 u32 rx_int_delay;
277 u32 rx_abs_int_delay;
278 bool rx_csum;
279 u32 gorcl;
280 u64 gorcl_old;
281
282 /* OS defined structs */
283 struct net_device *netdev;
284 struct pci_dev *pdev;
285
286 /* structs defined in e1000_hw.h */
287 struct e1000_hw hw;
288 struct e1000_hw_stats stats;
289 struct e1000_phy_info phy_info;
290 struct e1000_phy_stats phy_stats;
291
292 u32 test_icr;
293 struct e1000_tx_ring test_tx_ring;
294 struct e1000_rx_ring test_rx_ring;
295
296 int msg_enable;
297
298 /* to not mess up cache alignment, always add to the bottom */
299 bool tso_force;
300 bool smart_power_down; /* phy smart power down */
301 bool quad_port_a;
302 unsigned long flags;
303 u32 eeprom_wol;
304
305 /* for ioport free */
306 int bars;
307 int need_ioport;
308
309 bool discarding;
310
311 struct work_struct fifo_stall_task;
312 struct work_struct phy_info_task;
313};
314
315enum e1000_state_t {
316 __E1000_TESTING,
317 __E1000_RESETTING,
318 __E1000_DOWN
319};
320
321#undef pr_fmt
322#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
323
324extern struct net_device *e1000_get_hw_dev(struct e1000_hw *hw);
325#define e_dbg(format, arg...) \
326 netdev_dbg(e1000_get_hw_dev(hw), format, ## arg)
327#define e_err(msglvl, format, arg...) \
328 netif_err(adapter, msglvl, adapter->netdev, format, ## arg)
329#define e_info(msglvl, format, arg...) \
330 netif_info(adapter, msglvl, adapter->netdev, format, ## arg)
331#define e_warn(msglvl, format, arg...) \
332 netif_warn(adapter, msglvl, adapter->netdev, format, ## arg)
333#define e_notice(msglvl, format, arg...) \
334 netif_notice(adapter, msglvl, adapter->netdev, format, ## arg)
335#define e_dev_info(format, arg...) \
336 dev_info(&adapter->pdev->dev, format, ## arg)
337#define e_dev_warn(format, arg...) \
338 dev_warn(&adapter->pdev->dev, format, ## arg)
339#define e_dev_err(format, arg...) \
340 dev_err(&adapter->pdev->dev, format, ## arg)
341
342extern char e1000_driver_name[];
343extern const char e1000_driver_version[];
344
345extern int e1000_up(struct e1000_adapter *adapter);
346extern void e1000_down(struct e1000_adapter *adapter);
347extern void e1000_reinit_locked(struct e1000_adapter *adapter);
348extern void e1000_reset(struct e1000_adapter *adapter);
349extern int e1000_set_spd_dplx(struct e1000_adapter *adapter, u32 spd, u8 dplx);
350extern int e1000_setup_all_rx_resources(struct e1000_adapter *adapter);
351extern int e1000_setup_all_tx_resources(struct e1000_adapter *adapter);
352extern void e1000_free_all_rx_resources(struct e1000_adapter *adapter);
353extern void e1000_free_all_tx_resources(struct e1000_adapter *adapter);
354extern void e1000_update_stats(struct e1000_adapter *adapter);
355extern bool e1000_has_link(struct e1000_adapter *adapter);
356extern void e1000_power_up_phy(struct e1000_adapter *);
357extern void e1000_set_ethtool_ops(struct net_device *netdev);
358extern void e1000_check_options(struct e1000_adapter *adapter);
359extern char *e1000_get_hw_dev_name(struct e1000_hw *hw);
360
361#endif /* _E1000_H_ */
diff --git a/drivers/net/ethernet/intel/e1000/e1000_ethtool.c b/drivers/net/ethernet/intel/e1000/e1000_ethtool.c
new file mode 100644
index 000000000000..5548d464261a
--- /dev/null
+++ b/drivers/net/ethernet/intel/e1000/e1000_ethtool.c
@@ -0,0 +1,1863 @@
1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* ethtool support for e1000 */
30
31#include "e1000.h"
32#include <asm/uaccess.h>
33
34enum {NETDEV_STATS, E1000_STATS};
35
36struct e1000_stats {
37 char stat_string[ETH_GSTRING_LEN];
38 int type;
39 int sizeof_stat;
40 int stat_offset;
41};
42
43#define E1000_STAT(m) E1000_STATS, \
44 sizeof(((struct e1000_adapter *)0)->m), \
45 offsetof(struct e1000_adapter, m)
46#define E1000_NETDEV_STAT(m) NETDEV_STATS, \
47 sizeof(((struct net_device *)0)->m), \
48 offsetof(struct net_device, m)
49
50static const struct e1000_stats e1000_gstrings_stats[] = {
51 { "rx_packets", E1000_STAT(stats.gprc) },
52 { "tx_packets", E1000_STAT(stats.gptc) },
53 { "rx_bytes", E1000_STAT(stats.gorcl) },
54 { "tx_bytes", E1000_STAT(stats.gotcl) },
55 { "rx_broadcast", E1000_STAT(stats.bprc) },
56 { "tx_broadcast", E1000_STAT(stats.bptc) },
57 { "rx_multicast", E1000_STAT(stats.mprc) },
58 { "tx_multicast", E1000_STAT(stats.mptc) },
59 { "rx_errors", E1000_STAT(stats.rxerrc) },
60 { "tx_errors", E1000_STAT(stats.txerrc) },
61 { "tx_dropped", E1000_NETDEV_STAT(stats.tx_dropped) },
62 { "multicast", E1000_STAT(stats.mprc) },
63 { "collisions", E1000_STAT(stats.colc) },
64 { "rx_length_errors", E1000_STAT(stats.rlerrc) },
65 { "rx_over_errors", E1000_NETDEV_STAT(stats.rx_over_errors) },
66 { "rx_crc_errors", E1000_STAT(stats.crcerrs) },
67 { "rx_frame_errors", E1000_NETDEV_STAT(stats.rx_frame_errors) },
68 { "rx_no_buffer_count", E1000_STAT(stats.rnbc) },
69 { "rx_missed_errors", E1000_STAT(stats.mpc) },
70 { "tx_aborted_errors", E1000_STAT(stats.ecol) },
71 { "tx_carrier_errors", E1000_STAT(stats.tncrs) },
72 { "tx_fifo_errors", E1000_NETDEV_STAT(stats.tx_fifo_errors) },
73 { "tx_heartbeat_errors", E1000_NETDEV_STAT(stats.tx_heartbeat_errors) },
74 { "tx_window_errors", E1000_STAT(stats.latecol) },
75 { "tx_abort_late_coll", E1000_STAT(stats.latecol) },
76 { "tx_deferred_ok", E1000_STAT(stats.dc) },
77 { "tx_single_coll_ok", E1000_STAT(stats.scc) },
78 { "tx_multi_coll_ok", E1000_STAT(stats.mcc) },
79 { "tx_timeout_count", E1000_STAT(tx_timeout_count) },
80 { "tx_restart_queue", E1000_STAT(restart_queue) },
81 { "rx_long_length_errors", E1000_STAT(stats.roc) },
82 { "rx_short_length_errors", E1000_STAT(stats.ruc) },
83 { "rx_align_errors", E1000_STAT(stats.algnerrc) },
84 { "tx_tcp_seg_good", E1000_STAT(stats.tsctc) },
85 { "tx_tcp_seg_failed", E1000_STAT(stats.tsctfc) },
86 { "rx_flow_control_xon", E1000_STAT(stats.xonrxc) },
87 { "rx_flow_control_xoff", E1000_STAT(stats.xoffrxc) },
88 { "tx_flow_control_xon", E1000_STAT(stats.xontxc) },
89 { "tx_flow_control_xoff", E1000_STAT(stats.xofftxc) },
90 { "rx_long_byte_count", E1000_STAT(stats.gorcl) },
91 { "rx_csum_offload_good", E1000_STAT(hw_csum_good) },
92 { "rx_csum_offload_errors", E1000_STAT(hw_csum_err) },
93 { "alloc_rx_buff_failed", E1000_STAT(alloc_rx_buff_failed) },
94 { "tx_smbus", E1000_STAT(stats.mgptc) },
95 { "rx_smbus", E1000_STAT(stats.mgprc) },
96 { "dropped_smbus", E1000_STAT(stats.mgpdc) },
97};
98
99#define E1000_QUEUE_STATS_LEN 0
100#define E1000_GLOBAL_STATS_LEN ARRAY_SIZE(e1000_gstrings_stats)
101#define E1000_STATS_LEN (E1000_GLOBAL_STATS_LEN + E1000_QUEUE_STATS_LEN)
102static const char e1000_gstrings_test[][ETH_GSTRING_LEN] = {
103 "Register test (offline)", "Eeprom test (offline)",
104 "Interrupt test (offline)", "Loopback test (offline)",
105 "Link test (on/offline)"
106};
107#define E1000_TEST_LEN ARRAY_SIZE(e1000_gstrings_test)
108
109static int e1000_get_settings(struct net_device *netdev,
110 struct ethtool_cmd *ecmd)
111{
112 struct e1000_adapter *adapter = netdev_priv(netdev);
113 struct e1000_hw *hw = &adapter->hw;
114
115 if (hw->media_type == e1000_media_type_copper) {
116
117 ecmd->supported = (SUPPORTED_10baseT_Half |
118 SUPPORTED_10baseT_Full |
119 SUPPORTED_100baseT_Half |
120 SUPPORTED_100baseT_Full |
121 SUPPORTED_1000baseT_Full|
122 SUPPORTED_Autoneg |
123 SUPPORTED_TP);
124 ecmd->advertising = ADVERTISED_TP;
125
126 if (hw->autoneg == 1) {
127 ecmd->advertising |= ADVERTISED_Autoneg;
128 /* the e1000 autoneg seems to match ethtool nicely */
129 ecmd->advertising |= hw->autoneg_advertised;
130 }
131
132 ecmd->port = PORT_TP;
133 ecmd->phy_address = hw->phy_addr;
134
135 if (hw->mac_type == e1000_82543)
136 ecmd->transceiver = XCVR_EXTERNAL;
137 else
138 ecmd->transceiver = XCVR_INTERNAL;
139
140 } else {
141 ecmd->supported = (SUPPORTED_1000baseT_Full |
142 SUPPORTED_FIBRE |
143 SUPPORTED_Autoneg);
144
145 ecmd->advertising = (ADVERTISED_1000baseT_Full |
146 ADVERTISED_FIBRE |
147 ADVERTISED_Autoneg);
148
149 ecmd->port = PORT_FIBRE;
150
151 if (hw->mac_type >= e1000_82545)
152 ecmd->transceiver = XCVR_INTERNAL;
153 else
154 ecmd->transceiver = XCVR_EXTERNAL;
155 }
156
157 if (er32(STATUS) & E1000_STATUS_LU) {
158
159 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
160 &adapter->link_duplex);
161 ethtool_cmd_speed_set(ecmd, adapter->link_speed);
162
163 /* unfortunately FULL_DUPLEX != DUPLEX_FULL
164 * and HALF_DUPLEX != DUPLEX_HALF */
165
166 if (adapter->link_duplex == FULL_DUPLEX)
167 ecmd->duplex = DUPLEX_FULL;
168 else
169 ecmd->duplex = DUPLEX_HALF;
170 } else {
171 ethtool_cmd_speed_set(ecmd, -1);
172 ecmd->duplex = -1;
173 }
174
175 ecmd->autoneg = ((hw->media_type == e1000_media_type_fiber) ||
176 hw->autoneg) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
177 return 0;
178}
179
180static int e1000_set_settings(struct net_device *netdev,
181 struct ethtool_cmd *ecmd)
182{
183 struct e1000_adapter *adapter = netdev_priv(netdev);
184 struct e1000_hw *hw = &adapter->hw;
185
186 while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
187 msleep(1);
188
189 if (ecmd->autoneg == AUTONEG_ENABLE) {
190 hw->autoneg = 1;
191 if (hw->media_type == e1000_media_type_fiber)
192 hw->autoneg_advertised = ADVERTISED_1000baseT_Full |
193 ADVERTISED_FIBRE |
194 ADVERTISED_Autoneg;
195 else
196 hw->autoneg_advertised = ecmd->advertising |
197 ADVERTISED_TP |
198 ADVERTISED_Autoneg;
199 ecmd->advertising = hw->autoneg_advertised;
200 } else {
201 u32 speed = ethtool_cmd_speed(ecmd);
202 if (e1000_set_spd_dplx(adapter, speed, ecmd->duplex)) {
203 clear_bit(__E1000_RESETTING, &adapter->flags);
204 return -EINVAL;
205 }
206 }
207
208 /* reset the link */
209
210 if (netif_running(adapter->netdev)) {
211 e1000_down(adapter);
212 e1000_up(adapter);
213 } else
214 e1000_reset(adapter);
215
216 clear_bit(__E1000_RESETTING, &adapter->flags);
217 return 0;
218}
219
220static u32 e1000_get_link(struct net_device *netdev)
221{
222 struct e1000_adapter *adapter = netdev_priv(netdev);
223
224 /*
225 * If the link is not reported up to netdev, interrupts are disabled,
226 * and so the physical link state may have changed since we last
227 * looked. Set get_link_status to make sure that the true link
228 * state is interrogated, rather than pulling a cached and possibly
229 * stale link state from the driver.
230 */
231 if (!netif_carrier_ok(netdev))
232 adapter->hw.get_link_status = 1;
233
234 return e1000_has_link(adapter);
235}
236
237static void e1000_get_pauseparam(struct net_device *netdev,
238 struct ethtool_pauseparam *pause)
239{
240 struct e1000_adapter *adapter = netdev_priv(netdev);
241 struct e1000_hw *hw = &adapter->hw;
242
243 pause->autoneg =
244 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
245
246 if (hw->fc == E1000_FC_RX_PAUSE)
247 pause->rx_pause = 1;
248 else if (hw->fc == E1000_FC_TX_PAUSE)
249 pause->tx_pause = 1;
250 else if (hw->fc == E1000_FC_FULL) {
251 pause->rx_pause = 1;
252 pause->tx_pause = 1;
253 }
254}
255
256static int e1000_set_pauseparam(struct net_device *netdev,
257 struct ethtool_pauseparam *pause)
258{
259 struct e1000_adapter *adapter = netdev_priv(netdev);
260 struct e1000_hw *hw = &adapter->hw;
261 int retval = 0;
262
263 adapter->fc_autoneg = pause->autoneg;
264
265 while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
266 msleep(1);
267
268 if (pause->rx_pause && pause->tx_pause)
269 hw->fc = E1000_FC_FULL;
270 else if (pause->rx_pause && !pause->tx_pause)
271 hw->fc = E1000_FC_RX_PAUSE;
272 else if (!pause->rx_pause && pause->tx_pause)
273 hw->fc = E1000_FC_TX_PAUSE;
274 else if (!pause->rx_pause && !pause->tx_pause)
275 hw->fc = E1000_FC_NONE;
276
277 hw->original_fc = hw->fc;
278
279 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
280 if (netif_running(adapter->netdev)) {
281 e1000_down(adapter);
282 e1000_up(adapter);
283 } else
284 e1000_reset(adapter);
285 } else
286 retval = ((hw->media_type == e1000_media_type_fiber) ?
287 e1000_setup_link(hw) : e1000_force_mac_fc(hw));
288
289 clear_bit(__E1000_RESETTING, &adapter->flags);
290 return retval;
291}
292
293static u32 e1000_get_msglevel(struct net_device *netdev)
294{
295 struct e1000_adapter *adapter = netdev_priv(netdev);
296 return adapter->msg_enable;
297}
298
299static void e1000_set_msglevel(struct net_device *netdev, u32 data)
300{
301 struct e1000_adapter *adapter = netdev_priv(netdev);
302 adapter->msg_enable = data;
303}
304
305static int e1000_get_regs_len(struct net_device *netdev)
306{
307#define E1000_REGS_LEN 32
308 return E1000_REGS_LEN * sizeof(u32);
309}
310
311static void e1000_get_regs(struct net_device *netdev, struct ethtool_regs *regs,
312 void *p)
313{
314 struct e1000_adapter *adapter = netdev_priv(netdev);
315 struct e1000_hw *hw = &adapter->hw;
316 u32 *regs_buff = p;
317 u16 phy_data;
318
319 memset(p, 0, E1000_REGS_LEN * sizeof(u32));
320
321 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
322
323 regs_buff[0] = er32(CTRL);
324 regs_buff[1] = er32(STATUS);
325
326 regs_buff[2] = er32(RCTL);
327 regs_buff[3] = er32(RDLEN);
328 regs_buff[4] = er32(RDH);
329 regs_buff[5] = er32(RDT);
330 regs_buff[6] = er32(RDTR);
331
332 regs_buff[7] = er32(TCTL);
333 regs_buff[8] = er32(TDLEN);
334 regs_buff[9] = er32(TDH);
335 regs_buff[10] = er32(TDT);
336 regs_buff[11] = er32(TIDV);
337
338 regs_buff[12] = hw->phy_type; /* PHY type (IGP=1, M88=0) */
339 if (hw->phy_type == e1000_phy_igp) {
340 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
341 IGP01E1000_PHY_AGC_A);
342 e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_A &
343 IGP01E1000_PHY_PAGE_SELECT, &phy_data);
344 regs_buff[13] = (u32)phy_data; /* cable length */
345 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
346 IGP01E1000_PHY_AGC_B);
347 e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_B &
348 IGP01E1000_PHY_PAGE_SELECT, &phy_data);
349 regs_buff[14] = (u32)phy_data; /* cable length */
350 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
351 IGP01E1000_PHY_AGC_C);
352 e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_C &
353 IGP01E1000_PHY_PAGE_SELECT, &phy_data);
354 regs_buff[15] = (u32)phy_data; /* cable length */
355 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
356 IGP01E1000_PHY_AGC_D);
357 e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_D &
358 IGP01E1000_PHY_PAGE_SELECT, &phy_data);
359 regs_buff[16] = (u32)phy_data; /* cable length */
360 regs_buff[17] = 0; /* extended 10bt distance (not needed) */
361 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0);
362 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS &
363 IGP01E1000_PHY_PAGE_SELECT, &phy_data);
364 regs_buff[18] = (u32)phy_data; /* cable polarity */
365 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
366 IGP01E1000_PHY_PCS_INIT_REG);
367 e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG &
368 IGP01E1000_PHY_PAGE_SELECT, &phy_data);
369 regs_buff[19] = (u32)phy_data; /* cable polarity */
370 regs_buff[20] = 0; /* polarity correction enabled (always) */
371 regs_buff[22] = 0; /* phy receive errors (unavailable) */
372 regs_buff[23] = regs_buff[18]; /* mdix mode */
373 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0);
374 } else {
375 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
376 regs_buff[13] = (u32)phy_data; /* cable length */
377 regs_buff[14] = 0; /* Dummy (to align w/ IGP phy reg dump) */
378 regs_buff[15] = 0; /* Dummy (to align w/ IGP phy reg dump) */
379 regs_buff[16] = 0; /* Dummy (to align w/ IGP phy reg dump) */
380 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
381 regs_buff[17] = (u32)phy_data; /* extended 10bt distance */
382 regs_buff[18] = regs_buff[13]; /* cable polarity */
383 regs_buff[19] = 0; /* Dummy (to align w/ IGP phy reg dump) */
384 regs_buff[20] = regs_buff[17]; /* polarity correction */
385 /* phy receive errors */
386 regs_buff[22] = adapter->phy_stats.receive_errors;
387 regs_buff[23] = regs_buff[13]; /* mdix mode */
388 }
389 regs_buff[21] = adapter->phy_stats.idle_errors; /* phy idle errors */
390 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
391 regs_buff[24] = (u32)phy_data; /* phy local receiver status */
392 regs_buff[25] = regs_buff[24]; /* phy remote receiver status */
393 if (hw->mac_type >= e1000_82540 &&
394 hw->media_type == e1000_media_type_copper) {
395 regs_buff[26] = er32(MANC);
396 }
397}
398
399static int e1000_get_eeprom_len(struct net_device *netdev)
400{
401 struct e1000_adapter *adapter = netdev_priv(netdev);
402 struct e1000_hw *hw = &adapter->hw;
403
404 return hw->eeprom.word_size * 2;
405}
406
407static int e1000_get_eeprom(struct net_device *netdev,
408 struct ethtool_eeprom *eeprom, u8 *bytes)
409{
410 struct e1000_adapter *adapter = netdev_priv(netdev);
411 struct e1000_hw *hw = &adapter->hw;
412 u16 *eeprom_buff;
413 int first_word, last_word;
414 int ret_val = 0;
415 u16 i;
416
417 if (eeprom->len == 0)
418 return -EINVAL;
419
420 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
421
422 first_word = eeprom->offset >> 1;
423 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
424
425 eeprom_buff = kmalloc(sizeof(u16) *
426 (last_word - first_word + 1), GFP_KERNEL);
427 if (!eeprom_buff)
428 return -ENOMEM;
429
430 if (hw->eeprom.type == e1000_eeprom_spi)
431 ret_val = e1000_read_eeprom(hw, first_word,
432 last_word - first_word + 1,
433 eeprom_buff);
434 else {
435 for (i = 0; i < last_word - first_word + 1; i++) {
436 ret_val = e1000_read_eeprom(hw, first_word + i, 1,
437 &eeprom_buff[i]);
438 if (ret_val)
439 break;
440 }
441 }
442
443 /* Device's eeprom is always little-endian, word addressable */
444 for (i = 0; i < last_word - first_word + 1; i++)
445 le16_to_cpus(&eeprom_buff[i]);
446
447 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
448 eeprom->len);
449 kfree(eeprom_buff);
450
451 return ret_val;
452}
453
454static int e1000_set_eeprom(struct net_device *netdev,
455 struct ethtool_eeprom *eeprom, u8 *bytes)
456{
457 struct e1000_adapter *adapter = netdev_priv(netdev);
458 struct e1000_hw *hw = &adapter->hw;
459 u16 *eeprom_buff;
460 void *ptr;
461 int max_len, first_word, last_word, ret_val = 0;
462 u16 i;
463
464 if (eeprom->len == 0)
465 return -EOPNOTSUPP;
466
467 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
468 return -EFAULT;
469
470 max_len = hw->eeprom.word_size * 2;
471
472 first_word = eeprom->offset >> 1;
473 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
474 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
475 if (!eeprom_buff)
476 return -ENOMEM;
477
478 ptr = (void *)eeprom_buff;
479
480 if (eeprom->offset & 1) {
481 /* need read/modify/write of first changed EEPROM word */
482 /* only the second byte of the word is being modified */
483 ret_val = e1000_read_eeprom(hw, first_word, 1,
484 &eeprom_buff[0]);
485 ptr++;
486 }
487 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
488 /* need read/modify/write of last changed EEPROM word */
489 /* only the first byte of the word is being modified */
490 ret_val = e1000_read_eeprom(hw, last_word, 1,
491 &eeprom_buff[last_word - first_word]);
492 }
493
494 /* Device's eeprom is always little-endian, word addressable */
495 for (i = 0; i < last_word - first_word + 1; i++)
496 le16_to_cpus(&eeprom_buff[i]);
497
498 memcpy(ptr, bytes, eeprom->len);
499
500 for (i = 0; i < last_word - first_word + 1; i++)
501 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
502
503 ret_val = e1000_write_eeprom(hw, first_word,
504 last_word - first_word + 1, eeprom_buff);
505
506 /* Update the checksum over the first part of the EEPROM if needed */
507 if ((ret_val == 0) && (first_word <= EEPROM_CHECKSUM_REG))
508 e1000_update_eeprom_checksum(hw);
509
510 kfree(eeprom_buff);
511 return ret_val;
512}
513
514static void e1000_get_drvinfo(struct net_device *netdev,
515 struct ethtool_drvinfo *drvinfo)
516{
517 struct e1000_adapter *adapter = netdev_priv(netdev);
518 char firmware_version[32];
519
520 strncpy(drvinfo->driver, e1000_driver_name, 32);
521 strncpy(drvinfo->version, e1000_driver_version, 32);
522
523 sprintf(firmware_version, "N/A");
524 strncpy(drvinfo->fw_version, firmware_version, 32);
525 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
526 drvinfo->regdump_len = e1000_get_regs_len(netdev);
527 drvinfo->eedump_len = e1000_get_eeprom_len(netdev);
528}
529
530static void e1000_get_ringparam(struct net_device *netdev,
531 struct ethtool_ringparam *ring)
532{
533 struct e1000_adapter *adapter = netdev_priv(netdev);
534 struct e1000_hw *hw = &adapter->hw;
535 e1000_mac_type mac_type = hw->mac_type;
536 struct e1000_tx_ring *txdr = adapter->tx_ring;
537 struct e1000_rx_ring *rxdr = adapter->rx_ring;
538
539 ring->rx_max_pending = (mac_type < e1000_82544) ? E1000_MAX_RXD :
540 E1000_MAX_82544_RXD;
541 ring->tx_max_pending = (mac_type < e1000_82544) ? E1000_MAX_TXD :
542 E1000_MAX_82544_TXD;
543 ring->rx_mini_max_pending = 0;
544 ring->rx_jumbo_max_pending = 0;
545 ring->rx_pending = rxdr->count;
546 ring->tx_pending = txdr->count;
547 ring->rx_mini_pending = 0;
548 ring->rx_jumbo_pending = 0;
549}
550
551static int e1000_set_ringparam(struct net_device *netdev,
552 struct ethtool_ringparam *ring)
553{
554 struct e1000_adapter *adapter = netdev_priv(netdev);
555 struct e1000_hw *hw = &adapter->hw;
556 e1000_mac_type mac_type = hw->mac_type;
557 struct e1000_tx_ring *txdr, *tx_old;
558 struct e1000_rx_ring *rxdr, *rx_old;
559 int i, err;
560
561 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
562 return -EINVAL;
563
564 while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
565 msleep(1);
566
567 if (netif_running(adapter->netdev))
568 e1000_down(adapter);
569
570 tx_old = adapter->tx_ring;
571 rx_old = adapter->rx_ring;
572
573 err = -ENOMEM;
574 txdr = kcalloc(adapter->num_tx_queues, sizeof(struct e1000_tx_ring), GFP_KERNEL);
575 if (!txdr)
576 goto err_alloc_tx;
577
578 rxdr = kcalloc(adapter->num_rx_queues, sizeof(struct e1000_rx_ring), GFP_KERNEL);
579 if (!rxdr)
580 goto err_alloc_rx;
581
582 adapter->tx_ring = txdr;
583 adapter->rx_ring = rxdr;
584
585 rxdr->count = max(ring->rx_pending,(u32)E1000_MIN_RXD);
586 rxdr->count = min(rxdr->count,(u32)(mac_type < e1000_82544 ?
587 E1000_MAX_RXD : E1000_MAX_82544_RXD));
588 rxdr->count = ALIGN(rxdr->count, REQ_RX_DESCRIPTOR_MULTIPLE);
589
590 txdr->count = max(ring->tx_pending,(u32)E1000_MIN_TXD);
591 txdr->count = min(txdr->count,(u32)(mac_type < e1000_82544 ?
592 E1000_MAX_TXD : E1000_MAX_82544_TXD));
593 txdr->count = ALIGN(txdr->count, REQ_TX_DESCRIPTOR_MULTIPLE);
594
595 for (i = 0; i < adapter->num_tx_queues; i++)
596 txdr[i].count = txdr->count;
597 for (i = 0; i < adapter->num_rx_queues; i++)
598 rxdr[i].count = rxdr->count;
599
600 if (netif_running(adapter->netdev)) {
601 /* Try to get new resources before deleting old */
602 err = e1000_setup_all_rx_resources(adapter);
603 if (err)
604 goto err_setup_rx;
605 err = e1000_setup_all_tx_resources(adapter);
606 if (err)
607 goto err_setup_tx;
608
609 /* save the new, restore the old in order to free it,
610 * then restore the new back again */
611
612 adapter->rx_ring = rx_old;
613 adapter->tx_ring = tx_old;
614 e1000_free_all_rx_resources(adapter);
615 e1000_free_all_tx_resources(adapter);
616 kfree(tx_old);
617 kfree(rx_old);
618 adapter->rx_ring = rxdr;
619 adapter->tx_ring = txdr;
620 err = e1000_up(adapter);
621 if (err)
622 goto err_setup;
623 }
624
625 clear_bit(__E1000_RESETTING, &adapter->flags);
626 return 0;
627err_setup_tx:
628 e1000_free_all_rx_resources(adapter);
629err_setup_rx:
630 adapter->rx_ring = rx_old;
631 adapter->tx_ring = tx_old;
632 kfree(rxdr);
633err_alloc_rx:
634 kfree(txdr);
635err_alloc_tx:
636 e1000_up(adapter);
637err_setup:
638 clear_bit(__E1000_RESETTING, &adapter->flags);
639 return err;
640}
641
642static bool reg_pattern_test(struct e1000_adapter *adapter, u64 *data, int reg,
643 u32 mask, u32 write)
644{
645 struct e1000_hw *hw = &adapter->hw;
646 static const u32 test[] =
647 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
648 u8 __iomem *address = hw->hw_addr + reg;
649 u32 read;
650 int i;
651
652 for (i = 0; i < ARRAY_SIZE(test); i++) {
653 writel(write & test[i], address);
654 read = readl(address);
655 if (read != (write & test[i] & mask)) {
656 e_err(drv, "pattern test reg %04X failed: "
657 "got 0x%08X expected 0x%08X\n",
658 reg, read, (write & test[i] & mask));
659 *data = reg;
660 return true;
661 }
662 }
663 return false;
664}
665
666static bool reg_set_and_check(struct e1000_adapter *adapter, u64 *data, int reg,
667 u32 mask, u32 write)
668{
669 struct e1000_hw *hw = &adapter->hw;
670 u8 __iomem *address = hw->hw_addr + reg;
671 u32 read;
672
673 writel(write & mask, address);
674 read = readl(address);
675 if ((read & mask) != (write & mask)) {
676 e_err(drv, "set/check reg %04X test failed: "
677 "got 0x%08X expected 0x%08X\n",
678 reg, (read & mask), (write & mask));
679 *data = reg;
680 return true;
681 }
682 return false;
683}
684
685#define REG_PATTERN_TEST(reg, mask, write) \
686 do { \
687 if (reg_pattern_test(adapter, data, \
688 (hw->mac_type >= e1000_82543) \
689 ? E1000_##reg : E1000_82542_##reg, \
690 mask, write)) \
691 return 1; \
692 } while (0)
693
694#define REG_SET_AND_CHECK(reg, mask, write) \
695 do { \
696 if (reg_set_and_check(adapter, data, \
697 (hw->mac_type >= e1000_82543) \
698 ? E1000_##reg : E1000_82542_##reg, \
699 mask, write)) \
700 return 1; \
701 } while (0)
702
703static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
704{
705 u32 value, before, after;
706 u32 i, toggle;
707 struct e1000_hw *hw = &adapter->hw;
708
709 /* The status register is Read Only, so a write should fail.
710 * Some bits that get toggled are ignored.
711 */
712
713 /* there are several bits on newer hardware that are r/w */
714 toggle = 0xFFFFF833;
715
716 before = er32(STATUS);
717 value = (er32(STATUS) & toggle);
718 ew32(STATUS, toggle);
719 after = er32(STATUS) & toggle;
720 if (value != after) {
721 e_err(drv, "failed STATUS register test got: "
722 "0x%08X expected: 0x%08X\n", after, value);
723 *data = 1;
724 return 1;
725 }
726 /* restore previous status */
727 ew32(STATUS, before);
728
729 REG_PATTERN_TEST(FCAL, 0xFFFFFFFF, 0xFFFFFFFF);
730 REG_PATTERN_TEST(FCAH, 0x0000FFFF, 0xFFFFFFFF);
731 REG_PATTERN_TEST(FCT, 0x0000FFFF, 0xFFFFFFFF);
732 REG_PATTERN_TEST(VET, 0x0000FFFF, 0xFFFFFFFF);
733
734 REG_PATTERN_TEST(RDTR, 0x0000FFFF, 0xFFFFFFFF);
735 REG_PATTERN_TEST(RDBAH, 0xFFFFFFFF, 0xFFFFFFFF);
736 REG_PATTERN_TEST(RDLEN, 0x000FFF80, 0x000FFFFF);
737 REG_PATTERN_TEST(RDH, 0x0000FFFF, 0x0000FFFF);
738 REG_PATTERN_TEST(RDT, 0x0000FFFF, 0x0000FFFF);
739 REG_PATTERN_TEST(FCRTH, 0x0000FFF8, 0x0000FFF8);
740 REG_PATTERN_TEST(FCTTV, 0x0000FFFF, 0x0000FFFF);
741 REG_PATTERN_TEST(TIPG, 0x3FFFFFFF, 0x3FFFFFFF);
742 REG_PATTERN_TEST(TDBAH, 0xFFFFFFFF, 0xFFFFFFFF);
743 REG_PATTERN_TEST(TDLEN, 0x000FFF80, 0x000FFFFF);
744
745 REG_SET_AND_CHECK(RCTL, 0xFFFFFFFF, 0x00000000);
746
747 before = 0x06DFB3FE;
748 REG_SET_AND_CHECK(RCTL, before, 0x003FFFFB);
749 REG_SET_AND_CHECK(TCTL, 0xFFFFFFFF, 0x00000000);
750
751 if (hw->mac_type >= e1000_82543) {
752
753 REG_SET_AND_CHECK(RCTL, before, 0xFFFFFFFF);
754 REG_PATTERN_TEST(RDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
755 REG_PATTERN_TEST(TXCW, 0xC000FFFF, 0x0000FFFF);
756 REG_PATTERN_TEST(TDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
757 REG_PATTERN_TEST(TIDV, 0x0000FFFF, 0x0000FFFF);
758 value = E1000_RAR_ENTRIES;
759 for (i = 0; i < value; i++) {
760 REG_PATTERN_TEST(RA + (((i << 1) + 1) << 2), 0x8003FFFF,
761 0xFFFFFFFF);
762 }
763
764 } else {
765
766 REG_SET_AND_CHECK(RCTL, 0xFFFFFFFF, 0x01FFFFFF);
767 REG_PATTERN_TEST(RDBAL, 0xFFFFF000, 0xFFFFFFFF);
768 REG_PATTERN_TEST(TXCW, 0x0000FFFF, 0x0000FFFF);
769 REG_PATTERN_TEST(TDBAL, 0xFFFFF000, 0xFFFFFFFF);
770
771 }
772
773 value = E1000_MC_TBL_SIZE;
774 for (i = 0; i < value; i++)
775 REG_PATTERN_TEST(MTA + (i << 2), 0xFFFFFFFF, 0xFFFFFFFF);
776
777 *data = 0;
778 return 0;
779}
780
781static int e1000_eeprom_test(struct e1000_adapter *adapter, u64 *data)
782{
783 struct e1000_hw *hw = &adapter->hw;
784 u16 temp;
785 u16 checksum = 0;
786 u16 i;
787
788 *data = 0;
789 /* Read and add up the contents of the EEPROM */
790 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
791 if ((e1000_read_eeprom(hw, i, 1, &temp)) < 0) {
792 *data = 1;
793 break;
794 }
795 checksum += temp;
796 }
797
798 /* If Checksum is not Correct return error else test passed */
799 if ((checksum != (u16)EEPROM_SUM) && !(*data))
800 *data = 2;
801
802 return *data;
803}
804
805static irqreturn_t e1000_test_intr(int irq, void *data)
806{
807 struct net_device *netdev = (struct net_device *)data;
808 struct e1000_adapter *adapter = netdev_priv(netdev);
809 struct e1000_hw *hw = &adapter->hw;
810
811 adapter->test_icr |= er32(ICR);
812
813 return IRQ_HANDLED;
814}
815
816static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
817{
818 struct net_device *netdev = adapter->netdev;
819 u32 mask, i = 0;
820 bool shared_int = true;
821 u32 irq = adapter->pdev->irq;
822 struct e1000_hw *hw = &adapter->hw;
823
824 *data = 0;
825
826 /* NOTE: we don't test MSI interrupts here, yet */
827 /* Hook up test interrupt handler just for this test */
828 if (!request_irq(irq, e1000_test_intr, IRQF_PROBE_SHARED, netdev->name,
829 netdev))
830 shared_int = false;
831 else if (request_irq(irq, e1000_test_intr, IRQF_SHARED,
832 netdev->name, netdev)) {
833 *data = 1;
834 return -1;
835 }
836 e_info(hw, "testing %s interrupt\n", (shared_int ?
837 "shared" : "unshared"));
838
839 /* Disable all the interrupts */
840 ew32(IMC, 0xFFFFFFFF);
841 E1000_WRITE_FLUSH();
842 msleep(10);
843
844 /* Test each interrupt */
845 for (; i < 10; i++) {
846
847 /* Interrupt to test */
848 mask = 1 << i;
849
850 if (!shared_int) {
851 /* Disable the interrupt to be reported in
852 * the cause register and then force the same
853 * interrupt and see if one gets posted. If
854 * an interrupt was posted to the bus, the
855 * test failed.
856 */
857 adapter->test_icr = 0;
858 ew32(IMC, mask);
859 ew32(ICS, mask);
860 E1000_WRITE_FLUSH();
861 msleep(10);
862
863 if (adapter->test_icr & mask) {
864 *data = 3;
865 break;
866 }
867 }
868
869 /* Enable the interrupt to be reported in
870 * the cause register and then force the same
871 * interrupt and see if one gets posted. If
872 * an interrupt was not posted to the bus, the
873 * test failed.
874 */
875 adapter->test_icr = 0;
876 ew32(IMS, mask);
877 ew32(ICS, mask);
878 E1000_WRITE_FLUSH();
879 msleep(10);
880
881 if (!(adapter->test_icr & mask)) {
882 *data = 4;
883 break;
884 }
885
886 if (!shared_int) {
887 /* Disable the other interrupts to be reported in
888 * the cause register and then force the other
889 * interrupts and see if any get posted. If
890 * an interrupt was posted to the bus, the
891 * test failed.
892 */
893 adapter->test_icr = 0;
894 ew32(IMC, ~mask & 0x00007FFF);
895 ew32(ICS, ~mask & 0x00007FFF);
896 E1000_WRITE_FLUSH();
897 msleep(10);
898
899 if (adapter->test_icr) {
900 *data = 5;
901 break;
902 }
903 }
904 }
905
906 /* Disable all the interrupts */
907 ew32(IMC, 0xFFFFFFFF);
908 E1000_WRITE_FLUSH();
909 msleep(10);
910
911 /* Unhook test interrupt handler */
912 free_irq(irq, netdev);
913
914 return *data;
915}
916
917static void e1000_free_desc_rings(struct e1000_adapter *adapter)
918{
919 struct e1000_tx_ring *txdr = &adapter->test_tx_ring;
920 struct e1000_rx_ring *rxdr = &adapter->test_rx_ring;
921 struct pci_dev *pdev = adapter->pdev;
922 int i;
923
924 if (txdr->desc && txdr->buffer_info) {
925 for (i = 0; i < txdr->count; i++) {
926 if (txdr->buffer_info[i].dma)
927 dma_unmap_single(&pdev->dev,
928 txdr->buffer_info[i].dma,
929 txdr->buffer_info[i].length,
930 DMA_TO_DEVICE);
931 if (txdr->buffer_info[i].skb)
932 dev_kfree_skb(txdr->buffer_info[i].skb);
933 }
934 }
935
936 if (rxdr->desc && rxdr->buffer_info) {
937 for (i = 0; i < rxdr->count; i++) {
938 if (rxdr->buffer_info[i].dma)
939 dma_unmap_single(&pdev->dev,
940 rxdr->buffer_info[i].dma,
941 rxdr->buffer_info[i].length,
942 DMA_FROM_DEVICE);
943 if (rxdr->buffer_info[i].skb)
944 dev_kfree_skb(rxdr->buffer_info[i].skb);
945 }
946 }
947
948 if (txdr->desc) {
949 dma_free_coherent(&pdev->dev, txdr->size, txdr->desc,
950 txdr->dma);
951 txdr->desc = NULL;
952 }
953 if (rxdr->desc) {
954 dma_free_coherent(&pdev->dev, rxdr->size, rxdr->desc,
955 rxdr->dma);
956 rxdr->desc = NULL;
957 }
958
959 kfree(txdr->buffer_info);
960 txdr->buffer_info = NULL;
961 kfree(rxdr->buffer_info);
962 rxdr->buffer_info = NULL;
963}
964
965static int e1000_setup_desc_rings(struct e1000_adapter *adapter)
966{
967 struct e1000_hw *hw = &adapter->hw;
968 struct e1000_tx_ring *txdr = &adapter->test_tx_ring;
969 struct e1000_rx_ring *rxdr = &adapter->test_rx_ring;
970 struct pci_dev *pdev = adapter->pdev;
971 u32 rctl;
972 int i, ret_val;
973
974 /* Setup Tx descriptor ring and Tx buffers */
975
976 if (!txdr->count)
977 txdr->count = E1000_DEFAULT_TXD;
978
979 txdr->buffer_info = kcalloc(txdr->count, sizeof(struct e1000_buffer),
980 GFP_KERNEL);
981 if (!txdr->buffer_info) {
982 ret_val = 1;
983 goto err_nomem;
984 }
985
986 txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
987 txdr->size = ALIGN(txdr->size, 4096);
988 txdr->desc = dma_alloc_coherent(&pdev->dev, txdr->size, &txdr->dma,
989 GFP_KERNEL);
990 if (!txdr->desc) {
991 ret_val = 2;
992 goto err_nomem;
993 }
994 memset(txdr->desc, 0, txdr->size);
995 txdr->next_to_use = txdr->next_to_clean = 0;
996
997 ew32(TDBAL, ((u64)txdr->dma & 0x00000000FFFFFFFF));
998 ew32(TDBAH, ((u64)txdr->dma >> 32));
999 ew32(TDLEN, txdr->count * sizeof(struct e1000_tx_desc));
1000 ew32(TDH, 0);
1001 ew32(TDT, 0);
1002 ew32(TCTL, E1000_TCTL_PSP | E1000_TCTL_EN |
1003 E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT |
1004 E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT);
1005
1006 for (i = 0; i < txdr->count; i++) {
1007 struct e1000_tx_desc *tx_desc = E1000_TX_DESC(*txdr, i);
1008 struct sk_buff *skb;
1009 unsigned int size = 1024;
1010
1011 skb = alloc_skb(size, GFP_KERNEL);
1012 if (!skb) {
1013 ret_val = 3;
1014 goto err_nomem;
1015 }
1016 skb_put(skb, size);
1017 txdr->buffer_info[i].skb = skb;
1018 txdr->buffer_info[i].length = skb->len;
1019 txdr->buffer_info[i].dma =
1020 dma_map_single(&pdev->dev, skb->data, skb->len,
1021 DMA_TO_DEVICE);
1022 tx_desc->buffer_addr = cpu_to_le64(txdr->buffer_info[i].dma);
1023 tx_desc->lower.data = cpu_to_le32(skb->len);
1024 tx_desc->lower.data |= cpu_to_le32(E1000_TXD_CMD_EOP |
1025 E1000_TXD_CMD_IFCS |
1026 E1000_TXD_CMD_RPS);
1027 tx_desc->upper.data = 0;
1028 }
1029
1030 /* Setup Rx descriptor ring and Rx buffers */
1031
1032 if (!rxdr->count)
1033 rxdr->count = E1000_DEFAULT_RXD;
1034
1035 rxdr->buffer_info = kcalloc(rxdr->count, sizeof(struct e1000_buffer),
1036 GFP_KERNEL);
1037 if (!rxdr->buffer_info) {
1038 ret_val = 4;
1039 goto err_nomem;
1040 }
1041
1042 rxdr->size = rxdr->count * sizeof(struct e1000_rx_desc);
1043 rxdr->desc = dma_alloc_coherent(&pdev->dev, rxdr->size, &rxdr->dma,
1044 GFP_KERNEL);
1045 if (!rxdr->desc) {
1046 ret_val = 5;
1047 goto err_nomem;
1048 }
1049 memset(rxdr->desc, 0, rxdr->size);
1050 rxdr->next_to_use = rxdr->next_to_clean = 0;
1051
1052 rctl = er32(RCTL);
1053 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1054 ew32(RDBAL, ((u64)rxdr->dma & 0xFFFFFFFF));
1055 ew32(RDBAH, ((u64)rxdr->dma >> 32));
1056 ew32(RDLEN, rxdr->size);
1057 ew32(RDH, 0);
1058 ew32(RDT, 0);
1059 rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |
1060 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1061 (hw->mc_filter_type << E1000_RCTL_MO_SHIFT);
1062 ew32(RCTL, rctl);
1063
1064 for (i = 0; i < rxdr->count; i++) {
1065 struct e1000_rx_desc *rx_desc = E1000_RX_DESC(*rxdr, i);
1066 struct sk_buff *skb;
1067
1068 skb = alloc_skb(E1000_RXBUFFER_2048 + NET_IP_ALIGN, GFP_KERNEL);
1069 if (!skb) {
1070 ret_val = 6;
1071 goto err_nomem;
1072 }
1073 skb_reserve(skb, NET_IP_ALIGN);
1074 rxdr->buffer_info[i].skb = skb;
1075 rxdr->buffer_info[i].length = E1000_RXBUFFER_2048;
1076 rxdr->buffer_info[i].dma =
1077 dma_map_single(&pdev->dev, skb->data,
1078 E1000_RXBUFFER_2048, DMA_FROM_DEVICE);
1079 rx_desc->buffer_addr = cpu_to_le64(rxdr->buffer_info[i].dma);
1080 memset(skb->data, 0x00, skb->len);
1081 }
1082
1083 return 0;
1084
1085err_nomem:
1086 e1000_free_desc_rings(adapter);
1087 return ret_val;
1088}
1089
1090static void e1000_phy_disable_receiver(struct e1000_adapter *adapter)
1091{
1092 struct e1000_hw *hw = &adapter->hw;
1093
1094 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1095 e1000_write_phy_reg(hw, 29, 0x001F);
1096 e1000_write_phy_reg(hw, 30, 0x8FFC);
1097 e1000_write_phy_reg(hw, 29, 0x001A);
1098 e1000_write_phy_reg(hw, 30, 0x8FF0);
1099}
1100
1101static void e1000_phy_reset_clk_and_crs(struct e1000_adapter *adapter)
1102{
1103 struct e1000_hw *hw = &adapter->hw;
1104 u16 phy_reg;
1105
1106 /* Because we reset the PHY above, we need to re-force TX_CLK in the
1107 * Extended PHY Specific Control Register to 25MHz clock. This
1108 * value defaults back to a 2.5MHz clock when the PHY is reset.
1109 */
1110 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_reg);
1111 phy_reg |= M88E1000_EPSCR_TX_CLK_25;
1112 e1000_write_phy_reg(hw,
1113 M88E1000_EXT_PHY_SPEC_CTRL, phy_reg);
1114
1115 /* In addition, because of the s/w reset above, we need to enable
1116 * CRS on TX. This must be set for both full and half duplex
1117 * operation.
1118 */
1119 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_reg);
1120 phy_reg |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1121 e1000_write_phy_reg(hw,
1122 M88E1000_PHY_SPEC_CTRL, phy_reg);
1123}
1124
1125static int e1000_nonintegrated_phy_loopback(struct e1000_adapter *adapter)
1126{
1127 struct e1000_hw *hw = &adapter->hw;
1128 u32 ctrl_reg;
1129 u16 phy_reg;
1130
1131 /* Setup the Device Control Register for PHY loopback test. */
1132
1133 ctrl_reg = er32(CTRL);
1134 ctrl_reg |= (E1000_CTRL_ILOS | /* Invert Loss-Of-Signal */
1135 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1136 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1137 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */
1138 E1000_CTRL_FD); /* Force Duplex to FULL */
1139
1140 ew32(CTRL, ctrl_reg);
1141
1142 /* Read the PHY Specific Control Register (0x10) */
1143 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_reg);
1144
1145 /* Clear Auto-Crossover bits in PHY Specific Control Register
1146 * (bits 6:5).
1147 */
1148 phy_reg &= ~M88E1000_PSCR_AUTO_X_MODE;
1149 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_reg);
1150
1151 /* Perform software reset on the PHY */
1152 e1000_phy_reset(hw);
1153
1154 /* Have to setup TX_CLK and TX_CRS after software reset */
1155 e1000_phy_reset_clk_and_crs(adapter);
1156
1157 e1000_write_phy_reg(hw, PHY_CTRL, 0x8100);
1158
1159 /* Wait for reset to complete. */
1160 udelay(500);
1161
1162 /* Have to setup TX_CLK and TX_CRS after software reset */
1163 e1000_phy_reset_clk_and_crs(adapter);
1164
1165 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1166 e1000_phy_disable_receiver(adapter);
1167
1168 /* Set the loopback bit in the PHY control register. */
1169 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg);
1170 phy_reg |= MII_CR_LOOPBACK;
1171 e1000_write_phy_reg(hw, PHY_CTRL, phy_reg);
1172
1173 /* Setup TX_CLK and TX_CRS one more time. */
1174 e1000_phy_reset_clk_and_crs(adapter);
1175
1176 /* Check Phy Configuration */
1177 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg);
1178 if (phy_reg != 0x4100)
1179 return 9;
1180
1181 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_reg);
1182 if (phy_reg != 0x0070)
1183 return 10;
1184
1185 e1000_read_phy_reg(hw, 29, &phy_reg);
1186 if (phy_reg != 0x001A)
1187 return 11;
1188
1189 return 0;
1190}
1191
1192static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
1193{
1194 struct e1000_hw *hw = &adapter->hw;
1195 u32 ctrl_reg = 0;
1196 u32 stat_reg = 0;
1197
1198 hw->autoneg = false;
1199
1200 if (hw->phy_type == e1000_phy_m88) {
1201 /* Auto-MDI/MDIX Off */
1202 e1000_write_phy_reg(hw,
1203 M88E1000_PHY_SPEC_CTRL, 0x0808);
1204 /* reset to update Auto-MDI/MDIX */
1205 e1000_write_phy_reg(hw, PHY_CTRL, 0x9140);
1206 /* autoneg off */
1207 e1000_write_phy_reg(hw, PHY_CTRL, 0x8140);
1208 }
1209
1210 ctrl_reg = er32(CTRL);
1211
1212 /* force 1000, set loopback */
1213 e1000_write_phy_reg(hw, PHY_CTRL, 0x4140);
1214
1215 /* Now set up the MAC to the same speed/duplex as the PHY. */
1216 ctrl_reg = er32(CTRL);
1217 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1218 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1219 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1220 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1221 E1000_CTRL_FD); /* Force Duplex to FULL */
1222
1223 if (hw->media_type == e1000_media_type_copper &&
1224 hw->phy_type == e1000_phy_m88)
1225 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1226 else {
1227 /* Set the ILOS bit on the fiber Nic is half
1228 * duplex link is detected. */
1229 stat_reg = er32(STATUS);
1230 if ((stat_reg & E1000_STATUS_FD) == 0)
1231 ctrl_reg |= (E1000_CTRL_ILOS | E1000_CTRL_SLU);
1232 }
1233
1234 ew32(CTRL, ctrl_reg);
1235
1236 /* Disable the receiver on the PHY so when a cable is plugged in, the
1237 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1238 */
1239 if (hw->phy_type == e1000_phy_m88)
1240 e1000_phy_disable_receiver(adapter);
1241
1242 udelay(500);
1243
1244 return 0;
1245}
1246
1247static int e1000_set_phy_loopback(struct e1000_adapter *adapter)
1248{
1249 struct e1000_hw *hw = &adapter->hw;
1250 u16 phy_reg = 0;
1251 u16 count = 0;
1252
1253 switch (hw->mac_type) {
1254 case e1000_82543:
1255 if (hw->media_type == e1000_media_type_copper) {
1256 /* Attempt to setup Loopback mode on Non-integrated PHY.
1257 * Some PHY registers get corrupted at random, so
1258 * attempt this 10 times.
1259 */
1260 while (e1000_nonintegrated_phy_loopback(adapter) &&
1261 count++ < 10);
1262 if (count < 11)
1263 return 0;
1264 }
1265 break;
1266
1267 case e1000_82544:
1268 case e1000_82540:
1269 case e1000_82545:
1270 case e1000_82545_rev_3:
1271 case e1000_82546:
1272 case e1000_82546_rev_3:
1273 case e1000_82541:
1274 case e1000_82541_rev_2:
1275 case e1000_82547:
1276 case e1000_82547_rev_2:
1277 return e1000_integrated_phy_loopback(adapter);
1278 break;
1279 default:
1280 /* Default PHY loopback work is to read the MII
1281 * control register and assert bit 14 (loopback mode).
1282 */
1283 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg);
1284 phy_reg |= MII_CR_LOOPBACK;
1285 e1000_write_phy_reg(hw, PHY_CTRL, phy_reg);
1286 return 0;
1287 break;
1288 }
1289
1290 return 8;
1291}
1292
1293static int e1000_setup_loopback_test(struct e1000_adapter *adapter)
1294{
1295 struct e1000_hw *hw = &adapter->hw;
1296 u32 rctl;
1297
1298 if (hw->media_type == e1000_media_type_fiber ||
1299 hw->media_type == e1000_media_type_internal_serdes) {
1300 switch (hw->mac_type) {
1301 case e1000_82545:
1302 case e1000_82546:
1303 case e1000_82545_rev_3:
1304 case e1000_82546_rev_3:
1305 return e1000_set_phy_loopback(adapter);
1306 break;
1307 default:
1308 rctl = er32(RCTL);
1309 rctl |= E1000_RCTL_LBM_TCVR;
1310 ew32(RCTL, rctl);
1311 return 0;
1312 }
1313 } else if (hw->media_type == e1000_media_type_copper)
1314 return e1000_set_phy_loopback(adapter);
1315
1316 return 7;
1317}
1318
1319static void e1000_loopback_cleanup(struct e1000_adapter *adapter)
1320{
1321 struct e1000_hw *hw = &adapter->hw;
1322 u32 rctl;
1323 u16 phy_reg;
1324
1325 rctl = er32(RCTL);
1326 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1327 ew32(RCTL, rctl);
1328
1329 switch (hw->mac_type) {
1330 case e1000_82545:
1331 case e1000_82546:
1332 case e1000_82545_rev_3:
1333 case e1000_82546_rev_3:
1334 default:
1335 hw->autoneg = true;
1336 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg);
1337 if (phy_reg & MII_CR_LOOPBACK) {
1338 phy_reg &= ~MII_CR_LOOPBACK;
1339 e1000_write_phy_reg(hw, PHY_CTRL, phy_reg);
1340 e1000_phy_reset(hw);
1341 }
1342 break;
1343 }
1344}
1345
1346static void e1000_create_lbtest_frame(struct sk_buff *skb,
1347 unsigned int frame_size)
1348{
1349 memset(skb->data, 0xFF, frame_size);
1350 frame_size &= ~1;
1351 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1352 memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1353 memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1354}
1355
1356static int e1000_check_lbtest_frame(struct sk_buff *skb,
1357 unsigned int frame_size)
1358{
1359 frame_size &= ~1;
1360 if (*(skb->data + 3) == 0xFF) {
1361 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1362 (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
1363 return 0;
1364 }
1365 }
1366 return 13;
1367}
1368
1369static int e1000_run_loopback_test(struct e1000_adapter *adapter)
1370{
1371 struct e1000_hw *hw = &adapter->hw;
1372 struct e1000_tx_ring *txdr = &adapter->test_tx_ring;
1373 struct e1000_rx_ring *rxdr = &adapter->test_rx_ring;
1374 struct pci_dev *pdev = adapter->pdev;
1375 int i, j, k, l, lc, good_cnt, ret_val=0;
1376 unsigned long time;
1377
1378 ew32(RDT, rxdr->count - 1);
1379
1380 /* Calculate the loop count based on the largest descriptor ring
1381 * The idea is to wrap the largest ring a number of times using 64
1382 * send/receive pairs during each loop
1383 */
1384
1385 if (rxdr->count <= txdr->count)
1386 lc = ((txdr->count / 64) * 2) + 1;
1387 else
1388 lc = ((rxdr->count / 64) * 2) + 1;
1389
1390 k = l = 0;
1391 for (j = 0; j <= lc; j++) { /* loop count loop */
1392 for (i = 0; i < 64; i++) { /* send the packets */
1393 e1000_create_lbtest_frame(txdr->buffer_info[i].skb,
1394 1024);
1395 dma_sync_single_for_device(&pdev->dev,
1396 txdr->buffer_info[k].dma,
1397 txdr->buffer_info[k].length,
1398 DMA_TO_DEVICE);
1399 if (unlikely(++k == txdr->count)) k = 0;
1400 }
1401 ew32(TDT, k);
1402 E1000_WRITE_FLUSH();
1403 msleep(200);
1404 time = jiffies; /* set the start time for the receive */
1405 good_cnt = 0;
1406 do { /* receive the sent packets */
1407 dma_sync_single_for_cpu(&pdev->dev,
1408 rxdr->buffer_info[l].dma,
1409 rxdr->buffer_info[l].length,
1410 DMA_FROM_DEVICE);
1411
1412 ret_val = e1000_check_lbtest_frame(
1413 rxdr->buffer_info[l].skb,
1414 1024);
1415 if (!ret_val)
1416 good_cnt++;
1417 if (unlikely(++l == rxdr->count)) l = 0;
1418 /* time + 20 msecs (200 msecs on 2.4) is more than
1419 * enough time to complete the receives, if it's
1420 * exceeded, break and error off
1421 */
1422 } while (good_cnt < 64 && jiffies < (time + 20));
1423 if (good_cnt != 64) {
1424 ret_val = 13; /* ret_val is the same as mis-compare */
1425 break;
1426 }
1427 if (jiffies >= (time + 2)) {
1428 ret_val = 14; /* error code for time out error */
1429 break;
1430 }
1431 } /* end loop count loop */
1432 return ret_val;
1433}
1434
1435static int e1000_loopback_test(struct e1000_adapter *adapter, u64 *data)
1436{
1437 *data = e1000_setup_desc_rings(adapter);
1438 if (*data)
1439 goto out;
1440 *data = e1000_setup_loopback_test(adapter);
1441 if (*data)
1442 goto err_loopback;
1443 *data = e1000_run_loopback_test(adapter);
1444 e1000_loopback_cleanup(adapter);
1445
1446err_loopback:
1447 e1000_free_desc_rings(adapter);
1448out:
1449 return *data;
1450}
1451
1452static int e1000_link_test(struct e1000_adapter *adapter, u64 *data)
1453{
1454 struct e1000_hw *hw = &adapter->hw;
1455 *data = 0;
1456 if (hw->media_type == e1000_media_type_internal_serdes) {
1457 int i = 0;
1458 hw->serdes_has_link = false;
1459
1460 /* On some blade server designs, link establishment
1461 * could take as long as 2-3 minutes */
1462 do {
1463 e1000_check_for_link(hw);
1464 if (hw->serdes_has_link)
1465 return *data;
1466 msleep(20);
1467 } while (i++ < 3750);
1468
1469 *data = 1;
1470 } else {
1471 e1000_check_for_link(hw);
1472 if (hw->autoneg) /* if auto_neg is set wait for it */
1473 msleep(4000);
1474
1475 if (!(er32(STATUS) & E1000_STATUS_LU)) {
1476 *data = 1;
1477 }
1478 }
1479 return *data;
1480}
1481
1482static int e1000_get_sset_count(struct net_device *netdev, int sset)
1483{
1484 switch (sset) {
1485 case ETH_SS_TEST:
1486 return E1000_TEST_LEN;
1487 case ETH_SS_STATS:
1488 return E1000_STATS_LEN;
1489 default:
1490 return -EOPNOTSUPP;
1491 }
1492}
1493
1494static void e1000_diag_test(struct net_device *netdev,
1495 struct ethtool_test *eth_test, u64 *data)
1496{
1497 struct e1000_adapter *adapter = netdev_priv(netdev);
1498 struct e1000_hw *hw = &adapter->hw;
1499 bool if_running = netif_running(netdev);
1500
1501 set_bit(__E1000_TESTING, &adapter->flags);
1502 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1503 /* Offline tests */
1504
1505 /* save speed, duplex, autoneg settings */
1506 u16 autoneg_advertised = hw->autoneg_advertised;
1507 u8 forced_speed_duplex = hw->forced_speed_duplex;
1508 u8 autoneg = hw->autoneg;
1509
1510 e_info(hw, "offline testing starting\n");
1511
1512 /* Link test performed before hardware reset so autoneg doesn't
1513 * interfere with test result */
1514 if (e1000_link_test(adapter, &data[4]))
1515 eth_test->flags |= ETH_TEST_FL_FAILED;
1516
1517 if (if_running)
1518 /* indicate we're in test mode */
1519 dev_close(netdev);
1520 else
1521 e1000_reset(adapter);
1522
1523 if (e1000_reg_test(adapter, &data[0]))
1524 eth_test->flags |= ETH_TEST_FL_FAILED;
1525
1526 e1000_reset(adapter);
1527 if (e1000_eeprom_test(adapter, &data[1]))
1528 eth_test->flags |= ETH_TEST_FL_FAILED;
1529
1530 e1000_reset(adapter);
1531 if (e1000_intr_test(adapter, &data[2]))
1532 eth_test->flags |= ETH_TEST_FL_FAILED;
1533
1534 e1000_reset(adapter);
1535 /* make sure the phy is powered up */
1536 e1000_power_up_phy(adapter);
1537 if (e1000_loopback_test(adapter, &data[3]))
1538 eth_test->flags |= ETH_TEST_FL_FAILED;
1539
1540 /* restore speed, duplex, autoneg settings */
1541 hw->autoneg_advertised = autoneg_advertised;
1542 hw->forced_speed_duplex = forced_speed_duplex;
1543 hw->autoneg = autoneg;
1544
1545 e1000_reset(adapter);
1546 clear_bit(__E1000_TESTING, &adapter->flags);
1547 if (if_running)
1548 dev_open(netdev);
1549 } else {
1550 e_info(hw, "online testing starting\n");
1551 /* Online tests */
1552 if (e1000_link_test(adapter, &data[4]))
1553 eth_test->flags |= ETH_TEST_FL_FAILED;
1554
1555 /* Online tests aren't run; pass by default */
1556 data[0] = 0;
1557 data[1] = 0;
1558 data[2] = 0;
1559 data[3] = 0;
1560
1561 clear_bit(__E1000_TESTING, &adapter->flags);
1562 }
1563 msleep_interruptible(4 * 1000);
1564}
1565
1566static int e1000_wol_exclusion(struct e1000_adapter *adapter,
1567 struct ethtool_wolinfo *wol)
1568{
1569 struct e1000_hw *hw = &adapter->hw;
1570 int retval = 1; /* fail by default */
1571
1572 switch (hw->device_id) {
1573 case E1000_DEV_ID_82542:
1574 case E1000_DEV_ID_82543GC_FIBER:
1575 case E1000_DEV_ID_82543GC_COPPER:
1576 case E1000_DEV_ID_82544EI_FIBER:
1577 case E1000_DEV_ID_82546EB_QUAD_COPPER:
1578 case E1000_DEV_ID_82545EM_FIBER:
1579 case E1000_DEV_ID_82545EM_COPPER:
1580 case E1000_DEV_ID_82546GB_QUAD_COPPER:
1581 case E1000_DEV_ID_82546GB_PCIE:
1582 /* these don't support WoL at all */
1583 wol->supported = 0;
1584 break;
1585 case E1000_DEV_ID_82546EB_FIBER:
1586 case E1000_DEV_ID_82546GB_FIBER:
1587 /* Wake events not supported on port B */
1588 if (er32(STATUS) & E1000_STATUS_FUNC_1) {
1589 wol->supported = 0;
1590 break;
1591 }
1592 /* return success for non excluded adapter ports */
1593 retval = 0;
1594 break;
1595 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1596 /* quad port adapters only support WoL on port A */
1597 if (!adapter->quad_port_a) {
1598 wol->supported = 0;
1599 break;
1600 }
1601 /* return success for non excluded adapter ports */
1602 retval = 0;
1603 break;
1604 default:
1605 /* dual port cards only support WoL on port A from now on
1606 * unless it was enabled in the eeprom for port B
1607 * so exclude FUNC_1 ports from having WoL enabled */
1608 if (er32(STATUS) & E1000_STATUS_FUNC_1 &&
1609 !adapter->eeprom_wol) {
1610 wol->supported = 0;
1611 break;
1612 }
1613
1614 retval = 0;
1615 }
1616
1617 return retval;
1618}
1619
1620static void e1000_get_wol(struct net_device *netdev,
1621 struct ethtool_wolinfo *wol)
1622{
1623 struct e1000_adapter *adapter = netdev_priv(netdev);
1624 struct e1000_hw *hw = &adapter->hw;
1625
1626 wol->supported = WAKE_UCAST | WAKE_MCAST |
1627 WAKE_BCAST | WAKE_MAGIC;
1628 wol->wolopts = 0;
1629
1630 /* this function will set ->supported = 0 and return 1 if wol is not
1631 * supported by this hardware */
1632 if (e1000_wol_exclusion(adapter, wol) ||
1633 !device_can_wakeup(&adapter->pdev->dev))
1634 return;
1635
1636 /* apply any specific unsupported masks here */
1637 switch (hw->device_id) {
1638 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1639 /* KSP3 does not suppport UCAST wake-ups */
1640 wol->supported &= ~WAKE_UCAST;
1641
1642 if (adapter->wol & E1000_WUFC_EX)
1643 e_err(drv, "Interface does not support directed "
1644 "(unicast) frame wake-up packets\n");
1645 break;
1646 default:
1647 break;
1648 }
1649
1650 if (adapter->wol & E1000_WUFC_EX)
1651 wol->wolopts |= WAKE_UCAST;
1652 if (adapter->wol & E1000_WUFC_MC)
1653 wol->wolopts |= WAKE_MCAST;
1654 if (adapter->wol & E1000_WUFC_BC)
1655 wol->wolopts |= WAKE_BCAST;
1656 if (adapter->wol & E1000_WUFC_MAG)
1657 wol->wolopts |= WAKE_MAGIC;
1658}
1659
1660static int e1000_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1661{
1662 struct e1000_adapter *adapter = netdev_priv(netdev);
1663 struct e1000_hw *hw = &adapter->hw;
1664
1665 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1666 return -EOPNOTSUPP;
1667
1668 if (e1000_wol_exclusion(adapter, wol) ||
1669 !device_can_wakeup(&adapter->pdev->dev))
1670 return wol->wolopts ? -EOPNOTSUPP : 0;
1671
1672 switch (hw->device_id) {
1673 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1674 if (wol->wolopts & WAKE_UCAST) {
1675 e_err(drv, "Interface does not support directed "
1676 "(unicast) frame wake-up packets\n");
1677 return -EOPNOTSUPP;
1678 }
1679 break;
1680 default:
1681 break;
1682 }
1683
1684 /* these settings will always override what we currently have */
1685 adapter->wol = 0;
1686
1687 if (wol->wolopts & WAKE_UCAST)
1688 adapter->wol |= E1000_WUFC_EX;
1689 if (wol->wolopts & WAKE_MCAST)
1690 adapter->wol |= E1000_WUFC_MC;
1691 if (wol->wolopts & WAKE_BCAST)
1692 adapter->wol |= E1000_WUFC_BC;
1693 if (wol->wolopts & WAKE_MAGIC)
1694 adapter->wol |= E1000_WUFC_MAG;
1695
1696 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1697
1698 return 0;
1699}
1700
1701static int e1000_set_phys_id(struct net_device *netdev,
1702 enum ethtool_phys_id_state state)
1703{
1704 struct e1000_adapter *adapter = netdev_priv(netdev);
1705 struct e1000_hw *hw = &adapter->hw;
1706
1707 switch (state) {
1708 case ETHTOOL_ID_ACTIVE:
1709 e1000_setup_led(hw);
1710 return 2;
1711
1712 case ETHTOOL_ID_ON:
1713 e1000_led_on(hw);
1714 break;
1715
1716 case ETHTOOL_ID_OFF:
1717 e1000_led_off(hw);
1718 break;
1719
1720 case ETHTOOL_ID_INACTIVE:
1721 e1000_cleanup_led(hw);
1722 }
1723
1724 return 0;
1725}
1726
1727static int e1000_get_coalesce(struct net_device *netdev,
1728 struct ethtool_coalesce *ec)
1729{
1730 struct e1000_adapter *adapter = netdev_priv(netdev);
1731
1732 if (adapter->hw.mac_type < e1000_82545)
1733 return -EOPNOTSUPP;
1734
1735 if (adapter->itr_setting <= 4)
1736 ec->rx_coalesce_usecs = adapter->itr_setting;
1737 else
1738 ec->rx_coalesce_usecs = 1000000 / adapter->itr_setting;
1739
1740 return 0;
1741}
1742
1743static int e1000_set_coalesce(struct net_device *netdev,
1744 struct ethtool_coalesce *ec)
1745{
1746 struct e1000_adapter *adapter = netdev_priv(netdev);
1747 struct e1000_hw *hw = &adapter->hw;
1748
1749 if (hw->mac_type < e1000_82545)
1750 return -EOPNOTSUPP;
1751
1752 if ((ec->rx_coalesce_usecs > E1000_MAX_ITR_USECS) ||
1753 ((ec->rx_coalesce_usecs > 4) &&
1754 (ec->rx_coalesce_usecs < E1000_MIN_ITR_USECS)) ||
1755 (ec->rx_coalesce_usecs == 2))
1756 return -EINVAL;
1757
1758 if (ec->rx_coalesce_usecs == 4) {
1759 adapter->itr = adapter->itr_setting = 4;
1760 } else if (ec->rx_coalesce_usecs <= 3) {
1761 adapter->itr = 20000;
1762 adapter->itr_setting = ec->rx_coalesce_usecs;
1763 } else {
1764 adapter->itr = (1000000 / ec->rx_coalesce_usecs);
1765 adapter->itr_setting = adapter->itr & ~3;
1766 }
1767
1768 if (adapter->itr_setting != 0)
1769 ew32(ITR, 1000000000 / (adapter->itr * 256));
1770 else
1771 ew32(ITR, 0);
1772
1773 return 0;
1774}
1775
1776static int e1000_nway_reset(struct net_device *netdev)
1777{
1778 struct e1000_adapter *adapter = netdev_priv(netdev);
1779 if (netif_running(netdev))
1780 e1000_reinit_locked(adapter);
1781 return 0;
1782}
1783
1784static void e1000_get_ethtool_stats(struct net_device *netdev,
1785 struct ethtool_stats *stats, u64 *data)
1786{
1787 struct e1000_adapter *adapter = netdev_priv(netdev);
1788 int i;
1789 char *p = NULL;
1790
1791 e1000_update_stats(adapter);
1792 for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) {
1793 switch (e1000_gstrings_stats[i].type) {
1794 case NETDEV_STATS:
1795 p = (char *) netdev +
1796 e1000_gstrings_stats[i].stat_offset;
1797 break;
1798 case E1000_STATS:
1799 p = (char *) adapter +
1800 e1000_gstrings_stats[i].stat_offset;
1801 break;
1802 }
1803
1804 data[i] = (e1000_gstrings_stats[i].sizeof_stat ==
1805 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1806 }
1807/* BUG_ON(i != E1000_STATS_LEN); */
1808}
1809
1810static void e1000_get_strings(struct net_device *netdev, u32 stringset,
1811 u8 *data)
1812{
1813 u8 *p = data;
1814 int i;
1815
1816 switch (stringset) {
1817 case ETH_SS_TEST:
1818 memcpy(data, *e1000_gstrings_test,
1819 sizeof(e1000_gstrings_test));
1820 break;
1821 case ETH_SS_STATS:
1822 for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) {
1823 memcpy(p, e1000_gstrings_stats[i].stat_string,
1824 ETH_GSTRING_LEN);
1825 p += ETH_GSTRING_LEN;
1826 }
1827/* BUG_ON(p - data != E1000_STATS_LEN * ETH_GSTRING_LEN); */
1828 break;
1829 }
1830}
1831
1832static const struct ethtool_ops e1000_ethtool_ops = {
1833 .get_settings = e1000_get_settings,
1834 .set_settings = e1000_set_settings,
1835 .get_drvinfo = e1000_get_drvinfo,
1836 .get_regs_len = e1000_get_regs_len,
1837 .get_regs = e1000_get_regs,
1838 .get_wol = e1000_get_wol,
1839 .set_wol = e1000_set_wol,
1840 .get_msglevel = e1000_get_msglevel,
1841 .set_msglevel = e1000_set_msglevel,
1842 .nway_reset = e1000_nway_reset,
1843 .get_link = e1000_get_link,
1844 .get_eeprom_len = e1000_get_eeprom_len,
1845 .get_eeprom = e1000_get_eeprom,
1846 .set_eeprom = e1000_set_eeprom,
1847 .get_ringparam = e1000_get_ringparam,
1848 .set_ringparam = e1000_set_ringparam,
1849 .get_pauseparam = e1000_get_pauseparam,
1850 .set_pauseparam = e1000_set_pauseparam,
1851 .self_test = e1000_diag_test,
1852 .get_strings = e1000_get_strings,
1853 .set_phys_id = e1000_set_phys_id,
1854 .get_ethtool_stats = e1000_get_ethtool_stats,
1855 .get_sset_count = e1000_get_sset_count,
1856 .get_coalesce = e1000_get_coalesce,
1857 .set_coalesce = e1000_set_coalesce,
1858};
1859
1860void e1000_set_ethtool_ops(struct net_device *netdev)
1861{
1862 SET_ETHTOOL_OPS(netdev, &e1000_ethtool_ops);
1863}
diff --git a/drivers/net/ethernet/intel/e1000/e1000_hw.c b/drivers/net/ethernet/intel/e1000/e1000_hw.c
new file mode 100644
index 000000000000..8545c7aa93eb
--- /dev/null
+++ b/drivers/net/ethernet/intel/e1000/e1000_hw.c
@@ -0,0 +1,5824 @@
1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 */
28
29/* e1000_hw.c
30 * Shared functions for accessing and configuring the MAC
31 */
32
33#include "e1000.h"
34
35static s32 e1000_check_downshift(struct e1000_hw *hw);
36static s32 e1000_check_polarity(struct e1000_hw *hw,
37 e1000_rev_polarity *polarity);
38static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
39static void e1000_clear_vfta(struct e1000_hw *hw);
40static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
41 bool link_up);
42static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);
43static s32 e1000_detect_gig_phy(struct e1000_hw *hw);
44static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);
45static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
46 u16 *max_length);
47static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
48static s32 e1000_id_led_init(struct e1000_hw *hw);
49static void e1000_init_rx_addrs(struct e1000_hw *hw);
50static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
51 struct e1000_phy_info *phy_info);
52static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
53 struct e1000_phy_info *phy_info);
54static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
55static s32 e1000_wait_autoneg(struct e1000_hw *hw);
56static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);
57static s32 e1000_set_phy_type(struct e1000_hw *hw);
58static void e1000_phy_init_script(struct e1000_hw *hw);
59static s32 e1000_setup_copper_link(struct e1000_hw *hw);
60static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
61static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
62static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
63static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);
64static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
65static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
66static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);
67static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);
68static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
69static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,
70 u16 words, u16 *data);
71static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
72 u16 words, u16 *data);
73static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);
74static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);
75static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);
76static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);
77static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
78 u16 phy_data);
79static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
80 u16 *phy_data);
81static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);
82static s32 e1000_acquire_eeprom(struct e1000_hw *hw);
83static void e1000_release_eeprom(struct e1000_hw *hw);
84static void e1000_standby_eeprom(struct e1000_hw *hw);
85static s32 e1000_set_vco_speed(struct e1000_hw *hw);
86static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);
87static s32 e1000_set_phy_mode(struct e1000_hw *hw);
88static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
89 u16 *data);
90static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
91 u16 *data);
92
93/* IGP cable length table */
94static const
95u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {
96 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
97 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
98 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
99 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
100 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
101 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,
102 100,
103 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
104 110, 110,
105 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,
106 120, 120
107};
108
109static DEFINE_SPINLOCK(e1000_eeprom_lock);
110
111/**
112 * e1000_set_phy_type - Set the phy type member in the hw struct.
113 * @hw: Struct containing variables accessed by shared code
114 */
115static s32 e1000_set_phy_type(struct e1000_hw *hw)
116{
117 e_dbg("e1000_set_phy_type");
118
119 if (hw->mac_type == e1000_undefined)
120 return -E1000_ERR_PHY_TYPE;
121
122 switch (hw->phy_id) {
123 case M88E1000_E_PHY_ID:
124 case M88E1000_I_PHY_ID:
125 case M88E1011_I_PHY_ID:
126 case M88E1111_I_PHY_ID:
127 case M88E1118_E_PHY_ID:
128 hw->phy_type = e1000_phy_m88;
129 break;
130 case IGP01E1000_I_PHY_ID:
131 if (hw->mac_type == e1000_82541 ||
132 hw->mac_type == e1000_82541_rev_2 ||
133 hw->mac_type == e1000_82547 ||
134 hw->mac_type == e1000_82547_rev_2)
135 hw->phy_type = e1000_phy_igp;
136 break;
137 case RTL8211B_PHY_ID:
138 hw->phy_type = e1000_phy_8211;
139 break;
140 case RTL8201N_PHY_ID:
141 hw->phy_type = e1000_phy_8201;
142 break;
143 default:
144 /* Should never have loaded on this device */
145 hw->phy_type = e1000_phy_undefined;
146 return -E1000_ERR_PHY_TYPE;
147 }
148
149 return E1000_SUCCESS;
150}
151
152/**
153 * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY
154 * @hw: Struct containing variables accessed by shared code
155 */
156static void e1000_phy_init_script(struct e1000_hw *hw)
157{
158 u32 ret_val;
159 u16 phy_saved_data;
160
161 e_dbg("e1000_phy_init_script");
162
163 if (hw->phy_init_script) {
164 msleep(20);
165
166 /* Save off the current value of register 0x2F5B to be restored at
167 * the end of this routine. */
168 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
169
170 /* Disabled the PHY transmitter */
171 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
172 msleep(20);
173
174 e1000_write_phy_reg(hw, 0x0000, 0x0140);
175 msleep(5);
176
177 switch (hw->mac_type) {
178 case e1000_82541:
179 case e1000_82547:
180 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
181 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
182 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
183 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
184 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
185 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
186 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
187 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
188 e1000_write_phy_reg(hw, 0x2010, 0x0008);
189 break;
190
191 case e1000_82541_rev_2:
192 case e1000_82547_rev_2:
193 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
194 break;
195 default:
196 break;
197 }
198
199 e1000_write_phy_reg(hw, 0x0000, 0x3300);
200 msleep(20);
201
202 /* Now enable the transmitter */
203 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
204
205 if (hw->mac_type == e1000_82547) {
206 u16 fused, fine, coarse;
207
208 /* Move to analog registers page */
209 e1000_read_phy_reg(hw,
210 IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
211 &fused);
212
213 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
214 e1000_read_phy_reg(hw,
215 IGP01E1000_ANALOG_FUSE_STATUS,
216 &fused);
217
218 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
219 coarse =
220 fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
221
222 if (coarse >
223 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
224 coarse -=
225 IGP01E1000_ANALOG_FUSE_COARSE_10;
226 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
227 } else if (coarse ==
228 IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
229 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
230
231 fused =
232 (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
233 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
234 (coarse &
235 IGP01E1000_ANALOG_FUSE_COARSE_MASK);
236
237 e1000_write_phy_reg(hw,
238 IGP01E1000_ANALOG_FUSE_CONTROL,
239 fused);
240 e1000_write_phy_reg(hw,
241 IGP01E1000_ANALOG_FUSE_BYPASS,
242 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
243 }
244 }
245 }
246}
247
248/**
249 * e1000_set_mac_type - Set the mac type member in the hw struct.
250 * @hw: Struct containing variables accessed by shared code
251 */
252s32 e1000_set_mac_type(struct e1000_hw *hw)
253{
254 e_dbg("e1000_set_mac_type");
255
256 switch (hw->device_id) {
257 case E1000_DEV_ID_82542:
258 switch (hw->revision_id) {
259 case E1000_82542_2_0_REV_ID:
260 hw->mac_type = e1000_82542_rev2_0;
261 break;
262 case E1000_82542_2_1_REV_ID:
263 hw->mac_type = e1000_82542_rev2_1;
264 break;
265 default:
266 /* Invalid 82542 revision ID */
267 return -E1000_ERR_MAC_TYPE;
268 }
269 break;
270 case E1000_DEV_ID_82543GC_FIBER:
271 case E1000_DEV_ID_82543GC_COPPER:
272 hw->mac_type = e1000_82543;
273 break;
274 case E1000_DEV_ID_82544EI_COPPER:
275 case E1000_DEV_ID_82544EI_FIBER:
276 case E1000_DEV_ID_82544GC_COPPER:
277 case E1000_DEV_ID_82544GC_LOM:
278 hw->mac_type = e1000_82544;
279 break;
280 case E1000_DEV_ID_82540EM:
281 case E1000_DEV_ID_82540EM_LOM:
282 case E1000_DEV_ID_82540EP:
283 case E1000_DEV_ID_82540EP_LOM:
284 case E1000_DEV_ID_82540EP_LP:
285 hw->mac_type = e1000_82540;
286 break;
287 case E1000_DEV_ID_82545EM_COPPER:
288 case E1000_DEV_ID_82545EM_FIBER:
289 hw->mac_type = e1000_82545;
290 break;
291 case E1000_DEV_ID_82545GM_COPPER:
292 case E1000_DEV_ID_82545GM_FIBER:
293 case E1000_DEV_ID_82545GM_SERDES:
294 hw->mac_type = e1000_82545_rev_3;
295 break;
296 case E1000_DEV_ID_82546EB_COPPER:
297 case E1000_DEV_ID_82546EB_FIBER:
298 case E1000_DEV_ID_82546EB_QUAD_COPPER:
299 hw->mac_type = e1000_82546;
300 break;
301 case E1000_DEV_ID_82546GB_COPPER:
302 case E1000_DEV_ID_82546GB_FIBER:
303 case E1000_DEV_ID_82546GB_SERDES:
304 case E1000_DEV_ID_82546GB_PCIE:
305 case E1000_DEV_ID_82546GB_QUAD_COPPER:
306 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
307 hw->mac_type = e1000_82546_rev_3;
308 break;
309 case E1000_DEV_ID_82541EI:
310 case E1000_DEV_ID_82541EI_MOBILE:
311 case E1000_DEV_ID_82541ER_LOM:
312 hw->mac_type = e1000_82541;
313 break;
314 case E1000_DEV_ID_82541ER:
315 case E1000_DEV_ID_82541GI:
316 case E1000_DEV_ID_82541GI_LF:
317 case E1000_DEV_ID_82541GI_MOBILE:
318 hw->mac_type = e1000_82541_rev_2;
319 break;
320 case E1000_DEV_ID_82547EI:
321 case E1000_DEV_ID_82547EI_MOBILE:
322 hw->mac_type = e1000_82547;
323 break;
324 case E1000_DEV_ID_82547GI:
325 hw->mac_type = e1000_82547_rev_2;
326 break;
327 case E1000_DEV_ID_INTEL_CE4100_GBE:
328 hw->mac_type = e1000_ce4100;
329 break;
330 default:
331 /* Should never have loaded on this device */
332 return -E1000_ERR_MAC_TYPE;
333 }
334
335 switch (hw->mac_type) {
336 case e1000_82541:
337 case e1000_82547:
338 case e1000_82541_rev_2:
339 case e1000_82547_rev_2:
340 hw->asf_firmware_present = true;
341 break;
342 default:
343 break;
344 }
345
346 /* The 82543 chip does not count tx_carrier_errors properly in
347 * FD mode
348 */
349 if (hw->mac_type == e1000_82543)
350 hw->bad_tx_carr_stats_fd = true;
351
352 if (hw->mac_type > e1000_82544)
353 hw->has_smbus = true;
354
355 return E1000_SUCCESS;
356}
357
358/**
359 * e1000_set_media_type - Set media type and TBI compatibility.
360 * @hw: Struct containing variables accessed by shared code
361 */
362void e1000_set_media_type(struct e1000_hw *hw)
363{
364 u32 status;
365
366 e_dbg("e1000_set_media_type");
367
368 if (hw->mac_type != e1000_82543) {
369 /* tbi_compatibility is only valid on 82543 */
370 hw->tbi_compatibility_en = false;
371 }
372
373 switch (hw->device_id) {
374 case E1000_DEV_ID_82545GM_SERDES:
375 case E1000_DEV_ID_82546GB_SERDES:
376 hw->media_type = e1000_media_type_internal_serdes;
377 break;
378 default:
379 switch (hw->mac_type) {
380 case e1000_82542_rev2_0:
381 case e1000_82542_rev2_1:
382 hw->media_type = e1000_media_type_fiber;
383 break;
384 case e1000_ce4100:
385 hw->media_type = e1000_media_type_copper;
386 break;
387 default:
388 status = er32(STATUS);
389 if (status & E1000_STATUS_TBIMODE) {
390 hw->media_type = e1000_media_type_fiber;
391 /* tbi_compatibility not valid on fiber */
392 hw->tbi_compatibility_en = false;
393 } else {
394 hw->media_type = e1000_media_type_copper;
395 }
396 break;
397 }
398 }
399}
400
401/**
402 * e1000_reset_hw: reset the hardware completely
403 * @hw: Struct containing variables accessed by shared code
404 *
405 * Reset the transmit and receive units; mask and clear all interrupts.
406 */
407s32 e1000_reset_hw(struct e1000_hw *hw)
408{
409 u32 ctrl;
410 u32 ctrl_ext;
411 u32 icr;
412 u32 manc;
413 u32 led_ctrl;
414 s32 ret_val;
415
416 e_dbg("e1000_reset_hw");
417
418 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
419 if (hw->mac_type == e1000_82542_rev2_0) {
420 e_dbg("Disabling MWI on 82542 rev 2.0\n");
421 e1000_pci_clear_mwi(hw);
422 }
423
424 /* Clear interrupt mask to stop board from generating interrupts */
425 e_dbg("Masking off all interrupts\n");
426 ew32(IMC, 0xffffffff);
427
428 /* Disable the Transmit and Receive units. Then delay to allow
429 * any pending transactions to complete before we hit the MAC with
430 * the global reset.
431 */
432 ew32(RCTL, 0);
433 ew32(TCTL, E1000_TCTL_PSP);
434 E1000_WRITE_FLUSH();
435
436 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
437 hw->tbi_compatibility_on = false;
438
439 /* Delay to allow any outstanding PCI transactions to complete before
440 * resetting the device
441 */
442 msleep(10);
443
444 ctrl = er32(CTRL);
445
446 /* Must reset the PHY before resetting the MAC */
447 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
448 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));
449 E1000_WRITE_FLUSH();
450 msleep(5);
451 }
452
453 /* Issue a global reset to the MAC. This will reset the chip's
454 * transmit, receive, DMA, and link units. It will not effect
455 * the current PCI configuration. The global reset bit is self-
456 * clearing, and should clear within a microsecond.
457 */
458 e_dbg("Issuing a global reset to MAC\n");
459
460 switch (hw->mac_type) {
461 case e1000_82544:
462 case e1000_82540:
463 case e1000_82545:
464 case e1000_82546:
465 case e1000_82541:
466 case e1000_82541_rev_2:
467 /* These controllers can't ack the 64-bit write when issuing the
468 * reset, so use IO-mapping as a workaround to issue the reset */
469 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
470 break;
471 case e1000_82545_rev_3:
472 case e1000_82546_rev_3:
473 /* Reset is performed on a shadow of the control register */
474 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
475 break;
476 case e1000_ce4100:
477 default:
478 ew32(CTRL, (ctrl | E1000_CTRL_RST));
479 break;
480 }
481
482 /* After MAC reset, force reload of EEPROM to restore power-on settings to
483 * device. Later controllers reload the EEPROM automatically, so just wait
484 * for reload to complete.
485 */
486 switch (hw->mac_type) {
487 case e1000_82542_rev2_0:
488 case e1000_82542_rev2_1:
489 case e1000_82543:
490 case e1000_82544:
491 /* Wait for reset to complete */
492 udelay(10);
493 ctrl_ext = er32(CTRL_EXT);
494 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
495 ew32(CTRL_EXT, ctrl_ext);
496 E1000_WRITE_FLUSH();
497 /* Wait for EEPROM reload */
498 msleep(2);
499 break;
500 case e1000_82541:
501 case e1000_82541_rev_2:
502 case e1000_82547:
503 case e1000_82547_rev_2:
504 /* Wait for EEPROM reload */
505 msleep(20);
506 break;
507 default:
508 /* Auto read done will delay 5ms or poll based on mac type */
509 ret_val = e1000_get_auto_rd_done(hw);
510 if (ret_val)
511 return ret_val;
512 break;
513 }
514
515 /* Disable HW ARPs on ASF enabled adapters */
516 if (hw->mac_type >= e1000_82540) {
517 manc = er32(MANC);
518 manc &= ~(E1000_MANC_ARP_EN);
519 ew32(MANC, manc);
520 }
521
522 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
523 e1000_phy_init_script(hw);
524
525 /* Configure activity LED after PHY reset */
526 led_ctrl = er32(LEDCTL);
527 led_ctrl &= IGP_ACTIVITY_LED_MASK;
528 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
529 ew32(LEDCTL, led_ctrl);
530 }
531
532 /* Clear interrupt mask to stop board from generating interrupts */
533 e_dbg("Masking off all interrupts\n");
534 ew32(IMC, 0xffffffff);
535
536 /* Clear any pending interrupt events. */
537 icr = er32(ICR);
538
539 /* If MWI was previously enabled, reenable it. */
540 if (hw->mac_type == e1000_82542_rev2_0) {
541 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
542 e1000_pci_set_mwi(hw);
543 }
544
545 return E1000_SUCCESS;
546}
547
548/**
549 * e1000_init_hw: Performs basic configuration of the adapter.
550 * @hw: Struct containing variables accessed by shared code
551 *
552 * Assumes that the controller has previously been reset and is in a
553 * post-reset uninitialized state. Initializes the receive address registers,
554 * multicast table, and VLAN filter table. Calls routines to setup link
555 * configuration and flow control settings. Clears all on-chip counters. Leaves
556 * the transmit and receive units disabled and uninitialized.
557 */
558s32 e1000_init_hw(struct e1000_hw *hw)
559{
560 u32 ctrl;
561 u32 i;
562 s32 ret_val;
563 u32 mta_size;
564 u32 ctrl_ext;
565
566 e_dbg("e1000_init_hw");
567
568 /* Initialize Identification LED */
569 ret_val = e1000_id_led_init(hw);
570 if (ret_val) {
571 e_dbg("Error Initializing Identification LED\n");
572 return ret_val;
573 }
574
575 /* Set the media type and TBI compatibility */
576 e1000_set_media_type(hw);
577
578 /* Disabling VLAN filtering. */
579 e_dbg("Initializing the IEEE VLAN\n");
580 if (hw->mac_type < e1000_82545_rev_3)
581 ew32(VET, 0);
582 e1000_clear_vfta(hw);
583
584 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
585 if (hw->mac_type == e1000_82542_rev2_0) {
586 e_dbg("Disabling MWI on 82542 rev 2.0\n");
587 e1000_pci_clear_mwi(hw);
588 ew32(RCTL, E1000_RCTL_RST);
589 E1000_WRITE_FLUSH();
590 msleep(5);
591 }
592
593 /* Setup the receive address. This involves initializing all of the Receive
594 * Address Registers (RARs 0 - 15).
595 */
596 e1000_init_rx_addrs(hw);
597
598 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
599 if (hw->mac_type == e1000_82542_rev2_0) {
600 ew32(RCTL, 0);
601 E1000_WRITE_FLUSH();
602 msleep(1);
603 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
604 e1000_pci_set_mwi(hw);
605 }
606
607 /* Zero out the Multicast HASH table */
608 e_dbg("Zeroing the MTA\n");
609 mta_size = E1000_MC_TBL_SIZE;
610 for (i = 0; i < mta_size; i++) {
611 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
612 /* use write flush to prevent Memory Write Block (MWB) from
613 * occurring when accessing our register space */
614 E1000_WRITE_FLUSH();
615 }
616
617 /* Set the PCI priority bit correctly in the CTRL register. This
618 * determines if the adapter gives priority to receives, or if it
619 * gives equal priority to transmits and receives. Valid only on
620 * 82542 and 82543 silicon.
621 */
622 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
623 ctrl = er32(CTRL);
624 ew32(CTRL, ctrl | E1000_CTRL_PRIOR);
625 }
626
627 switch (hw->mac_type) {
628 case e1000_82545_rev_3:
629 case e1000_82546_rev_3:
630 break;
631 default:
632 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
633 if (hw->bus_type == e1000_bus_type_pcix
634 && e1000_pcix_get_mmrbc(hw) > 2048)
635 e1000_pcix_set_mmrbc(hw, 2048);
636 break;
637 }
638
639 /* Call a subroutine to configure the link and setup flow control. */
640 ret_val = e1000_setup_link(hw);
641
642 /* Set the transmit descriptor write-back policy */
643 if (hw->mac_type > e1000_82544) {
644 ctrl = er32(TXDCTL);
645 ctrl =
646 (ctrl & ~E1000_TXDCTL_WTHRESH) |
647 E1000_TXDCTL_FULL_TX_DESC_WB;
648 ew32(TXDCTL, ctrl);
649 }
650
651 /* Clear all of the statistics registers (clear on read). It is
652 * important that we do this after we have tried to establish link
653 * because the symbol error count will increment wildly if there
654 * is no link.
655 */
656 e1000_clear_hw_cntrs(hw);
657
658 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
659 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
660 ctrl_ext = er32(CTRL_EXT);
661 /* Relaxed ordering must be disabled to avoid a parity
662 * error crash in a PCI slot. */
663 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
664 ew32(CTRL_EXT, ctrl_ext);
665 }
666
667 return ret_val;
668}
669
670/**
671 * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting.
672 * @hw: Struct containing variables accessed by shared code.
673 */
674static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
675{
676 u16 eeprom_data;
677 s32 ret_val;
678
679 e_dbg("e1000_adjust_serdes_amplitude");
680
681 if (hw->media_type != e1000_media_type_internal_serdes)
682 return E1000_SUCCESS;
683
684 switch (hw->mac_type) {
685 case e1000_82545_rev_3:
686 case e1000_82546_rev_3:
687 break;
688 default:
689 return E1000_SUCCESS;
690 }
691
692 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
693 &eeprom_data);
694 if (ret_val) {
695 return ret_val;
696 }
697
698 if (eeprom_data != EEPROM_RESERVED_WORD) {
699 /* Adjust SERDES output amplitude only. */
700 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
701 ret_val =
702 e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
703 if (ret_val)
704 return ret_val;
705 }
706
707 return E1000_SUCCESS;
708}
709
710/**
711 * e1000_setup_link - Configures flow control and link settings.
712 * @hw: Struct containing variables accessed by shared code
713 *
714 * Determines which flow control settings to use. Calls the appropriate media-
715 * specific link configuration function. Configures the flow control settings.
716 * Assuming the adapter has a valid link partner, a valid link should be
717 * established. Assumes the hardware has previously been reset and the
718 * transmitter and receiver are not enabled.
719 */
720s32 e1000_setup_link(struct e1000_hw *hw)
721{
722 u32 ctrl_ext;
723 s32 ret_val;
724 u16 eeprom_data;
725
726 e_dbg("e1000_setup_link");
727
728 /* Read and store word 0x0F of the EEPROM. This word contains bits
729 * that determine the hardware's default PAUSE (flow control) mode,
730 * a bit that determines whether the HW defaults to enabling or
731 * disabling auto-negotiation, and the direction of the
732 * SW defined pins. If there is no SW over-ride of the flow
733 * control setting, then the variable hw->fc will
734 * be initialized based on a value in the EEPROM.
735 */
736 if (hw->fc == E1000_FC_DEFAULT) {
737 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
738 1, &eeprom_data);
739 if (ret_val) {
740 e_dbg("EEPROM Read Error\n");
741 return -E1000_ERR_EEPROM;
742 }
743 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
744 hw->fc = E1000_FC_NONE;
745 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
746 EEPROM_WORD0F_ASM_DIR)
747 hw->fc = E1000_FC_TX_PAUSE;
748 else
749 hw->fc = E1000_FC_FULL;
750 }
751
752 /* We want to save off the original Flow Control configuration just
753 * in case we get disconnected and then reconnected into a different
754 * hub or switch with different Flow Control capabilities.
755 */
756 if (hw->mac_type == e1000_82542_rev2_0)
757 hw->fc &= (~E1000_FC_TX_PAUSE);
758
759 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
760 hw->fc &= (~E1000_FC_RX_PAUSE);
761
762 hw->original_fc = hw->fc;
763
764 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc);
765
766 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
767 * polarity value for the SW controlled pins, and setup the
768 * Extended Device Control reg with that info.
769 * This is needed because one of the SW controlled pins is used for
770 * signal detection. So this should be done before e1000_setup_pcs_link()
771 * or e1000_phy_setup() is called.
772 */
773 if (hw->mac_type == e1000_82543) {
774 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
775 1, &eeprom_data);
776 if (ret_val) {
777 e_dbg("EEPROM Read Error\n");
778 return -E1000_ERR_EEPROM;
779 }
780 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
781 SWDPIO__EXT_SHIFT);
782 ew32(CTRL_EXT, ctrl_ext);
783 }
784
785 /* Call the necessary subroutine to configure the link. */
786 ret_val = (hw->media_type == e1000_media_type_copper) ?
787 e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw);
788
789 /* Initialize the flow control address, type, and PAUSE timer
790 * registers to their default values. This is done even if flow
791 * control is disabled, because it does not hurt anything to
792 * initialize these registers.
793 */
794 e_dbg("Initializing the Flow Control address, type and timer regs\n");
795
796 ew32(FCT, FLOW_CONTROL_TYPE);
797 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
798 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
799
800 ew32(FCTTV, hw->fc_pause_time);
801
802 /* Set the flow control receive threshold registers. Normally,
803 * these registers will be set to a default threshold that may be
804 * adjusted later by the driver's runtime code. However, if the
805 * ability to transmit pause frames in not enabled, then these
806 * registers will be set to 0.
807 */
808 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
809 ew32(FCRTL, 0);
810 ew32(FCRTH, 0);
811 } else {
812 /* We need to set up the Receive Threshold high and low water marks
813 * as well as (optionally) enabling the transmission of XON frames.
814 */
815 if (hw->fc_send_xon) {
816 ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
817 ew32(FCRTH, hw->fc_high_water);
818 } else {
819 ew32(FCRTL, hw->fc_low_water);
820 ew32(FCRTH, hw->fc_high_water);
821 }
822 }
823 return ret_val;
824}
825
826/**
827 * e1000_setup_fiber_serdes_link - prepare fiber or serdes link
828 * @hw: Struct containing variables accessed by shared code
829 *
830 * Manipulates Physical Coding Sublayer functions in order to configure
831 * link. Assumes the hardware has been previously reset and the transmitter
832 * and receiver are not enabled.
833 */
834static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
835{
836 u32 ctrl;
837 u32 status;
838 u32 txcw = 0;
839 u32 i;
840 u32 signal = 0;
841 s32 ret_val;
842
843 e_dbg("e1000_setup_fiber_serdes_link");
844
845 /* On adapters with a MAC newer than 82544, SWDP 1 will be
846 * set when the optics detect a signal. On older adapters, it will be
847 * cleared when there is a signal. This applies to fiber media only.
848 * If we're on serdes media, adjust the output amplitude to value
849 * set in the EEPROM.
850 */
851 ctrl = er32(CTRL);
852 if (hw->media_type == e1000_media_type_fiber)
853 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
854
855 ret_val = e1000_adjust_serdes_amplitude(hw);
856 if (ret_val)
857 return ret_val;
858
859 /* Take the link out of reset */
860 ctrl &= ~(E1000_CTRL_LRST);
861
862 /* Adjust VCO speed to improve BER performance */
863 ret_val = e1000_set_vco_speed(hw);
864 if (ret_val)
865 return ret_val;
866
867 e1000_config_collision_dist(hw);
868
869 /* Check for a software override of the flow control settings, and setup
870 * the device accordingly. If auto-negotiation is enabled, then software
871 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
872 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
873 * auto-negotiation is disabled, then software will have to manually
874 * configure the two flow control enable bits in the CTRL register.
875 *
876 * The possible values of the "fc" parameter are:
877 * 0: Flow control is completely disabled
878 * 1: Rx flow control is enabled (we can receive pause frames, but
879 * not send pause frames).
880 * 2: Tx flow control is enabled (we can send pause frames but we do
881 * not support receiving pause frames).
882 * 3: Both Rx and TX flow control (symmetric) are enabled.
883 */
884 switch (hw->fc) {
885 case E1000_FC_NONE:
886 /* Flow control is completely disabled by a software over-ride. */
887 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
888 break;
889 case E1000_FC_RX_PAUSE:
890 /* RX Flow control is enabled and TX Flow control is disabled by a
891 * software over-ride. Since there really isn't a way to advertise
892 * that we are capable of RX Pause ONLY, we will advertise that we
893 * support both symmetric and asymmetric RX PAUSE. Later, we will
894 * disable the adapter's ability to send PAUSE frames.
895 */
896 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
897 break;
898 case E1000_FC_TX_PAUSE:
899 /* TX Flow control is enabled, and RX Flow control is disabled, by a
900 * software over-ride.
901 */
902 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
903 break;
904 case E1000_FC_FULL:
905 /* Flow control (both RX and TX) is enabled by a software over-ride. */
906 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
907 break;
908 default:
909 e_dbg("Flow control param set incorrectly\n");
910 return -E1000_ERR_CONFIG;
911 break;
912 }
913
914 /* Since auto-negotiation is enabled, take the link out of reset (the link
915 * will be in reset, because we previously reset the chip). This will
916 * restart auto-negotiation. If auto-negotiation is successful then the
917 * link-up status bit will be set and the flow control enable bits (RFCE
918 * and TFCE) will be set according to their negotiated value.
919 */
920 e_dbg("Auto-negotiation enabled\n");
921
922 ew32(TXCW, txcw);
923 ew32(CTRL, ctrl);
924 E1000_WRITE_FLUSH();
925
926 hw->txcw = txcw;
927 msleep(1);
928
929 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
930 * indication in the Device Status Register. Time-out if a link isn't
931 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
932 * less than 500 milliseconds even if the other end is doing it in SW).
933 * For internal serdes, we just assume a signal is present, then poll.
934 */
935 if (hw->media_type == e1000_media_type_internal_serdes ||
936 (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {
937 e_dbg("Looking for Link\n");
938 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
939 msleep(10);
940 status = er32(STATUS);
941 if (status & E1000_STATUS_LU)
942 break;
943 }
944 if (i == (LINK_UP_TIMEOUT / 10)) {
945 e_dbg("Never got a valid link from auto-neg!!!\n");
946 hw->autoneg_failed = 1;
947 /* AutoNeg failed to achieve a link, so we'll call
948 * e1000_check_for_link. This routine will force the link up if
949 * we detect a signal. This will allow us to communicate with
950 * non-autonegotiating link partners.
951 */
952 ret_val = e1000_check_for_link(hw);
953 if (ret_val) {
954 e_dbg("Error while checking for link\n");
955 return ret_val;
956 }
957 hw->autoneg_failed = 0;
958 } else {
959 hw->autoneg_failed = 0;
960 e_dbg("Valid Link Found\n");
961 }
962 } else {
963 e_dbg("No Signal Detected\n");
964 }
965 return E1000_SUCCESS;
966}
967
968/**
969 * e1000_copper_link_rtl_setup - Copper link setup for e1000_phy_rtl series.
970 * @hw: Struct containing variables accessed by shared code
971 *
972 * Commits changes to PHY configuration by calling e1000_phy_reset().
973 */
974static s32 e1000_copper_link_rtl_setup(struct e1000_hw *hw)
975{
976 s32 ret_val;
977
978 /* SW reset the PHY so all changes take effect */
979 ret_val = e1000_phy_reset(hw);
980 if (ret_val) {
981 e_dbg("Error Resetting the PHY\n");
982 return ret_val;
983 }
984
985 return E1000_SUCCESS;
986}
987
988static s32 gbe_dhg_phy_setup(struct e1000_hw *hw)
989{
990 s32 ret_val;
991 u32 ctrl_aux;
992
993 switch (hw->phy_type) {
994 case e1000_phy_8211:
995 ret_val = e1000_copper_link_rtl_setup(hw);
996 if (ret_val) {
997 e_dbg("e1000_copper_link_rtl_setup failed!\n");
998 return ret_val;
999 }
1000 break;
1001 case e1000_phy_8201:
1002 /* Set RMII mode */
1003 ctrl_aux = er32(CTL_AUX);
1004 ctrl_aux |= E1000_CTL_AUX_RMII;
1005 ew32(CTL_AUX, ctrl_aux);
1006 E1000_WRITE_FLUSH();
1007
1008 /* Disable the J/K bits required for receive */
1009 ctrl_aux = er32(CTL_AUX);
1010 ctrl_aux |= 0x4;
1011 ctrl_aux &= ~0x2;
1012 ew32(CTL_AUX, ctrl_aux);
1013 E1000_WRITE_FLUSH();
1014 ret_val = e1000_copper_link_rtl_setup(hw);
1015
1016 if (ret_val) {
1017 e_dbg("e1000_copper_link_rtl_setup failed!\n");
1018 return ret_val;
1019 }
1020 break;
1021 default:
1022 e_dbg("Error Resetting the PHY\n");
1023 return E1000_ERR_PHY_TYPE;
1024 }
1025
1026 return E1000_SUCCESS;
1027}
1028
1029/**
1030 * e1000_copper_link_preconfig - early configuration for copper
1031 * @hw: Struct containing variables accessed by shared code
1032 *
1033 * Make sure we have a valid PHY and change PHY mode before link setup.
1034 */
1035static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
1036{
1037 u32 ctrl;
1038 s32 ret_val;
1039 u16 phy_data;
1040
1041 e_dbg("e1000_copper_link_preconfig");
1042
1043 ctrl = er32(CTRL);
1044 /* With 82543, we need to force speed and duplex on the MAC equal to what
1045 * the PHY speed and duplex configuration is. In addition, we need to
1046 * perform a hardware reset on the PHY to take it out of reset.
1047 */
1048 if (hw->mac_type > e1000_82543) {
1049 ctrl |= E1000_CTRL_SLU;
1050 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1051 ew32(CTRL, ctrl);
1052 } else {
1053 ctrl |=
1054 (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1055 ew32(CTRL, ctrl);
1056 ret_val = e1000_phy_hw_reset(hw);
1057 if (ret_val)
1058 return ret_val;
1059 }
1060
1061 /* Make sure we have a valid PHY */
1062 ret_val = e1000_detect_gig_phy(hw);
1063 if (ret_val) {
1064 e_dbg("Error, did not detect valid phy.\n");
1065 return ret_val;
1066 }
1067 e_dbg("Phy ID = %x\n", hw->phy_id);
1068
1069 /* Set PHY to class A mode (if necessary) */
1070 ret_val = e1000_set_phy_mode(hw);
1071 if (ret_val)
1072 return ret_val;
1073
1074 if ((hw->mac_type == e1000_82545_rev_3) ||
1075 (hw->mac_type == e1000_82546_rev_3)) {
1076 ret_val =
1077 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1078 phy_data |= 0x00000008;
1079 ret_val =
1080 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1081 }
1082
1083 if (hw->mac_type <= e1000_82543 ||
1084 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1085 hw->mac_type == e1000_82541_rev_2
1086 || hw->mac_type == e1000_82547_rev_2)
1087 hw->phy_reset_disable = false;
1088
1089 return E1000_SUCCESS;
1090}
1091
1092/**
1093 * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series.
1094 * @hw: Struct containing variables accessed by shared code
1095 */
1096static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1097{
1098 u32 led_ctrl;
1099 s32 ret_val;
1100 u16 phy_data;
1101
1102 e_dbg("e1000_copper_link_igp_setup");
1103
1104 if (hw->phy_reset_disable)
1105 return E1000_SUCCESS;
1106
1107 ret_val = e1000_phy_reset(hw);
1108 if (ret_val) {
1109 e_dbg("Error Resetting the PHY\n");
1110 return ret_val;
1111 }
1112
1113 /* Wait 15ms for MAC to configure PHY from eeprom settings */
1114 msleep(15);
1115 /* Configure activity LED after PHY reset */
1116 led_ctrl = er32(LEDCTL);
1117 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1118 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1119 ew32(LEDCTL, led_ctrl);
1120
1121 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1122 if (hw->phy_type == e1000_phy_igp) {
1123 /* disable lplu d3 during driver init */
1124 ret_val = e1000_set_d3_lplu_state(hw, false);
1125 if (ret_val) {
1126 e_dbg("Error Disabling LPLU D3\n");
1127 return ret_val;
1128 }
1129 }
1130
1131 /* Configure mdi-mdix settings */
1132 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1133 if (ret_val)
1134 return ret_val;
1135
1136 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1137 hw->dsp_config_state = e1000_dsp_config_disabled;
1138 /* Force MDI for earlier revs of the IGP PHY */
1139 phy_data &=
1140 ~(IGP01E1000_PSCR_AUTO_MDIX |
1141 IGP01E1000_PSCR_FORCE_MDI_MDIX);
1142 hw->mdix = 1;
1143
1144 } else {
1145 hw->dsp_config_state = e1000_dsp_config_enabled;
1146 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1147
1148 switch (hw->mdix) {
1149 case 1:
1150 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1151 break;
1152 case 2:
1153 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1154 break;
1155 case 0:
1156 default:
1157 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1158 break;
1159 }
1160 }
1161 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1162 if (ret_val)
1163 return ret_val;
1164
1165 /* set auto-master slave resolution settings */
1166 if (hw->autoneg) {
1167 e1000_ms_type phy_ms_setting = hw->master_slave;
1168
1169 if (hw->ffe_config_state == e1000_ffe_config_active)
1170 hw->ffe_config_state = e1000_ffe_config_enabled;
1171
1172 if (hw->dsp_config_state == e1000_dsp_config_activated)
1173 hw->dsp_config_state = e1000_dsp_config_enabled;
1174
1175 /* when autonegotiation advertisement is only 1000Mbps then we
1176 * should disable SmartSpeed and enable Auto MasterSlave
1177 * resolution as hardware default. */
1178 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1179 /* Disable SmartSpeed */
1180 ret_val =
1181 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1182 &phy_data);
1183 if (ret_val)
1184 return ret_val;
1185 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1186 ret_val =
1187 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1188 phy_data);
1189 if (ret_val)
1190 return ret_val;
1191 /* Set auto Master/Slave resolution process */
1192 ret_val =
1193 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1194 if (ret_val)
1195 return ret_val;
1196 phy_data &= ~CR_1000T_MS_ENABLE;
1197 ret_val =
1198 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1199 if (ret_val)
1200 return ret_val;
1201 }
1202
1203 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1204 if (ret_val)
1205 return ret_val;
1206
1207 /* load defaults for future use */
1208 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1209 ((phy_data & CR_1000T_MS_VALUE) ?
1210 e1000_ms_force_master :
1211 e1000_ms_force_slave) : e1000_ms_auto;
1212
1213 switch (phy_ms_setting) {
1214 case e1000_ms_force_master:
1215 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1216 break;
1217 case e1000_ms_force_slave:
1218 phy_data |= CR_1000T_MS_ENABLE;
1219 phy_data &= ~(CR_1000T_MS_VALUE);
1220 break;
1221 case e1000_ms_auto:
1222 phy_data &= ~CR_1000T_MS_ENABLE;
1223 default:
1224 break;
1225 }
1226 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1227 if (ret_val)
1228 return ret_val;
1229 }
1230
1231 return E1000_SUCCESS;
1232}
1233
1234/**
1235 * e1000_copper_link_mgp_setup - Copper link setup for e1000_phy_m88 series.
1236 * @hw: Struct containing variables accessed by shared code
1237 */
1238static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1239{
1240 s32 ret_val;
1241 u16 phy_data;
1242
1243 e_dbg("e1000_copper_link_mgp_setup");
1244
1245 if (hw->phy_reset_disable)
1246 return E1000_SUCCESS;
1247
1248 /* Enable CRS on TX. This must be set for half-duplex operation. */
1249 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1250 if (ret_val)
1251 return ret_val;
1252
1253 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1254
1255 /* Options:
1256 * MDI/MDI-X = 0 (default)
1257 * 0 - Auto for all speeds
1258 * 1 - MDI mode
1259 * 2 - MDI-X mode
1260 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1261 */
1262 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1263
1264 switch (hw->mdix) {
1265 case 1:
1266 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1267 break;
1268 case 2:
1269 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1270 break;
1271 case 3:
1272 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1273 break;
1274 case 0:
1275 default:
1276 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1277 break;
1278 }
1279
1280 /* Options:
1281 * disable_polarity_correction = 0 (default)
1282 * Automatic Correction for Reversed Cable Polarity
1283 * 0 - Disabled
1284 * 1 - Enabled
1285 */
1286 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1287 if (hw->disable_polarity_correction == 1)
1288 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1289 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1290 if (ret_val)
1291 return ret_val;
1292
1293 if (hw->phy_revision < M88E1011_I_REV_4) {
1294 /* Force TX_CLK in the Extended PHY Specific Control Register
1295 * to 25MHz clock.
1296 */
1297 ret_val =
1298 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1299 &phy_data);
1300 if (ret_val)
1301 return ret_val;
1302
1303 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1304
1305 if ((hw->phy_revision == E1000_REVISION_2) &&
1306 (hw->phy_id == M88E1111_I_PHY_ID)) {
1307 /* Vidalia Phy, set the downshift counter to 5x */
1308 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1309 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1310 ret_val = e1000_write_phy_reg(hw,
1311 M88E1000_EXT_PHY_SPEC_CTRL,
1312 phy_data);
1313 if (ret_val)
1314 return ret_val;
1315 } else {
1316 /* Configure Master and Slave downshift values */
1317 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1318 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1319 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1320 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1321 ret_val = e1000_write_phy_reg(hw,
1322 M88E1000_EXT_PHY_SPEC_CTRL,
1323 phy_data);
1324 if (ret_val)
1325 return ret_val;
1326 }
1327 }
1328
1329 /* SW Reset the PHY so all changes take effect */
1330 ret_val = e1000_phy_reset(hw);
1331 if (ret_val) {
1332 e_dbg("Error Resetting the PHY\n");
1333 return ret_val;
1334 }
1335
1336 return E1000_SUCCESS;
1337}
1338
1339/**
1340 * e1000_copper_link_autoneg - setup auto-neg
1341 * @hw: Struct containing variables accessed by shared code
1342 *
1343 * Setup auto-negotiation and flow control advertisements,
1344 * and then perform auto-negotiation.
1345 */
1346static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1347{
1348 s32 ret_val;
1349 u16 phy_data;
1350
1351 e_dbg("e1000_copper_link_autoneg");
1352
1353 /* Perform some bounds checking on the hw->autoneg_advertised
1354 * parameter. If this variable is zero, then set it to the default.
1355 */
1356 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1357
1358 /* If autoneg_advertised is zero, we assume it was not defaulted
1359 * by the calling code so we set to advertise full capability.
1360 */
1361 if (hw->autoneg_advertised == 0)
1362 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1363
1364 /* IFE/RTL8201N PHY only supports 10/100 */
1365 if (hw->phy_type == e1000_phy_8201)
1366 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1367
1368 e_dbg("Reconfiguring auto-neg advertisement params\n");
1369 ret_val = e1000_phy_setup_autoneg(hw);
1370 if (ret_val) {
1371 e_dbg("Error Setting up Auto-Negotiation\n");
1372 return ret_val;
1373 }
1374 e_dbg("Restarting Auto-Neg\n");
1375
1376 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1377 * the Auto Neg Restart bit in the PHY control register.
1378 */
1379 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1380 if (ret_val)
1381 return ret_val;
1382
1383 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1384 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1385 if (ret_val)
1386 return ret_val;
1387
1388 /* Does the user want to wait for Auto-Neg to complete here, or
1389 * check at a later time (for example, callback routine).
1390 */
1391 if (hw->wait_autoneg_complete) {
1392 ret_val = e1000_wait_autoneg(hw);
1393 if (ret_val) {
1394 e_dbg
1395 ("Error while waiting for autoneg to complete\n");
1396 return ret_val;
1397 }
1398 }
1399
1400 hw->get_link_status = true;
1401
1402 return E1000_SUCCESS;
1403}
1404
1405/**
1406 * e1000_copper_link_postconfig - post link setup
1407 * @hw: Struct containing variables accessed by shared code
1408 *
1409 * Config the MAC and the PHY after link is up.
1410 * 1) Set up the MAC to the current PHY speed/duplex
1411 * if we are on 82543. If we
1412 * are on newer silicon, we only need to configure
1413 * collision distance in the Transmit Control Register.
1414 * 2) Set up flow control on the MAC to that established with
1415 * the link partner.
1416 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1417 */
1418static s32 e1000_copper_link_postconfig(struct e1000_hw *hw)
1419{
1420 s32 ret_val;
1421 e_dbg("e1000_copper_link_postconfig");
1422
1423 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100)) {
1424 e1000_config_collision_dist(hw);
1425 } else {
1426 ret_val = e1000_config_mac_to_phy(hw);
1427 if (ret_val) {
1428 e_dbg("Error configuring MAC to PHY settings\n");
1429 return ret_val;
1430 }
1431 }
1432 ret_val = e1000_config_fc_after_link_up(hw);
1433 if (ret_val) {
1434 e_dbg("Error Configuring Flow Control\n");
1435 return ret_val;
1436 }
1437
1438 /* Config DSP to improve Giga link quality */
1439 if (hw->phy_type == e1000_phy_igp) {
1440 ret_val = e1000_config_dsp_after_link_change(hw, true);
1441 if (ret_val) {
1442 e_dbg("Error Configuring DSP after link up\n");
1443 return ret_val;
1444 }
1445 }
1446
1447 return E1000_SUCCESS;
1448}
1449
1450/**
1451 * e1000_setup_copper_link - phy/speed/duplex setting
1452 * @hw: Struct containing variables accessed by shared code
1453 *
1454 * Detects which PHY is present and sets up the speed and duplex
1455 */
1456static s32 e1000_setup_copper_link(struct e1000_hw *hw)
1457{
1458 s32 ret_val;
1459 u16 i;
1460 u16 phy_data;
1461
1462 e_dbg("e1000_setup_copper_link");
1463
1464 /* Check if it is a valid PHY and set PHY mode if necessary. */
1465 ret_val = e1000_copper_link_preconfig(hw);
1466 if (ret_val)
1467 return ret_val;
1468
1469 if (hw->phy_type == e1000_phy_igp) {
1470 ret_val = e1000_copper_link_igp_setup(hw);
1471 if (ret_val)
1472 return ret_val;
1473 } else if (hw->phy_type == e1000_phy_m88) {
1474 ret_val = e1000_copper_link_mgp_setup(hw);
1475 if (ret_val)
1476 return ret_val;
1477 } else {
1478 ret_val = gbe_dhg_phy_setup(hw);
1479 if (ret_val) {
1480 e_dbg("gbe_dhg_phy_setup failed!\n");
1481 return ret_val;
1482 }
1483 }
1484
1485 if (hw->autoneg) {
1486 /* Setup autoneg and flow control advertisement
1487 * and perform autonegotiation */
1488 ret_val = e1000_copper_link_autoneg(hw);
1489 if (ret_val)
1490 return ret_val;
1491 } else {
1492 /* PHY will be set to 10H, 10F, 100H,or 100F
1493 * depending on value from forced_speed_duplex. */
1494 e_dbg("Forcing speed and duplex\n");
1495 ret_val = e1000_phy_force_speed_duplex(hw);
1496 if (ret_val) {
1497 e_dbg("Error Forcing Speed and Duplex\n");
1498 return ret_val;
1499 }
1500 }
1501
1502 /* Check link status. Wait up to 100 microseconds for link to become
1503 * valid.
1504 */
1505 for (i = 0; i < 10; i++) {
1506 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1507 if (ret_val)
1508 return ret_val;
1509 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1510 if (ret_val)
1511 return ret_val;
1512
1513 if (phy_data & MII_SR_LINK_STATUS) {
1514 /* Config the MAC and PHY after link is up */
1515 ret_val = e1000_copper_link_postconfig(hw);
1516 if (ret_val)
1517 return ret_val;
1518
1519 e_dbg("Valid link established!!!\n");
1520 return E1000_SUCCESS;
1521 }
1522 udelay(10);
1523 }
1524
1525 e_dbg("Unable to establish link!!!\n");
1526 return E1000_SUCCESS;
1527}
1528
1529/**
1530 * e1000_phy_setup_autoneg - phy settings
1531 * @hw: Struct containing variables accessed by shared code
1532 *
1533 * Configures PHY autoneg and flow control advertisement settings
1534 */
1535s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1536{
1537 s32 ret_val;
1538 u16 mii_autoneg_adv_reg;
1539 u16 mii_1000t_ctrl_reg;
1540
1541 e_dbg("e1000_phy_setup_autoneg");
1542
1543 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1544 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1545 if (ret_val)
1546 return ret_val;
1547
1548 /* Read the MII 1000Base-T Control Register (Address 9). */
1549 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1550 if (ret_val)
1551 return ret_val;
1552 else if (hw->phy_type == e1000_phy_8201)
1553 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1554
1555 /* Need to parse both autoneg_advertised and fc and set up
1556 * the appropriate PHY registers. First we will parse for
1557 * autoneg_advertised software override. Since we can advertise
1558 * a plethora of combinations, we need to check each bit
1559 * individually.
1560 */
1561
1562 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1563 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1564 * the 1000Base-T Control Register (Address 9).
1565 */
1566 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1567 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1568
1569 e_dbg("autoneg_advertised %x\n", hw->autoneg_advertised);
1570
1571 /* Do we want to advertise 10 Mb Half Duplex? */
1572 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
1573 e_dbg("Advertise 10mb Half duplex\n");
1574 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1575 }
1576
1577 /* Do we want to advertise 10 Mb Full Duplex? */
1578 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
1579 e_dbg("Advertise 10mb Full duplex\n");
1580 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1581 }
1582
1583 /* Do we want to advertise 100 Mb Half Duplex? */
1584 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
1585 e_dbg("Advertise 100mb Half duplex\n");
1586 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1587 }
1588
1589 /* Do we want to advertise 100 Mb Full Duplex? */
1590 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
1591 e_dbg("Advertise 100mb Full duplex\n");
1592 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1593 }
1594
1595 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1596 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1597 e_dbg
1598 ("Advertise 1000mb Half duplex requested, request denied!\n");
1599 }
1600
1601 /* Do we want to advertise 1000 Mb Full Duplex? */
1602 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1603 e_dbg("Advertise 1000mb Full duplex\n");
1604 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1605 }
1606
1607 /* Check for a software override of the flow control settings, and
1608 * setup the PHY advertisement registers accordingly. If
1609 * auto-negotiation is enabled, then software will have to set the
1610 * "PAUSE" bits to the correct value in the Auto-Negotiation
1611 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1612 *
1613 * The possible values of the "fc" parameter are:
1614 * 0: Flow control is completely disabled
1615 * 1: Rx flow control is enabled (we can receive pause frames
1616 * but not send pause frames).
1617 * 2: Tx flow control is enabled (we can send pause frames
1618 * but we do not support receiving pause frames).
1619 * 3: Both Rx and TX flow control (symmetric) are enabled.
1620 * other: No software override. The flow control configuration
1621 * in the EEPROM is used.
1622 */
1623 switch (hw->fc) {
1624 case E1000_FC_NONE: /* 0 */
1625 /* Flow control (RX & TX) is completely disabled by a
1626 * software over-ride.
1627 */
1628 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1629 break;
1630 case E1000_FC_RX_PAUSE: /* 1 */
1631 /* RX Flow control is enabled, and TX Flow control is
1632 * disabled, by a software over-ride.
1633 */
1634 /* Since there really isn't a way to advertise that we are
1635 * capable of RX Pause ONLY, we will advertise that we
1636 * support both symmetric and asymmetric RX PAUSE. Later
1637 * (in e1000_config_fc_after_link_up) we will disable the
1638 *hw's ability to send PAUSE frames.
1639 */
1640 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1641 break;
1642 case E1000_FC_TX_PAUSE: /* 2 */
1643 /* TX Flow control is enabled, and RX Flow control is
1644 * disabled, by a software over-ride.
1645 */
1646 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1647 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1648 break;
1649 case E1000_FC_FULL: /* 3 */
1650 /* Flow control (both RX and TX) is enabled by a software
1651 * over-ride.
1652 */
1653 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1654 break;
1655 default:
1656 e_dbg("Flow control param set incorrectly\n");
1657 return -E1000_ERR_CONFIG;
1658 }
1659
1660 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1661 if (ret_val)
1662 return ret_val;
1663
1664 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1665
1666 if (hw->phy_type == e1000_phy_8201) {
1667 mii_1000t_ctrl_reg = 0;
1668 } else {
1669 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1670 mii_1000t_ctrl_reg);
1671 if (ret_val)
1672 return ret_val;
1673 }
1674
1675 return E1000_SUCCESS;
1676}
1677
1678/**
1679 * e1000_phy_force_speed_duplex - force link settings
1680 * @hw: Struct containing variables accessed by shared code
1681 *
1682 * Force PHY speed and duplex settings to hw->forced_speed_duplex
1683 */
1684static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1685{
1686 u32 ctrl;
1687 s32 ret_val;
1688 u16 mii_ctrl_reg;
1689 u16 mii_status_reg;
1690 u16 phy_data;
1691 u16 i;
1692
1693 e_dbg("e1000_phy_force_speed_duplex");
1694
1695 /* Turn off Flow control if we are forcing speed and duplex. */
1696 hw->fc = E1000_FC_NONE;
1697
1698 e_dbg("hw->fc = %d\n", hw->fc);
1699
1700 /* Read the Device Control Register. */
1701 ctrl = er32(CTRL);
1702
1703 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1704 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1705 ctrl &= ~(DEVICE_SPEED_MASK);
1706
1707 /* Clear the Auto Speed Detect Enable bit. */
1708 ctrl &= ~E1000_CTRL_ASDE;
1709
1710 /* Read the MII Control Register. */
1711 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
1712 if (ret_val)
1713 return ret_val;
1714
1715 /* We need to disable autoneg in order to force link and duplex. */
1716
1717 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
1718
1719 /* Are we forcing Full or Half Duplex? */
1720 if (hw->forced_speed_duplex == e1000_100_full ||
1721 hw->forced_speed_duplex == e1000_10_full) {
1722 /* We want to force full duplex so we SET the full duplex bits in the
1723 * Device and MII Control Registers.
1724 */
1725 ctrl |= E1000_CTRL_FD;
1726 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
1727 e_dbg("Full Duplex\n");
1728 } else {
1729 /* We want to force half duplex so we CLEAR the full duplex bits in
1730 * the Device and MII Control Registers.
1731 */
1732 ctrl &= ~E1000_CTRL_FD;
1733 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
1734 e_dbg("Half Duplex\n");
1735 }
1736
1737 /* Are we forcing 100Mbps??? */
1738 if (hw->forced_speed_duplex == e1000_100_full ||
1739 hw->forced_speed_duplex == e1000_100_half) {
1740 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
1741 ctrl |= E1000_CTRL_SPD_100;
1742 mii_ctrl_reg |= MII_CR_SPEED_100;
1743 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1744 e_dbg("Forcing 100mb ");
1745 } else {
1746 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
1747 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1748 mii_ctrl_reg |= MII_CR_SPEED_10;
1749 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1750 e_dbg("Forcing 10mb ");
1751 }
1752
1753 e1000_config_collision_dist(hw);
1754
1755 /* Write the configured values back to the Device Control Reg. */
1756 ew32(CTRL, ctrl);
1757
1758 if (hw->phy_type == e1000_phy_m88) {
1759 ret_val =
1760 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1761 if (ret_val)
1762 return ret_val;
1763
1764 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1765 * forced whenever speed are duplex are forced.
1766 */
1767 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1768 ret_val =
1769 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1770 if (ret_val)
1771 return ret_val;
1772
1773 e_dbg("M88E1000 PSCR: %x\n", phy_data);
1774
1775 /* Need to reset the PHY or these changes will be ignored */
1776 mii_ctrl_reg |= MII_CR_RESET;
1777
1778 /* Disable MDI-X support for 10/100 */
1779 } else {
1780 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1781 * forced whenever speed or duplex are forced.
1782 */
1783 ret_val =
1784 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1785 if (ret_val)
1786 return ret_val;
1787
1788 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1789 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1790
1791 ret_val =
1792 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1793 if (ret_val)
1794 return ret_val;
1795 }
1796
1797 /* Write back the modified PHY MII control register. */
1798 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
1799 if (ret_val)
1800 return ret_val;
1801
1802 udelay(1);
1803
1804 /* The wait_autoneg_complete flag may be a little misleading here.
1805 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
1806 * But we do want to delay for a period while forcing only so we
1807 * don't generate false No Link messages. So we will wait here
1808 * only if the user has set wait_autoneg_complete to 1, which is
1809 * the default.
1810 */
1811 if (hw->wait_autoneg_complete) {
1812 /* We will wait for autoneg to complete. */
1813 e_dbg("Waiting for forced speed/duplex link.\n");
1814 mii_status_reg = 0;
1815
1816 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
1817 for (i = PHY_FORCE_TIME; i > 0; i--) {
1818 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1819 * to be set.
1820 */
1821 ret_val =
1822 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1823 if (ret_val)
1824 return ret_val;
1825
1826 ret_val =
1827 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1828 if (ret_val)
1829 return ret_val;
1830
1831 if (mii_status_reg & MII_SR_LINK_STATUS)
1832 break;
1833 msleep(100);
1834 }
1835 if ((i == 0) && (hw->phy_type == e1000_phy_m88)) {
1836 /* We didn't get link. Reset the DSP and wait again for link. */
1837 ret_val = e1000_phy_reset_dsp(hw);
1838 if (ret_val) {
1839 e_dbg("Error Resetting PHY DSP\n");
1840 return ret_val;
1841 }
1842 }
1843 /* This loop will early-out if the link condition has been met. */
1844 for (i = PHY_FORCE_TIME; i > 0; i--) {
1845 if (mii_status_reg & MII_SR_LINK_STATUS)
1846 break;
1847 msleep(100);
1848 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1849 * to be set.
1850 */
1851 ret_val =
1852 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1853 if (ret_val)
1854 return ret_val;
1855
1856 ret_val =
1857 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1858 if (ret_val)
1859 return ret_val;
1860 }
1861 }
1862
1863 if (hw->phy_type == e1000_phy_m88) {
1864 /* Because we reset the PHY above, we need to re-force TX_CLK in the
1865 * Extended PHY Specific Control Register to 25MHz clock. This value
1866 * defaults back to a 2.5MHz clock when the PHY is reset.
1867 */
1868 ret_val =
1869 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1870 &phy_data);
1871 if (ret_val)
1872 return ret_val;
1873
1874 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1875 ret_val =
1876 e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1877 phy_data);
1878 if (ret_val)
1879 return ret_val;
1880
1881 /* In addition, because of the s/w reset above, we need to enable CRS on
1882 * TX. This must be set for both full and half duplex operation.
1883 */
1884 ret_val =
1885 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1886 if (ret_val)
1887 return ret_val;
1888
1889 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1890 ret_val =
1891 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1892 if (ret_val)
1893 return ret_val;
1894
1895 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543)
1896 && (!hw->autoneg)
1897 && (hw->forced_speed_duplex == e1000_10_full
1898 || hw->forced_speed_duplex == e1000_10_half)) {
1899 ret_val = e1000_polarity_reversal_workaround(hw);
1900 if (ret_val)
1901 return ret_val;
1902 }
1903 }
1904 return E1000_SUCCESS;
1905}
1906
1907/**
1908 * e1000_config_collision_dist - set collision distance register
1909 * @hw: Struct containing variables accessed by shared code
1910 *
1911 * Sets the collision distance in the Transmit Control register.
1912 * Link should have been established previously. Reads the speed and duplex
1913 * information from the Device Status register.
1914 */
1915void e1000_config_collision_dist(struct e1000_hw *hw)
1916{
1917 u32 tctl, coll_dist;
1918
1919 e_dbg("e1000_config_collision_dist");
1920
1921 if (hw->mac_type < e1000_82543)
1922 coll_dist = E1000_COLLISION_DISTANCE_82542;
1923 else
1924 coll_dist = E1000_COLLISION_DISTANCE;
1925
1926 tctl = er32(TCTL);
1927
1928 tctl &= ~E1000_TCTL_COLD;
1929 tctl |= coll_dist << E1000_COLD_SHIFT;
1930
1931 ew32(TCTL, tctl);
1932 E1000_WRITE_FLUSH();
1933}
1934
1935/**
1936 * e1000_config_mac_to_phy - sync phy and mac settings
1937 * @hw: Struct containing variables accessed by shared code
1938 * @mii_reg: data to write to the MII control register
1939 *
1940 * Sets MAC speed and duplex settings to reflect the those in the PHY
1941 * The contents of the PHY register containing the needed information need to
1942 * be passed in.
1943 */
1944static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
1945{
1946 u32 ctrl;
1947 s32 ret_val;
1948 u16 phy_data;
1949
1950 e_dbg("e1000_config_mac_to_phy");
1951
1952 /* 82544 or newer MAC, Auto Speed Detection takes care of
1953 * MAC speed/duplex configuration.*/
1954 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100))
1955 return E1000_SUCCESS;
1956
1957 /* Read the Device Control Register and set the bits to Force Speed
1958 * and Duplex.
1959 */
1960 ctrl = er32(CTRL);
1961 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1962 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1963
1964 switch (hw->phy_type) {
1965 case e1000_phy_8201:
1966 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1967 if (ret_val)
1968 return ret_val;
1969
1970 if (phy_data & RTL_PHY_CTRL_FD)
1971 ctrl |= E1000_CTRL_FD;
1972 else
1973 ctrl &= ~E1000_CTRL_FD;
1974
1975 if (phy_data & RTL_PHY_CTRL_SPD_100)
1976 ctrl |= E1000_CTRL_SPD_100;
1977 else
1978 ctrl |= E1000_CTRL_SPD_10;
1979
1980 e1000_config_collision_dist(hw);
1981 break;
1982 default:
1983 /* Set up duplex in the Device Control and Transmit Control
1984 * registers depending on negotiated values.
1985 */
1986 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1987 &phy_data);
1988 if (ret_val)
1989 return ret_val;
1990
1991 if (phy_data & M88E1000_PSSR_DPLX)
1992 ctrl |= E1000_CTRL_FD;
1993 else
1994 ctrl &= ~E1000_CTRL_FD;
1995
1996 e1000_config_collision_dist(hw);
1997
1998 /* Set up speed in the Device Control register depending on
1999 * negotiated values.
2000 */
2001 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2002 ctrl |= E1000_CTRL_SPD_1000;
2003 else if ((phy_data & M88E1000_PSSR_SPEED) ==
2004 M88E1000_PSSR_100MBS)
2005 ctrl |= E1000_CTRL_SPD_100;
2006 }
2007
2008 /* Write the configured values back to the Device Control Reg. */
2009 ew32(CTRL, ctrl);
2010 return E1000_SUCCESS;
2011}
2012
2013/**
2014 * e1000_force_mac_fc - force flow control settings
2015 * @hw: Struct containing variables accessed by shared code
2016 *
2017 * Forces the MAC's flow control settings.
2018 * Sets the TFCE and RFCE bits in the device control register to reflect
2019 * the adapter settings. TFCE and RFCE need to be explicitly set by
2020 * software when a Copper PHY is used because autonegotiation is managed
2021 * by the PHY rather than the MAC. Software must also configure these
2022 * bits when link is forced on a fiber connection.
2023 */
2024s32 e1000_force_mac_fc(struct e1000_hw *hw)
2025{
2026 u32 ctrl;
2027
2028 e_dbg("e1000_force_mac_fc");
2029
2030 /* Get the current configuration of the Device Control Register */
2031 ctrl = er32(CTRL);
2032
2033 /* Because we didn't get link via the internal auto-negotiation
2034 * mechanism (we either forced link or we got link via PHY
2035 * auto-neg), we have to manually enable/disable transmit an
2036 * receive flow control.
2037 *
2038 * The "Case" statement below enables/disable flow control
2039 * according to the "hw->fc" parameter.
2040 *
2041 * The possible values of the "fc" parameter are:
2042 * 0: Flow control is completely disabled
2043 * 1: Rx flow control is enabled (we can receive pause
2044 * frames but not send pause frames).
2045 * 2: Tx flow control is enabled (we can send pause frames
2046 * frames but we do not receive pause frames).
2047 * 3: Both Rx and TX flow control (symmetric) is enabled.
2048 * other: No other values should be possible at this point.
2049 */
2050
2051 switch (hw->fc) {
2052 case E1000_FC_NONE:
2053 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2054 break;
2055 case E1000_FC_RX_PAUSE:
2056 ctrl &= (~E1000_CTRL_TFCE);
2057 ctrl |= E1000_CTRL_RFCE;
2058 break;
2059 case E1000_FC_TX_PAUSE:
2060 ctrl &= (~E1000_CTRL_RFCE);
2061 ctrl |= E1000_CTRL_TFCE;
2062 break;
2063 case E1000_FC_FULL:
2064 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2065 break;
2066 default:
2067 e_dbg("Flow control param set incorrectly\n");
2068 return -E1000_ERR_CONFIG;
2069 }
2070
2071 /* Disable TX Flow Control for 82542 (rev 2.0) */
2072 if (hw->mac_type == e1000_82542_rev2_0)
2073 ctrl &= (~E1000_CTRL_TFCE);
2074
2075 ew32(CTRL, ctrl);
2076 return E1000_SUCCESS;
2077}
2078
2079/**
2080 * e1000_config_fc_after_link_up - configure flow control after autoneg
2081 * @hw: Struct containing variables accessed by shared code
2082 *
2083 * Configures flow control settings after link is established
2084 * Should be called immediately after a valid link has been established.
2085 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2086 * and autonegotiation is enabled, the MAC flow control settings will be set
2087 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2088 * and RFCE bits will be automatically set to the negotiated flow control mode.
2089 */
2090static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2091{
2092 s32 ret_val;
2093 u16 mii_status_reg;
2094 u16 mii_nway_adv_reg;
2095 u16 mii_nway_lp_ability_reg;
2096 u16 speed;
2097 u16 duplex;
2098
2099 e_dbg("e1000_config_fc_after_link_up");
2100
2101 /* Check for the case where we have fiber media and auto-neg failed
2102 * so we had to force link. In this case, we need to force the
2103 * configuration of the MAC to match the "fc" parameter.
2104 */
2105 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
2106 || ((hw->media_type == e1000_media_type_internal_serdes)
2107 && (hw->autoneg_failed))
2108 || ((hw->media_type == e1000_media_type_copper)
2109 && (!hw->autoneg))) {
2110 ret_val = e1000_force_mac_fc(hw);
2111 if (ret_val) {
2112 e_dbg("Error forcing flow control settings\n");
2113 return ret_val;
2114 }
2115 }
2116
2117 /* Check for the case where we have copper media and auto-neg is
2118 * enabled. In this case, we need to check and see if Auto-Neg
2119 * has completed, and if so, how the PHY and link partner has
2120 * flow control configured.
2121 */
2122 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2123 /* Read the MII Status Register and check to see if AutoNeg
2124 * has completed. We read this twice because this reg has
2125 * some "sticky" (latched) bits.
2126 */
2127 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2128 if (ret_val)
2129 return ret_val;
2130 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2131 if (ret_val)
2132 return ret_val;
2133
2134 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2135 /* The AutoNeg process has completed, so we now need to
2136 * read both the Auto Negotiation Advertisement Register
2137 * (Address 4) and the Auto_Negotiation Base Page Ability
2138 * Register (Address 5) to determine how flow control was
2139 * negotiated.
2140 */
2141 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2142 &mii_nway_adv_reg);
2143 if (ret_val)
2144 return ret_val;
2145 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2146 &mii_nway_lp_ability_reg);
2147 if (ret_val)
2148 return ret_val;
2149
2150 /* Two bits in the Auto Negotiation Advertisement Register
2151 * (Address 4) and two bits in the Auto Negotiation Base
2152 * Page Ability Register (Address 5) determine flow control
2153 * for both the PHY and the link partner. The following
2154 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2155 * 1999, describes these PAUSE resolution bits and how flow
2156 * control is determined based upon these settings.
2157 * NOTE: DC = Don't Care
2158 *
2159 * LOCAL DEVICE | LINK PARTNER
2160 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2161 *-------|---------|-------|---------|--------------------
2162 * 0 | 0 | DC | DC | E1000_FC_NONE
2163 * 0 | 1 | 0 | DC | E1000_FC_NONE
2164 * 0 | 1 | 1 | 0 | E1000_FC_NONE
2165 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2166 * 1 | 0 | 0 | DC | E1000_FC_NONE
2167 * 1 | DC | 1 | DC | E1000_FC_FULL
2168 * 1 | 1 | 0 | 0 | E1000_FC_NONE
2169 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2170 *
2171 */
2172 /* Are both PAUSE bits set to 1? If so, this implies
2173 * Symmetric Flow Control is enabled at both ends. The
2174 * ASM_DIR bits are irrelevant per the spec.
2175 *
2176 * For Symmetric Flow Control:
2177 *
2178 * LOCAL DEVICE | LINK PARTNER
2179 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2180 *-------|---------|-------|---------|--------------------
2181 * 1 | DC | 1 | DC | E1000_FC_FULL
2182 *
2183 */
2184 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2185 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2186 /* Now we need to check if the user selected RX ONLY
2187 * of pause frames. In this case, we had to advertise
2188 * FULL flow control because we could not advertise RX
2189 * ONLY. Hence, we must now check to see if we need to
2190 * turn OFF the TRANSMISSION of PAUSE frames.
2191 */
2192 if (hw->original_fc == E1000_FC_FULL) {
2193 hw->fc = E1000_FC_FULL;
2194 e_dbg("Flow Control = FULL.\n");
2195 } else {
2196 hw->fc = E1000_FC_RX_PAUSE;
2197 e_dbg
2198 ("Flow Control = RX PAUSE frames only.\n");
2199 }
2200 }
2201 /* For receiving PAUSE frames ONLY.
2202 *
2203 * LOCAL DEVICE | LINK PARTNER
2204 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2205 *-------|---------|-------|---------|--------------------
2206 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2207 *
2208 */
2209 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2210 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2211 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2212 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
2213 {
2214 hw->fc = E1000_FC_TX_PAUSE;
2215 e_dbg
2216 ("Flow Control = TX PAUSE frames only.\n");
2217 }
2218 /* For transmitting PAUSE frames ONLY.
2219 *
2220 * LOCAL DEVICE | LINK PARTNER
2221 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2222 *-------|---------|-------|---------|--------------------
2223 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2224 *
2225 */
2226 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2227 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2228 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2229 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
2230 {
2231 hw->fc = E1000_FC_RX_PAUSE;
2232 e_dbg
2233 ("Flow Control = RX PAUSE frames only.\n");
2234 }
2235 /* Per the IEEE spec, at this point flow control should be
2236 * disabled. However, we want to consider that we could
2237 * be connected to a legacy switch that doesn't advertise
2238 * desired flow control, but can be forced on the link
2239 * partner. So if we advertised no flow control, that is
2240 * what we will resolve to. If we advertised some kind of
2241 * receive capability (Rx Pause Only or Full Flow Control)
2242 * and the link partner advertised none, we will configure
2243 * ourselves to enable Rx Flow Control only. We can do
2244 * this safely for two reasons: If the link partner really
2245 * didn't want flow control enabled, and we enable Rx, no
2246 * harm done since we won't be receiving any PAUSE frames
2247 * anyway. If the intent on the link partner was to have
2248 * flow control enabled, then by us enabling RX only, we
2249 * can at least receive pause frames and process them.
2250 * This is a good idea because in most cases, since we are
2251 * predominantly a server NIC, more times than not we will
2252 * be asked to delay transmission of packets than asking
2253 * our link partner to pause transmission of frames.
2254 */
2255 else if ((hw->original_fc == E1000_FC_NONE ||
2256 hw->original_fc == E1000_FC_TX_PAUSE) ||
2257 hw->fc_strict_ieee) {
2258 hw->fc = E1000_FC_NONE;
2259 e_dbg("Flow Control = NONE.\n");
2260 } else {
2261 hw->fc = E1000_FC_RX_PAUSE;
2262 e_dbg
2263 ("Flow Control = RX PAUSE frames only.\n");
2264 }
2265
2266 /* Now we need to do one last check... If we auto-
2267 * negotiated to HALF DUPLEX, flow control should not be
2268 * enabled per IEEE 802.3 spec.
2269 */
2270 ret_val =
2271 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2272 if (ret_val) {
2273 e_dbg
2274 ("Error getting link speed and duplex\n");
2275 return ret_val;
2276 }
2277
2278 if (duplex == HALF_DUPLEX)
2279 hw->fc = E1000_FC_NONE;
2280
2281 /* Now we call a subroutine to actually force the MAC
2282 * controller to use the correct flow control settings.
2283 */
2284 ret_val = e1000_force_mac_fc(hw);
2285 if (ret_val) {
2286 e_dbg
2287 ("Error forcing flow control settings\n");
2288 return ret_val;
2289 }
2290 } else {
2291 e_dbg
2292 ("Copper PHY and Auto Neg has not completed.\n");
2293 }
2294 }
2295 return E1000_SUCCESS;
2296}
2297
2298/**
2299 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
2300 * @hw: pointer to the HW structure
2301 *
2302 * Checks for link up on the hardware. If link is not up and we have
2303 * a signal, then we need to force link up.
2304 */
2305static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
2306{
2307 u32 rxcw;
2308 u32 ctrl;
2309 u32 status;
2310 s32 ret_val = E1000_SUCCESS;
2311
2312 e_dbg("e1000_check_for_serdes_link_generic");
2313
2314 ctrl = er32(CTRL);
2315 status = er32(STATUS);
2316 rxcw = er32(RXCW);
2317
2318 /*
2319 * If we don't have link (auto-negotiation failed or link partner
2320 * cannot auto-negotiate), and our link partner is not trying to
2321 * auto-negotiate with us (we are receiving idles or data),
2322 * we need to force link up. We also need to give auto-negotiation
2323 * time to complete.
2324 */
2325 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
2326 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
2327 if (hw->autoneg_failed == 0) {
2328 hw->autoneg_failed = 1;
2329 goto out;
2330 }
2331 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
2332
2333 /* Disable auto-negotiation in the TXCW register */
2334 ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2335
2336 /* Force link-up and also force full-duplex. */
2337 ctrl = er32(CTRL);
2338 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2339 ew32(CTRL, ctrl);
2340
2341 /* Configure Flow Control after forcing link up. */
2342 ret_val = e1000_config_fc_after_link_up(hw);
2343 if (ret_val) {
2344 e_dbg("Error configuring flow control\n");
2345 goto out;
2346 }
2347 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2348 /*
2349 * If we are forcing link and we are receiving /C/ ordered
2350 * sets, re-enable auto-negotiation in the TXCW register
2351 * and disable forced link in the Device Control register
2352 * in an attempt to auto-negotiate with our link partner.
2353 */
2354 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
2355 ew32(TXCW, hw->txcw);
2356 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
2357
2358 hw->serdes_has_link = true;
2359 } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
2360 /*
2361 * If we force link for non-auto-negotiation switch, check
2362 * link status based on MAC synchronization for internal
2363 * serdes media type.
2364 */
2365 /* SYNCH bit and IV bit are sticky. */
2366 udelay(10);
2367 rxcw = er32(RXCW);
2368 if (rxcw & E1000_RXCW_SYNCH) {
2369 if (!(rxcw & E1000_RXCW_IV)) {
2370 hw->serdes_has_link = true;
2371 e_dbg("SERDES: Link up - forced.\n");
2372 }
2373 } else {
2374 hw->serdes_has_link = false;
2375 e_dbg("SERDES: Link down - force failed.\n");
2376 }
2377 }
2378
2379 if (E1000_TXCW_ANE & er32(TXCW)) {
2380 status = er32(STATUS);
2381 if (status & E1000_STATUS_LU) {
2382 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
2383 udelay(10);
2384 rxcw = er32(RXCW);
2385 if (rxcw & E1000_RXCW_SYNCH) {
2386 if (!(rxcw & E1000_RXCW_IV)) {
2387 hw->serdes_has_link = true;
2388 e_dbg("SERDES: Link up - autoneg "
2389 "completed successfully.\n");
2390 } else {
2391 hw->serdes_has_link = false;
2392 e_dbg("SERDES: Link down - invalid"
2393 "codewords detected in autoneg.\n");
2394 }
2395 } else {
2396 hw->serdes_has_link = false;
2397 e_dbg("SERDES: Link down - no sync.\n");
2398 }
2399 } else {
2400 hw->serdes_has_link = false;
2401 e_dbg("SERDES: Link down - autoneg failed\n");
2402 }
2403 }
2404
2405 out:
2406 return ret_val;
2407}
2408
2409/**
2410 * e1000_check_for_link
2411 * @hw: Struct containing variables accessed by shared code
2412 *
2413 * Checks to see if the link status of the hardware has changed.
2414 * Called by any function that needs to check the link status of the adapter.
2415 */
2416s32 e1000_check_for_link(struct e1000_hw *hw)
2417{
2418 u32 rxcw = 0;
2419 u32 ctrl;
2420 u32 status;
2421 u32 rctl;
2422 u32 icr;
2423 u32 signal = 0;
2424 s32 ret_val;
2425 u16 phy_data;
2426
2427 e_dbg("e1000_check_for_link");
2428
2429 ctrl = er32(CTRL);
2430 status = er32(STATUS);
2431
2432 /* On adapters with a MAC newer than 82544, SW Definable pin 1 will be
2433 * set when the optics detect a signal. On older adapters, it will be
2434 * cleared when there is a signal. This applies to fiber media only.
2435 */
2436 if ((hw->media_type == e1000_media_type_fiber) ||
2437 (hw->media_type == e1000_media_type_internal_serdes)) {
2438 rxcw = er32(RXCW);
2439
2440 if (hw->media_type == e1000_media_type_fiber) {
2441 signal =
2442 (hw->mac_type >
2443 e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2444 if (status & E1000_STATUS_LU)
2445 hw->get_link_status = false;
2446 }
2447 }
2448
2449 /* If we have a copper PHY then we only want to go out to the PHY
2450 * registers to see if Auto-Neg has completed and/or if our link
2451 * status has changed. The get_link_status flag will be set if we
2452 * receive a Link Status Change interrupt or we have Rx Sequence
2453 * Errors.
2454 */
2455 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2456 /* First we want to see if the MII Status Register reports
2457 * link. If so, then we want to get the current speed/duplex
2458 * of the PHY.
2459 * Read the register twice since the link bit is sticky.
2460 */
2461 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2462 if (ret_val)
2463 return ret_val;
2464 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2465 if (ret_val)
2466 return ret_val;
2467
2468 if (phy_data & MII_SR_LINK_STATUS) {
2469 hw->get_link_status = false;
2470 /* Check if there was DownShift, must be checked immediately after
2471 * link-up */
2472 e1000_check_downshift(hw);
2473
2474 /* If we are on 82544 or 82543 silicon and speed/duplex
2475 * are forced to 10H or 10F, then we will implement the polarity
2476 * reversal workaround. We disable interrupts first, and upon
2477 * returning, place the devices interrupt state to its previous
2478 * value except for the link status change interrupt which will
2479 * happen due to the execution of this workaround.
2480 */
2481
2482 if ((hw->mac_type == e1000_82544
2483 || hw->mac_type == e1000_82543) && (!hw->autoneg)
2484 && (hw->forced_speed_duplex == e1000_10_full
2485 || hw->forced_speed_duplex == e1000_10_half)) {
2486 ew32(IMC, 0xffffffff);
2487 ret_val =
2488 e1000_polarity_reversal_workaround(hw);
2489 icr = er32(ICR);
2490 ew32(ICS, (icr & ~E1000_ICS_LSC));
2491 ew32(IMS, IMS_ENABLE_MASK);
2492 }
2493
2494 } else {
2495 /* No link detected */
2496 e1000_config_dsp_after_link_change(hw, false);
2497 return 0;
2498 }
2499
2500 /* If we are forcing speed/duplex, then we simply return since
2501 * we have already determined whether we have link or not.
2502 */
2503 if (!hw->autoneg)
2504 return -E1000_ERR_CONFIG;
2505
2506 /* optimize the dsp settings for the igp phy */
2507 e1000_config_dsp_after_link_change(hw, true);
2508
2509 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2510 * have Si on board that is 82544 or newer, Auto
2511 * Speed Detection takes care of MAC speed/duplex
2512 * configuration. So we only need to configure Collision
2513 * Distance in the MAC. Otherwise, we need to force
2514 * speed/duplex on the MAC to the current PHY speed/duplex
2515 * settings.
2516 */
2517 if ((hw->mac_type >= e1000_82544) &&
2518 (hw->mac_type != e1000_ce4100))
2519 e1000_config_collision_dist(hw);
2520 else {
2521 ret_val = e1000_config_mac_to_phy(hw);
2522 if (ret_val) {
2523 e_dbg
2524 ("Error configuring MAC to PHY settings\n");
2525 return ret_val;
2526 }
2527 }
2528
2529 /* Configure Flow Control now that Auto-Neg has completed. First, we
2530 * need to restore the desired flow control settings because we may
2531 * have had to re-autoneg with a different link partner.
2532 */
2533 ret_val = e1000_config_fc_after_link_up(hw);
2534 if (ret_val) {
2535 e_dbg("Error configuring flow control\n");
2536 return ret_val;
2537 }
2538
2539 /* At this point we know that we are on copper and we have
2540 * auto-negotiated link. These are conditions for checking the link
2541 * partner capability register. We use the link speed to determine if
2542 * TBI compatibility needs to be turned on or off. If the link is not
2543 * at gigabit speed, then TBI compatibility is not needed. If we are
2544 * at gigabit speed, we turn on TBI compatibility.
2545 */
2546 if (hw->tbi_compatibility_en) {
2547 u16 speed, duplex;
2548 ret_val =
2549 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2550 if (ret_val) {
2551 e_dbg
2552 ("Error getting link speed and duplex\n");
2553 return ret_val;
2554 }
2555 if (speed != SPEED_1000) {
2556 /* If link speed is not set to gigabit speed, we do not need
2557 * to enable TBI compatibility.
2558 */
2559 if (hw->tbi_compatibility_on) {
2560 /* If we previously were in the mode, turn it off. */
2561 rctl = er32(RCTL);
2562 rctl &= ~E1000_RCTL_SBP;
2563 ew32(RCTL, rctl);
2564 hw->tbi_compatibility_on = false;
2565 }
2566 } else {
2567 /* If TBI compatibility is was previously off, turn it on. For
2568 * compatibility with a TBI link partner, we will store bad
2569 * packets. Some frames have an additional byte on the end and
2570 * will look like CRC errors to to the hardware.
2571 */
2572 if (!hw->tbi_compatibility_on) {
2573 hw->tbi_compatibility_on = true;
2574 rctl = er32(RCTL);
2575 rctl |= E1000_RCTL_SBP;
2576 ew32(RCTL, rctl);
2577 }
2578 }
2579 }
2580 }
2581
2582 if ((hw->media_type == e1000_media_type_fiber) ||
2583 (hw->media_type == e1000_media_type_internal_serdes))
2584 e1000_check_for_serdes_link_generic(hw);
2585
2586 return E1000_SUCCESS;
2587}
2588
2589/**
2590 * e1000_get_speed_and_duplex
2591 * @hw: Struct containing variables accessed by shared code
2592 * @speed: Speed of the connection
2593 * @duplex: Duplex setting of the connection
2594
2595 * Detects the current speed and duplex settings of the hardware.
2596 */
2597s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)
2598{
2599 u32 status;
2600 s32 ret_val;
2601 u16 phy_data;
2602
2603 e_dbg("e1000_get_speed_and_duplex");
2604
2605 if (hw->mac_type >= e1000_82543) {
2606 status = er32(STATUS);
2607 if (status & E1000_STATUS_SPEED_1000) {
2608 *speed = SPEED_1000;
2609 e_dbg("1000 Mbs, ");
2610 } else if (status & E1000_STATUS_SPEED_100) {
2611 *speed = SPEED_100;
2612 e_dbg("100 Mbs, ");
2613 } else {
2614 *speed = SPEED_10;
2615 e_dbg("10 Mbs, ");
2616 }
2617
2618 if (status & E1000_STATUS_FD) {
2619 *duplex = FULL_DUPLEX;
2620 e_dbg("Full Duplex\n");
2621 } else {
2622 *duplex = HALF_DUPLEX;
2623 e_dbg(" Half Duplex\n");
2624 }
2625 } else {
2626 e_dbg("1000 Mbs, Full Duplex\n");
2627 *speed = SPEED_1000;
2628 *duplex = FULL_DUPLEX;
2629 }
2630
2631 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
2632 * if it is operating at half duplex. Here we set the duplex settings to
2633 * match the duplex in the link partner's capabilities.
2634 */
2635 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
2636 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
2637 if (ret_val)
2638 return ret_val;
2639
2640 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
2641 *duplex = HALF_DUPLEX;
2642 else {
2643 ret_val =
2644 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
2645 if (ret_val)
2646 return ret_val;
2647 if ((*speed == SPEED_100
2648 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
2649 || (*speed == SPEED_10
2650 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
2651 *duplex = HALF_DUPLEX;
2652 }
2653 }
2654
2655 return E1000_SUCCESS;
2656}
2657
2658/**
2659 * e1000_wait_autoneg
2660 * @hw: Struct containing variables accessed by shared code
2661 *
2662 * Blocks until autoneg completes or times out (~4.5 seconds)
2663 */
2664static s32 e1000_wait_autoneg(struct e1000_hw *hw)
2665{
2666 s32 ret_val;
2667 u16 i;
2668 u16 phy_data;
2669
2670 e_dbg("e1000_wait_autoneg");
2671 e_dbg("Waiting for Auto-Neg to complete.\n");
2672
2673 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2674 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2675 /* Read the MII Status Register and wait for Auto-Neg
2676 * Complete bit to be set.
2677 */
2678 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2679 if (ret_val)
2680 return ret_val;
2681 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2682 if (ret_val)
2683 return ret_val;
2684 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
2685 return E1000_SUCCESS;
2686 }
2687 msleep(100);
2688 }
2689 return E1000_SUCCESS;
2690}
2691
2692/**
2693 * e1000_raise_mdi_clk - Raises the Management Data Clock
2694 * @hw: Struct containing variables accessed by shared code
2695 * @ctrl: Device control register's current value
2696 */
2697static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
2698{
2699 /* Raise the clock input to the Management Data Clock (by setting the MDC
2700 * bit), and then delay 10 microseconds.
2701 */
2702 ew32(CTRL, (*ctrl | E1000_CTRL_MDC));
2703 E1000_WRITE_FLUSH();
2704 udelay(10);
2705}
2706
2707/**
2708 * e1000_lower_mdi_clk - Lowers the Management Data Clock
2709 * @hw: Struct containing variables accessed by shared code
2710 * @ctrl: Device control register's current value
2711 */
2712static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
2713{
2714 /* Lower the clock input to the Management Data Clock (by clearing the MDC
2715 * bit), and then delay 10 microseconds.
2716 */
2717 ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC));
2718 E1000_WRITE_FLUSH();
2719 udelay(10);
2720}
2721
2722/**
2723 * e1000_shift_out_mdi_bits - Shifts data bits out to the PHY
2724 * @hw: Struct containing variables accessed by shared code
2725 * @data: Data to send out to the PHY
2726 * @count: Number of bits to shift out
2727 *
2728 * Bits are shifted out in MSB to LSB order.
2729 */
2730static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count)
2731{
2732 u32 ctrl;
2733 u32 mask;
2734
2735 /* We need to shift "count" number of bits out to the PHY. So, the value
2736 * in the "data" parameter will be shifted out to the PHY one bit at a
2737 * time. In order to do this, "data" must be broken down into bits.
2738 */
2739 mask = 0x01;
2740 mask <<= (count - 1);
2741
2742 ctrl = er32(CTRL);
2743
2744 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2745 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2746
2747 while (mask) {
2748 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2749 * then raising and lowering the Management Data Clock. A "0" is
2750 * shifted out to the PHY by setting the MDIO bit to "0" and then
2751 * raising and lowering the clock.
2752 */
2753 if (data & mask)
2754 ctrl |= E1000_CTRL_MDIO;
2755 else
2756 ctrl &= ~E1000_CTRL_MDIO;
2757
2758 ew32(CTRL, ctrl);
2759 E1000_WRITE_FLUSH();
2760
2761 udelay(10);
2762
2763 e1000_raise_mdi_clk(hw, &ctrl);
2764 e1000_lower_mdi_clk(hw, &ctrl);
2765
2766 mask = mask >> 1;
2767 }
2768}
2769
2770/**
2771 * e1000_shift_in_mdi_bits - Shifts data bits in from the PHY
2772 * @hw: Struct containing variables accessed by shared code
2773 *
2774 * Bits are shifted in in MSB to LSB order.
2775 */
2776static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2777{
2778 u32 ctrl;
2779 u16 data = 0;
2780 u8 i;
2781
2782 /* In order to read a register from the PHY, we need to shift in a total
2783 * of 18 bits from the PHY. The first two bit (turnaround) times are used
2784 * to avoid contention on the MDIO pin when a read operation is performed.
2785 * These two bits are ignored by us and thrown away. Bits are "shifted in"
2786 * by raising the input to the Management Data Clock (setting the MDC bit),
2787 * and then reading the value of the MDIO bit.
2788 */
2789 ctrl = er32(CTRL);
2790
2791 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2792 ctrl &= ~E1000_CTRL_MDIO_DIR;
2793 ctrl &= ~E1000_CTRL_MDIO;
2794
2795 ew32(CTRL, ctrl);
2796 E1000_WRITE_FLUSH();
2797
2798 /* Raise and Lower the clock before reading in the data. This accounts for
2799 * the turnaround bits. The first clock occurred when we clocked out the
2800 * last bit of the Register Address.
2801 */
2802 e1000_raise_mdi_clk(hw, &ctrl);
2803 e1000_lower_mdi_clk(hw, &ctrl);
2804
2805 for (data = 0, i = 0; i < 16; i++) {
2806 data = data << 1;
2807 e1000_raise_mdi_clk(hw, &ctrl);
2808 ctrl = er32(CTRL);
2809 /* Check to see if we shifted in a "1". */
2810 if (ctrl & E1000_CTRL_MDIO)
2811 data |= 1;
2812 e1000_lower_mdi_clk(hw, &ctrl);
2813 }
2814
2815 e1000_raise_mdi_clk(hw, &ctrl);
2816 e1000_lower_mdi_clk(hw, &ctrl);
2817
2818 return data;
2819}
2820
2821
2822/**
2823 * e1000_read_phy_reg - read a phy register
2824 * @hw: Struct containing variables accessed by shared code
2825 * @reg_addr: address of the PHY register to read
2826 *
2827 * Reads the value from a PHY register, if the value is on a specific non zero
2828 * page, sets the page first.
2829 */
2830s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data)
2831{
2832 u32 ret_val;
2833
2834 e_dbg("e1000_read_phy_reg");
2835
2836 if ((hw->phy_type == e1000_phy_igp) &&
2837 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2838 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2839 (u16) reg_addr);
2840 if (ret_val)
2841 return ret_val;
2842 }
2843
2844 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2845 phy_data);
2846
2847 return ret_val;
2848}
2849
2850static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2851 u16 *phy_data)
2852{
2853 u32 i;
2854 u32 mdic = 0;
2855 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
2856
2857 e_dbg("e1000_read_phy_reg_ex");
2858
2859 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2860 e_dbg("PHY Address %d is out of range\n", reg_addr);
2861 return -E1000_ERR_PARAM;
2862 }
2863
2864 if (hw->mac_type > e1000_82543) {
2865 /* Set up Op-code, Phy Address, and register address in the MDI
2866 * Control register. The MAC will take care of interfacing with the
2867 * PHY to retrieve the desired data.
2868 */
2869 if (hw->mac_type == e1000_ce4100) {
2870 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2871 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2872 (INTEL_CE_GBE_MDIC_OP_READ) |
2873 (INTEL_CE_GBE_MDIC_GO));
2874
2875 writel(mdic, E1000_MDIO_CMD);
2876
2877 /* Poll the ready bit to see if the MDI read
2878 * completed
2879 */
2880 for (i = 0; i < 64; i++) {
2881 udelay(50);
2882 mdic = readl(E1000_MDIO_CMD);
2883 if (!(mdic & INTEL_CE_GBE_MDIC_GO))
2884 break;
2885 }
2886
2887 if (mdic & INTEL_CE_GBE_MDIC_GO) {
2888 e_dbg("MDI Read did not complete\n");
2889 return -E1000_ERR_PHY;
2890 }
2891
2892 mdic = readl(E1000_MDIO_STS);
2893 if (mdic & INTEL_CE_GBE_MDIC_READ_ERROR) {
2894 e_dbg("MDI Read Error\n");
2895 return -E1000_ERR_PHY;
2896 }
2897 *phy_data = (u16) mdic;
2898 } else {
2899 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2900 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2901 (E1000_MDIC_OP_READ));
2902
2903 ew32(MDIC, mdic);
2904
2905 /* Poll the ready bit to see if the MDI read
2906 * completed
2907 */
2908 for (i = 0; i < 64; i++) {
2909 udelay(50);
2910 mdic = er32(MDIC);
2911 if (mdic & E1000_MDIC_READY)
2912 break;
2913 }
2914 if (!(mdic & E1000_MDIC_READY)) {
2915 e_dbg("MDI Read did not complete\n");
2916 return -E1000_ERR_PHY;
2917 }
2918 if (mdic & E1000_MDIC_ERROR) {
2919 e_dbg("MDI Error\n");
2920 return -E1000_ERR_PHY;
2921 }
2922 *phy_data = (u16) mdic;
2923 }
2924 } else {
2925 /* We must first send a preamble through the MDIO pin to signal the
2926 * beginning of an MII instruction. This is done by sending 32
2927 * consecutive "1" bits.
2928 */
2929 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2930
2931 /* Now combine the next few fields that are required for a read
2932 * operation. We use this method instead of calling the
2933 * e1000_shift_out_mdi_bits routine five different times. The format of
2934 * a MII read instruction consists of a shift out of 14 bits and is
2935 * defined as follows:
2936 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2937 * followed by a shift in of 18 bits. This first two bits shifted in
2938 * are TurnAround bits used to avoid contention on the MDIO pin when a
2939 * READ operation is performed. These two bits are thrown away
2940 * followed by a shift in of 16 bits which contains the desired data.
2941 */
2942 mdic = ((reg_addr) | (phy_addr << 5) |
2943 (PHY_OP_READ << 10) | (PHY_SOF << 12));
2944
2945 e1000_shift_out_mdi_bits(hw, mdic, 14);
2946
2947 /* Now that we've shifted out the read command to the MII, we need to
2948 * "shift in" the 16-bit value (18 total bits) of the requested PHY
2949 * register address.
2950 */
2951 *phy_data = e1000_shift_in_mdi_bits(hw);
2952 }
2953 return E1000_SUCCESS;
2954}
2955
2956/**
2957 * e1000_write_phy_reg - write a phy register
2958 *
2959 * @hw: Struct containing variables accessed by shared code
2960 * @reg_addr: address of the PHY register to write
2961 * @data: data to write to the PHY
2962
2963 * Writes a value to a PHY register
2964 */
2965s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)
2966{
2967 u32 ret_val;
2968
2969 e_dbg("e1000_write_phy_reg");
2970
2971 if ((hw->phy_type == e1000_phy_igp) &&
2972 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2973 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2974 (u16) reg_addr);
2975 if (ret_val)
2976 return ret_val;
2977 }
2978
2979 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2980 phy_data);
2981
2982 return ret_val;
2983}
2984
2985static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2986 u16 phy_data)
2987{
2988 u32 i;
2989 u32 mdic = 0;
2990 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
2991
2992 e_dbg("e1000_write_phy_reg_ex");
2993
2994 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2995 e_dbg("PHY Address %d is out of range\n", reg_addr);
2996 return -E1000_ERR_PARAM;
2997 }
2998
2999 if (hw->mac_type > e1000_82543) {
3000 /* Set up Op-code, Phy Address, register address, and data
3001 * intended for the PHY register in the MDI Control register.
3002 * The MAC will take care of interfacing with the PHY to send
3003 * the desired data.
3004 */
3005 if (hw->mac_type == e1000_ce4100) {
3006 mdic = (((u32) phy_data) |
3007 (reg_addr << E1000_MDIC_REG_SHIFT) |
3008 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3009 (INTEL_CE_GBE_MDIC_OP_WRITE) |
3010 (INTEL_CE_GBE_MDIC_GO));
3011
3012 writel(mdic, E1000_MDIO_CMD);
3013
3014 /* Poll the ready bit to see if the MDI read
3015 * completed
3016 */
3017 for (i = 0; i < 640; i++) {
3018 udelay(5);
3019 mdic = readl(E1000_MDIO_CMD);
3020 if (!(mdic & INTEL_CE_GBE_MDIC_GO))
3021 break;
3022 }
3023 if (mdic & INTEL_CE_GBE_MDIC_GO) {
3024 e_dbg("MDI Write did not complete\n");
3025 return -E1000_ERR_PHY;
3026 }
3027 } else {
3028 mdic = (((u32) phy_data) |
3029 (reg_addr << E1000_MDIC_REG_SHIFT) |
3030 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3031 (E1000_MDIC_OP_WRITE));
3032
3033 ew32(MDIC, mdic);
3034
3035 /* Poll the ready bit to see if the MDI read
3036 * completed
3037 */
3038 for (i = 0; i < 641; i++) {
3039 udelay(5);
3040 mdic = er32(MDIC);
3041 if (mdic & E1000_MDIC_READY)
3042 break;
3043 }
3044 if (!(mdic & E1000_MDIC_READY)) {
3045 e_dbg("MDI Write did not complete\n");
3046 return -E1000_ERR_PHY;
3047 }
3048 }
3049 } else {
3050 /* We'll need to use the SW defined pins to shift the write command
3051 * out to the PHY. We first send a preamble to the PHY to signal the
3052 * beginning of the MII instruction. This is done by sending 32
3053 * consecutive "1" bits.
3054 */
3055 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3056
3057 /* Now combine the remaining required fields that will indicate a
3058 * write operation. We use this method instead of calling the
3059 * e1000_shift_out_mdi_bits routine for each field in the command. The
3060 * format of a MII write instruction is as follows:
3061 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
3062 */
3063 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3064 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3065 mdic <<= 16;
3066 mdic |= (u32) phy_data;
3067
3068 e1000_shift_out_mdi_bits(hw, mdic, 32);
3069 }
3070
3071 return E1000_SUCCESS;
3072}
3073
3074/**
3075 * e1000_phy_hw_reset - reset the phy, hardware style
3076 * @hw: Struct containing variables accessed by shared code
3077 *
3078 * Returns the PHY to the power-on reset state
3079 */
3080s32 e1000_phy_hw_reset(struct e1000_hw *hw)
3081{
3082 u32 ctrl, ctrl_ext;
3083 u32 led_ctrl;
3084
3085 e_dbg("e1000_phy_hw_reset");
3086
3087 e_dbg("Resetting Phy...\n");
3088
3089 if (hw->mac_type > e1000_82543) {
3090 /* Read the device control register and assert the E1000_CTRL_PHY_RST
3091 * bit. Then, take it out of reset.
3092 * For e1000 hardware, we delay for 10ms between the assert
3093 * and deassert.
3094 */
3095 ctrl = er32(CTRL);
3096 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
3097 E1000_WRITE_FLUSH();
3098
3099 msleep(10);
3100
3101 ew32(CTRL, ctrl);
3102 E1000_WRITE_FLUSH();
3103
3104 } else {
3105 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3106 * bit to put the PHY into reset. Then, take it out of reset.
3107 */
3108 ctrl_ext = er32(CTRL_EXT);
3109 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3110 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3111 ew32(CTRL_EXT, ctrl_ext);
3112 E1000_WRITE_FLUSH();
3113 msleep(10);
3114 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3115 ew32(CTRL_EXT, ctrl_ext);
3116 E1000_WRITE_FLUSH();
3117 }
3118 udelay(150);
3119
3120 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3121 /* Configure activity LED after PHY reset */
3122 led_ctrl = er32(LEDCTL);
3123 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3124 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3125 ew32(LEDCTL, led_ctrl);
3126 }
3127
3128 /* Wait for FW to finish PHY configuration. */
3129 return e1000_get_phy_cfg_done(hw);
3130}
3131
3132/**
3133 * e1000_phy_reset - reset the phy to commit settings
3134 * @hw: Struct containing variables accessed by shared code
3135 *
3136 * Resets the PHY
3137 * Sets bit 15 of the MII Control register
3138 */
3139s32 e1000_phy_reset(struct e1000_hw *hw)
3140{
3141 s32 ret_val;
3142 u16 phy_data;
3143
3144 e_dbg("e1000_phy_reset");
3145
3146 switch (hw->phy_type) {
3147 case e1000_phy_igp:
3148 ret_val = e1000_phy_hw_reset(hw);
3149 if (ret_val)
3150 return ret_val;
3151 break;
3152 default:
3153 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3154 if (ret_val)
3155 return ret_val;
3156
3157 phy_data |= MII_CR_RESET;
3158 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3159 if (ret_val)
3160 return ret_val;
3161
3162 udelay(1);
3163 break;
3164 }
3165
3166 if (hw->phy_type == e1000_phy_igp)
3167 e1000_phy_init_script(hw);
3168
3169 return E1000_SUCCESS;
3170}
3171
3172/**
3173 * e1000_detect_gig_phy - check the phy type
3174 * @hw: Struct containing variables accessed by shared code
3175 *
3176 * Probes the expected PHY address for known PHY IDs
3177 */
3178static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
3179{
3180 s32 phy_init_status, ret_val;
3181 u16 phy_id_high, phy_id_low;
3182 bool match = false;
3183
3184 e_dbg("e1000_detect_gig_phy");
3185
3186 if (hw->phy_id != 0)
3187 return E1000_SUCCESS;
3188
3189 /* Read the PHY ID Registers to identify which PHY is onboard. */
3190 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
3191 if (ret_val)
3192 return ret_val;
3193
3194 hw->phy_id = (u32) (phy_id_high << 16);
3195 udelay(20);
3196 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
3197 if (ret_val)
3198 return ret_val;
3199
3200 hw->phy_id |= (u32) (phy_id_low & PHY_REVISION_MASK);
3201 hw->phy_revision = (u32) phy_id_low & ~PHY_REVISION_MASK;
3202
3203 switch (hw->mac_type) {
3204 case e1000_82543:
3205 if (hw->phy_id == M88E1000_E_PHY_ID)
3206 match = true;
3207 break;
3208 case e1000_82544:
3209 if (hw->phy_id == M88E1000_I_PHY_ID)
3210 match = true;
3211 break;
3212 case e1000_82540:
3213 case e1000_82545:
3214 case e1000_82545_rev_3:
3215 case e1000_82546:
3216 case e1000_82546_rev_3:
3217 if (hw->phy_id == M88E1011_I_PHY_ID)
3218 match = true;
3219 break;
3220 case e1000_ce4100:
3221 if ((hw->phy_id == RTL8211B_PHY_ID) ||
3222 (hw->phy_id == RTL8201N_PHY_ID) ||
3223 (hw->phy_id == M88E1118_E_PHY_ID))
3224 match = true;
3225 break;
3226 case e1000_82541:
3227 case e1000_82541_rev_2:
3228 case e1000_82547:
3229 case e1000_82547_rev_2:
3230 if (hw->phy_id == IGP01E1000_I_PHY_ID)
3231 match = true;
3232 break;
3233 default:
3234 e_dbg("Invalid MAC type %d\n", hw->mac_type);
3235 return -E1000_ERR_CONFIG;
3236 }
3237 phy_init_status = e1000_set_phy_type(hw);
3238
3239 if ((match) && (phy_init_status == E1000_SUCCESS)) {
3240 e_dbg("PHY ID 0x%X detected\n", hw->phy_id);
3241 return E1000_SUCCESS;
3242 }
3243 e_dbg("Invalid PHY ID 0x%X\n", hw->phy_id);
3244 return -E1000_ERR_PHY;
3245}
3246
3247/**
3248 * e1000_phy_reset_dsp - reset DSP
3249 * @hw: Struct containing variables accessed by shared code
3250 *
3251 * Resets the PHY's DSP
3252 */
3253static s32 e1000_phy_reset_dsp(struct e1000_hw *hw)
3254{
3255 s32 ret_val;
3256 e_dbg("e1000_phy_reset_dsp");
3257
3258 do {
3259 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
3260 if (ret_val)
3261 break;
3262 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
3263 if (ret_val)
3264 break;
3265 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
3266 if (ret_val)
3267 break;
3268 ret_val = E1000_SUCCESS;
3269 } while (0);
3270
3271 return ret_val;
3272}
3273
3274/**
3275 * e1000_phy_igp_get_info - get igp specific registers
3276 * @hw: Struct containing variables accessed by shared code
3277 * @phy_info: PHY information structure
3278 *
3279 * Get PHY information from various PHY registers for igp PHY only.
3280 */
3281static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
3282 struct e1000_phy_info *phy_info)
3283{
3284 s32 ret_val;
3285 u16 phy_data, min_length, max_length, average;
3286 e1000_rev_polarity polarity;
3287
3288 e_dbg("e1000_phy_igp_get_info");
3289
3290 /* The downshift status is checked only once, after link is established,
3291 * and it stored in the hw->speed_downgraded parameter. */
3292 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
3293
3294 /* IGP01E1000 does not need to support it. */
3295 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
3296
3297 /* IGP01E1000 always correct polarity reversal */
3298 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
3299
3300 /* Check polarity status */
3301 ret_val = e1000_check_polarity(hw, &polarity);
3302 if (ret_val)
3303 return ret_val;
3304
3305 phy_info->cable_polarity = polarity;
3306
3307 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
3308 if (ret_val)
3309 return ret_val;
3310
3311 phy_info->mdix_mode =
3312 (e1000_auto_x_mode) ((phy_data & IGP01E1000_PSSR_MDIX) >>
3313 IGP01E1000_PSSR_MDIX_SHIFT);
3314
3315 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
3316 IGP01E1000_PSSR_SPEED_1000MBPS) {
3317 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
3318 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3319 if (ret_val)
3320 return ret_val;
3321
3322 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3323 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
3324 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3325 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3326 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
3327 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3328
3329 /* Get cable length */
3330 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
3331 if (ret_val)
3332 return ret_val;
3333
3334 /* Translate to old method */
3335 average = (max_length + min_length) / 2;
3336
3337 if (average <= e1000_igp_cable_length_50)
3338 phy_info->cable_length = e1000_cable_length_50;
3339 else if (average <= e1000_igp_cable_length_80)
3340 phy_info->cable_length = e1000_cable_length_50_80;
3341 else if (average <= e1000_igp_cable_length_110)
3342 phy_info->cable_length = e1000_cable_length_80_110;
3343 else if (average <= e1000_igp_cable_length_140)
3344 phy_info->cable_length = e1000_cable_length_110_140;
3345 else
3346 phy_info->cable_length = e1000_cable_length_140;
3347 }
3348
3349 return E1000_SUCCESS;
3350}
3351
3352/**
3353 * e1000_phy_m88_get_info - get m88 specific registers
3354 * @hw: Struct containing variables accessed by shared code
3355 * @phy_info: PHY information structure
3356 *
3357 * Get PHY information from various PHY registers for m88 PHY only.
3358 */
3359static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
3360 struct e1000_phy_info *phy_info)
3361{
3362 s32 ret_val;
3363 u16 phy_data;
3364 e1000_rev_polarity polarity;
3365
3366 e_dbg("e1000_phy_m88_get_info");
3367
3368 /* The downshift status is checked only once, after link is established,
3369 * and it stored in the hw->speed_downgraded parameter. */
3370 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
3371
3372 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
3373 if (ret_val)
3374 return ret_val;
3375
3376 phy_info->extended_10bt_distance =
3377 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
3378 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
3379 e1000_10bt_ext_dist_enable_lower :
3380 e1000_10bt_ext_dist_enable_normal;
3381
3382 phy_info->polarity_correction =
3383 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
3384 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
3385 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
3386
3387 /* Check polarity status */
3388 ret_val = e1000_check_polarity(hw, &polarity);
3389 if (ret_val)
3390 return ret_val;
3391 phy_info->cable_polarity = polarity;
3392
3393 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
3394 if (ret_val)
3395 return ret_val;
3396
3397 phy_info->mdix_mode =
3398 (e1000_auto_x_mode) ((phy_data & M88E1000_PSSR_MDIX) >>
3399 M88E1000_PSSR_MDIX_SHIFT);
3400
3401 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
3402 /* Cable Length Estimation and Local/Remote Receiver Information
3403 * are only valid at 1000 Mbps.
3404 */
3405 phy_info->cable_length =
3406 (e1000_cable_length) ((phy_data &
3407 M88E1000_PSSR_CABLE_LENGTH) >>
3408 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
3409
3410 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3411 if (ret_val)
3412 return ret_val;
3413
3414 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3415 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
3416 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3417 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3418 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
3419 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3420
3421 }
3422
3423 return E1000_SUCCESS;
3424}
3425
3426/**
3427 * e1000_phy_get_info - request phy info
3428 * @hw: Struct containing variables accessed by shared code
3429 * @phy_info: PHY information structure
3430 *
3431 * Get PHY information from various PHY registers
3432 */
3433s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)
3434{
3435 s32 ret_val;
3436 u16 phy_data;
3437
3438 e_dbg("e1000_phy_get_info");
3439
3440 phy_info->cable_length = e1000_cable_length_undefined;
3441 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
3442 phy_info->cable_polarity = e1000_rev_polarity_undefined;
3443 phy_info->downshift = e1000_downshift_undefined;
3444 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
3445 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
3446 phy_info->local_rx = e1000_1000t_rx_status_undefined;
3447 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
3448
3449 if (hw->media_type != e1000_media_type_copper) {
3450 e_dbg("PHY info is only valid for copper media\n");
3451 return -E1000_ERR_CONFIG;
3452 }
3453
3454 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3455 if (ret_val)
3456 return ret_val;
3457
3458 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3459 if (ret_val)
3460 return ret_val;
3461
3462 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
3463 e_dbg("PHY info is only valid if link is up\n");
3464 return -E1000_ERR_CONFIG;
3465 }
3466
3467 if (hw->phy_type == e1000_phy_igp)
3468 return e1000_phy_igp_get_info(hw, phy_info);
3469 else if ((hw->phy_type == e1000_phy_8211) ||
3470 (hw->phy_type == e1000_phy_8201))
3471 return E1000_SUCCESS;
3472 else
3473 return e1000_phy_m88_get_info(hw, phy_info);
3474}
3475
3476s32 e1000_validate_mdi_setting(struct e1000_hw *hw)
3477{
3478 e_dbg("e1000_validate_mdi_settings");
3479
3480 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
3481 e_dbg("Invalid MDI setting detected\n");
3482 hw->mdix = 1;
3483 return -E1000_ERR_CONFIG;
3484 }
3485 return E1000_SUCCESS;
3486}
3487
3488/**
3489 * e1000_init_eeprom_params - initialize sw eeprom vars
3490 * @hw: Struct containing variables accessed by shared code
3491 *
3492 * Sets up eeprom variables in the hw struct. Must be called after mac_type
3493 * is configured.
3494 */
3495s32 e1000_init_eeprom_params(struct e1000_hw *hw)
3496{
3497 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3498 u32 eecd = er32(EECD);
3499 s32 ret_val = E1000_SUCCESS;
3500 u16 eeprom_size;
3501
3502 e_dbg("e1000_init_eeprom_params");
3503
3504 switch (hw->mac_type) {
3505 case e1000_82542_rev2_0:
3506 case e1000_82542_rev2_1:
3507 case e1000_82543:
3508 case e1000_82544:
3509 eeprom->type = e1000_eeprom_microwire;
3510 eeprom->word_size = 64;
3511 eeprom->opcode_bits = 3;
3512 eeprom->address_bits = 6;
3513 eeprom->delay_usec = 50;
3514 break;
3515 case e1000_82540:
3516 case e1000_82545:
3517 case e1000_82545_rev_3:
3518 case e1000_82546:
3519 case e1000_82546_rev_3:
3520 eeprom->type = e1000_eeprom_microwire;
3521 eeprom->opcode_bits = 3;
3522 eeprom->delay_usec = 50;
3523 if (eecd & E1000_EECD_SIZE) {
3524 eeprom->word_size = 256;
3525 eeprom->address_bits = 8;
3526 } else {
3527 eeprom->word_size = 64;
3528 eeprom->address_bits = 6;
3529 }
3530 break;
3531 case e1000_82541:
3532 case e1000_82541_rev_2:
3533 case e1000_82547:
3534 case e1000_82547_rev_2:
3535 if (eecd & E1000_EECD_TYPE) {
3536 eeprom->type = e1000_eeprom_spi;
3537 eeprom->opcode_bits = 8;
3538 eeprom->delay_usec = 1;
3539 if (eecd & E1000_EECD_ADDR_BITS) {
3540 eeprom->page_size = 32;
3541 eeprom->address_bits = 16;
3542 } else {
3543 eeprom->page_size = 8;
3544 eeprom->address_bits = 8;
3545 }
3546 } else {
3547 eeprom->type = e1000_eeprom_microwire;
3548 eeprom->opcode_bits = 3;
3549 eeprom->delay_usec = 50;
3550 if (eecd & E1000_EECD_ADDR_BITS) {
3551 eeprom->word_size = 256;
3552 eeprom->address_bits = 8;
3553 } else {
3554 eeprom->word_size = 64;
3555 eeprom->address_bits = 6;
3556 }
3557 }
3558 break;
3559 default:
3560 break;
3561 }
3562
3563 if (eeprom->type == e1000_eeprom_spi) {
3564 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
3565 * 32KB (incremented by powers of 2).
3566 */
3567 /* Set to default value for initial eeprom read. */
3568 eeprom->word_size = 64;
3569 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
3570 if (ret_val)
3571 return ret_val;
3572 eeprom_size =
3573 (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
3574 /* 256B eeprom size was not supported in earlier hardware, so we
3575 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
3576 * is never the result used in the shifting logic below. */
3577 if (eeprom_size)
3578 eeprom_size++;
3579
3580 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
3581 }
3582 return ret_val;
3583}
3584
3585/**
3586 * e1000_raise_ee_clk - Raises the EEPROM's clock input.
3587 * @hw: Struct containing variables accessed by shared code
3588 * @eecd: EECD's current value
3589 */
3590static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd)
3591{
3592 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
3593 * wait <delay> microseconds.
3594 */
3595 *eecd = *eecd | E1000_EECD_SK;
3596 ew32(EECD, *eecd);
3597 E1000_WRITE_FLUSH();
3598 udelay(hw->eeprom.delay_usec);
3599}
3600
3601/**
3602 * e1000_lower_ee_clk - Lowers the EEPROM's clock input.
3603 * @hw: Struct containing variables accessed by shared code
3604 * @eecd: EECD's current value
3605 */
3606static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd)
3607{
3608 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
3609 * wait 50 microseconds.
3610 */
3611 *eecd = *eecd & ~E1000_EECD_SK;
3612 ew32(EECD, *eecd);
3613 E1000_WRITE_FLUSH();
3614 udelay(hw->eeprom.delay_usec);
3615}
3616
3617/**
3618 * e1000_shift_out_ee_bits - Shift data bits out to the EEPROM.
3619 * @hw: Struct containing variables accessed by shared code
3620 * @data: data to send to the EEPROM
3621 * @count: number of bits to shift out
3622 */
3623static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)
3624{
3625 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3626 u32 eecd;
3627 u32 mask;
3628
3629 /* We need to shift "count" bits out to the EEPROM. So, value in the
3630 * "data" parameter will be shifted out to the EEPROM one bit at a time.
3631 * In order to do this, "data" must be broken down into bits.
3632 */
3633 mask = 0x01 << (count - 1);
3634 eecd = er32(EECD);
3635 if (eeprom->type == e1000_eeprom_microwire) {
3636 eecd &= ~E1000_EECD_DO;
3637 } else if (eeprom->type == e1000_eeprom_spi) {
3638 eecd |= E1000_EECD_DO;
3639 }
3640 do {
3641 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
3642 * and then raising and then lowering the clock (the SK bit controls
3643 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
3644 * by setting "DI" to "0" and then raising and then lowering the clock.
3645 */
3646 eecd &= ~E1000_EECD_DI;
3647
3648 if (data & mask)
3649 eecd |= E1000_EECD_DI;
3650
3651 ew32(EECD, eecd);
3652 E1000_WRITE_FLUSH();
3653
3654 udelay(eeprom->delay_usec);
3655
3656 e1000_raise_ee_clk(hw, &eecd);
3657 e1000_lower_ee_clk(hw, &eecd);
3658
3659 mask = mask >> 1;
3660
3661 } while (mask);
3662
3663 /* We leave the "DI" bit set to "0" when we leave this routine. */
3664 eecd &= ~E1000_EECD_DI;
3665 ew32(EECD, eecd);
3666}
3667
3668/**
3669 * e1000_shift_in_ee_bits - Shift data bits in from the EEPROM
3670 * @hw: Struct containing variables accessed by shared code
3671 * @count: number of bits to shift in
3672 */
3673static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count)
3674{
3675 u32 eecd;
3676 u32 i;
3677 u16 data;
3678
3679 /* In order to read a register from the EEPROM, we need to shift 'count'
3680 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
3681 * input to the EEPROM (setting the SK bit), and then reading the value of
3682 * the "DO" bit. During this "shifting in" process the "DI" bit should
3683 * always be clear.
3684 */
3685
3686 eecd = er32(EECD);
3687
3688 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
3689 data = 0;
3690
3691 for (i = 0; i < count; i++) {
3692 data = data << 1;
3693 e1000_raise_ee_clk(hw, &eecd);
3694
3695 eecd = er32(EECD);
3696
3697 eecd &= ~(E1000_EECD_DI);
3698 if (eecd & E1000_EECD_DO)
3699 data |= 1;
3700
3701 e1000_lower_ee_clk(hw, &eecd);
3702 }
3703
3704 return data;
3705}
3706
3707/**
3708 * e1000_acquire_eeprom - Prepares EEPROM for access
3709 * @hw: Struct containing variables accessed by shared code
3710 *
3711 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
3712 * function should be called before issuing a command to the EEPROM.
3713 */
3714static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
3715{
3716 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3717 u32 eecd, i = 0;
3718
3719 e_dbg("e1000_acquire_eeprom");
3720
3721 eecd = er32(EECD);
3722
3723 /* Request EEPROM Access */
3724 if (hw->mac_type > e1000_82544) {
3725 eecd |= E1000_EECD_REQ;
3726 ew32(EECD, eecd);
3727 eecd = er32(EECD);
3728 while ((!(eecd & E1000_EECD_GNT)) &&
3729 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3730 i++;
3731 udelay(5);
3732 eecd = er32(EECD);
3733 }
3734 if (!(eecd & E1000_EECD_GNT)) {
3735 eecd &= ~E1000_EECD_REQ;
3736 ew32(EECD, eecd);
3737 e_dbg("Could not acquire EEPROM grant\n");
3738 return -E1000_ERR_EEPROM;
3739 }
3740 }
3741
3742 /* Setup EEPROM for Read/Write */
3743
3744 if (eeprom->type == e1000_eeprom_microwire) {
3745 /* Clear SK and DI */
3746 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
3747 ew32(EECD, eecd);
3748
3749 /* Set CS */
3750 eecd |= E1000_EECD_CS;
3751 ew32(EECD, eecd);
3752 } else if (eeprom->type == e1000_eeprom_spi) {
3753 /* Clear SK and CS */
3754 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3755 ew32(EECD, eecd);
3756 E1000_WRITE_FLUSH();
3757 udelay(1);
3758 }
3759
3760 return E1000_SUCCESS;
3761}
3762
3763/**
3764 * e1000_standby_eeprom - Returns EEPROM to a "standby" state
3765 * @hw: Struct containing variables accessed by shared code
3766 */
3767static void e1000_standby_eeprom(struct e1000_hw *hw)
3768{
3769 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3770 u32 eecd;
3771
3772 eecd = er32(EECD);
3773
3774 if (eeprom->type == e1000_eeprom_microwire) {
3775 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3776 ew32(EECD, eecd);
3777 E1000_WRITE_FLUSH();
3778 udelay(eeprom->delay_usec);
3779
3780 /* Clock high */
3781 eecd |= E1000_EECD_SK;
3782 ew32(EECD, eecd);
3783 E1000_WRITE_FLUSH();
3784 udelay(eeprom->delay_usec);
3785
3786 /* Select EEPROM */
3787 eecd |= E1000_EECD_CS;
3788 ew32(EECD, eecd);
3789 E1000_WRITE_FLUSH();
3790 udelay(eeprom->delay_usec);
3791
3792 /* Clock low */
3793 eecd &= ~E1000_EECD_SK;
3794 ew32(EECD, eecd);
3795 E1000_WRITE_FLUSH();
3796 udelay(eeprom->delay_usec);
3797 } else if (eeprom->type == e1000_eeprom_spi) {
3798 /* Toggle CS to flush commands */
3799 eecd |= E1000_EECD_CS;
3800 ew32(EECD, eecd);
3801 E1000_WRITE_FLUSH();
3802 udelay(eeprom->delay_usec);
3803 eecd &= ~E1000_EECD_CS;
3804 ew32(EECD, eecd);
3805 E1000_WRITE_FLUSH();
3806 udelay(eeprom->delay_usec);
3807 }
3808}
3809
3810/**
3811 * e1000_release_eeprom - drop chip select
3812 * @hw: Struct containing variables accessed by shared code
3813 *
3814 * Terminates a command by inverting the EEPROM's chip select pin
3815 */
3816static void e1000_release_eeprom(struct e1000_hw *hw)
3817{
3818 u32 eecd;
3819
3820 e_dbg("e1000_release_eeprom");
3821
3822 eecd = er32(EECD);
3823
3824 if (hw->eeprom.type == e1000_eeprom_spi) {
3825 eecd |= E1000_EECD_CS; /* Pull CS high */
3826 eecd &= ~E1000_EECD_SK; /* Lower SCK */
3827
3828 ew32(EECD, eecd);
3829 E1000_WRITE_FLUSH();
3830
3831 udelay(hw->eeprom.delay_usec);
3832 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
3833 /* cleanup eeprom */
3834
3835 /* CS on Microwire is active-high */
3836 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
3837
3838 ew32(EECD, eecd);
3839
3840 /* Rising edge of clock */
3841 eecd |= E1000_EECD_SK;
3842 ew32(EECD, eecd);
3843 E1000_WRITE_FLUSH();
3844 udelay(hw->eeprom.delay_usec);
3845
3846 /* Falling edge of clock */
3847 eecd &= ~E1000_EECD_SK;
3848 ew32(EECD, eecd);
3849 E1000_WRITE_FLUSH();
3850 udelay(hw->eeprom.delay_usec);
3851 }
3852
3853 /* Stop requesting EEPROM access */
3854 if (hw->mac_type > e1000_82544) {
3855 eecd &= ~E1000_EECD_REQ;
3856 ew32(EECD, eecd);
3857 }
3858}
3859
3860/**
3861 * e1000_spi_eeprom_ready - Reads a 16 bit word from the EEPROM.
3862 * @hw: Struct containing variables accessed by shared code
3863 */
3864static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)
3865{
3866 u16 retry_count = 0;
3867 u8 spi_stat_reg;
3868
3869 e_dbg("e1000_spi_eeprom_ready");
3870
3871 /* Read "Status Register" repeatedly until the LSB is cleared. The
3872 * EEPROM will signal that the command has been completed by clearing
3873 * bit 0 of the internal status register. If it's not cleared within
3874 * 5 milliseconds, then error out.
3875 */
3876 retry_count = 0;
3877 do {
3878 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3879 hw->eeprom.opcode_bits);
3880 spi_stat_reg = (u8) e1000_shift_in_ee_bits(hw, 8);
3881 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3882 break;
3883
3884 udelay(5);
3885 retry_count += 5;
3886
3887 e1000_standby_eeprom(hw);
3888 } while (retry_count < EEPROM_MAX_RETRY_SPI);
3889
3890 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3891 * only 0-5mSec on 5V devices)
3892 */
3893 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
3894 e_dbg("SPI EEPROM Status error\n");
3895 return -E1000_ERR_EEPROM;
3896 }
3897
3898 return E1000_SUCCESS;
3899}
3900
3901/**
3902 * e1000_read_eeprom - Reads a 16 bit word from the EEPROM.
3903 * @hw: Struct containing variables accessed by shared code
3904 * @offset: offset of word in the EEPROM to read
3905 * @data: word read from the EEPROM
3906 * @words: number of words to read
3907 */
3908s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
3909{
3910 s32 ret;
3911 spin_lock(&e1000_eeprom_lock);
3912 ret = e1000_do_read_eeprom(hw, offset, words, data);
3913 spin_unlock(&e1000_eeprom_lock);
3914 return ret;
3915}
3916
3917static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
3918 u16 *data)
3919{
3920 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3921 u32 i = 0;
3922
3923 e_dbg("e1000_read_eeprom");
3924
3925 if (hw->mac_type == e1000_ce4100) {
3926 GBE_CONFIG_FLASH_READ(GBE_CONFIG_BASE_VIRT, offset, words,
3927 data);
3928 return E1000_SUCCESS;
3929 }
3930
3931 /* If eeprom is not yet detected, do so now */
3932 if (eeprom->word_size == 0)
3933 e1000_init_eeprom_params(hw);
3934
3935 /* A check for invalid values: offset too large, too many words, and not
3936 * enough words.
3937 */
3938 if ((offset >= eeprom->word_size)
3939 || (words > eeprom->word_size - offset) || (words == 0)) {
3940 e_dbg("\"words\" parameter out of bounds. Words = %d,"
3941 "size = %d\n", offset, eeprom->word_size);
3942 return -E1000_ERR_EEPROM;
3943 }
3944
3945 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
3946 * directly. In this case, we need to acquire the EEPROM so that
3947 * FW or other port software does not interrupt.
3948 */
3949 /* Prepare the EEPROM for bit-bang reading */
3950 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3951 return -E1000_ERR_EEPROM;
3952
3953 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
3954 * acquired the EEPROM at this point, so any returns should release it */
3955 if (eeprom->type == e1000_eeprom_spi) {
3956 u16 word_in;
3957 u8 read_opcode = EEPROM_READ_OPCODE_SPI;
3958
3959 if (e1000_spi_eeprom_ready(hw)) {
3960 e1000_release_eeprom(hw);
3961 return -E1000_ERR_EEPROM;
3962 }
3963
3964 e1000_standby_eeprom(hw);
3965
3966 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3967 if ((eeprom->address_bits == 8) && (offset >= 128))
3968 read_opcode |= EEPROM_A8_OPCODE_SPI;
3969
3970 /* Send the READ command (opcode + addr) */
3971 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3972 e1000_shift_out_ee_bits(hw, (u16) (offset * 2),
3973 eeprom->address_bits);
3974
3975 /* Read the data. The address of the eeprom internally increments with
3976 * each byte (spi) being read, saving on the overhead of eeprom setup
3977 * and tear-down. The address counter will roll over if reading beyond
3978 * the size of the eeprom, thus allowing the entire memory to be read
3979 * starting from any offset. */
3980 for (i = 0; i < words; i++) {
3981 word_in = e1000_shift_in_ee_bits(hw, 16);
3982 data[i] = (word_in >> 8) | (word_in << 8);
3983 }
3984 } else if (eeprom->type == e1000_eeprom_microwire) {
3985 for (i = 0; i < words; i++) {
3986 /* Send the READ command (opcode + addr) */
3987 e1000_shift_out_ee_bits(hw,
3988 EEPROM_READ_OPCODE_MICROWIRE,
3989 eeprom->opcode_bits);
3990 e1000_shift_out_ee_bits(hw, (u16) (offset + i),
3991 eeprom->address_bits);
3992
3993 /* Read the data. For microwire, each word requires the overhead
3994 * of eeprom setup and tear-down. */
3995 data[i] = e1000_shift_in_ee_bits(hw, 16);
3996 e1000_standby_eeprom(hw);
3997 }
3998 }
3999
4000 /* End this read operation */
4001 e1000_release_eeprom(hw);
4002
4003 return E1000_SUCCESS;
4004}
4005
4006/**
4007 * e1000_validate_eeprom_checksum - Verifies that the EEPROM has a valid checksum
4008 * @hw: Struct containing variables accessed by shared code
4009 *
4010 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
4011 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
4012 * valid.
4013 */
4014s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
4015{
4016 u16 checksum = 0;
4017 u16 i, eeprom_data;
4018
4019 e_dbg("e1000_validate_eeprom_checksum");
4020
4021 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
4022 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
4023 e_dbg("EEPROM Read Error\n");
4024 return -E1000_ERR_EEPROM;
4025 }
4026 checksum += eeprom_data;
4027 }
4028
4029 if (checksum == (u16) EEPROM_SUM)
4030 return E1000_SUCCESS;
4031 else {
4032 e_dbg("EEPROM Checksum Invalid\n");
4033 return -E1000_ERR_EEPROM;
4034 }
4035}
4036
4037/**
4038 * e1000_update_eeprom_checksum - Calculates/writes the EEPROM checksum
4039 * @hw: Struct containing variables accessed by shared code
4040 *
4041 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
4042 * Writes the difference to word offset 63 of the EEPROM.
4043 */
4044s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
4045{
4046 u16 checksum = 0;
4047 u16 i, eeprom_data;
4048
4049 e_dbg("e1000_update_eeprom_checksum");
4050
4051 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
4052 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
4053 e_dbg("EEPROM Read Error\n");
4054 return -E1000_ERR_EEPROM;
4055 }
4056 checksum += eeprom_data;
4057 }
4058 checksum = (u16) EEPROM_SUM - checksum;
4059 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
4060 e_dbg("EEPROM Write Error\n");
4061 return -E1000_ERR_EEPROM;
4062 }
4063 return E1000_SUCCESS;
4064}
4065
4066/**
4067 * e1000_write_eeprom - write words to the different EEPROM types.
4068 * @hw: Struct containing variables accessed by shared code
4069 * @offset: offset within the EEPROM to be written to
4070 * @words: number of words to write
4071 * @data: 16 bit word to be written to the EEPROM
4072 *
4073 * If e1000_update_eeprom_checksum is not called after this function, the
4074 * EEPROM will most likely contain an invalid checksum.
4075 */
4076s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
4077{
4078 s32 ret;
4079 spin_lock(&e1000_eeprom_lock);
4080 ret = e1000_do_write_eeprom(hw, offset, words, data);
4081 spin_unlock(&e1000_eeprom_lock);
4082 return ret;
4083}
4084
4085static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
4086 u16 *data)
4087{
4088 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4089 s32 status = 0;
4090
4091 e_dbg("e1000_write_eeprom");
4092
4093 if (hw->mac_type == e1000_ce4100) {
4094 GBE_CONFIG_FLASH_WRITE(GBE_CONFIG_BASE_VIRT, offset, words,
4095 data);
4096 return E1000_SUCCESS;
4097 }
4098
4099 /* If eeprom is not yet detected, do so now */
4100 if (eeprom->word_size == 0)
4101 e1000_init_eeprom_params(hw);
4102
4103 /* A check for invalid values: offset too large, too many words, and not
4104 * enough words.
4105 */
4106 if ((offset >= eeprom->word_size)
4107 || (words > eeprom->word_size - offset) || (words == 0)) {
4108 e_dbg("\"words\" parameter out of bounds\n");
4109 return -E1000_ERR_EEPROM;
4110 }
4111
4112 /* Prepare the EEPROM for writing */
4113 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4114 return -E1000_ERR_EEPROM;
4115
4116 if (eeprom->type == e1000_eeprom_microwire) {
4117 status = e1000_write_eeprom_microwire(hw, offset, words, data);
4118 } else {
4119 status = e1000_write_eeprom_spi(hw, offset, words, data);
4120 msleep(10);
4121 }
4122
4123 /* Done with writing */
4124 e1000_release_eeprom(hw);
4125
4126 return status;
4127}
4128
4129/**
4130 * e1000_write_eeprom_spi - Writes a 16 bit word to a given offset in an SPI EEPROM.
4131 * @hw: Struct containing variables accessed by shared code
4132 * @offset: offset within the EEPROM to be written to
4133 * @words: number of words to write
4134 * @data: pointer to array of 8 bit words to be written to the EEPROM
4135 */
4136static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,
4137 u16 *data)
4138{
4139 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4140 u16 widx = 0;
4141
4142 e_dbg("e1000_write_eeprom_spi");
4143
4144 while (widx < words) {
4145 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI;
4146
4147 if (e1000_spi_eeprom_ready(hw))
4148 return -E1000_ERR_EEPROM;
4149
4150 e1000_standby_eeprom(hw);
4151
4152 /* Send the WRITE ENABLE command (8 bit opcode ) */
4153 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
4154 eeprom->opcode_bits);
4155
4156 e1000_standby_eeprom(hw);
4157
4158 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
4159 if ((eeprom->address_bits == 8) && (offset >= 128))
4160 write_opcode |= EEPROM_A8_OPCODE_SPI;
4161
4162 /* Send the Write command (8-bit opcode + addr) */
4163 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
4164
4165 e1000_shift_out_ee_bits(hw, (u16) ((offset + widx) * 2),
4166 eeprom->address_bits);
4167
4168 /* Send the data */
4169
4170 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
4171 while (widx < words) {
4172 u16 word_out = data[widx];
4173 word_out = (word_out >> 8) | (word_out << 8);
4174 e1000_shift_out_ee_bits(hw, word_out, 16);
4175 widx++;
4176
4177 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
4178 * operation, while the smaller eeproms are capable of an 8-byte
4179 * PAGE WRITE operation. Break the inner loop to pass new address
4180 */
4181 if ((((offset + widx) * 2) % eeprom->page_size) == 0) {
4182 e1000_standby_eeprom(hw);
4183 break;
4184 }
4185 }
4186 }
4187
4188 return E1000_SUCCESS;
4189}
4190
4191/**
4192 * e1000_write_eeprom_microwire - Writes a 16 bit word to a given offset in a Microwire EEPROM.
4193 * @hw: Struct containing variables accessed by shared code
4194 * @offset: offset within the EEPROM to be written to
4195 * @words: number of words to write
4196 * @data: pointer to array of 8 bit words to be written to the EEPROM
4197 */
4198static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
4199 u16 words, u16 *data)
4200{
4201 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4202 u32 eecd;
4203 u16 words_written = 0;
4204 u16 i = 0;
4205
4206 e_dbg("e1000_write_eeprom_microwire");
4207
4208 /* Send the write enable command to the EEPROM (3-bit opcode plus
4209 * 6/8-bit dummy address beginning with 11). It's less work to include
4210 * the 11 of the dummy address as part of the opcode than it is to shift
4211 * it over the correct number of bits for the address. This puts the
4212 * EEPROM into write/erase mode.
4213 */
4214 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
4215 (u16) (eeprom->opcode_bits + 2));
4216
4217 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2));
4218
4219 /* Prepare the EEPROM */
4220 e1000_standby_eeprom(hw);
4221
4222 while (words_written < words) {
4223 /* Send the Write command (3-bit opcode + addr) */
4224 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
4225 eeprom->opcode_bits);
4226
4227 e1000_shift_out_ee_bits(hw, (u16) (offset + words_written),
4228 eeprom->address_bits);
4229
4230 /* Send the data */
4231 e1000_shift_out_ee_bits(hw, data[words_written], 16);
4232
4233 /* Toggle the CS line. This in effect tells the EEPROM to execute
4234 * the previous command.
4235 */
4236 e1000_standby_eeprom(hw);
4237
4238 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
4239 * signal that the command has been completed by raising the DO signal.
4240 * If DO does not go high in 10 milliseconds, then error out.
4241 */
4242 for (i = 0; i < 200; i++) {
4243 eecd = er32(EECD);
4244 if (eecd & E1000_EECD_DO)
4245 break;
4246 udelay(50);
4247 }
4248 if (i == 200) {
4249 e_dbg("EEPROM Write did not complete\n");
4250 return -E1000_ERR_EEPROM;
4251 }
4252
4253 /* Recover from write */
4254 e1000_standby_eeprom(hw);
4255
4256 words_written++;
4257 }
4258
4259 /* Send the write disable command to the EEPROM (3-bit opcode plus
4260 * 6/8-bit dummy address beginning with 10). It's less work to include
4261 * the 10 of the dummy address as part of the opcode than it is to shift
4262 * it over the correct number of bits for the address. This takes the
4263 * EEPROM out of write/erase mode.
4264 */
4265 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
4266 (u16) (eeprom->opcode_bits + 2));
4267
4268 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2));
4269
4270 return E1000_SUCCESS;
4271}
4272
4273/**
4274 * e1000_read_mac_addr - read the adapters MAC from eeprom
4275 * @hw: Struct containing variables accessed by shared code
4276 *
4277 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
4278 * second function of dual function devices
4279 */
4280s32 e1000_read_mac_addr(struct e1000_hw *hw)
4281{
4282 u16 offset;
4283 u16 eeprom_data, i;
4284
4285 e_dbg("e1000_read_mac_addr");
4286
4287 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
4288 offset = i >> 1;
4289 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
4290 e_dbg("EEPROM Read Error\n");
4291 return -E1000_ERR_EEPROM;
4292 }
4293 hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF);
4294 hw->perm_mac_addr[i + 1] = (u8) (eeprom_data >> 8);
4295 }
4296
4297 switch (hw->mac_type) {
4298 default:
4299 break;
4300 case e1000_82546:
4301 case e1000_82546_rev_3:
4302 if (er32(STATUS) & E1000_STATUS_FUNC_1)
4303 hw->perm_mac_addr[5] ^= 0x01;
4304 break;
4305 }
4306
4307 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
4308 hw->mac_addr[i] = hw->perm_mac_addr[i];
4309 return E1000_SUCCESS;
4310}
4311
4312/**
4313 * e1000_init_rx_addrs - Initializes receive address filters.
4314 * @hw: Struct containing variables accessed by shared code
4315 *
4316 * Places the MAC address in receive address register 0 and clears the rest
4317 * of the receive address registers. Clears the multicast table. Assumes
4318 * the receiver is in reset when the routine is called.
4319 */
4320static void e1000_init_rx_addrs(struct e1000_hw *hw)
4321{
4322 u32 i;
4323 u32 rar_num;
4324
4325 e_dbg("e1000_init_rx_addrs");
4326
4327 /* Setup the receive address. */
4328 e_dbg("Programming MAC Address into RAR[0]\n");
4329
4330 e1000_rar_set(hw, hw->mac_addr, 0);
4331
4332 rar_num = E1000_RAR_ENTRIES;
4333
4334 /* Zero out the other 15 receive addresses. */
4335 e_dbg("Clearing RAR[1-15]\n");
4336 for (i = 1; i < rar_num; i++) {
4337 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
4338 E1000_WRITE_FLUSH();
4339 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
4340 E1000_WRITE_FLUSH();
4341 }
4342}
4343
4344/**
4345 * e1000_hash_mc_addr - Hashes an address to determine its location in the multicast table
4346 * @hw: Struct containing variables accessed by shared code
4347 * @mc_addr: the multicast address to hash
4348 */
4349u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
4350{
4351 u32 hash_value = 0;
4352
4353 /* The portion of the address that is used for the hash table is
4354 * determined by the mc_filter_type setting.
4355 */
4356 switch (hw->mc_filter_type) {
4357 /* [0] [1] [2] [3] [4] [5]
4358 * 01 AA 00 12 34 56
4359 * LSB MSB
4360 */
4361 case 0:
4362 /* [47:36] i.e. 0x563 for above example address */
4363 hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
4364 break;
4365 case 1:
4366 /* [46:35] i.e. 0xAC6 for above example address */
4367 hash_value = ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5));
4368 break;
4369 case 2:
4370 /* [45:34] i.e. 0x5D8 for above example address */
4371 hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
4372 break;
4373 case 3:
4374 /* [43:32] i.e. 0x634 for above example address */
4375 hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8));
4376 break;
4377 }
4378
4379 hash_value &= 0xFFF;
4380 return hash_value;
4381}
4382
4383/**
4384 * e1000_rar_set - Puts an ethernet address into a receive address register.
4385 * @hw: Struct containing variables accessed by shared code
4386 * @addr: Address to put into receive address register
4387 * @index: Receive address register to write
4388 */
4389void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
4390{
4391 u32 rar_low, rar_high;
4392
4393 /* HW expects these in little endian so we reverse the byte order
4394 * from network order (big endian) to little endian
4395 */
4396 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
4397 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
4398 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
4399
4400 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
4401 * unit hang.
4402 *
4403 * Description:
4404 * If there are any Rx frames queued up or otherwise present in the HW
4405 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
4406 * hang. To work around this issue, we have to disable receives and
4407 * flush out all Rx frames before we enable RSS. To do so, we modify we
4408 * redirect all Rx traffic to manageability and then reset the HW.
4409 * This flushes away Rx frames, and (since the redirections to
4410 * manageability persists across resets) keeps new ones from coming in
4411 * while we work. Then, we clear the Address Valid AV bit for all MAC
4412 * addresses and undo the re-direction to manageability.
4413 * Now, frames are coming in again, but the MAC won't accept them, so
4414 * far so good. We now proceed to initialize RSS (if necessary) and
4415 * configure the Rx unit. Last, we re-enable the AV bits and continue
4416 * on our merry way.
4417 */
4418 switch (hw->mac_type) {
4419 default:
4420 /* Indicate to hardware the Address is Valid. */
4421 rar_high |= E1000_RAH_AV;
4422 break;
4423 }
4424
4425 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
4426 E1000_WRITE_FLUSH();
4427 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
4428 E1000_WRITE_FLUSH();
4429}
4430
4431/**
4432 * e1000_write_vfta - Writes a value to the specified offset in the VLAN filter table.
4433 * @hw: Struct containing variables accessed by shared code
4434 * @offset: Offset in VLAN filer table to write
4435 * @value: Value to write into VLAN filter table
4436 */
4437void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
4438{
4439 u32 temp;
4440
4441 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
4442 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
4443 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4444 E1000_WRITE_FLUSH();
4445 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
4446 E1000_WRITE_FLUSH();
4447 } else {
4448 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4449 E1000_WRITE_FLUSH();
4450 }
4451}
4452
4453/**
4454 * e1000_clear_vfta - Clears the VLAN filer table
4455 * @hw: Struct containing variables accessed by shared code
4456 */
4457static void e1000_clear_vfta(struct e1000_hw *hw)
4458{
4459 u32 offset;
4460 u32 vfta_value = 0;
4461 u32 vfta_offset = 0;
4462 u32 vfta_bit_in_reg = 0;
4463
4464 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
4465 /* If the offset we want to clear is the same offset of the
4466 * manageability VLAN ID, then clear all bits except that of the
4467 * manageability unit */
4468 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
4469 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
4470 E1000_WRITE_FLUSH();
4471 }
4472}
4473
4474static s32 e1000_id_led_init(struct e1000_hw *hw)
4475{
4476 u32 ledctl;
4477 const u32 ledctl_mask = 0x000000FF;
4478 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
4479 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
4480 u16 eeprom_data, i, temp;
4481 const u16 led_mask = 0x0F;
4482
4483 e_dbg("e1000_id_led_init");
4484
4485 if (hw->mac_type < e1000_82540) {
4486 /* Nothing to do */
4487 return E1000_SUCCESS;
4488 }
4489
4490 ledctl = er32(LEDCTL);
4491 hw->ledctl_default = ledctl;
4492 hw->ledctl_mode1 = hw->ledctl_default;
4493 hw->ledctl_mode2 = hw->ledctl_default;
4494
4495 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
4496 e_dbg("EEPROM Read Error\n");
4497 return -E1000_ERR_EEPROM;
4498 }
4499
4500 if ((eeprom_data == ID_LED_RESERVED_0000) ||
4501 (eeprom_data == ID_LED_RESERVED_FFFF)) {
4502 eeprom_data = ID_LED_DEFAULT;
4503 }
4504
4505 for (i = 0; i < 4; i++) {
4506 temp = (eeprom_data >> (i << 2)) & led_mask;
4507 switch (temp) {
4508 case ID_LED_ON1_DEF2:
4509 case ID_LED_ON1_ON2:
4510 case ID_LED_ON1_OFF2:
4511 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4512 hw->ledctl_mode1 |= ledctl_on << (i << 3);
4513 break;
4514 case ID_LED_OFF1_DEF2:
4515 case ID_LED_OFF1_ON2:
4516 case ID_LED_OFF1_OFF2:
4517 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4518 hw->ledctl_mode1 |= ledctl_off << (i << 3);
4519 break;
4520 default:
4521 /* Do nothing */
4522 break;
4523 }
4524 switch (temp) {
4525 case ID_LED_DEF1_ON2:
4526 case ID_LED_ON1_ON2:
4527 case ID_LED_OFF1_ON2:
4528 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4529 hw->ledctl_mode2 |= ledctl_on << (i << 3);
4530 break;
4531 case ID_LED_DEF1_OFF2:
4532 case ID_LED_ON1_OFF2:
4533 case ID_LED_OFF1_OFF2:
4534 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4535 hw->ledctl_mode2 |= ledctl_off << (i << 3);
4536 break;
4537 default:
4538 /* Do nothing */
4539 break;
4540 }
4541 }
4542 return E1000_SUCCESS;
4543}
4544
4545/**
4546 * e1000_setup_led
4547 * @hw: Struct containing variables accessed by shared code
4548 *
4549 * Prepares SW controlable LED for use and saves the current state of the LED.
4550 */
4551s32 e1000_setup_led(struct e1000_hw *hw)
4552{
4553 u32 ledctl;
4554 s32 ret_val = E1000_SUCCESS;
4555
4556 e_dbg("e1000_setup_led");
4557
4558 switch (hw->mac_type) {
4559 case e1000_82542_rev2_0:
4560 case e1000_82542_rev2_1:
4561 case e1000_82543:
4562 case e1000_82544:
4563 /* No setup necessary */
4564 break;
4565 case e1000_82541:
4566 case e1000_82547:
4567 case e1000_82541_rev_2:
4568 case e1000_82547_rev_2:
4569 /* Turn off PHY Smart Power Down (if enabled) */
4570 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
4571 &hw->phy_spd_default);
4572 if (ret_val)
4573 return ret_val;
4574 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4575 (u16) (hw->phy_spd_default &
4576 ~IGP01E1000_GMII_SPD));
4577 if (ret_val)
4578 return ret_val;
4579 /* Fall Through */
4580 default:
4581 if (hw->media_type == e1000_media_type_fiber) {
4582 ledctl = er32(LEDCTL);
4583 /* Save current LEDCTL settings */
4584 hw->ledctl_default = ledctl;
4585 /* Turn off LED0 */
4586 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
4587 E1000_LEDCTL_LED0_BLINK |
4588 E1000_LEDCTL_LED0_MODE_MASK);
4589 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
4590 E1000_LEDCTL_LED0_MODE_SHIFT);
4591 ew32(LEDCTL, ledctl);
4592 } else if (hw->media_type == e1000_media_type_copper)
4593 ew32(LEDCTL, hw->ledctl_mode1);
4594 break;
4595 }
4596
4597 return E1000_SUCCESS;
4598}
4599
4600/**
4601 * e1000_cleanup_led - Restores the saved state of the SW controlable LED.
4602 * @hw: Struct containing variables accessed by shared code
4603 */
4604s32 e1000_cleanup_led(struct e1000_hw *hw)
4605{
4606 s32 ret_val = E1000_SUCCESS;
4607
4608 e_dbg("e1000_cleanup_led");
4609
4610 switch (hw->mac_type) {
4611 case e1000_82542_rev2_0:
4612 case e1000_82542_rev2_1:
4613 case e1000_82543:
4614 case e1000_82544:
4615 /* No cleanup necessary */
4616 break;
4617 case e1000_82541:
4618 case e1000_82547:
4619 case e1000_82541_rev_2:
4620 case e1000_82547_rev_2:
4621 /* Turn on PHY Smart Power Down (if previously enabled) */
4622 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4623 hw->phy_spd_default);
4624 if (ret_val)
4625 return ret_val;
4626 /* Fall Through */
4627 default:
4628 /* Restore LEDCTL settings */
4629 ew32(LEDCTL, hw->ledctl_default);
4630 break;
4631 }
4632
4633 return E1000_SUCCESS;
4634}
4635
4636/**
4637 * e1000_led_on - Turns on the software controllable LED
4638 * @hw: Struct containing variables accessed by shared code
4639 */
4640s32 e1000_led_on(struct e1000_hw *hw)
4641{
4642 u32 ctrl = er32(CTRL);
4643
4644 e_dbg("e1000_led_on");
4645
4646 switch (hw->mac_type) {
4647 case e1000_82542_rev2_0:
4648 case e1000_82542_rev2_1:
4649 case e1000_82543:
4650 /* Set SW Defineable Pin 0 to turn on the LED */
4651 ctrl |= E1000_CTRL_SWDPIN0;
4652 ctrl |= E1000_CTRL_SWDPIO0;
4653 break;
4654 case e1000_82544:
4655 if (hw->media_type == e1000_media_type_fiber) {
4656 /* Set SW Defineable Pin 0 to turn on the LED */
4657 ctrl |= E1000_CTRL_SWDPIN0;
4658 ctrl |= E1000_CTRL_SWDPIO0;
4659 } else {
4660 /* Clear SW Defineable Pin 0 to turn on the LED */
4661 ctrl &= ~E1000_CTRL_SWDPIN0;
4662 ctrl |= E1000_CTRL_SWDPIO0;
4663 }
4664 break;
4665 default:
4666 if (hw->media_type == e1000_media_type_fiber) {
4667 /* Clear SW Defineable Pin 0 to turn on the LED */
4668 ctrl &= ~E1000_CTRL_SWDPIN0;
4669 ctrl |= E1000_CTRL_SWDPIO0;
4670 } else if (hw->media_type == e1000_media_type_copper) {
4671 ew32(LEDCTL, hw->ledctl_mode2);
4672 return E1000_SUCCESS;
4673 }
4674 break;
4675 }
4676
4677 ew32(CTRL, ctrl);
4678
4679 return E1000_SUCCESS;
4680}
4681
4682/**
4683 * e1000_led_off - Turns off the software controllable LED
4684 * @hw: Struct containing variables accessed by shared code
4685 */
4686s32 e1000_led_off(struct e1000_hw *hw)
4687{
4688 u32 ctrl = er32(CTRL);
4689
4690 e_dbg("e1000_led_off");
4691
4692 switch (hw->mac_type) {
4693 case e1000_82542_rev2_0:
4694 case e1000_82542_rev2_1:
4695 case e1000_82543:
4696 /* Clear SW Defineable Pin 0 to turn off the LED */
4697 ctrl &= ~E1000_CTRL_SWDPIN0;
4698 ctrl |= E1000_CTRL_SWDPIO0;
4699 break;
4700 case e1000_82544:
4701 if (hw->media_type == e1000_media_type_fiber) {
4702 /* Clear SW Defineable Pin 0 to turn off the LED */
4703 ctrl &= ~E1000_CTRL_SWDPIN0;
4704 ctrl |= E1000_CTRL_SWDPIO0;
4705 } else {
4706 /* Set SW Defineable Pin 0 to turn off the LED */
4707 ctrl |= E1000_CTRL_SWDPIN0;
4708 ctrl |= E1000_CTRL_SWDPIO0;
4709 }
4710 break;
4711 default:
4712 if (hw->media_type == e1000_media_type_fiber) {
4713 /* Set SW Defineable Pin 0 to turn off the LED */
4714 ctrl |= E1000_CTRL_SWDPIN0;
4715 ctrl |= E1000_CTRL_SWDPIO0;
4716 } else if (hw->media_type == e1000_media_type_copper) {
4717 ew32(LEDCTL, hw->ledctl_mode1);
4718 return E1000_SUCCESS;
4719 }
4720 break;
4721 }
4722
4723 ew32(CTRL, ctrl);
4724
4725 return E1000_SUCCESS;
4726}
4727
4728/**
4729 * e1000_clear_hw_cntrs - Clears all hardware statistics counters.
4730 * @hw: Struct containing variables accessed by shared code
4731 */
4732static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
4733{
4734 volatile u32 temp;
4735
4736 temp = er32(CRCERRS);
4737 temp = er32(SYMERRS);
4738 temp = er32(MPC);
4739 temp = er32(SCC);
4740 temp = er32(ECOL);
4741 temp = er32(MCC);
4742 temp = er32(LATECOL);
4743 temp = er32(COLC);
4744 temp = er32(DC);
4745 temp = er32(SEC);
4746 temp = er32(RLEC);
4747 temp = er32(XONRXC);
4748 temp = er32(XONTXC);
4749 temp = er32(XOFFRXC);
4750 temp = er32(XOFFTXC);
4751 temp = er32(FCRUC);
4752
4753 temp = er32(PRC64);
4754 temp = er32(PRC127);
4755 temp = er32(PRC255);
4756 temp = er32(PRC511);
4757 temp = er32(PRC1023);
4758 temp = er32(PRC1522);
4759
4760 temp = er32(GPRC);
4761 temp = er32(BPRC);
4762 temp = er32(MPRC);
4763 temp = er32(GPTC);
4764 temp = er32(GORCL);
4765 temp = er32(GORCH);
4766 temp = er32(GOTCL);
4767 temp = er32(GOTCH);
4768 temp = er32(RNBC);
4769 temp = er32(RUC);
4770 temp = er32(RFC);
4771 temp = er32(ROC);
4772 temp = er32(RJC);
4773 temp = er32(TORL);
4774 temp = er32(TORH);
4775 temp = er32(TOTL);
4776 temp = er32(TOTH);
4777 temp = er32(TPR);
4778 temp = er32(TPT);
4779
4780 temp = er32(PTC64);
4781 temp = er32(PTC127);
4782 temp = er32(PTC255);
4783 temp = er32(PTC511);
4784 temp = er32(PTC1023);
4785 temp = er32(PTC1522);
4786
4787 temp = er32(MPTC);
4788 temp = er32(BPTC);
4789
4790 if (hw->mac_type < e1000_82543)
4791 return;
4792
4793 temp = er32(ALGNERRC);
4794 temp = er32(RXERRC);
4795 temp = er32(TNCRS);
4796 temp = er32(CEXTERR);
4797 temp = er32(TSCTC);
4798 temp = er32(TSCTFC);
4799
4800 if (hw->mac_type <= e1000_82544)
4801 return;
4802
4803 temp = er32(MGTPRC);
4804 temp = er32(MGTPDC);
4805 temp = er32(MGTPTC);
4806}
4807
4808/**
4809 * e1000_reset_adaptive - Resets Adaptive IFS to its default state.
4810 * @hw: Struct containing variables accessed by shared code
4811 *
4812 * Call this after e1000_init_hw. You may override the IFS defaults by setting
4813 * hw->ifs_params_forced to true. However, you must initialize hw->
4814 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
4815 * before calling this function.
4816 */
4817void e1000_reset_adaptive(struct e1000_hw *hw)
4818{
4819 e_dbg("e1000_reset_adaptive");
4820
4821 if (hw->adaptive_ifs) {
4822 if (!hw->ifs_params_forced) {
4823 hw->current_ifs_val = 0;
4824 hw->ifs_min_val = IFS_MIN;
4825 hw->ifs_max_val = IFS_MAX;
4826 hw->ifs_step_size = IFS_STEP;
4827 hw->ifs_ratio = IFS_RATIO;
4828 }
4829 hw->in_ifs_mode = false;
4830 ew32(AIT, 0);
4831 } else {
4832 e_dbg("Not in Adaptive IFS mode!\n");
4833 }
4834}
4835
4836/**
4837 * e1000_update_adaptive - update adaptive IFS
4838 * @hw: Struct containing variables accessed by shared code
4839 * @tx_packets: Number of transmits since last callback
4840 * @total_collisions: Number of collisions since last callback
4841 *
4842 * Called during the callback/watchdog routine to update IFS value based on
4843 * the ratio of transmits to collisions.
4844 */
4845void e1000_update_adaptive(struct e1000_hw *hw)
4846{
4847 e_dbg("e1000_update_adaptive");
4848
4849 if (hw->adaptive_ifs) {
4850 if ((hw->collision_delta *hw->ifs_ratio) > hw->tx_packet_delta) {
4851 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
4852 hw->in_ifs_mode = true;
4853 if (hw->current_ifs_val < hw->ifs_max_val) {
4854 if (hw->current_ifs_val == 0)
4855 hw->current_ifs_val =
4856 hw->ifs_min_val;
4857 else
4858 hw->current_ifs_val +=
4859 hw->ifs_step_size;
4860 ew32(AIT, hw->current_ifs_val);
4861 }
4862 }
4863 } else {
4864 if (hw->in_ifs_mode
4865 && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
4866 hw->current_ifs_val = 0;
4867 hw->in_ifs_mode = false;
4868 ew32(AIT, 0);
4869 }
4870 }
4871 } else {
4872 e_dbg("Not in Adaptive IFS mode!\n");
4873 }
4874}
4875
4876/**
4877 * e1000_tbi_adjust_stats
4878 * @hw: Struct containing variables accessed by shared code
4879 * @frame_len: The length of the frame in question
4880 * @mac_addr: The Ethernet destination address of the frame in question
4881 *
4882 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
4883 */
4884void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats,
4885 u32 frame_len, u8 *mac_addr)
4886{
4887 u64 carry_bit;
4888
4889 /* First adjust the frame length. */
4890 frame_len--;
4891 /* We need to adjust the statistics counters, since the hardware
4892 * counters overcount this packet as a CRC error and undercount
4893 * the packet as a good packet
4894 */
4895 /* This packet should not be counted as a CRC error. */
4896 stats->crcerrs--;
4897 /* This packet does count as a Good Packet Received. */
4898 stats->gprc++;
4899
4900 /* Adjust the Good Octets received counters */
4901 carry_bit = 0x80000000 & stats->gorcl;
4902 stats->gorcl += frame_len;
4903 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
4904 * Received Count) was one before the addition,
4905 * AND it is zero after, then we lost the carry out,
4906 * need to add one to Gorch (Good Octets Received Count High).
4907 * This could be simplified if all environments supported
4908 * 64-bit integers.
4909 */
4910 if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
4911 stats->gorch++;
4912 /* Is this a broadcast or multicast? Check broadcast first,
4913 * since the test for a multicast frame will test positive on
4914 * a broadcast frame.
4915 */
4916 if ((mac_addr[0] == (u8) 0xff) && (mac_addr[1] == (u8) 0xff))
4917 /* Broadcast packet */
4918 stats->bprc++;
4919 else if (*mac_addr & 0x01)
4920 /* Multicast packet */
4921 stats->mprc++;
4922
4923 if (frame_len == hw->max_frame_size) {
4924 /* In this case, the hardware has overcounted the number of
4925 * oversize frames.
4926 */
4927 if (stats->roc > 0)
4928 stats->roc--;
4929 }
4930
4931 /* Adjust the bin counters when the extra byte put the frame in the
4932 * wrong bin. Remember that the frame_len was adjusted above.
4933 */
4934 if (frame_len == 64) {
4935 stats->prc64++;
4936 stats->prc127--;
4937 } else if (frame_len == 127) {
4938 stats->prc127++;
4939 stats->prc255--;
4940 } else if (frame_len == 255) {
4941 stats->prc255++;
4942 stats->prc511--;
4943 } else if (frame_len == 511) {
4944 stats->prc511++;
4945 stats->prc1023--;
4946 } else if (frame_len == 1023) {
4947 stats->prc1023++;
4948 stats->prc1522--;
4949 } else if (frame_len == 1522) {
4950 stats->prc1522++;
4951 }
4952}
4953
4954/**
4955 * e1000_get_bus_info
4956 * @hw: Struct containing variables accessed by shared code
4957 *
4958 * Gets the current PCI bus type, speed, and width of the hardware
4959 */
4960void e1000_get_bus_info(struct e1000_hw *hw)
4961{
4962 u32 status;
4963
4964 switch (hw->mac_type) {
4965 case e1000_82542_rev2_0:
4966 case e1000_82542_rev2_1:
4967 hw->bus_type = e1000_bus_type_pci;
4968 hw->bus_speed = e1000_bus_speed_unknown;
4969 hw->bus_width = e1000_bus_width_unknown;
4970 break;
4971 default:
4972 status = er32(STATUS);
4973 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
4974 e1000_bus_type_pcix : e1000_bus_type_pci;
4975
4976 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
4977 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
4978 e1000_bus_speed_66 : e1000_bus_speed_120;
4979 } else if (hw->bus_type == e1000_bus_type_pci) {
4980 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
4981 e1000_bus_speed_66 : e1000_bus_speed_33;
4982 } else {
4983 switch (status & E1000_STATUS_PCIX_SPEED) {
4984 case E1000_STATUS_PCIX_SPEED_66:
4985 hw->bus_speed = e1000_bus_speed_66;
4986 break;
4987 case E1000_STATUS_PCIX_SPEED_100:
4988 hw->bus_speed = e1000_bus_speed_100;
4989 break;
4990 case E1000_STATUS_PCIX_SPEED_133:
4991 hw->bus_speed = e1000_bus_speed_133;
4992 break;
4993 default:
4994 hw->bus_speed = e1000_bus_speed_reserved;
4995 break;
4996 }
4997 }
4998 hw->bus_width = (status & E1000_STATUS_BUS64) ?
4999 e1000_bus_width_64 : e1000_bus_width_32;
5000 break;
5001 }
5002}
5003
5004/**
5005 * e1000_write_reg_io
5006 * @hw: Struct containing variables accessed by shared code
5007 * @offset: offset to write to
5008 * @value: value to write
5009 *
5010 * Writes a value to one of the devices registers using port I/O (as opposed to
5011 * memory mapped I/O). Only 82544 and newer devices support port I/O.
5012 */
5013static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value)
5014{
5015 unsigned long io_addr = hw->io_base;
5016 unsigned long io_data = hw->io_base + 4;
5017
5018 e1000_io_write(hw, io_addr, offset);
5019 e1000_io_write(hw, io_data, value);
5020}
5021
5022/**
5023 * e1000_get_cable_length - Estimates the cable length.
5024 * @hw: Struct containing variables accessed by shared code
5025 * @min_length: The estimated minimum length
5026 * @max_length: The estimated maximum length
5027 *
5028 * returns: - E1000_ERR_XXX
5029 * E1000_SUCCESS
5030 *
5031 * This function always returns a ranged length (minimum & maximum).
5032 * So for M88 phy's, this function interprets the one value returned from the
5033 * register to the minimum and maximum range.
5034 * For IGP phy's, the function calculates the range by the AGC registers.
5035 */
5036static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
5037 u16 *max_length)
5038{
5039 s32 ret_val;
5040 u16 agc_value = 0;
5041 u16 i, phy_data;
5042 u16 cable_length;
5043
5044 e_dbg("e1000_get_cable_length");
5045
5046 *min_length = *max_length = 0;
5047
5048 /* Use old method for Phy older than IGP */
5049 if (hw->phy_type == e1000_phy_m88) {
5050
5051 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5052 &phy_data);
5053 if (ret_val)
5054 return ret_val;
5055 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
5056 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
5057
5058 /* Convert the enum value to ranged values */
5059 switch (cable_length) {
5060 case e1000_cable_length_50:
5061 *min_length = 0;
5062 *max_length = e1000_igp_cable_length_50;
5063 break;
5064 case e1000_cable_length_50_80:
5065 *min_length = e1000_igp_cable_length_50;
5066 *max_length = e1000_igp_cable_length_80;
5067 break;
5068 case e1000_cable_length_80_110:
5069 *min_length = e1000_igp_cable_length_80;
5070 *max_length = e1000_igp_cable_length_110;
5071 break;
5072 case e1000_cable_length_110_140:
5073 *min_length = e1000_igp_cable_length_110;
5074 *max_length = e1000_igp_cable_length_140;
5075 break;
5076 case e1000_cable_length_140:
5077 *min_length = e1000_igp_cable_length_140;
5078 *max_length = e1000_igp_cable_length_170;
5079 break;
5080 default:
5081 return -E1000_ERR_PHY;
5082 break;
5083 }
5084 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
5085 u16 cur_agc_value;
5086 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
5087 static const u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
5088 IGP01E1000_PHY_AGC_A,
5089 IGP01E1000_PHY_AGC_B,
5090 IGP01E1000_PHY_AGC_C,
5091 IGP01E1000_PHY_AGC_D
5092 };
5093 /* Read the AGC registers for all channels */
5094 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5095
5096 ret_val =
5097 e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
5098 if (ret_val)
5099 return ret_val;
5100
5101 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
5102
5103 /* Value bound check. */
5104 if ((cur_agc_value >=
5105 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1)
5106 || (cur_agc_value == 0))
5107 return -E1000_ERR_PHY;
5108
5109 agc_value += cur_agc_value;
5110
5111 /* Update minimal AGC value. */
5112 if (min_agc_value > cur_agc_value)
5113 min_agc_value = cur_agc_value;
5114 }
5115
5116 /* Remove the minimal AGC result for length < 50m */
5117 if (agc_value <
5118 IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
5119 agc_value -= min_agc_value;
5120
5121 /* Get the average length of the remaining 3 channels */
5122 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
5123 } else {
5124 /* Get the average length of all the 4 channels. */
5125 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
5126 }
5127
5128 /* Set the range of the calculated length. */
5129 *min_length = ((e1000_igp_cable_length_table[agc_value] -
5130 IGP01E1000_AGC_RANGE) > 0) ?
5131 (e1000_igp_cable_length_table[agc_value] -
5132 IGP01E1000_AGC_RANGE) : 0;
5133 *max_length = e1000_igp_cable_length_table[agc_value] +
5134 IGP01E1000_AGC_RANGE;
5135 }
5136
5137 return E1000_SUCCESS;
5138}
5139
5140/**
5141 * e1000_check_polarity - Check the cable polarity
5142 * @hw: Struct containing variables accessed by shared code
5143 * @polarity: output parameter : 0 - Polarity is not reversed
5144 * 1 - Polarity is reversed.
5145 *
5146 * returns: - E1000_ERR_XXX
5147 * E1000_SUCCESS
5148 *
5149 * For phy's older than IGP, this function simply reads the polarity bit in the
5150 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
5151 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
5152 * return 0. If the link speed is 1000 Mbps the polarity status is in the
5153 * IGP01E1000_PHY_PCS_INIT_REG.
5154 */
5155static s32 e1000_check_polarity(struct e1000_hw *hw,
5156 e1000_rev_polarity *polarity)
5157{
5158 s32 ret_val;
5159 u16 phy_data;
5160
5161 e_dbg("e1000_check_polarity");
5162
5163 if (hw->phy_type == e1000_phy_m88) {
5164 /* return the Polarity bit in the Status register. */
5165 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5166 &phy_data);
5167 if (ret_val)
5168 return ret_val;
5169 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
5170 M88E1000_PSSR_REV_POLARITY_SHIFT) ?
5171 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
5172
5173 } else if (hw->phy_type == e1000_phy_igp) {
5174 /* Read the Status register to check the speed */
5175 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
5176 &phy_data);
5177 if (ret_val)
5178 return ret_val;
5179
5180 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
5181 * find the polarity status */
5182 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
5183 IGP01E1000_PSSR_SPEED_1000MBPS) {
5184
5185 /* Read the GIG initialization PCS register (0x00B4) */
5186 ret_val =
5187 e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
5188 &phy_data);
5189 if (ret_val)
5190 return ret_val;
5191
5192 /* Check the polarity bits */
5193 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
5194 e1000_rev_polarity_reversed :
5195 e1000_rev_polarity_normal;
5196 } else {
5197 /* For 10 Mbps, read the polarity bit in the status register. (for
5198 * 100 Mbps this bit is always 0) */
5199 *polarity =
5200 (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
5201 e1000_rev_polarity_reversed :
5202 e1000_rev_polarity_normal;
5203 }
5204 }
5205 return E1000_SUCCESS;
5206}
5207
5208/**
5209 * e1000_check_downshift - Check if Downshift occurred
5210 * @hw: Struct containing variables accessed by shared code
5211 * @downshift: output parameter : 0 - No Downshift occurred.
5212 * 1 - Downshift occurred.
5213 *
5214 * returns: - E1000_ERR_XXX
5215 * E1000_SUCCESS
5216 *
5217 * For phy's older than IGP, this function reads the Downshift bit in the Phy
5218 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
5219 * Link Health register. In IGP this bit is latched high, so the driver must
5220 * read it immediately after link is established.
5221 */
5222static s32 e1000_check_downshift(struct e1000_hw *hw)
5223{
5224 s32 ret_val;
5225 u16 phy_data;
5226
5227 e_dbg("e1000_check_downshift");
5228
5229 if (hw->phy_type == e1000_phy_igp) {
5230 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
5231 &phy_data);
5232 if (ret_val)
5233 return ret_val;
5234
5235 hw->speed_downgraded =
5236 (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
5237 } else if (hw->phy_type == e1000_phy_m88) {
5238 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5239 &phy_data);
5240 if (ret_val)
5241 return ret_val;
5242
5243 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
5244 M88E1000_PSSR_DOWNSHIFT_SHIFT;
5245 }
5246
5247 return E1000_SUCCESS;
5248}
5249
5250/**
5251 * e1000_config_dsp_after_link_change
5252 * @hw: Struct containing variables accessed by shared code
5253 * @link_up: was link up at the time this was called
5254 *
5255 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5256 * E1000_SUCCESS at any other case.
5257 *
5258 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
5259 * gigabit link is achieved to improve link quality.
5260 */
5261
5262static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
5263{
5264 s32 ret_val;
5265 u16 phy_data, phy_saved_data, speed, duplex, i;
5266 static const u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
5267 IGP01E1000_PHY_AGC_PARAM_A,
5268 IGP01E1000_PHY_AGC_PARAM_B,
5269 IGP01E1000_PHY_AGC_PARAM_C,
5270 IGP01E1000_PHY_AGC_PARAM_D
5271 };
5272 u16 min_length, max_length;
5273
5274 e_dbg("e1000_config_dsp_after_link_change");
5275
5276 if (hw->phy_type != e1000_phy_igp)
5277 return E1000_SUCCESS;
5278
5279 if (link_up) {
5280 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
5281 if (ret_val) {
5282 e_dbg("Error getting link speed and duplex\n");
5283 return ret_val;
5284 }
5285
5286 if (speed == SPEED_1000) {
5287
5288 ret_val =
5289 e1000_get_cable_length(hw, &min_length,
5290 &max_length);
5291 if (ret_val)
5292 return ret_val;
5293
5294 if ((hw->dsp_config_state == e1000_dsp_config_enabled)
5295 && min_length >= e1000_igp_cable_length_50) {
5296
5297 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5298 ret_val =
5299 e1000_read_phy_reg(hw,
5300 dsp_reg_array[i],
5301 &phy_data);
5302 if (ret_val)
5303 return ret_val;
5304
5305 phy_data &=
5306 ~IGP01E1000_PHY_EDAC_MU_INDEX;
5307
5308 ret_val =
5309 e1000_write_phy_reg(hw,
5310 dsp_reg_array
5311 [i], phy_data);
5312 if (ret_val)
5313 return ret_val;
5314 }
5315 hw->dsp_config_state =
5316 e1000_dsp_config_activated;
5317 }
5318
5319 if ((hw->ffe_config_state == e1000_ffe_config_enabled)
5320 && (min_length < e1000_igp_cable_length_50)) {
5321
5322 u16 ffe_idle_err_timeout =
5323 FFE_IDLE_ERR_COUNT_TIMEOUT_20;
5324 u32 idle_errs = 0;
5325
5326 /* clear previous idle error counts */
5327 ret_val =
5328 e1000_read_phy_reg(hw, PHY_1000T_STATUS,
5329 &phy_data);
5330 if (ret_val)
5331 return ret_val;
5332
5333 for (i = 0; i < ffe_idle_err_timeout; i++) {
5334 udelay(1000);
5335 ret_val =
5336 e1000_read_phy_reg(hw,
5337 PHY_1000T_STATUS,
5338 &phy_data);
5339 if (ret_val)
5340 return ret_val;
5341
5342 idle_errs +=
5343 (phy_data &
5344 SR_1000T_IDLE_ERROR_CNT);
5345 if (idle_errs >
5346 SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT)
5347 {
5348 hw->ffe_config_state =
5349 e1000_ffe_config_active;
5350
5351 ret_val =
5352 e1000_write_phy_reg(hw,
5353 IGP01E1000_PHY_DSP_FFE,
5354 IGP01E1000_PHY_DSP_FFE_CM_CP);
5355 if (ret_val)
5356 return ret_val;
5357 break;
5358 }
5359
5360 if (idle_errs)
5361 ffe_idle_err_timeout =
5362 FFE_IDLE_ERR_COUNT_TIMEOUT_100;
5363 }
5364 }
5365 }
5366 } else {
5367 if (hw->dsp_config_state == e1000_dsp_config_activated) {
5368 /* Save off the current value of register 0x2F5B to be restored at
5369 * the end of the routines. */
5370 ret_val =
5371 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5372
5373 if (ret_val)
5374 return ret_val;
5375
5376 /* Disable the PHY transmitter */
5377 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5378
5379 if (ret_val)
5380 return ret_val;
5381
5382 mdelay(20);
5383
5384 ret_val = e1000_write_phy_reg(hw, 0x0000,
5385 IGP01E1000_IEEE_FORCE_GIGA);
5386 if (ret_val)
5387 return ret_val;
5388 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5389 ret_val =
5390 e1000_read_phy_reg(hw, dsp_reg_array[i],
5391 &phy_data);
5392 if (ret_val)
5393 return ret_val;
5394
5395 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5396 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
5397
5398 ret_val =
5399 e1000_write_phy_reg(hw, dsp_reg_array[i],
5400 phy_data);
5401 if (ret_val)
5402 return ret_val;
5403 }
5404
5405 ret_val = e1000_write_phy_reg(hw, 0x0000,
5406 IGP01E1000_IEEE_RESTART_AUTONEG);
5407 if (ret_val)
5408 return ret_val;
5409
5410 mdelay(20);
5411
5412 /* Now enable the transmitter */
5413 ret_val =
5414 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5415
5416 if (ret_val)
5417 return ret_val;
5418
5419 hw->dsp_config_state = e1000_dsp_config_enabled;
5420 }
5421
5422 if (hw->ffe_config_state == e1000_ffe_config_active) {
5423 /* Save off the current value of register 0x2F5B to be restored at
5424 * the end of the routines. */
5425 ret_val =
5426 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5427
5428 if (ret_val)
5429 return ret_val;
5430
5431 /* Disable the PHY transmitter */
5432 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5433
5434 if (ret_val)
5435 return ret_val;
5436
5437 mdelay(20);
5438
5439 ret_val = e1000_write_phy_reg(hw, 0x0000,
5440 IGP01E1000_IEEE_FORCE_GIGA);
5441 if (ret_val)
5442 return ret_val;
5443 ret_val =
5444 e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
5445 IGP01E1000_PHY_DSP_FFE_DEFAULT);
5446 if (ret_val)
5447 return ret_val;
5448
5449 ret_val = e1000_write_phy_reg(hw, 0x0000,
5450 IGP01E1000_IEEE_RESTART_AUTONEG);
5451 if (ret_val)
5452 return ret_val;
5453
5454 mdelay(20);
5455
5456 /* Now enable the transmitter */
5457 ret_val =
5458 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5459
5460 if (ret_val)
5461 return ret_val;
5462
5463 hw->ffe_config_state = e1000_ffe_config_enabled;
5464 }
5465 }
5466 return E1000_SUCCESS;
5467}
5468
5469/**
5470 * e1000_set_phy_mode - Set PHY to class A mode
5471 * @hw: Struct containing variables accessed by shared code
5472 *
5473 * Assumes the following operations will follow to enable the new class mode.
5474 * 1. Do a PHY soft reset
5475 * 2. Restart auto-negotiation or force link.
5476 */
5477static s32 e1000_set_phy_mode(struct e1000_hw *hw)
5478{
5479 s32 ret_val;
5480 u16 eeprom_data;
5481
5482 e_dbg("e1000_set_phy_mode");
5483
5484 if ((hw->mac_type == e1000_82545_rev_3) &&
5485 (hw->media_type == e1000_media_type_copper)) {
5486 ret_val =
5487 e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1,
5488 &eeprom_data);
5489 if (ret_val) {
5490 return ret_val;
5491 }
5492
5493 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
5494 (eeprom_data & EEPROM_PHY_CLASS_A)) {
5495 ret_val =
5496 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
5497 0x000B);
5498 if (ret_val)
5499 return ret_val;
5500 ret_val =
5501 e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,
5502 0x8104);
5503 if (ret_val)
5504 return ret_val;
5505
5506 hw->phy_reset_disable = false;
5507 }
5508 }
5509
5510 return E1000_SUCCESS;
5511}
5512
5513/**
5514 * e1000_set_d3_lplu_state - set d3 link power state
5515 * @hw: Struct containing variables accessed by shared code
5516 * @active: true to enable lplu false to disable lplu.
5517 *
5518 * This function sets the lplu state according to the active flag. When
5519 * activating lplu this function also disables smart speed and vise versa.
5520 * lplu will not be activated unless the device autonegotiation advertisement
5521 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
5522 *
5523 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5524 * E1000_SUCCESS at any other case.
5525 */
5526static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
5527{
5528 s32 ret_val;
5529 u16 phy_data;
5530 e_dbg("e1000_set_d3_lplu_state");
5531
5532 if (hw->phy_type != e1000_phy_igp)
5533 return E1000_SUCCESS;
5534
5535 /* During driver activity LPLU should not be used or it will attain link
5536 * from the lowest speeds starting from 10Mbps. The capability is used for
5537 * Dx transitions and states */
5538 if (hw->mac_type == e1000_82541_rev_2
5539 || hw->mac_type == e1000_82547_rev_2) {
5540 ret_val =
5541 e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
5542 if (ret_val)
5543 return ret_val;
5544 }
5545
5546 if (!active) {
5547 if (hw->mac_type == e1000_82541_rev_2 ||
5548 hw->mac_type == e1000_82547_rev_2) {
5549 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5550 ret_val =
5551 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5552 phy_data);
5553 if (ret_val)
5554 return ret_val;
5555 }
5556
5557 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
5558 * Dx states where the power conservation is most important. During
5559 * driver activity we should enable SmartSpeed, so performance is
5560 * maintained. */
5561 if (hw->smart_speed == e1000_smart_speed_on) {
5562 ret_val =
5563 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5564 &phy_data);
5565 if (ret_val)
5566 return ret_val;
5567
5568 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
5569 ret_val =
5570 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5571 phy_data);
5572 if (ret_val)
5573 return ret_val;
5574 } else if (hw->smart_speed == e1000_smart_speed_off) {
5575 ret_val =
5576 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5577 &phy_data);
5578 if (ret_val)
5579 return ret_val;
5580
5581 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5582 ret_val =
5583 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5584 phy_data);
5585 if (ret_val)
5586 return ret_val;
5587 }
5588 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
5589 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL)
5590 || (hw->autoneg_advertised ==
5591 AUTONEG_ADVERTISE_10_100_ALL)) {
5592
5593 if (hw->mac_type == e1000_82541_rev_2 ||
5594 hw->mac_type == e1000_82547_rev_2) {
5595 phy_data |= IGP01E1000_GMII_FLEX_SPD;
5596 ret_val =
5597 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5598 phy_data);
5599 if (ret_val)
5600 return ret_val;
5601 }
5602
5603 /* When LPLU is enabled we should disable SmartSpeed */
5604 ret_val =
5605 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5606 &phy_data);
5607 if (ret_val)
5608 return ret_val;
5609
5610 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5611 ret_val =
5612 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5613 phy_data);
5614 if (ret_val)
5615 return ret_val;
5616
5617 }
5618 return E1000_SUCCESS;
5619}
5620
5621/**
5622 * e1000_set_vco_speed
5623 * @hw: Struct containing variables accessed by shared code
5624 *
5625 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
5626 */
5627static s32 e1000_set_vco_speed(struct e1000_hw *hw)
5628{
5629 s32 ret_val;
5630 u16 default_page = 0;
5631 u16 phy_data;
5632
5633 e_dbg("e1000_set_vco_speed");
5634
5635 switch (hw->mac_type) {
5636 case e1000_82545_rev_3:
5637 case e1000_82546_rev_3:
5638 break;
5639 default:
5640 return E1000_SUCCESS;
5641 }
5642
5643 /* Set PHY register 30, page 5, bit 8 to 0 */
5644
5645 ret_val =
5646 e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
5647 if (ret_val)
5648 return ret_val;
5649
5650 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
5651 if (ret_val)
5652 return ret_val;
5653
5654 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5655 if (ret_val)
5656 return ret_val;
5657
5658 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
5659 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5660 if (ret_val)
5661 return ret_val;
5662
5663 /* Set PHY register 30, page 4, bit 11 to 1 */
5664
5665 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
5666 if (ret_val)
5667 return ret_val;
5668
5669 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5670 if (ret_val)
5671 return ret_val;
5672
5673 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
5674 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5675 if (ret_val)
5676 return ret_val;
5677
5678 ret_val =
5679 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
5680 if (ret_val)
5681 return ret_val;
5682
5683 return E1000_SUCCESS;
5684}
5685
5686
5687/**
5688 * e1000_enable_mng_pass_thru - check for bmc pass through
5689 * @hw: Struct containing variables accessed by shared code
5690 *
5691 * Verifies the hardware needs to allow ARPs to be processed by the host
5692 * returns: - true/false
5693 */
5694u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
5695{
5696 u32 manc;
5697
5698 if (hw->asf_firmware_present) {
5699 manc = er32(MANC);
5700
5701 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
5702 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
5703 return false;
5704 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
5705 return true;
5706 }
5707 return false;
5708}
5709
5710static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
5711{
5712 s32 ret_val;
5713 u16 mii_status_reg;
5714 u16 i;
5715
5716 /* Polarity reversal workaround for forced 10F/10H links. */
5717
5718 /* Disable the transmitter on the PHY */
5719
5720 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5721 if (ret_val)
5722 return ret_val;
5723 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
5724 if (ret_val)
5725 return ret_val;
5726
5727 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5728 if (ret_val)
5729 return ret_val;
5730
5731 /* This loop will early-out if the NO link condition has been met. */
5732 for (i = PHY_FORCE_TIME; i > 0; i--) {
5733 /* Read the MII Status Register and wait for Link Status bit
5734 * to be clear.
5735 */
5736
5737 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5738 if (ret_val)
5739 return ret_val;
5740
5741 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5742 if (ret_val)
5743 return ret_val;
5744
5745 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0)
5746 break;
5747 mdelay(100);
5748 }
5749
5750 /* Recommended delay time after link has been lost */
5751 mdelay(1000);
5752
5753 /* Now we will re-enable th transmitter on the PHY */
5754
5755 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5756 if (ret_val)
5757 return ret_val;
5758 mdelay(50);
5759 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
5760 if (ret_val)
5761 return ret_val;
5762 mdelay(50);
5763 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
5764 if (ret_val)
5765 return ret_val;
5766 mdelay(50);
5767 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
5768 if (ret_val)
5769 return ret_val;
5770
5771 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5772 if (ret_val)
5773 return ret_val;
5774
5775 /* This loop will early-out if the link condition has been met. */
5776 for (i = PHY_FORCE_TIME; i > 0; i--) {
5777 /* Read the MII Status Register and wait for Link Status bit
5778 * to be set.
5779 */
5780
5781 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5782 if (ret_val)
5783 return ret_val;
5784
5785 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5786 if (ret_val)
5787 return ret_val;
5788
5789 if (mii_status_reg & MII_SR_LINK_STATUS)
5790 break;
5791 mdelay(100);
5792 }
5793 return E1000_SUCCESS;
5794}
5795
5796/**
5797 * e1000_get_auto_rd_done
5798 * @hw: Struct containing variables accessed by shared code
5799 *
5800 * Check for EEPROM Auto Read bit done.
5801 * returns: - E1000_ERR_RESET if fail to reset MAC
5802 * E1000_SUCCESS at any other case.
5803 */
5804static s32 e1000_get_auto_rd_done(struct e1000_hw *hw)
5805{
5806 e_dbg("e1000_get_auto_rd_done");
5807 msleep(5);
5808 return E1000_SUCCESS;
5809}
5810
5811/**
5812 * e1000_get_phy_cfg_done
5813 * @hw: Struct containing variables accessed by shared code
5814 *
5815 * Checks if the PHY configuration is done
5816 * returns: - E1000_ERR_RESET if fail to reset MAC
5817 * E1000_SUCCESS at any other case.
5818 */
5819static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
5820{
5821 e_dbg("e1000_get_phy_cfg_done");
5822 mdelay(10);
5823 return E1000_SUCCESS;
5824}
diff --git a/drivers/net/ethernet/intel/e1000/e1000_hw.h b/drivers/net/ethernet/intel/e1000/e1000_hw.h
new file mode 100644
index 000000000000..5c9a8403668b
--- /dev/null
+++ b/drivers/net/ethernet/intel/e1000/e1000_hw.h
@@ -0,0 +1,3103 @@
1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* e1000_hw.h
30 * Structures, enums, and macros for the MAC
31 */
32
33#ifndef _E1000_HW_H_
34#define _E1000_HW_H_
35
36#include "e1000_osdep.h"
37
38
39/* Forward declarations of structures used by the shared code */
40struct e1000_hw;
41struct e1000_hw_stats;
42
43/* Enumerated types specific to the e1000 hardware */
44/* Media Access Controllers */
45typedef enum {
46 e1000_undefined = 0,
47 e1000_82542_rev2_0,
48 e1000_82542_rev2_1,
49 e1000_82543,
50 e1000_82544,
51 e1000_82540,
52 e1000_82545,
53 e1000_82545_rev_3,
54 e1000_82546,
55 e1000_ce4100,
56 e1000_82546_rev_3,
57 e1000_82541,
58 e1000_82541_rev_2,
59 e1000_82547,
60 e1000_82547_rev_2,
61 e1000_num_macs
62} e1000_mac_type;
63
64typedef enum {
65 e1000_eeprom_uninitialized = 0,
66 e1000_eeprom_spi,
67 e1000_eeprom_microwire,
68 e1000_eeprom_flash,
69 e1000_eeprom_none, /* No NVM support */
70 e1000_num_eeprom_types
71} e1000_eeprom_type;
72
73/* Media Types */
74typedef enum {
75 e1000_media_type_copper = 0,
76 e1000_media_type_fiber = 1,
77 e1000_media_type_internal_serdes = 2,
78 e1000_num_media_types
79} e1000_media_type;
80
81typedef enum {
82 e1000_10_half = 0,
83 e1000_10_full = 1,
84 e1000_100_half = 2,
85 e1000_100_full = 3
86} e1000_speed_duplex_type;
87
88/* Flow Control Settings */
89typedef enum {
90 E1000_FC_NONE = 0,
91 E1000_FC_RX_PAUSE = 1,
92 E1000_FC_TX_PAUSE = 2,
93 E1000_FC_FULL = 3,
94 E1000_FC_DEFAULT = 0xFF
95} e1000_fc_type;
96
97struct e1000_shadow_ram {
98 u16 eeprom_word;
99 bool modified;
100};
101
102/* PCI bus types */
103typedef enum {
104 e1000_bus_type_unknown = 0,
105 e1000_bus_type_pci,
106 e1000_bus_type_pcix,
107 e1000_bus_type_reserved
108} e1000_bus_type;
109
110/* PCI bus speeds */
111typedef enum {
112 e1000_bus_speed_unknown = 0,
113 e1000_bus_speed_33,
114 e1000_bus_speed_66,
115 e1000_bus_speed_100,
116 e1000_bus_speed_120,
117 e1000_bus_speed_133,
118 e1000_bus_speed_reserved
119} e1000_bus_speed;
120
121/* PCI bus widths */
122typedef enum {
123 e1000_bus_width_unknown = 0,
124 e1000_bus_width_32,
125 e1000_bus_width_64,
126 e1000_bus_width_reserved
127} e1000_bus_width;
128
129/* PHY status info structure and supporting enums */
130typedef enum {
131 e1000_cable_length_50 = 0,
132 e1000_cable_length_50_80,
133 e1000_cable_length_80_110,
134 e1000_cable_length_110_140,
135 e1000_cable_length_140,
136 e1000_cable_length_undefined = 0xFF
137} e1000_cable_length;
138
139typedef enum {
140 e1000_gg_cable_length_60 = 0,
141 e1000_gg_cable_length_60_115 = 1,
142 e1000_gg_cable_length_115_150 = 2,
143 e1000_gg_cable_length_150 = 4
144} e1000_gg_cable_length;
145
146typedef enum {
147 e1000_igp_cable_length_10 = 10,
148 e1000_igp_cable_length_20 = 20,
149 e1000_igp_cable_length_30 = 30,
150 e1000_igp_cable_length_40 = 40,
151 e1000_igp_cable_length_50 = 50,
152 e1000_igp_cable_length_60 = 60,
153 e1000_igp_cable_length_70 = 70,
154 e1000_igp_cable_length_80 = 80,
155 e1000_igp_cable_length_90 = 90,
156 e1000_igp_cable_length_100 = 100,
157 e1000_igp_cable_length_110 = 110,
158 e1000_igp_cable_length_115 = 115,
159 e1000_igp_cable_length_120 = 120,
160 e1000_igp_cable_length_130 = 130,
161 e1000_igp_cable_length_140 = 140,
162 e1000_igp_cable_length_150 = 150,
163 e1000_igp_cable_length_160 = 160,
164 e1000_igp_cable_length_170 = 170,
165 e1000_igp_cable_length_180 = 180
166} e1000_igp_cable_length;
167
168typedef enum {
169 e1000_10bt_ext_dist_enable_normal = 0,
170 e1000_10bt_ext_dist_enable_lower,
171 e1000_10bt_ext_dist_enable_undefined = 0xFF
172} e1000_10bt_ext_dist_enable;
173
174typedef enum {
175 e1000_rev_polarity_normal = 0,
176 e1000_rev_polarity_reversed,
177 e1000_rev_polarity_undefined = 0xFF
178} e1000_rev_polarity;
179
180typedef enum {
181 e1000_downshift_normal = 0,
182 e1000_downshift_activated,
183 e1000_downshift_undefined = 0xFF
184} e1000_downshift;
185
186typedef enum {
187 e1000_smart_speed_default = 0,
188 e1000_smart_speed_on,
189 e1000_smart_speed_off
190} e1000_smart_speed;
191
192typedef enum {
193 e1000_polarity_reversal_enabled = 0,
194 e1000_polarity_reversal_disabled,
195 e1000_polarity_reversal_undefined = 0xFF
196} e1000_polarity_reversal;
197
198typedef enum {
199 e1000_auto_x_mode_manual_mdi = 0,
200 e1000_auto_x_mode_manual_mdix,
201 e1000_auto_x_mode_auto1,
202 e1000_auto_x_mode_auto2,
203 e1000_auto_x_mode_undefined = 0xFF
204} e1000_auto_x_mode;
205
206typedef enum {
207 e1000_1000t_rx_status_not_ok = 0,
208 e1000_1000t_rx_status_ok,
209 e1000_1000t_rx_status_undefined = 0xFF
210} e1000_1000t_rx_status;
211
212typedef enum {
213 e1000_phy_m88 = 0,
214 e1000_phy_igp,
215 e1000_phy_8211,
216 e1000_phy_8201,
217 e1000_phy_undefined = 0xFF
218} e1000_phy_type;
219
220typedef enum {
221 e1000_ms_hw_default = 0,
222 e1000_ms_force_master,
223 e1000_ms_force_slave,
224 e1000_ms_auto
225} e1000_ms_type;
226
227typedef enum {
228 e1000_ffe_config_enabled = 0,
229 e1000_ffe_config_active,
230 e1000_ffe_config_blocked
231} e1000_ffe_config;
232
233typedef enum {
234 e1000_dsp_config_disabled = 0,
235 e1000_dsp_config_enabled,
236 e1000_dsp_config_activated,
237 e1000_dsp_config_undefined = 0xFF
238} e1000_dsp_config;
239
240struct e1000_phy_info {
241 e1000_cable_length cable_length;
242 e1000_10bt_ext_dist_enable extended_10bt_distance;
243 e1000_rev_polarity cable_polarity;
244 e1000_downshift downshift;
245 e1000_polarity_reversal polarity_correction;
246 e1000_auto_x_mode mdix_mode;
247 e1000_1000t_rx_status local_rx;
248 e1000_1000t_rx_status remote_rx;
249};
250
251struct e1000_phy_stats {
252 u32 idle_errors;
253 u32 receive_errors;
254};
255
256struct e1000_eeprom_info {
257 e1000_eeprom_type type;
258 u16 word_size;
259 u16 opcode_bits;
260 u16 address_bits;
261 u16 delay_usec;
262 u16 page_size;
263};
264
265/* Flex ASF Information */
266#define E1000_HOST_IF_MAX_SIZE 2048
267
268typedef enum {
269 e1000_byte_align = 0,
270 e1000_word_align = 1,
271 e1000_dword_align = 2
272} e1000_align_type;
273
274/* Error Codes */
275#define E1000_SUCCESS 0
276#define E1000_ERR_EEPROM 1
277#define E1000_ERR_PHY 2
278#define E1000_ERR_CONFIG 3
279#define E1000_ERR_PARAM 4
280#define E1000_ERR_MAC_TYPE 5
281#define E1000_ERR_PHY_TYPE 6
282#define E1000_ERR_RESET 9
283#define E1000_ERR_MASTER_REQUESTS_PENDING 10
284#define E1000_ERR_HOST_INTERFACE_COMMAND 11
285#define E1000_BLK_PHY_RESET 12
286
287#define E1000_BYTE_SWAP_WORD(_value) ((((_value) & 0x00ff) << 8) | \
288 (((_value) & 0xff00) >> 8))
289
290/* Function prototypes */
291/* Initialization */
292s32 e1000_reset_hw(struct e1000_hw *hw);
293s32 e1000_init_hw(struct e1000_hw *hw);
294s32 e1000_set_mac_type(struct e1000_hw *hw);
295void e1000_set_media_type(struct e1000_hw *hw);
296
297/* Link Configuration */
298s32 e1000_setup_link(struct e1000_hw *hw);
299s32 e1000_phy_setup_autoneg(struct e1000_hw *hw);
300void e1000_config_collision_dist(struct e1000_hw *hw);
301s32 e1000_check_for_link(struct e1000_hw *hw);
302s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 * speed, u16 * duplex);
303s32 e1000_force_mac_fc(struct e1000_hw *hw);
304
305/* PHY */
306s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 * phy_data);
307s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 data);
308s32 e1000_phy_hw_reset(struct e1000_hw *hw);
309s32 e1000_phy_reset(struct e1000_hw *hw);
310s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
311s32 e1000_validate_mdi_setting(struct e1000_hw *hw);
312
313/* EEPROM Functions */
314s32 e1000_init_eeprom_params(struct e1000_hw *hw);
315
316/* MNG HOST IF functions */
317u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw);
318
319#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
320#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */
321
322#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */
323#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */
324#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */
325#define E1000_MNG_IAMT_MODE 0x3
326#define E1000_MNG_ICH_IAMT_MODE 0x2
327#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */
328
329#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */
330#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT 0x2 /* DHCP parsing enabled */
331#define E1000_VFTA_ENTRY_SHIFT 0x5
332#define E1000_VFTA_ENTRY_MASK 0x7F
333#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
334
335struct e1000_host_mng_command_header {
336 u8 command_id;
337 u8 checksum;
338 u16 reserved1;
339 u16 reserved2;
340 u16 command_length;
341};
342
343struct e1000_host_mng_command_info {
344 struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
345 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658 */
346};
347#ifdef __BIG_ENDIAN
348struct e1000_host_mng_dhcp_cookie {
349 u32 signature;
350 u16 vlan_id;
351 u8 reserved0;
352 u8 status;
353 u32 reserved1;
354 u8 checksum;
355 u8 reserved3;
356 u16 reserved2;
357};
358#else
359struct e1000_host_mng_dhcp_cookie {
360 u32 signature;
361 u8 status;
362 u8 reserved0;
363 u16 vlan_id;
364 u32 reserved1;
365 u16 reserved2;
366 u8 reserved3;
367 u8 checksum;
368};
369#endif
370
371bool e1000_check_mng_mode(struct e1000_hw *hw);
372s32 e1000_read_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 * data);
373s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw);
374s32 e1000_update_eeprom_checksum(struct e1000_hw *hw);
375s32 e1000_write_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 * data);
376s32 e1000_read_mac_addr(struct e1000_hw *hw);
377
378/* Filters (multicast, vlan, receive) */
379u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 * mc_addr);
380void e1000_mta_set(struct e1000_hw *hw, u32 hash_value);
381void e1000_rar_set(struct e1000_hw *hw, u8 * mc_addr, u32 rar_index);
382void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value);
383
384/* LED functions */
385s32 e1000_setup_led(struct e1000_hw *hw);
386s32 e1000_cleanup_led(struct e1000_hw *hw);
387s32 e1000_led_on(struct e1000_hw *hw);
388s32 e1000_led_off(struct e1000_hw *hw);
389s32 e1000_blink_led_start(struct e1000_hw *hw);
390
391/* Adaptive IFS Functions */
392
393/* Everything else */
394void e1000_reset_adaptive(struct e1000_hw *hw);
395void e1000_update_adaptive(struct e1000_hw *hw);
396void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats,
397 u32 frame_len, u8 * mac_addr);
398void e1000_get_bus_info(struct e1000_hw *hw);
399void e1000_pci_set_mwi(struct e1000_hw *hw);
400void e1000_pci_clear_mwi(struct e1000_hw *hw);
401void e1000_pcix_set_mmrbc(struct e1000_hw *hw, int mmrbc);
402int e1000_pcix_get_mmrbc(struct e1000_hw *hw);
403/* Port I/O is only supported on 82544 and newer */
404void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value);
405
406#define E1000_READ_REG_IO(a, reg) \
407 e1000_read_reg_io((a), E1000_##reg)
408#define E1000_WRITE_REG_IO(a, reg, val) \
409 e1000_write_reg_io((a), E1000_##reg, val)
410
411/* PCI Device IDs */
412#define E1000_DEV_ID_82542 0x1000
413#define E1000_DEV_ID_82543GC_FIBER 0x1001
414#define E1000_DEV_ID_82543GC_COPPER 0x1004
415#define E1000_DEV_ID_82544EI_COPPER 0x1008
416#define E1000_DEV_ID_82544EI_FIBER 0x1009
417#define E1000_DEV_ID_82544GC_COPPER 0x100C
418#define E1000_DEV_ID_82544GC_LOM 0x100D
419#define E1000_DEV_ID_82540EM 0x100E
420#define E1000_DEV_ID_82540EM_LOM 0x1015
421#define E1000_DEV_ID_82540EP_LOM 0x1016
422#define E1000_DEV_ID_82540EP 0x1017
423#define E1000_DEV_ID_82540EP_LP 0x101E
424#define E1000_DEV_ID_82545EM_COPPER 0x100F
425#define E1000_DEV_ID_82545EM_FIBER 0x1011
426#define E1000_DEV_ID_82545GM_COPPER 0x1026
427#define E1000_DEV_ID_82545GM_FIBER 0x1027
428#define E1000_DEV_ID_82545GM_SERDES 0x1028
429#define E1000_DEV_ID_82546EB_COPPER 0x1010
430#define E1000_DEV_ID_82546EB_FIBER 0x1012
431#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
432#define E1000_DEV_ID_82541EI 0x1013
433#define E1000_DEV_ID_82541EI_MOBILE 0x1018
434#define E1000_DEV_ID_82541ER_LOM 0x1014
435#define E1000_DEV_ID_82541ER 0x1078
436#define E1000_DEV_ID_82547GI 0x1075
437#define E1000_DEV_ID_82541GI 0x1076
438#define E1000_DEV_ID_82541GI_MOBILE 0x1077
439#define E1000_DEV_ID_82541GI_LF 0x107C
440#define E1000_DEV_ID_82546GB_COPPER 0x1079
441#define E1000_DEV_ID_82546GB_FIBER 0x107A
442#define E1000_DEV_ID_82546GB_SERDES 0x107B
443#define E1000_DEV_ID_82546GB_PCIE 0x108A
444#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
445#define E1000_DEV_ID_82547EI 0x1019
446#define E1000_DEV_ID_82547EI_MOBILE 0x101A
447#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
448#define E1000_DEV_ID_INTEL_CE4100_GBE 0x2E6E
449
450#define NODE_ADDRESS_SIZE 6
451#define ETH_LENGTH_OF_ADDRESS 6
452
453/* MAC decode size is 128K - This is the size of BAR0 */
454#define MAC_DECODE_SIZE (128 * 1024)
455
456#define E1000_82542_2_0_REV_ID 2
457#define E1000_82542_2_1_REV_ID 3
458#define E1000_REVISION_0 0
459#define E1000_REVISION_1 1
460#define E1000_REVISION_2 2
461#define E1000_REVISION_3 3
462
463#define SPEED_10 10
464#define SPEED_100 100
465#define SPEED_1000 1000
466#define HALF_DUPLEX 1
467#define FULL_DUPLEX 2
468
469/* The sizes (in bytes) of a ethernet packet */
470#define ENET_HEADER_SIZE 14
471#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
472#define ETHERNET_FCS_SIZE 4
473#define MINIMUM_ETHERNET_PACKET_SIZE \
474 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
475#define CRC_LENGTH ETHERNET_FCS_SIZE
476#define MAX_JUMBO_FRAME_SIZE 0x3F00
477
478/* 802.1q VLAN Packet Sizes */
479#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */
480
481/* Ethertype field values */
482#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
483#define ETHERNET_IP_TYPE 0x0800 /* IP packets */
484#define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */
485
486/* Packet Header defines */
487#define IP_PROTOCOL_TCP 6
488#define IP_PROTOCOL_UDP 0x11
489
490/* This defines the bits that are set in the Interrupt Mask
491 * Set/Read Register. Each bit is documented below:
492 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
493 * o RXSEQ = Receive Sequence Error
494 */
495#define POLL_IMS_ENABLE_MASK ( \
496 E1000_IMS_RXDMT0 | \
497 E1000_IMS_RXSEQ)
498
499/* This defines the bits that are set in the Interrupt Mask
500 * Set/Read Register. Each bit is documented below:
501 * o RXT0 = Receiver Timer Interrupt (ring 0)
502 * o TXDW = Transmit Descriptor Written Back
503 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
504 * o RXSEQ = Receive Sequence Error
505 * o LSC = Link Status Change
506 */
507#define IMS_ENABLE_MASK ( \
508 E1000_IMS_RXT0 | \
509 E1000_IMS_TXDW | \
510 E1000_IMS_RXDMT0 | \
511 E1000_IMS_RXSEQ | \
512 E1000_IMS_LSC)
513
514/* Number of high/low register pairs in the RAR. The RAR (Receive Address
515 * Registers) holds the directed and multicast addresses that we monitor. We
516 * reserve one of these spots for our directed address, allowing us room for
517 * E1000_RAR_ENTRIES - 1 multicast addresses.
518 */
519#define E1000_RAR_ENTRIES 15
520
521#define MIN_NUMBER_OF_DESCRIPTORS 8
522#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
523
524/* Receive Descriptor */
525struct e1000_rx_desc {
526 __le64 buffer_addr; /* Address of the descriptor's data buffer */
527 __le16 length; /* Length of data DMAed into data buffer */
528 __le16 csum; /* Packet checksum */
529 u8 status; /* Descriptor status */
530 u8 errors; /* Descriptor Errors */
531 __le16 special;
532};
533
534/* Receive Descriptor - Extended */
535union e1000_rx_desc_extended {
536 struct {
537 __le64 buffer_addr;
538 __le64 reserved;
539 } read;
540 struct {
541 struct {
542 __le32 mrq; /* Multiple Rx Queues */
543 union {
544 __le32 rss; /* RSS Hash */
545 struct {
546 __le16 ip_id; /* IP id */
547 __le16 csum; /* Packet Checksum */
548 } csum_ip;
549 } hi_dword;
550 } lower;
551 struct {
552 __le32 status_error; /* ext status/error */
553 __le16 length;
554 __le16 vlan; /* VLAN tag */
555 } upper;
556 } wb; /* writeback */
557};
558
559#define MAX_PS_BUFFERS 4
560/* Receive Descriptor - Packet Split */
561union e1000_rx_desc_packet_split {
562 struct {
563 /* one buffer for protocol header(s), three data buffers */
564 __le64 buffer_addr[MAX_PS_BUFFERS];
565 } read;
566 struct {
567 struct {
568 __le32 mrq; /* Multiple Rx Queues */
569 union {
570 __le32 rss; /* RSS Hash */
571 struct {
572 __le16 ip_id; /* IP id */
573 __le16 csum; /* Packet Checksum */
574 } csum_ip;
575 } hi_dword;
576 } lower;
577 struct {
578 __le32 status_error; /* ext status/error */
579 __le16 length0; /* length of buffer 0 */
580 __le16 vlan; /* VLAN tag */
581 } middle;
582 struct {
583 __le16 header_status;
584 __le16 length[3]; /* length of buffers 1-3 */
585 } upper;
586 __le64 reserved;
587 } wb; /* writeback */
588};
589
590/* Receive Descriptor bit definitions */
591#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
592#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
593#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
594#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
595#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
596#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
597#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
598#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
599#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
600#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
601#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
602#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
603#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
604#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
605#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
606#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
607#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
608#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
609#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
610#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
611#define E1000_RXD_SPC_PRI_SHIFT 13
612#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
613#define E1000_RXD_SPC_CFI_SHIFT 12
614
615#define E1000_RXDEXT_STATERR_CE 0x01000000
616#define E1000_RXDEXT_STATERR_SE 0x02000000
617#define E1000_RXDEXT_STATERR_SEQ 0x04000000
618#define E1000_RXDEXT_STATERR_CXE 0x10000000
619#define E1000_RXDEXT_STATERR_TCPE 0x20000000
620#define E1000_RXDEXT_STATERR_IPE 0x40000000
621#define E1000_RXDEXT_STATERR_RXE 0x80000000
622
623#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
624#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
625
626/* mask to determine if packets should be dropped due to frame errors */
627#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
628 E1000_RXD_ERR_CE | \
629 E1000_RXD_ERR_SE | \
630 E1000_RXD_ERR_SEQ | \
631 E1000_RXD_ERR_CXE | \
632 E1000_RXD_ERR_RXE)
633
634/* Same mask, but for extended and packet split descriptors */
635#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
636 E1000_RXDEXT_STATERR_CE | \
637 E1000_RXDEXT_STATERR_SE | \
638 E1000_RXDEXT_STATERR_SEQ | \
639 E1000_RXDEXT_STATERR_CXE | \
640 E1000_RXDEXT_STATERR_RXE)
641
642/* Transmit Descriptor */
643struct e1000_tx_desc {
644 __le64 buffer_addr; /* Address of the descriptor's data buffer */
645 union {
646 __le32 data;
647 struct {
648 __le16 length; /* Data buffer length */
649 u8 cso; /* Checksum offset */
650 u8 cmd; /* Descriptor control */
651 } flags;
652 } lower;
653 union {
654 __le32 data;
655 struct {
656 u8 status; /* Descriptor status */
657 u8 css; /* Checksum start */
658 __le16 special;
659 } fields;
660 } upper;
661};
662
663/* Transmit Descriptor bit definitions */
664#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
665#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
666#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
667#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
668#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
669#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
670#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
671#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
672#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
673#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
674#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
675#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
676#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
677#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
678#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
679#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
680#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
681#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
682#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
683#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
684
685/* Offload Context Descriptor */
686struct e1000_context_desc {
687 union {
688 __le32 ip_config;
689 struct {
690 u8 ipcss; /* IP checksum start */
691 u8 ipcso; /* IP checksum offset */
692 __le16 ipcse; /* IP checksum end */
693 } ip_fields;
694 } lower_setup;
695 union {
696 __le32 tcp_config;
697 struct {
698 u8 tucss; /* TCP checksum start */
699 u8 tucso; /* TCP checksum offset */
700 __le16 tucse; /* TCP checksum end */
701 } tcp_fields;
702 } upper_setup;
703 __le32 cmd_and_length; /* */
704 union {
705 __le32 data;
706 struct {
707 u8 status; /* Descriptor status */
708 u8 hdr_len; /* Header length */
709 __le16 mss; /* Maximum segment size */
710 } fields;
711 } tcp_seg_setup;
712};
713
714/* Offload data descriptor */
715struct e1000_data_desc {
716 __le64 buffer_addr; /* Address of the descriptor's buffer address */
717 union {
718 __le32 data;
719 struct {
720 __le16 length; /* Data buffer length */
721 u8 typ_len_ext; /* */
722 u8 cmd; /* */
723 } flags;
724 } lower;
725 union {
726 __le32 data;
727 struct {
728 u8 status; /* Descriptor status */
729 u8 popts; /* Packet Options */
730 __le16 special; /* */
731 } fields;
732 } upper;
733};
734
735/* Filters */
736#define E1000_NUM_UNICAST 16 /* Unicast filter entries */
737#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
738#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
739
740/* Receive Address Register */
741struct e1000_rar {
742 volatile __le32 low; /* receive address low */
743 volatile __le32 high; /* receive address high */
744};
745
746/* Number of entries in the Multicast Table Array (MTA). */
747#define E1000_NUM_MTA_REGISTERS 128
748
749/* IPv4 Address Table Entry */
750struct e1000_ipv4_at_entry {
751 volatile u32 ipv4_addr; /* IP Address (RW) */
752 volatile u32 reserved;
753};
754
755/* Four wakeup IP addresses are supported */
756#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
757#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
758#define E1000_IP6AT_SIZE 1
759
760/* IPv6 Address Table Entry */
761struct e1000_ipv6_at_entry {
762 volatile u8 ipv6_addr[16];
763};
764
765/* Flexible Filter Length Table Entry */
766struct e1000_fflt_entry {
767 volatile u32 length; /* Flexible Filter Length (RW) */
768 volatile u32 reserved;
769};
770
771/* Flexible Filter Mask Table Entry */
772struct e1000_ffmt_entry {
773 volatile u32 mask; /* Flexible Filter Mask (RW) */
774 volatile u32 reserved;
775};
776
777/* Flexible Filter Value Table Entry */
778struct e1000_ffvt_entry {
779 volatile u32 value; /* Flexible Filter Value (RW) */
780 volatile u32 reserved;
781};
782
783/* Four Flexible Filters are supported */
784#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
785
786/* Each Flexible Filter is at most 128 (0x80) bytes in length */
787#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
788
789#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
790#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
791#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
792
793#define E1000_DISABLE_SERDES_LOOPBACK 0x0400
794
795/* Register Set. (82543, 82544)
796 *
797 * Registers are defined to be 32 bits and should be accessed as 32 bit values.
798 * These registers are physically located on the NIC, but are mapped into the
799 * host memory address space.
800 *
801 * RW - register is both readable and writable
802 * RO - register is read only
803 * WO - register is write only
804 * R/clr - register is read only and is cleared when read
805 * A - register array
806 */
807#define E1000_CTRL 0x00000 /* Device Control - RW */
808#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
809#define E1000_STATUS 0x00008 /* Device Status - RO */
810#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
811#define E1000_EERD 0x00014 /* EEPROM Read - RW */
812#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
813#define E1000_FLA 0x0001C /* Flash Access - RW */
814#define E1000_MDIC 0x00020 /* MDI Control - RW */
815
816extern void __iomem *ce4100_gbe_mdio_base_virt;
817#define INTEL_CE_GBE_MDIO_RCOMP_BASE (ce4100_gbe_mdio_base_virt)
818#define E1000_MDIO_STS (INTEL_CE_GBE_MDIO_RCOMP_BASE + 0)
819#define E1000_MDIO_CMD (INTEL_CE_GBE_MDIO_RCOMP_BASE + 4)
820#define E1000_MDIO_DRV (INTEL_CE_GBE_MDIO_RCOMP_BASE + 8)
821#define E1000_MDC_CMD (INTEL_CE_GBE_MDIO_RCOMP_BASE + 0xC)
822#define E1000_RCOMP_CTL (INTEL_CE_GBE_MDIO_RCOMP_BASE + 0x20)
823#define E1000_RCOMP_STS (INTEL_CE_GBE_MDIO_RCOMP_BASE + 0x24)
824
825#define E1000_SCTL 0x00024 /* SerDes Control - RW */
826#define E1000_FEXTNVM 0x00028 /* Future Extended NVM register */
827#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
828#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
829#define E1000_FCT 0x00030 /* Flow Control Type - RW */
830#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
831#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
832#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
833#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
834#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
835#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
836#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
837
838/* Auxiliary Control Register. This register is CE4100 specific,
839 * RMII/RGMII function is switched by this register - RW
840 * Following are bits definitions of the Auxiliary Control Register
841 */
842#define E1000_CTL_AUX 0x000E0
843#define E1000_CTL_AUX_END_SEL_SHIFT 10
844#define E1000_CTL_AUX_ENDIANESS_SHIFT 8
845#define E1000_CTL_AUX_RGMII_RMII_SHIFT 0
846
847/* descriptor and packet transfer use CTL_AUX.ENDIANESS */
848#define E1000_CTL_AUX_DES_PKT (0x0 << E1000_CTL_AUX_END_SEL_SHIFT)
849/* descriptor use CTL_AUX.ENDIANESS, packet use default */
850#define E1000_CTL_AUX_DES (0x1 << E1000_CTL_AUX_END_SEL_SHIFT)
851/* descriptor use default, packet use CTL_AUX.ENDIANESS */
852#define E1000_CTL_AUX_PKT (0x2 << E1000_CTL_AUX_END_SEL_SHIFT)
853/* all use CTL_AUX.ENDIANESS */
854#define E1000_CTL_AUX_ALL (0x3 << E1000_CTL_AUX_END_SEL_SHIFT)
855
856#define E1000_CTL_AUX_RGMII (0x0 << E1000_CTL_AUX_RGMII_RMII_SHIFT)
857#define E1000_CTL_AUX_RMII (0x1 << E1000_CTL_AUX_RGMII_RMII_SHIFT)
858
859/* LW little endian, Byte big endian */
860#define E1000_CTL_AUX_LWLE_BBE (0x0 << E1000_CTL_AUX_ENDIANESS_SHIFT)
861#define E1000_CTL_AUX_LWLE_BLE (0x1 << E1000_CTL_AUX_ENDIANESS_SHIFT)
862#define E1000_CTL_AUX_LWBE_BBE (0x2 << E1000_CTL_AUX_ENDIANESS_SHIFT)
863#define E1000_CTL_AUX_LWBE_BLE (0x3 << E1000_CTL_AUX_ENDIANESS_SHIFT)
864
865#define E1000_RCTL 0x00100 /* RX Control - RW */
866#define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */
867#define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */
868#define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */
869#define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */
870#define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */
871#define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */
872#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
873#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
874#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
875#define E1000_TCTL 0x00400 /* TX Control - RW */
876#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */
877#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
878#define E1000_TBT 0x00448 /* TX Burst Timer - RW */
879#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
880#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
881#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
882#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
883#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
884#define FEXTNVM_SW_CONFIG 0x0001
885#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
886#define E1000_PBS 0x01008 /* Packet Buffer Size */
887#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
888#define E1000_FLASH_UPDATES 1000
889#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
890#define E1000_FLASHT 0x01028 /* FLASH Timer Register */
891#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
892#define E1000_FLSWCTL 0x01030 /* FLASH control register */
893#define E1000_FLSWDATA 0x01034 /* FLASH data register */
894#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
895#define E1000_FLOP 0x0103C /* FLASH Opcode Register */
896#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
897#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
898#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
899#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
900#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
901#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
902#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
903#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
904#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
905#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
906#define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */
907#define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */
908#define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */
909#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */
910#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */
911#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */
912#define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */
913#define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */
914#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
915#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
916#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
917#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
918#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
919#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
920#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
921#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
922#define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
923#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
924#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
925#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
926#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
927#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
928#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
929#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
930#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
931#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
932#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
933#define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */
934#define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */
935#define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */
936#define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */
937#define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */
938#define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */
939#define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */
940#define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */
941#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
942#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
943#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
944#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
945#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
946#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
947#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
948#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
949#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
950#define E1000_COLC 0x04028 /* Collision Count - R/clr */
951#define E1000_DC 0x04030 /* Defer Count - R/clr */
952#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
953#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
954#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
955#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
956#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
957#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
958#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
959#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
960#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
961#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
962#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
963#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
964#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
965#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
966#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
967#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
968#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
969#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
970#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
971#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
972#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
973#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
974#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
975#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
976#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
977#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
978#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
979#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
980#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
981#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
982#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
983#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
984#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
985#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
986#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
987#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
988#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
989#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
990#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
991#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
992#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
993#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
994#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
995#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
996#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
997#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
998#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
999#define E1000_IAC 0x04100 /* Interrupt Assertion Count */
1000#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */
1001#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */
1002#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */
1003#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */
1004#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */
1005#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */
1006#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */
1007#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */
1008#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
1009#define E1000_RFCTL 0x05008 /* Receive Filter Control */
1010#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
1011#define E1000_RA 0x05400 /* Receive Address - RW Array */
1012#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
1013#define E1000_WUC 0x05800 /* Wakeup Control - RW */
1014#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
1015#define E1000_WUS 0x05810 /* Wakeup Status - RO */
1016#define E1000_MANC 0x05820 /* Management Control - RW */
1017#define E1000_IPAV 0x05838 /* IP Address Valid - RW */
1018#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
1019#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
1020#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
1021#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
1022#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
1023#define E1000_HOST_IF 0x08800 /* Host Interface */
1024#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
1025#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
1026
1027#define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */
1028#define E1000_MDPHYA 0x0003C /* PHY address - RW */
1029#define E1000_MANC2H 0x05860 /* Management Control To Host - RW */
1030#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
1031
1032#define E1000_GCR 0x05B00 /* PCI-Ex Control */
1033#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
1034#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
1035#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
1036#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
1037#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
1038#define E1000_SWSM 0x05B50 /* SW Semaphore */
1039#define E1000_FWSM 0x05B54 /* FW Semaphore */
1040#define E1000_FFLT_DBG 0x05F04 /* Debug Register */
1041#define E1000_HICR 0x08F00 /* Host Interface Control */
1042
1043/* RSS registers */
1044#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */
1045#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
1046#define E1000_RETA 0x05C00 /* Redirection Table - RW Array */
1047#define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */
1048#define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */
1049#define E1000_RSSIR 0x05868 /* RSS Interrupt Request */
1050/* Register Set (82542)
1051 *
1052 * Some of the 82542 registers are located at different offsets than they are
1053 * in more current versions of the 8254x. Despite the difference in location,
1054 * the registers function in the same manner.
1055 */
1056#define E1000_82542_CTL_AUX E1000_CTL_AUX
1057#define E1000_82542_CTRL E1000_CTRL
1058#define E1000_82542_CTRL_DUP E1000_CTRL_DUP
1059#define E1000_82542_STATUS E1000_STATUS
1060#define E1000_82542_EECD E1000_EECD
1061#define E1000_82542_EERD E1000_EERD
1062#define E1000_82542_CTRL_EXT E1000_CTRL_EXT
1063#define E1000_82542_FLA E1000_FLA
1064#define E1000_82542_MDIC E1000_MDIC
1065#define E1000_82542_SCTL E1000_SCTL
1066#define E1000_82542_FEXTNVM E1000_FEXTNVM
1067#define E1000_82542_FCAL E1000_FCAL
1068#define E1000_82542_FCAH E1000_FCAH
1069#define E1000_82542_FCT E1000_FCT
1070#define E1000_82542_VET E1000_VET
1071#define E1000_82542_RA 0x00040
1072#define E1000_82542_ICR E1000_ICR
1073#define E1000_82542_ITR E1000_ITR
1074#define E1000_82542_ICS E1000_ICS
1075#define E1000_82542_IMS E1000_IMS
1076#define E1000_82542_IMC E1000_IMC
1077#define E1000_82542_RCTL E1000_RCTL
1078#define E1000_82542_RDTR 0x00108
1079#define E1000_82542_RDBAL 0x00110
1080#define E1000_82542_RDBAH 0x00114
1081#define E1000_82542_RDLEN 0x00118
1082#define E1000_82542_RDH 0x00120
1083#define E1000_82542_RDT 0x00128
1084#define E1000_82542_RDTR0 E1000_82542_RDTR
1085#define E1000_82542_RDBAL0 E1000_82542_RDBAL
1086#define E1000_82542_RDBAH0 E1000_82542_RDBAH
1087#define E1000_82542_RDLEN0 E1000_82542_RDLEN
1088#define E1000_82542_RDH0 E1000_82542_RDH
1089#define E1000_82542_RDT0 E1000_82542_RDT
1090#define E1000_82542_SRRCTL(_n) (0x280C + ((_n) << 8)) /* Split and Replication
1091 * RX Control - RW */
1092#define E1000_82542_DCA_RXCTRL(_n) (0x02814 + ((_n) << 8))
1093#define E1000_82542_RDBAH3 0x02B04 /* RX Desc Base High Queue 3 - RW */
1094#define E1000_82542_RDBAL3 0x02B00 /* RX Desc Low Queue 3 - RW */
1095#define E1000_82542_RDLEN3 0x02B08 /* RX Desc Length Queue 3 - RW */
1096#define E1000_82542_RDH3 0x02B10 /* RX Desc Head Queue 3 - RW */
1097#define E1000_82542_RDT3 0x02B18 /* RX Desc Tail Queue 3 - RW */
1098#define E1000_82542_RDBAL2 0x02A00 /* RX Desc Base Low Queue 2 - RW */
1099#define E1000_82542_RDBAH2 0x02A04 /* RX Desc Base High Queue 2 - RW */
1100#define E1000_82542_RDLEN2 0x02A08 /* RX Desc Length Queue 2 - RW */
1101#define E1000_82542_RDH2 0x02A10 /* RX Desc Head Queue 2 - RW */
1102#define E1000_82542_RDT2 0x02A18 /* RX Desc Tail Queue 2 - RW */
1103#define E1000_82542_RDTR1 0x00130
1104#define E1000_82542_RDBAL1 0x00138
1105#define E1000_82542_RDBAH1 0x0013C
1106#define E1000_82542_RDLEN1 0x00140
1107#define E1000_82542_RDH1 0x00148
1108#define E1000_82542_RDT1 0x00150
1109#define E1000_82542_FCRTH 0x00160
1110#define E1000_82542_FCRTL 0x00168
1111#define E1000_82542_FCTTV E1000_FCTTV
1112#define E1000_82542_TXCW E1000_TXCW
1113#define E1000_82542_RXCW E1000_RXCW
1114#define E1000_82542_MTA 0x00200
1115#define E1000_82542_TCTL E1000_TCTL
1116#define E1000_82542_TCTL_EXT E1000_TCTL_EXT
1117#define E1000_82542_TIPG E1000_TIPG
1118#define E1000_82542_TDBAL 0x00420
1119#define E1000_82542_TDBAH 0x00424
1120#define E1000_82542_TDLEN 0x00428
1121#define E1000_82542_TDH 0x00430
1122#define E1000_82542_TDT 0x00438
1123#define E1000_82542_TIDV 0x00440
1124#define E1000_82542_TBT E1000_TBT
1125#define E1000_82542_AIT E1000_AIT
1126#define E1000_82542_VFTA 0x00600
1127#define E1000_82542_LEDCTL E1000_LEDCTL
1128#define E1000_82542_PBA E1000_PBA
1129#define E1000_82542_PBS E1000_PBS
1130#define E1000_82542_EEMNGCTL E1000_EEMNGCTL
1131#define E1000_82542_EEARBC E1000_EEARBC
1132#define E1000_82542_FLASHT E1000_FLASHT
1133#define E1000_82542_EEWR E1000_EEWR
1134#define E1000_82542_FLSWCTL E1000_FLSWCTL
1135#define E1000_82542_FLSWDATA E1000_FLSWDATA
1136#define E1000_82542_FLSWCNT E1000_FLSWCNT
1137#define E1000_82542_FLOP E1000_FLOP
1138#define E1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL
1139#define E1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE
1140#define E1000_82542_PHY_CTRL E1000_PHY_CTRL
1141#define E1000_82542_ERT E1000_ERT
1142#define E1000_82542_RXDCTL E1000_RXDCTL
1143#define E1000_82542_RXDCTL1 E1000_RXDCTL1
1144#define E1000_82542_RADV E1000_RADV
1145#define E1000_82542_RSRPD E1000_RSRPD
1146#define E1000_82542_TXDMAC E1000_TXDMAC
1147#define E1000_82542_KABGTXD E1000_KABGTXD
1148#define E1000_82542_TDFHS E1000_TDFHS
1149#define E1000_82542_TDFTS E1000_TDFTS
1150#define E1000_82542_TDFPC E1000_TDFPC
1151#define E1000_82542_TXDCTL E1000_TXDCTL
1152#define E1000_82542_TADV E1000_TADV
1153#define E1000_82542_TSPMT E1000_TSPMT
1154#define E1000_82542_CRCERRS E1000_CRCERRS
1155#define E1000_82542_ALGNERRC E1000_ALGNERRC
1156#define E1000_82542_SYMERRS E1000_SYMERRS
1157#define E1000_82542_RXERRC E1000_RXERRC
1158#define E1000_82542_MPC E1000_MPC
1159#define E1000_82542_SCC E1000_SCC
1160#define E1000_82542_ECOL E1000_ECOL
1161#define E1000_82542_MCC E1000_MCC
1162#define E1000_82542_LATECOL E1000_LATECOL
1163#define E1000_82542_COLC E1000_COLC
1164#define E1000_82542_DC E1000_DC
1165#define E1000_82542_TNCRS E1000_TNCRS
1166#define E1000_82542_SEC E1000_SEC
1167#define E1000_82542_CEXTERR E1000_CEXTERR
1168#define E1000_82542_RLEC E1000_RLEC
1169#define E1000_82542_XONRXC E1000_XONRXC
1170#define E1000_82542_XONTXC E1000_XONTXC
1171#define E1000_82542_XOFFRXC E1000_XOFFRXC
1172#define E1000_82542_XOFFTXC E1000_XOFFTXC
1173#define E1000_82542_FCRUC E1000_FCRUC
1174#define E1000_82542_PRC64 E1000_PRC64
1175#define E1000_82542_PRC127 E1000_PRC127
1176#define E1000_82542_PRC255 E1000_PRC255
1177#define E1000_82542_PRC511 E1000_PRC511
1178#define E1000_82542_PRC1023 E1000_PRC1023
1179#define E1000_82542_PRC1522 E1000_PRC1522
1180#define E1000_82542_GPRC E1000_GPRC
1181#define E1000_82542_BPRC E1000_BPRC
1182#define E1000_82542_MPRC E1000_MPRC
1183#define E1000_82542_GPTC E1000_GPTC
1184#define E1000_82542_GORCL E1000_GORCL
1185#define E1000_82542_GORCH E1000_GORCH
1186#define E1000_82542_GOTCL E1000_GOTCL
1187#define E1000_82542_GOTCH E1000_GOTCH
1188#define E1000_82542_RNBC E1000_RNBC
1189#define E1000_82542_RUC E1000_RUC
1190#define E1000_82542_RFC E1000_RFC
1191#define E1000_82542_ROC E1000_ROC
1192#define E1000_82542_RJC E1000_RJC
1193#define E1000_82542_MGTPRC E1000_MGTPRC
1194#define E1000_82542_MGTPDC E1000_MGTPDC
1195#define E1000_82542_MGTPTC E1000_MGTPTC
1196#define E1000_82542_TORL E1000_TORL
1197#define E1000_82542_TORH E1000_TORH
1198#define E1000_82542_TOTL E1000_TOTL
1199#define E1000_82542_TOTH E1000_TOTH
1200#define E1000_82542_TPR E1000_TPR
1201#define E1000_82542_TPT E1000_TPT
1202#define E1000_82542_PTC64 E1000_PTC64
1203#define E1000_82542_PTC127 E1000_PTC127
1204#define E1000_82542_PTC255 E1000_PTC255
1205#define E1000_82542_PTC511 E1000_PTC511
1206#define E1000_82542_PTC1023 E1000_PTC1023
1207#define E1000_82542_PTC1522 E1000_PTC1522
1208#define E1000_82542_MPTC E1000_MPTC
1209#define E1000_82542_BPTC E1000_BPTC
1210#define E1000_82542_TSCTC E1000_TSCTC
1211#define E1000_82542_TSCTFC E1000_TSCTFC
1212#define E1000_82542_RXCSUM E1000_RXCSUM
1213#define E1000_82542_WUC E1000_WUC
1214#define E1000_82542_WUFC E1000_WUFC
1215#define E1000_82542_WUS E1000_WUS
1216#define E1000_82542_MANC E1000_MANC
1217#define E1000_82542_IPAV E1000_IPAV
1218#define E1000_82542_IP4AT E1000_IP4AT
1219#define E1000_82542_IP6AT E1000_IP6AT
1220#define E1000_82542_WUPL E1000_WUPL
1221#define E1000_82542_WUPM E1000_WUPM
1222#define E1000_82542_FFLT E1000_FFLT
1223#define E1000_82542_TDFH 0x08010
1224#define E1000_82542_TDFT 0x08018
1225#define E1000_82542_FFMT E1000_FFMT
1226#define E1000_82542_FFVT E1000_FFVT
1227#define E1000_82542_HOST_IF E1000_HOST_IF
1228#define E1000_82542_IAM E1000_IAM
1229#define E1000_82542_EEMNGCTL E1000_EEMNGCTL
1230#define E1000_82542_PSRCTL E1000_PSRCTL
1231#define E1000_82542_RAID E1000_RAID
1232#define E1000_82542_TARC0 E1000_TARC0
1233#define E1000_82542_TDBAL1 E1000_TDBAL1
1234#define E1000_82542_TDBAH1 E1000_TDBAH1
1235#define E1000_82542_TDLEN1 E1000_TDLEN1
1236#define E1000_82542_TDH1 E1000_TDH1
1237#define E1000_82542_TDT1 E1000_TDT1
1238#define E1000_82542_TXDCTL1 E1000_TXDCTL1
1239#define E1000_82542_TARC1 E1000_TARC1
1240#define E1000_82542_RFCTL E1000_RFCTL
1241#define E1000_82542_GCR E1000_GCR
1242#define E1000_82542_GSCL_1 E1000_GSCL_1
1243#define E1000_82542_GSCL_2 E1000_GSCL_2
1244#define E1000_82542_GSCL_3 E1000_GSCL_3
1245#define E1000_82542_GSCL_4 E1000_GSCL_4
1246#define E1000_82542_FACTPS E1000_FACTPS
1247#define E1000_82542_SWSM E1000_SWSM
1248#define E1000_82542_FWSM E1000_FWSM
1249#define E1000_82542_FFLT_DBG E1000_FFLT_DBG
1250#define E1000_82542_IAC E1000_IAC
1251#define E1000_82542_ICRXPTC E1000_ICRXPTC
1252#define E1000_82542_ICRXATC E1000_ICRXATC
1253#define E1000_82542_ICTXPTC E1000_ICTXPTC
1254#define E1000_82542_ICTXATC E1000_ICTXATC
1255#define E1000_82542_ICTXQEC E1000_ICTXQEC
1256#define E1000_82542_ICTXQMTC E1000_ICTXQMTC
1257#define E1000_82542_ICRXDMTC E1000_ICRXDMTC
1258#define E1000_82542_ICRXOC E1000_ICRXOC
1259#define E1000_82542_HICR E1000_HICR
1260
1261#define E1000_82542_CPUVEC E1000_CPUVEC
1262#define E1000_82542_MRQC E1000_MRQC
1263#define E1000_82542_RETA E1000_RETA
1264#define E1000_82542_RSSRK E1000_RSSRK
1265#define E1000_82542_RSSIM E1000_RSSIM
1266#define E1000_82542_RSSIR E1000_RSSIR
1267#define E1000_82542_KUMCTRLSTA E1000_KUMCTRLSTA
1268#define E1000_82542_SW_FW_SYNC E1000_SW_FW_SYNC
1269
1270/* Statistics counters collected by the MAC */
1271struct e1000_hw_stats {
1272 u64 crcerrs;
1273 u64 algnerrc;
1274 u64 symerrs;
1275 u64 rxerrc;
1276 u64 txerrc;
1277 u64 mpc;
1278 u64 scc;
1279 u64 ecol;
1280 u64 mcc;
1281 u64 latecol;
1282 u64 colc;
1283 u64 dc;
1284 u64 tncrs;
1285 u64 sec;
1286 u64 cexterr;
1287 u64 rlec;
1288 u64 xonrxc;
1289 u64 xontxc;
1290 u64 xoffrxc;
1291 u64 xofftxc;
1292 u64 fcruc;
1293 u64 prc64;
1294 u64 prc127;
1295 u64 prc255;
1296 u64 prc511;
1297 u64 prc1023;
1298 u64 prc1522;
1299 u64 gprc;
1300 u64 bprc;
1301 u64 mprc;
1302 u64 gptc;
1303 u64 gorcl;
1304 u64 gorch;
1305 u64 gotcl;
1306 u64 gotch;
1307 u64 rnbc;
1308 u64 ruc;
1309 u64 rfc;
1310 u64 roc;
1311 u64 rlerrc;
1312 u64 rjc;
1313 u64 mgprc;
1314 u64 mgpdc;
1315 u64 mgptc;
1316 u64 torl;
1317 u64 torh;
1318 u64 totl;
1319 u64 toth;
1320 u64 tpr;
1321 u64 tpt;
1322 u64 ptc64;
1323 u64 ptc127;
1324 u64 ptc255;
1325 u64 ptc511;
1326 u64 ptc1023;
1327 u64 ptc1522;
1328 u64 mptc;
1329 u64 bptc;
1330 u64 tsctc;
1331 u64 tsctfc;
1332 u64 iac;
1333 u64 icrxptc;
1334 u64 icrxatc;
1335 u64 ictxptc;
1336 u64 ictxatc;
1337 u64 ictxqec;
1338 u64 ictxqmtc;
1339 u64 icrxdmtc;
1340 u64 icrxoc;
1341};
1342
1343/* Structure containing variables used by the shared code (e1000_hw.c) */
1344struct e1000_hw {
1345 u8 __iomem *hw_addr;
1346 u8 __iomem *flash_address;
1347 e1000_mac_type mac_type;
1348 e1000_phy_type phy_type;
1349 u32 phy_init_script;
1350 e1000_media_type media_type;
1351 void *back;
1352 struct e1000_shadow_ram *eeprom_shadow_ram;
1353 u32 flash_bank_size;
1354 u32 flash_base_addr;
1355 e1000_fc_type fc;
1356 e1000_bus_speed bus_speed;
1357 e1000_bus_width bus_width;
1358 e1000_bus_type bus_type;
1359 struct e1000_eeprom_info eeprom;
1360 e1000_ms_type master_slave;
1361 e1000_ms_type original_master_slave;
1362 e1000_ffe_config ffe_config_state;
1363 u32 asf_firmware_present;
1364 u32 eeprom_semaphore_present;
1365 unsigned long io_base;
1366 u32 phy_id;
1367 u32 phy_revision;
1368 u32 phy_addr;
1369 u32 original_fc;
1370 u32 txcw;
1371 u32 autoneg_failed;
1372 u32 max_frame_size;
1373 u32 min_frame_size;
1374 u32 mc_filter_type;
1375 u32 num_mc_addrs;
1376 u32 collision_delta;
1377 u32 tx_packet_delta;
1378 u32 ledctl_default;
1379 u32 ledctl_mode1;
1380 u32 ledctl_mode2;
1381 bool tx_pkt_filtering;
1382 struct e1000_host_mng_dhcp_cookie mng_cookie;
1383 u16 phy_spd_default;
1384 u16 autoneg_advertised;
1385 u16 pci_cmd_word;
1386 u16 fc_high_water;
1387 u16 fc_low_water;
1388 u16 fc_pause_time;
1389 u16 current_ifs_val;
1390 u16 ifs_min_val;
1391 u16 ifs_max_val;
1392 u16 ifs_step_size;
1393 u16 ifs_ratio;
1394 u16 device_id;
1395 u16 vendor_id;
1396 u16 subsystem_id;
1397 u16 subsystem_vendor_id;
1398 u8 revision_id;
1399 u8 autoneg;
1400 u8 mdix;
1401 u8 forced_speed_duplex;
1402 u8 wait_autoneg_complete;
1403 u8 dma_fairness;
1404 u8 mac_addr[NODE_ADDRESS_SIZE];
1405 u8 perm_mac_addr[NODE_ADDRESS_SIZE];
1406 bool disable_polarity_correction;
1407 bool speed_downgraded;
1408 e1000_smart_speed smart_speed;
1409 e1000_dsp_config dsp_config_state;
1410 bool get_link_status;
1411 bool serdes_has_link;
1412 bool tbi_compatibility_en;
1413 bool tbi_compatibility_on;
1414 bool laa_is_present;
1415 bool phy_reset_disable;
1416 bool initialize_hw_bits_disable;
1417 bool fc_send_xon;
1418 bool fc_strict_ieee;
1419 bool report_tx_early;
1420 bool adaptive_ifs;
1421 bool ifs_params_forced;
1422 bool in_ifs_mode;
1423 bool mng_reg_access_disabled;
1424 bool leave_av_bit_off;
1425 bool bad_tx_carr_stats_fd;
1426 bool has_smbus;
1427};
1428
1429#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
1430#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
1431#define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */
1432#define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
1433#define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */
1434#define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1435#define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */
1436#define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */
1437/* Register Bit Masks */
1438/* Device Control */
1439#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
1440#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
1441#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
1442#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
1443#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
1444#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
1445#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
1446#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
1447#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
1448#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
1449#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
1450#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
1451#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
1452#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
1453#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
1454#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
1455#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
1456#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */
1457#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */
1458#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */
1459#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */
1460#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
1461#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
1462#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
1463#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
1464#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
1465#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
1466#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
1467#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
1468#define E1000_CTRL_RST 0x04000000 /* Global reset */
1469#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
1470#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
1471#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
1472#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
1473#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
1474#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */
1475
1476/* Device Status */
1477#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
1478#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
1479#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
1480#define E1000_STATUS_FUNC_SHIFT 2
1481#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
1482#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
1483#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
1484#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
1485#define E1000_STATUS_SPEED_MASK 0x000000C0
1486#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
1487#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
1488#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
1489#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion
1490 by EEPROM/Flash */
1491#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
1492#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */
1493#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
1494#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
1495#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
1496#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
1497#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
1498#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
1499#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */
1500#define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */
1501#define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */
1502#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */
1503#define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution disabled */
1504#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */
1505#define E1000_STATUS_FUSE_8 0x04000000
1506#define E1000_STATUS_FUSE_9 0x08000000
1507#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */
1508#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */
1509
1510/* Constants used to interpret the masked PCI-X bus speed. */
1511#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
1512#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
1513#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
1514
1515/* EEPROM/Flash Control */
1516#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */
1517#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */
1518#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */
1519#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */
1520#define E1000_EECD_FWE_MASK 0x00000030
1521#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
1522#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
1523#define E1000_EECD_FWE_SHIFT 4
1524#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */
1525#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */
1526#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */
1527#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
1528#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
1529 * (0-small, 1-large) */
1530#define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
1531#ifndef E1000_EEPROM_GRANT_ATTEMPTS
1532#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1533#endif
1534#define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */
1535#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */
1536#define E1000_EECD_SIZE_EX_SHIFT 11
1537#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
1538#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
1539#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
1540#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1541#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
1542#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
1543#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
1544#define E1000_EECD_SECVAL_SHIFT 22
1545#define E1000_STM_OPCODE 0xDB00
1546#define E1000_HICR_FW_RESET 0xC0
1547
1548#define E1000_SHADOW_RAM_WORDS 2048
1549#define E1000_ICH_NVM_SIG_WORD 0x13
1550#define E1000_ICH_NVM_SIG_MASK 0xC0
1551
1552/* EEPROM Read */
1553#define E1000_EERD_START 0x00000001 /* Start Read */
1554#define E1000_EERD_DONE 0x00000010 /* Read Done */
1555#define E1000_EERD_ADDR_SHIFT 8
1556#define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */
1557#define E1000_EERD_DATA_SHIFT 16
1558#define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */
1559
1560/* SPI EEPROM Status Register */
1561#define EEPROM_STATUS_RDY_SPI 0x01
1562#define EEPROM_STATUS_WEN_SPI 0x02
1563#define EEPROM_STATUS_BP0_SPI 0x04
1564#define EEPROM_STATUS_BP1_SPI 0x08
1565#define EEPROM_STATUS_WPEN_SPI 0x80
1566
1567/* Extended Device Control */
1568#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
1569#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
1570#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
1571#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
1572#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
1573#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
1574#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
1575#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
1576#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
1577#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
1578#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
1579#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
1580#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
1581#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
1582#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
1583#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
1584#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
1585#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
1586#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
1587#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
1588#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
1589#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
1590#define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000
1591#define E1000_CTRL_EXT_LINK_MODE_SERDES 0x00C00000
1592#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
1593#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
1594#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
1595#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
1596#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
1597#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
1598#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
1599#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
1600#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
1601#define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error detection enabled */
1602#define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity error detection enable */
1603#define E1000_CTRL_EXT_GHOST_PAREN 0x40000000
1604
1605/* MDI Control */
1606#define E1000_MDIC_DATA_MASK 0x0000FFFF
1607#define E1000_MDIC_REG_MASK 0x001F0000
1608#define E1000_MDIC_REG_SHIFT 16
1609#define E1000_MDIC_PHY_MASK 0x03E00000
1610#define E1000_MDIC_PHY_SHIFT 21
1611#define E1000_MDIC_OP_WRITE 0x04000000
1612#define E1000_MDIC_OP_READ 0x08000000
1613#define E1000_MDIC_READY 0x10000000
1614#define E1000_MDIC_INT_EN 0x20000000
1615#define E1000_MDIC_ERROR 0x40000000
1616
1617#define INTEL_CE_GBE_MDIC_OP_WRITE 0x04000000
1618#define INTEL_CE_GBE_MDIC_OP_READ 0x00000000
1619#define INTEL_CE_GBE_MDIC_GO 0x80000000
1620#define INTEL_CE_GBE_MDIC_READ_ERROR 0x80000000
1621
1622#define E1000_KUMCTRLSTA_MASK 0x0000FFFF
1623#define E1000_KUMCTRLSTA_OFFSET 0x001F0000
1624#define E1000_KUMCTRLSTA_OFFSET_SHIFT 16
1625#define E1000_KUMCTRLSTA_REN 0x00200000
1626
1627#define E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000
1628#define E1000_KUMCTRLSTA_OFFSET_CTRL 0x00000001
1629#define E1000_KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002
1630#define E1000_KUMCTRLSTA_OFFSET_DIAG 0x00000003
1631#define E1000_KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004
1632#define E1000_KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009
1633#define E1000_KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010
1634#define E1000_KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E
1635#define E1000_KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F
1636
1637/* FIFO Control */
1638#define E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008
1639#define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800
1640
1641/* In-Band Control */
1642#define E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT 0x00000500
1643#define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010
1644
1645/* Half-Duplex Control */
1646#define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004
1647#define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000
1648
1649#define E1000_KUMCTRLSTA_OFFSET_K0S_CTRL 0x0000001E
1650
1651#define E1000_KUMCTRLSTA_DIAG_FELPBK 0x2000
1652#define E1000_KUMCTRLSTA_DIAG_NELPBK 0x1000
1653
1654#define E1000_KUMCTRLSTA_K0S_100_EN 0x2000
1655#define E1000_KUMCTRLSTA_K0S_GBE_EN 0x1000
1656#define E1000_KUMCTRLSTA_K0S_ENTRY_LATENCY_MASK 0x0003
1657
1658#define E1000_KABGTXD_BGSQLBIAS 0x00050000
1659
1660#define E1000_PHY_CTRL_SPD_EN 0x00000001
1661#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
1662#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
1663#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
1664#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
1665#define E1000_PHY_CTRL_B2B_EN 0x00000080
1666
1667/* LED Control */
1668#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
1669#define E1000_LEDCTL_LED0_MODE_SHIFT 0
1670#define E1000_LEDCTL_LED0_BLINK_RATE 0x0000020
1671#define E1000_LEDCTL_LED0_IVRT 0x00000040
1672#define E1000_LEDCTL_LED0_BLINK 0x00000080
1673#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
1674#define E1000_LEDCTL_LED1_MODE_SHIFT 8
1675#define E1000_LEDCTL_LED1_BLINK_RATE 0x0002000
1676#define E1000_LEDCTL_LED1_IVRT 0x00004000
1677#define E1000_LEDCTL_LED1_BLINK 0x00008000
1678#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
1679#define E1000_LEDCTL_LED2_MODE_SHIFT 16
1680#define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000
1681#define E1000_LEDCTL_LED2_IVRT 0x00400000
1682#define E1000_LEDCTL_LED2_BLINK 0x00800000
1683#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
1684#define E1000_LEDCTL_LED3_MODE_SHIFT 24
1685#define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000
1686#define E1000_LEDCTL_LED3_IVRT 0x40000000
1687#define E1000_LEDCTL_LED3_BLINK 0x80000000
1688
1689#define E1000_LEDCTL_MODE_LINK_10_1000 0x0
1690#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
1691#define E1000_LEDCTL_MODE_LINK_UP 0x2
1692#define E1000_LEDCTL_MODE_ACTIVITY 0x3
1693#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
1694#define E1000_LEDCTL_MODE_LINK_10 0x5
1695#define E1000_LEDCTL_MODE_LINK_100 0x6
1696#define E1000_LEDCTL_MODE_LINK_1000 0x7
1697#define E1000_LEDCTL_MODE_PCIX_MODE 0x8
1698#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
1699#define E1000_LEDCTL_MODE_COLLISION 0xA
1700#define E1000_LEDCTL_MODE_BUS_SPEED 0xB
1701#define E1000_LEDCTL_MODE_BUS_SIZE 0xC
1702#define E1000_LEDCTL_MODE_PAUSED 0xD
1703#define E1000_LEDCTL_MODE_LED_ON 0xE
1704#define E1000_LEDCTL_MODE_LED_OFF 0xF
1705
1706/* Receive Address */
1707#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
1708
1709/* Interrupt Cause Read */
1710#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
1711#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
1712#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
1713#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
1714#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
1715#define E1000_ICR_RXO 0x00000040 /* rx overrun */
1716#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
1717#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
1718#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
1719#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
1720#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
1721#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
1722#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
1723#define E1000_ICR_TXD_LOW 0x00008000
1724#define E1000_ICR_SRPD 0x00010000
1725#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */
1726#define E1000_ICR_MNG 0x00040000 /* Manageability event */
1727#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */
1728#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */
1729#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */
1730#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */
1731#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity error */
1732#define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */
1733#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */
1734#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */
1735#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */
1736#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */
1737#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */
1738#define E1000_ICR_EPRST 0x00100000 /* ME hardware reset occurs */
1739
1740/* Interrupt Cause Set */
1741#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1742#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1743#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
1744#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1745#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1746#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
1747#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1748#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1749#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1750#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1751#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1752#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1753#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1754#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
1755#define E1000_ICS_SRPD E1000_ICR_SRPD
1756#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */
1757#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */
1758#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */
1759#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1760#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1761#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1762#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1763#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1764#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1765#define E1000_ICS_DSW E1000_ICR_DSW
1766#define E1000_ICS_PHYINT E1000_ICR_PHYINT
1767#define E1000_ICS_EPRST E1000_ICR_EPRST
1768
1769/* Interrupt Mask Set */
1770#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1771#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1772#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
1773#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1774#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1775#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
1776#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1777#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1778#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1779#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1780#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1781#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1782#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1783#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
1784#define E1000_IMS_SRPD E1000_ICR_SRPD
1785#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */
1786#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */
1787#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */
1788#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1789#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1790#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1791#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1792#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1793#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1794#define E1000_IMS_DSW E1000_ICR_DSW
1795#define E1000_IMS_PHYINT E1000_ICR_PHYINT
1796#define E1000_IMS_EPRST E1000_ICR_EPRST
1797
1798/* Interrupt Mask Clear */
1799#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1800#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1801#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */
1802#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1803#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1804#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
1805#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1806#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
1807#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1808#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1809#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1810#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1811#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1812#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
1813#define E1000_IMC_SRPD E1000_ICR_SRPD
1814#define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */
1815#define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */
1816#define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */
1817#define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1818#define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1819#define E1000_IMC_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1820#define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1821#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1822#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1823#define E1000_IMC_DSW E1000_ICR_DSW
1824#define E1000_IMC_PHYINT E1000_ICR_PHYINT
1825#define E1000_IMC_EPRST E1000_ICR_EPRST
1826
1827/* Receive Control */
1828#define E1000_RCTL_RST 0x00000001 /* Software reset */
1829#define E1000_RCTL_EN 0x00000002 /* enable */
1830#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
1831#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
1832#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
1833#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
1834#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
1835#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
1836#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
1837#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
1838#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
1839#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
1840#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
1841#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
1842#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
1843#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
1844#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
1845#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
1846#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
1847#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
1848#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
1849#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
1850/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
1851#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
1852#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
1853#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
1854#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
1855/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
1856#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
1857#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
1858#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
1859#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
1860#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
1861#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
1862#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
1863#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
1864#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
1865#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
1866#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */
1867#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */
1868
1869/* Use byte values for the following shift parameters
1870 * Usage:
1871 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
1872 * E1000_PSRCTL_BSIZE0_MASK) |
1873 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
1874 * E1000_PSRCTL_BSIZE1_MASK) |
1875 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
1876 * E1000_PSRCTL_BSIZE2_MASK) |
1877 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
1878 * E1000_PSRCTL_BSIZE3_MASK))
1879 * where value0 = [128..16256], default=256
1880 * value1 = [1024..64512], default=4096
1881 * value2 = [0..64512], default=4096
1882 * value3 = [0..64512], default=0
1883 */
1884
1885#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
1886#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
1887#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
1888#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
1889
1890#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
1891#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
1892#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
1893#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
1894
1895/* SW_W_SYNC definitions */
1896#define E1000_SWFW_EEP_SM 0x0001
1897#define E1000_SWFW_PHY0_SM 0x0002
1898#define E1000_SWFW_PHY1_SM 0x0004
1899#define E1000_SWFW_MAC_CSR_SM 0x0008
1900
1901/* Receive Descriptor */
1902#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
1903#define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */
1904#define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */
1905#define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */
1906#define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */
1907
1908/* Flow Control */
1909#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
1910#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
1911#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
1912#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
1913
1914/* Header split receive */
1915#define E1000_RFCTL_ISCSI_DIS 0x00000001
1916#define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E
1917#define E1000_RFCTL_ISCSI_DWC_SHIFT 1
1918#define E1000_RFCTL_NFSW_DIS 0x00000040
1919#define E1000_RFCTL_NFSR_DIS 0x00000080
1920#define E1000_RFCTL_NFS_VER_MASK 0x00000300
1921#define E1000_RFCTL_NFS_VER_SHIFT 8
1922#define E1000_RFCTL_IPV6_DIS 0x00000400
1923#define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800
1924#define E1000_RFCTL_ACK_DIS 0x00001000
1925#define E1000_RFCTL_ACKD_DIS 0x00002000
1926#define E1000_RFCTL_IPFRSP_DIS 0x00004000
1927#define E1000_RFCTL_EXTEN 0x00008000
1928#define E1000_RFCTL_IPV6_EX_DIS 0x00010000
1929#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
1930
1931/* Receive Descriptor Control */
1932#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
1933#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
1934#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
1935#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
1936
1937/* Transmit Descriptor Control */
1938#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
1939#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
1940#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
1941#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
1942#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
1943#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
1944#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.
1945 still to be processed. */
1946/* Transmit Configuration Word */
1947#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
1948#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
1949#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
1950#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
1951#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
1952#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
1953#define E1000_TXCW_NP 0x00008000 /* TXCW next page */
1954#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
1955#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
1956#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
1957
1958/* Receive Configuration Word */
1959#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
1960#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
1961#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
1962#define E1000_RXCW_CC 0x10000000 /* Receive config change */
1963#define E1000_RXCW_C 0x20000000 /* Receive config */
1964#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
1965#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
1966
1967/* Transmit Control */
1968#define E1000_TCTL_RST 0x00000001 /* software reset */
1969#define E1000_TCTL_EN 0x00000002 /* enable tx */
1970#define E1000_TCTL_BCE 0x00000004 /* busy check enable */
1971#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
1972#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
1973#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
1974#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
1975#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
1976#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
1977#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
1978#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
1979/* Extended Transmit Control */
1980#define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */
1981#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
1982
1983/* Receive Checksum Control */
1984#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
1985#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
1986#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
1987#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
1988#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
1989#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
1990
1991/* Multiple Receive Queue Control */
1992#define E1000_MRQC_ENABLE_MASK 0x00000003
1993#define E1000_MRQC_ENABLE_RSS_2Q 0x00000001
1994#define E1000_MRQC_ENABLE_RSS_INT 0x00000004
1995#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
1996#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
1997#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
1998#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
1999#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
2000#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
2001#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
2002
2003/* Definitions for power management and wakeup registers */
2004/* Wake Up Control */
2005#define E1000_WUC_APME 0x00000001 /* APM Enable */
2006#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
2007#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
2008#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
2009#define E1000_WUC_SPM 0x80000000 /* Enable SPM */
2010
2011/* Wake Up Filter Control */
2012#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
2013#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
2014#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
2015#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
2016#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
2017#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
2018#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
2019#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
2020#define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
2021#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
2022#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
2023#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
2024#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
2025#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
2026#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
2027#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
2028
2029/* Wake Up Status */
2030#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
2031#define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */
2032#define E1000_WUS_EX 0x00000004 /* Directed Exact Received */
2033#define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */
2034#define E1000_WUS_BC 0x00000010 /* Broadcast Received */
2035#define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */
2036#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
2037#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
2038#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
2039#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
2040#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
2041#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
2042#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
2043
2044/* Management Control */
2045#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
2046#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
2047#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
2048#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
2049#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
2050#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
2051#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
2052#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
2053#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
2054#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
2055 * Filtering */
2056#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */
2057#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
2058#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
2059#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
2060#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */
2061#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
2062#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address
2063 * filtering */
2064#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host
2065 * memory */
2066#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address
2067 * filtering */
2068#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */
2069#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */
2070#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
2071#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
2072#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
2073#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
2074#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
2075#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
2076
2077#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
2078#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
2079
2080/* SW Semaphore Register */
2081#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
2082#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
2083#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
2084#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
2085
2086/* FW Semaphore Register */
2087#define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */
2088#define E1000_FWSM_MODE_SHIFT 1
2089#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */
2090
2091#define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */
2092#define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */
2093#define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */
2094#define E1000_FWSM_SKUEL_SHIFT 29
2095#define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */
2096#define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */
2097#define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */
2098#define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */
2099
2100/* FFLT Debug Register */
2101#define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */
2102
2103typedef enum {
2104 e1000_mng_mode_none = 0,
2105 e1000_mng_mode_asf,
2106 e1000_mng_mode_pt,
2107 e1000_mng_mode_ipmi,
2108 e1000_mng_mode_host_interface_only
2109} e1000_mng_mode;
2110
2111/* Host Interface Control Register */
2112#define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */
2113#define E1000_HICR_C 0x00000002 /* Driver sets this bit when done
2114 * to put command in RAM */
2115#define E1000_HICR_SV 0x00000004 /* Status Validity */
2116#define E1000_HICR_FWR 0x00000080 /* FW reset. Set by the Host */
2117
2118/* Host Interface Command Interface - Address range 0x8800-0x8EFF */
2119#define E1000_HI_MAX_DATA_LENGTH 252 /* Host Interface data length */
2120#define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Number of bytes in range */
2121#define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Number of dwords in range */
2122#define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */
2123
2124struct e1000_host_command_header {
2125 u8 command_id;
2126 u8 command_length;
2127 u8 command_options; /* I/F bits for command, status for return */
2128 u8 checksum;
2129};
2130struct e1000_host_command_info {
2131 struct e1000_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
2132 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */
2133};
2134
2135/* Host SMB register #0 */
2136#define E1000_HSMC0R_CLKIN 0x00000001 /* SMB Clock in */
2137#define E1000_HSMC0R_DATAIN 0x00000002 /* SMB Data in */
2138#define E1000_HSMC0R_DATAOUT 0x00000004 /* SMB Data out */
2139#define E1000_HSMC0R_CLKOUT 0x00000008 /* SMB Clock out */
2140
2141/* Host SMB register #1 */
2142#define E1000_HSMC1R_CLKIN E1000_HSMC0R_CLKIN
2143#define E1000_HSMC1R_DATAIN E1000_HSMC0R_DATAIN
2144#define E1000_HSMC1R_DATAOUT E1000_HSMC0R_DATAOUT
2145#define E1000_HSMC1R_CLKOUT E1000_HSMC0R_CLKOUT
2146
2147/* FW Status Register */
2148#define E1000_FWSTS_FWS_MASK 0x000000FF /* FW Status */
2149
2150/* Wake Up Packet Length */
2151#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
2152
2153#define E1000_MDALIGN 4096
2154
2155/* PCI-Ex registers*/
2156
2157/* PCI-Ex Control Register */
2158#define E1000_GCR_RXD_NO_SNOOP 0x00000001
2159#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
2160#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
2161#define E1000_GCR_TXD_NO_SNOOP 0x00000008
2162#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
2163#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
2164
2165#define PCI_EX_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
2166 E1000_GCR_RXDSCW_NO_SNOOP | \
2167 E1000_GCR_RXDSCR_NO_SNOOP | \
2168 E1000_GCR_TXD_NO_SNOOP | \
2169 E1000_GCR_TXDSCW_NO_SNOOP | \
2170 E1000_GCR_TXDSCR_NO_SNOOP)
2171
2172#define PCI_EX_82566_SNOOP_ALL PCI_EX_NO_SNOOP_ALL
2173
2174#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
2175/* Function Active and Power State to MNG */
2176#define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003
2177#define E1000_FACTPS_LAN0_VALID 0x00000004
2178#define E1000_FACTPS_FUNC0_AUX_EN 0x00000008
2179#define E1000_FACTPS_FUNC1_POWER_STATE_MASK 0x000000C0
2180#define E1000_FACTPS_FUNC1_POWER_STATE_SHIFT 6
2181#define E1000_FACTPS_LAN1_VALID 0x00000100
2182#define E1000_FACTPS_FUNC1_AUX_EN 0x00000200
2183#define E1000_FACTPS_FUNC2_POWER_STATE_MASK 0x00003000
2184#define E1000_FACTPS_FUNC2_POWER_STATE_SHIFT 12
2185#define E1000_FACTPS_IDE_ENABLE 0x00004000
2186#define E1000_FACTPS_FUNC2_AUX_EN 0x00008000
2187#define E1000_FACTPS_FUNC3_POWER_STATE_MASK 0x000C0000
2188#define E1000_FACTPS_FUNC3_POWER_STATE_SHIFT 18
2189#define E1000_FACTPS_SP_ENABLE 0x00100000
2190#define E1000_FACTPS_FUNC3_AUX_EN 0x00200000
2191#define E1000_FACTPS_FUNC4_POWER_STATE_MASK 0x03000000
2192#define E1000_FACTPS_FUNC4_POWER_STATE_SHIFT 24
2193#define E1000_FACTPS_IPMI_ENABLE 0x04000000
2194#define E1000_FACTPS_FUNC4_AUX_EN 0x08000000
2195#define E1000_FACTPS_MNGCG 0x20000000
2196#define E1000_FACTPS_LAN_FUNC_SEL 0x40000000
2197#define E1000_FACTPS_PM_STATE_CHANGED 0x80000000
2198
2199/* PCI-Ex Config Space */
2200#define PCI_EX_LINK_STATUS 0x12
2201#define PCI_EX_LINK_WIDTH_MASK 0x3F0
2202#define PCI_EX_LINK_WIDTH_SHIFT 4
2203
2204/* EEPROM Commands - Microwire */
2205#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */
2206#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
2207#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */
2208#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */
2209#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erase/write disable */
2210
2211/* EEPROM Commands - SPI */
2212#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
2213#define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
2214#define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
2215#define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
2216#define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */
2217#define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */
2218#define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */
2219#define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */
2220#define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
2221#define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
2222#define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
2223
2224/* EEPROM Size definitions */
2225#define EEPROM_WORD_SIZE_SHIFT 6
2226#define EEPROM_SIZE_SHIFT 10
2227#define EEPROM_SIZE_MASK 0x1C00
2228
2229/* EEPROM Word Offsets */
2230#define EEPROM_COMPAT 0x0003
2231#define EEPROM_ID_LED_SETTINGS 0x0004
2232#define EEPROM_VERSION 0x0005
2233#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */
2234#define EEPROM_PHY_CLASS_WORD 0x0007
2235#define EEPROM_INIT_CONTROL1_REG 0x000A
2236#define EEPROM_INIT_CONTROL2_REG 0x000F
2237#define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010
2238#define EEPROM_INIT_CONTROL3_PORT_B 0x0014
2239#define EEPROM_INIT_3GIO_3 0x001A
2240#define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020
2241#define EEPROM_INIT_CONTROL3_PORT_A 0x0024
2242#define EEPROM_CFG 0x0012
2243#define EEPROM_FLASH_VERSION 0x0032
2244#define EEPROM_CHECKSUM_REG 0x003F
2245
2246#define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */
2247#define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */
2248
2249/* Word definitions for ID LED Settings */
2250#define ID_LED_RESERVED_0000 0x0000
2251#define ID_LED_RESERVED_FFFF 0xFFFF
2252#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
2253 (ID_LED_OFF1_OFF2 << 8) | \
2254 (ID_LED_DEF1_DEF2 << 4) | \
2255 (ID_LED_DEF1_DEF2))
2256#define ID_LED_DEF1_DEF2 0x1
2257#define ID_LED_DEF1_ON2 0x2
2258#define ID_LED_DEF1_OFF2 0x3
2259#define ID_LED_ON1_DEF2 0x4
2260#define ID_LED_ON1_ON2 0x5
2261#define ID_LED_ON1_OFF2 0x6
2262#define ID_LED_OFF1_DEF2 0x7
2263#define ID_LED_OFF1_ON2 0x8
2264#define ID_LED_OFF1_OFF2 0x9
2265
2266#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
2267#define IGP_ACTIVITY_LED_ENABLE 0x0300
2268#define IGP_LED3_MODE 0x07000000
2269
2270/* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */
2271#define EEPROM_SERDES_AMPLITUDE_MASK 0x000F
2272
2273/* Mask bit for PHY class in Word 7 of the EEPROM */
2274#define EEPROM_PHY_CLASS_A 0x8000
2275
2276/* Mask bits for fields in Word 0x0a of the EEPROM */
2277#define EEPROM_WORD0A_ILOS 0x0010
2278#define EEPROM_WORD0A_SWDPIO 0x01E0
2279#define EEPROM_WORD0A_LRST 0x0200
2280#define EEPROM_WORD0A_FD 0x0400
2281#define EEPROM_WORD0A_66MHZ 0x0800
2282
2283/* Mask bits for fields in Word 0x0f of the EEPROM */
2284#define EEPROM_WORD0F_PAUSE_MASK 0x3000
2285#define EEPROM_WORD0F_PAUSE 0x1000
2286#define EEPROM_WORD0F_ASM_DIR 0x2000
2287#define EEPROM_WORD0F_ANE 0x0800
2288#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
2289#define EEPROM_WORD0F_LPLU 0x0001
2290
2291/* Mask bits for fields in Word 0x10/0x20 of the EEPROM */
2292#define EEPROM_WORD1020_GIGA_DISABLE 0x0010
2293#define EEPROM_WORD1020_GIGA_DISABLE_NON_D0A 0x0008
2294
2295/* Mask bits for fields in Word 0x1a of the EEPROM */
2296#define EEPROM_WORD1A_ASPM_MASK 0x000C
2297
2298/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
2299#define EEPROM_SUM 0xBABA
2300
2301/* EEPROM Map defines (WORD OFFSETS)*/
2302#define EEPROM_NODE_ADDRESS_BYTE_0 0
2303#define EEPROM_PBA_BYTE_1 8
2304
2305#define EEPROM_RESERVED_WORD 0xFFFF
2306
2307/* EEPROM Map Sizes (Byte Counts) */
2308#define PBA_SIZE 4
2309
2310/* Collision related configuration parameters */
2311#define E1000_COLLISION_THRESHOLD 15
2312#define E1000_CT_SHIFT 4
2313/* Collision distance is a 0-based value that applies to
2314 * half-duplex-capable hardware only. */
2315#define E1000_COLLISION_DISTANCE 63
2316#define E1000_COLLISION_DISTANCE_82542 64
2317#define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
2318#define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
2319#define E1000_COLD_SHIFT 12
2320
2321/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
2322#define REQ_TX_DESCRIPTOR_MULTIPLE 8
2323#define REQ_RX_DESCRIPTOR_MULTIPLE 8
2324
2325/* Default values for the transmit IPG register */
2326#define DEFAULT_82542_TIPG_IPGT 10
2327#define DEFAULT_82543_TIPG_IPGT_FIBER 9
2328#define DEFAULT_82543_TIPG_IPGT_COPPER 8
2329
2330#define E1000_TIPG_IPGT_MASK 0x000003FF
2331#define E1000_TIPG_IPGR1_MASK 0x000FFC00
2332#define E1000_TIPG_IPGR2_MASK 0x3FF00000
2333
2334#define DEFAULT_82542_TIPG_IPGR1 2
2335#define DEFAULT_82543_TIPG_IPGR1 8
2336#define E1000_TIPG_IPGR1_SHIFT 10
2337
2338#define DEFAULT_82542_TIPG_IPGR2 10
2339#define DEFAULT_82543_TIPG_IPGR2 6
2340#define E1000_TIPG_IPGR2_SHIFT 20
2341
2342#define E1000_TXDMAC_DPP 0x00000001
2343
2344/* Adaptive IFS defines */
2345#define TX_THRESHOLD_START 8
2346#define TX_THRESHOLD_INCREMENT 10
2347#define TX_THRESHOLD_DECREMENT 1
2348#define TX_THRESHOLD_STOP 190
2349#define TX_THRESHOLD_DISABLE 0
2350#define TX_THRESHOLD_TIMER_MS 10000
2351#define MIN_NUM_XMITS 1000
2352#define IFS_MAX 80
2353#define IFS_STEP 10
2354#define IFS_MIN 40
2355#define IFS_RATIO 4
2356
2357/* Extended Configuration Control and Size */
2358#define E1000_EXTCNF_CTRL_PCIE_WRITE_ENABLE 0x00000001
2359#define E1000_EXTCNF_CTRL_PHY_WRITE_ENABLE 0x00000002
2360#define E1000_EXTCNF_CTRL_D_UD_ENABLE 0x00000004
2361#define E1000_EXTCNF_CTRL_D_UD_LATENCY 0x00000008
2362#define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010
2363#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
2364#define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040
2365#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x0FFF0000
2366
2367#define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF
2368#define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00
2369#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000
2370#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
2371#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
2372
2373/* PBA constants */
2374#define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */
2375#define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */
2376#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
2377#define E1000_PBA_20K 0x0014
2378#define E1000_PBA_22K 0x0016
2379#define E1000_PBA_24K 0x0018
2380#define E1000_PBA_30K 0x001E
2381#define E1000_PBA_32K 0x0020
2382#define E1000_PBA_34K 0x0022
2383#define E1000_PBA_38K 0x0026
2384#define E1000_PBA_40K 0x0028
2385#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
2386
2387#define E1000_PBS_16K E1000_PBA_16K
2388
2389/* Flow Control Constants */
2390#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
2391#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
2392#define FLOW_CONTROL_TYPE 0x8808
2393
2394/* The historical defaults for the flow control values are given below. */
2395#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
2396#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
2397#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
2398
2399/* PCIX Config space */
2400#define PCIX_COMMAND_REGISTER 0xE6
2401#define PCIX_STATUS_REGISTER_LO 0xE8
2402#define PCIX_STATUS_REGISTER_HI 0xEA
2403
2404#define PCIX_COMMAND_MMRBC_MASK 0x000C
2405#define PCIX_COMMAND_MMRBC_SHIFT 0x2
2406#define PCIX_STATUS_HI_MMRBC_MASK 0x0060
2407#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
2408#define PCIX_STATUS_HI_MMRBC_4K 0x3
2409#define PCIX_STATUS_HI_MMRBC_2K 0x2
2410
2411/* Number of bits required to shift right the "pause" bits from the
2412 * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register.
2413 */
2414#define PAUSE_SHIFT 5
2415
2416/* Number of bits required to shift left the "SWDPIO" bits from the
2417 * EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field in the CTRL register.
2418 */
2419#define SWDPIO_SHIFT 17
2420
2421/* Number of bits required to shift left the "SWDPIO_EXT" bits from the
2422 * EEPROM word F (bits 7:4) to the bits 11:8 of The Extended CTRL register.
2423 */
2424#define SWDPIO__EXT_SHIFT 4
2425
2426/* Number of bits required to shift left the "ILOS" bit from the EEPROM
2427 * (bit 4) to the "ILOS" (bit 7) field in the CTRL register.
2428 */
2429#define ILOS_SHIFT 3
2430
2431#define RECEIVE_BUFFER_ALIGN_SIZE (256)
2432
2433/* Number of milliseconds we wait for auto-negotiation to complete */
2434#define LINK_UP_TIMEOUT 500
2435
2436/* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */
2437#define AUTO_READ_DONE_TIMEOUT 10
2438/* Number of milliseconds we wait for PHY configuration done after MAC reset */
2439#define PHY_CFG_TIMEOUT 100
2440
2441#define E1000_TX_BUFFER_SIZE ((u32)1514)
2442
2443/* The carrier extension symbol, as received by the NIC. */
2444#define CARRIER_EXTENSION 0x0F
2445
2446/* TBI_ACCEPT macro definition:
2447 *
2448 * This macro requires:
2449 * adapter = a pointer to struct e1000_hw
2450 * status = the 8 bit status field of the RX descriptor with EOP set
2451 * error = the 8 bit error field of the RX descriptor with EOP set
2452 * length = the sum of all the length fields of the RX descriptors that
2453 * make up the current frame
2454 * last_byte = the last byte of the frame DMAed by the hardware
2455 * max_frame_length = the maximum frame length we want to accept.
2456 * min_frame_length = the minimum frame length we want to accept.
2457 *
2458 * This macro is a conditional that should be used in the interrupt
2459 * handler's Rx processing routine when RxErrors have been detected.
2460 *
2461 * Typical use:
2462 * ...
2463 * if (TBI_ACCEPT) {
2464 * accept_frame = true;
2465 * e1000_tbi_adjust_stats(adapter, MacAddress);
2466 * frame_length--;
2467 * } else {
2468 * accept_frame = false;
2469 * }
2470 * ...
2471 */
2472
2473#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
2474 ((adapter)->tbi_compatibility_on && \
2475 (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
2476 ((last_byte) == CARRIER_EXTENSION) && \
2477 (((status) & E1000_RXD_STAT_VP) ? \
2478 (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
2479 ((length) <= ((adapter)->max_frame_size + 1))) : \
2480 (((length) > (adapter)->min_frame_size) && \
2481 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
2482
2483/* Structures, enums, and macros for the PHY */
2484
2485/* Bit definitions for the Management Data IO (MDIO) and Management Data
2486 * Clock (MDC) pins in the Device Control Register.
2487 */
2488#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
2489#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
2490#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
2491#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
2492#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
2493#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
2494#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
2495#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
2496
2497/* PHY 1000 MII Register/Bit Definitions */
2498/* PHY Registers defined by IEEE */
2499#define PHY_CTRL 0x00 /* Control Register */
2500#define PHY_STATUS 0x01 /* Status Register */
2501#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
2502#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
2503#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
2504#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
2505#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
2506#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
2507#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
2508#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
2509#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
2510#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
2511
2512#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
2513#define MAX_PHY_MULTI_PAGE_REG 0xF /* Registers equal on all pages */
2514
2515/* M88E1000 Specific Registers */
2516#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
2517#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
2518#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
2519#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
2520#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
2521#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
2522
2523#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
2524#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
2525#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
2526#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
2527#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
2528
2529#define IGP01E1000_IEEE_REGS_PAGE 0x0000
2530#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
2531#define IGP01E1000_IEEE_FORCE_GIGA 0x0140
2532
2533/* IGP01E1000 Specific Registers */
2534#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
2535#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
2536#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */
2537#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
2538#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */
2539#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
2540#define IGP02E1000_PHY_POWER_MGMT 0x19
2541#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
2542
2543/* IGP01E1000 AGC Registers - stores the cable length values*/
2544#define IGP01E1000_PHY_AGC_A 0x1172
2545#define IGP01E1000_PHY_AGC_B 0x1272
2546#define IGP01E1000_PHY_AGC_C 0x1472
2547#define IGP01E1000_PHY_AGC_D 0x1872
2548
2549/* IGP02E1000 AGC Registers for cable length values */
2550#define IGP02E1000_PHY_AGC_A 0x11B1
2551#define IGP02E1000_PHY_AGC_B 0x12B1
2552#define IGP02E1000_PHY_AGC_C 0x14B1
2553#define IGP02E1000_PHY_AGC_D 0x18B1
2554
2555/* IGP01E1000 DSP Reset Register */
2556#define IGP01E1000_PHY_DSP_RESET 0x1F33
2557#define IGP01E1000_PHY_DSP_SET 0x1F71
2558#define IGP01E1000_PHY_DSP_FFE 0x1F35
2559
2560#define IGP01E1000_PHY_CHANNEL_NUM 4
2561#define IGP02E1000_PHY_CHANNEL_NUM 4
2562
2563#define IGP01E1000_PHY_AGC_PARAM_A 0x1171
2564#define IGP01E1000_PHY_AGC_PARAM_B 0x1271
2565#define IGP01E1000_PHY_AGC_PARAM_C 0x1471
2566#define IGP01E1000_PHY_AGC_PARAM_D 0x1871
2567
2568#define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
2569#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
2570
2571#define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890
2572#define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000
2573#define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004
2574#define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
2575
2576#define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
2577/* IGP01E1000 PCS Initialization register - stores the polarity status when
2578 * speed = 1000 Mbps. */
2579#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
2580#define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5
2581
2582#define IGP01E1000_ANALOG_REGS_PAGE 0x20C0
2583
2584/* PHY Control Register */
2585#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
2586#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
2587#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
2588#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
2589#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
2590#define MII_CR_POWER_DOWN 0x0800 /* Power down */
2591#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
2592#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
2593#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
2594#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
2595
2596/* PHY Status Register */
2597#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
2598#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
2599#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
2600#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
2601#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
2602#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
2603#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
2604#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
2605#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
2606#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
2607#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
2608#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
2609#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
2610#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
2611#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
2612
2613/* Autoneg Advertisement Register */
2614#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
2615#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
2616#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
2617#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
2618#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
2619#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
2620#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
2621#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
2622#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
2623#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
2624
2625/* Link Partner Ability Register (Base Page) */
2626#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
2627#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
2628#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
2629#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
2630#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
2631#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
2632#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
2633#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
2634#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
2635#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
2636#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
2637
2638/* Autoneg Expansion Register */
2639#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
2640#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
2641#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
2642#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
2643#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */
2644
2645/* Next Page TX Register */
2646#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2647#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges
2648 * of different NP
2649 */
2650#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2651 * 0 = cannot comply with msg
2652 */
2653#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2654#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2655 * 0 = sending last NP
2656 */
2657
2658/* Link Partner Next Page Register */
2659#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2660#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges
2661 * of different NP
2662 */
2663#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2664 * 0 = cannot comply with msg
2665 */
2666#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2667#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */
2668#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2669 * 0 = sending last NP
2670 */
2671
2672/* 1000BASE-T Control Register */
2673#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
2674#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
2675#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
2676#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
2677 /* 0=DTE device */
2678#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
2679 /* 0=Configure PHY as Slave */
2680#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
2681 /* 0=Automatic Master/Slave config */
2682#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
2683#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
2684#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
2685#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
2686#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
2687
2688/* 1000BASE-T Status Register */
2689#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
2690#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
2691#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
2692#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
2693#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
2694#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
2695#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
2696#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
2697#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
2698#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
2699#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
2700#define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20
2701#define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100
2702
2703/* Extended Status Register */
2704#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
2705#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
2706#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
2707#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
2708
2709#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */
2710#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */
2711
2712#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */
2713 /* (0=enable, 1=disable) */
2714
2715/* M88E1000 PHY Specific Control Register */
2716#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
2717#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
2718#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
2719#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
2720 * 0=CLK125 toggling
2721 */
2722#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
2723 /* Manual MDI configuration */
2724#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
2725#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
2726 * 100BASE-TX/10BASE-T:
2727 * MDI Mode
2728 */
2729#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
2730 * all speeds.
2731 */
2732#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
2733 /* 1=Enable Extended 10BASE-T distance
2734 * (Lower 10BASE-T RX Threshold)
2735 * 0=Normal 10BASE-T RX Threshold */
2736#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
2737 /* 1=5-Bit interface in 100BASE-TX
2738 * 0=MII interface in 100BASE-TX */
2739#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
2740#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
2741#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
2742
2743#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
2744#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
2745#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
2746
2747/* M88E1000 PHY Specific Status Register */
2748#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
2749#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
2750#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
2751#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
2752#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
2753 * 3=110-140M;4=>140M */
2754#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
2755#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
2756#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
2757#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
2758#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
2759#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
2760#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
2761#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
2762
2763#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
2764#define M88E1000_PSSR_DOWNSHIFT_SHIFT 5
2765#define M88E1000_PSSR_MDIX_SHIFT 6
2766#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
2767
2768/* M88E1000 Extended PHY Specific Control Register */
2769#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
2770#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
2771 * Will assert lost lock and bring
2772 * link down if idle not seen
2773 * within 1ms in 1000BASE-T
2774 */
2775/* Number of times we will attempt to autonegotiate before downshifting if we
2776 * are the master */
2777#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
2778#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
2779#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
2780#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
2781#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
2782/* Number of times we will attempt to autonegotiate before downshifting if we
2783 * are the slave */
2784#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
2785#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
2786#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
2787#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
2788#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
2789#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
2790#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
2791#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
2792
2793/* M88EC018 Rev 2 specific DownShift settings */
2794#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
2795#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
2796#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
2797#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
2798#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
2799#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
2800#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
2801#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
2802#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
2803
2804/* IGP01E1000 Specific Port Config Register - R/W */
2805#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
2806#define IGP01E1000_PSCFR_PRE_EN 0x0020
2807#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
2808#define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100
2809#define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400
2810#define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000
2811
2812/* IGP01E1000 Specific Port Status Register - R/O */
2813#define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */
2814#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
2815#define IGP01E1000_PSSR_CABLE_LENGTH 0x007C
2816#define IGP01E1000_PSSR_FULL_DUPLEX 0x0200
2817#define IGP01E1000_PSSR_LINK_UP 0x0400
2818#define IGP01E1000_PSSR_MDIX 0x0800
2819#define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */
2820#define IGP01E1000_PSSR_SPEED_10MBPS 0x4000
2821#define IGP01E1000_PSSR_SPEED_100MBPS 0x8000
2822#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
2823#define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */
2824#define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */
2825
2826/* IGP01E1000 Specific Port Control Register - R/W */
2827#define IGP01E1000_PSCR_TP_LOOPBACK 0x0010
2828#define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200
2829#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
2830#define IGP01E1000_PSCR_FLIP_CHIP 0x0800
2831#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
2832#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
2833
2834/* IGP01E1000 Specific Port Link Health Register */
2835#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
2836#define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000
2837#define IGP01E1000_PLHR_MASTER_FAULT 0x2000
2838#define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000
2839#define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */
2840#define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */
2841#define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */
2842#define IGP01E1000_PLHR_DATA_ERR_0 0x0100
2843#define IGP01E1000_PLHR_AUTONEG_FAULT 0x0040
2844#define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0010
2845#define IGP01E1000_PLHR_VALID_CHANNEL_D 0x0008
2846#define IGP01E1000_PLHR_VALID_CHANNEL_C 0x0004
2847#define IGP01E1000_PLHR_VALID_CHANNEL_B 0x0002
2848#define IGP01E1000_PLHR_VALID_CHANNEL_A 0x0001
2849
2850/* IGP01E1000 Channel Quality Register */
2851#define IGP01E1000_MSE_CHANNEL_D 0x000F
2852#define IGP01E1000_MSE_CHANNEL_C 0x00F0
2853#define IGP01E1000_MSE_CHANNEL_B 0x0F00
2854#define IGP01E1000_MSE_CHANNEL_A 0xF000
2855
2856#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
2857#define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in non-D0a modes */
2858#define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in D0a mode */
2859
2860/* IGP01E1000 DSP reset macros */
2861#define DSP_RESET_ENABLE 0x0
2862#define DSP_RESET_DISABLE 0x2
2863#define E1000_MAX_DSP_RESETS 10
2864
2865/* IGP01E1000 & IGP02E1000 AGC Registers */
2866
2867#define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */
2868#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Coarse - 15:13, Fine - 12:9 */
2869
2870/* IGP02E1000 AGC Register Length 9-bit mask */
2871#define IGP02E1000_AGC_LENGTH_MASK 0x7F
2872
2873/* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */
2874#define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128
2875#define IGP02E1000_AGC_LENGTH_TABLE_SIZE 113
2876
2877/* The precision error of the cable length is +/- 10 meters */
2878#define IGP01E1000_AGC_RANGE 10
2879#define IGP02E1000_AGC_RANGE 15
2880
2881/* IGP01E1000 PCS Initialization register */
2882/* bits 3:6 in the PCS registers stores the channels polarity */
2883#define IGP01E1000_PHY_POLARITY_MASK 0x0078
2884
2885/* IGP01E1000 GMII FIFO Register */
2886#define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed
2887 * on Link-Up */
2888#define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */
2889
2890/* IGP01E1000 Analog Register */
2891#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
2892#define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
2893#define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
2894#define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
2895
2896#define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
2897#define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
2898#define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
2899#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
2900#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
2901
2902#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
2903#define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
2904#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
2905#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
2906
2907/* Bit definitions for valid PHY IDs. */
2908/* I = Integrated
2909 * E = External
2910 */
2911#define M88_VENDOR 0x0141
2912#define M88E1000_E_PHY_ID 0x01410C50
2913#define M88E1000_I_PHY_ID 0x01410C30
2914#define M88E1011_I_PHY_ID 0x01410C20
2915#define IGP01E1000_I_PHY_ID 0x02A80380
2916#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
2917#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
2918#define M88E1011_I_REV_4 0x04
2919#define M88E1111_I_PHY_ID 0x01410CC0
2920#define M88E1118_E_PHY_ID 0x01410E40
2921#define L1LXT971A_PHY_ID 0x001378E0
2922
2923#define RTL8211B_PHY_ID 0x001CC910
2924#define RTL8201N_PHY_ID 0x8200
2925#define RTL_PHY_CTRL_FD 0x0100 /* Full duplex.0=half; 1=full */
2926#define RTL_PHY_CTRL_SPD_100 0x200000 /* Force 100Mb */
2927
2928/* Bits...
2929 * 15-5: page
2930 * 4-0: register offset
2931 */
2932#define PHY_PAGE_SHIFT 5
2933#define PHY_REG(page, reg) \
2934 (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
2935
2936#define IGP3_PHY_PORT_CTRL \
2937 PHY_REG(769, 17) /* Port General Configuration */
2938#define IGP3_PHY_RATE_ADAPT_CTRL \
2939 PHY_REG(769, 25) /* Rate Adapter Control Register */
2940
2941#define IGP3_KMRN_FIFO_CTRL_STATS \
2942 PHY_REG(770, 16) /* KMRN FIFO's control/status register */
2943#define IGP3_KMRN_POWER_MNG_CTRL \
2944 PHY_REG(770, 17) /* KMRN Power Management Control Register */
2945#define IGP3_KMRN_INBAND_CTRL \
2946 PHY_REG(770, 18) /* KMRN Inband Control Register */
2947#define IGP3_KMRN_DIAG \
2948 PHY_REG(770, 19) /* KMRN Diagnostic register */
2949#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 /* RX PCS is not synced */
2950#define IGP3_KMRN_ACK_TIMEOUT \
2951 PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */
2952
2953#define IGP3_VR_CTRL \
2954 PHY_REG(776, 18) /* Voltage regulator control register */
2955#define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */
2956#define IGP3_VR_CTRL_MODE_MASK 0x0300 /* Shutdown VR Mask */
2957
2958#define IGP3_CAPABILITY \
2959 PHY_REG(776, 19) /* IGP3 Capability Register */
2960
2961/* Capabilities for SKU Control */
2962#define IGP3_CAP_INITIATE_TEAM 0x0001 /* Able to initiate a team */
2963#define IGP3_CAP_WFM 0x0002 /* Support WoL and PXE */
2964#define IGP3_CAP_ASF 0x0004 /* Support ASF */
2965#define IGP3_CAP_LPLU 0x0008 /* Support Low Power Link Up */
2966#define IGP3_CAP_DC_AUTO_SPEED 0x0010 /* Support AC/DC Auto Link Speed */
2967#define IGP3_CAP_SPD 0x0020 /* Support Smart Power Down */
2968#define IGP3_CAP_MULT_QUEUE 0x0040 /* Support 2 tx & 2 rx queues */
2969#define IGP3_CAP_RSS 0x0080 /* Support RSS */
2970#define IGP3_CAP_8021PQ 0x0100 /* Support 802.1Q & 802.1p */
2971#define IGP3_CAP_AMT_CB 0x0200 /* Support active manageability and circuit breaker */
2972
2973#define IGP3_PPC_JORDAN_EN 0x0001
2974#define IGP3_PPC_JORDAN_GIGA_SPEED 0x0002
2975
2976#define IGP3_KMRN_PMC_EE_IDLE_LINK_DIS 0x0001
2977#define IGP3_KMRN_PMC_K0S_ENTRY_LATENCY_MASK 0x001E
2978#define IGP3_KMRN_PMC_K0S_MODE1_EN_GIGA 0x0020
2979#define IGP3_KMRN_PMC_K0S_MODE1_EN_100 0x0040
2980
2981#define IGP3E1000_PHY_MISC_CTRL 0x1B /* Misc. Ctrl register */
2982#define IGP3_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Duplex Manual Set */
2983
2984#define IGP3_KMRN_EXT_CTRL PHY_REG(770, 18)
2985#define IGP3_KMRN_EC_DIS_INBAND 0x0080
2986
2987#define IGP03E1000_E_PHY_ID 0x02A80390
2988#define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */
2989#define IFE_PLUS_E_PHY_ID 0x02A80320
2990#define IFE_C_E_PHY_ID 0x02A80310
2991
2992#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status, Control and Address */
2993#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special control register */
2994#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False Carrier Counter */
2995#define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnect Counter */
2996#define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error Frame Counter */
2997#define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error Counter */
2998#define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive Premature End Of Frame Error Counter */
2999#define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of Frame Error Counter */
3000#define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber Detect Counter */
3001#define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and Status */
3002#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and LED configuration */
3003#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */
3004#define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control (HWI) */
3005
3006#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Default 1 = Disable auto reduced power down */
3007#define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power state of 100BASE-TX */
3008#define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power state of 10BASE-T */
3009#define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T polarity */
3010#define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY address */
3011#define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed result 1=100Mbs, 0=10Mbs */
3012#define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation duplex result 1=Full, 0=Half */
3013#define IFE_PESC_POLARITY_REVERSED_SHIFT 8
3014
3015#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dynamic Power Down disabled */
3016#define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity, 0=Normal */
3017#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity Disabled, 0=Enabled */
3018#define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled, 0=Normal Jabber Operation */
3019#define IFE_PSC_FORCE_POLARITY_SHIFT 5
3020#define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4
3021
3022#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X feature, default 0=disabled */
3023#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X, 0=force MDI */
3024#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
3025#define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorithm is completed */
3026#define IFE_PMC_MDIX_MODE_SHIFT 6
3027#define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */
3028
3029#define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI feature */
3030#define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed, 0=failed */
3031#define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses on the wire */
3032#define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */
3033#define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */
3034#define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication type of problem on the line */
3035#define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to the cable problem, in 80cm granularity */
3036#define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */
3037#define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */
3038#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
3039#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
3040
3041#define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */
3042#define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */
3043#define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */
3044#define ICH_FLASH_SEG_SIZE_256 256
3045#define ICH_FLASH_SEG_SIZE_4K 4096
3046#define ICH_FLASH_SEG_SIZE_64K 65536
3047
3048#define ICH_CYCLE_READ 0x0
3049#define ICH_CYCLE_RESERVED 0x1
3050#define ICH_CYCLE_WRITE 0x2
3051#define ICH_CYCLE_ERASE 0x3
3052
3053#define ICH_FLASH_GFPREG 0x0000
3054#define ICH_FLASH_HSFSTS 0x0004
3055#define ICH_FLASH_HSFCTL 0x0006
3056#define ICH_FLASH_FADDR 0x0008
3057#define ICH_FLASH_FDATA0 0x0010
3058#define ICH_FLASH_FRACC 0x0050
3059#define ICH_FLASH_FREG0 0x0054
3060#define ICH_FLASH_FREG1 0x0058
3061#define ICH_FLASH_FREG2 0x005C
3062#define ICH_FLASH_FREG3 0x0060
3063#define ICH_FLASH_FPR0 0x0074
3064#define ICH_FLASH_FPR1 0x0078
3065#define ICH_FLASH_SSFSTS 0x0090
3066#define ICH_FLASH_SSFCTL 0x0092
3067#define ICH_FLASH_PREOP 0x0094
3068#define ICH_FLASH_OPTYPE 0x0096
3069#define ICH_FLASH_OPMENU 0x0098
3070
3071#define ICH_FLASH_REG_MAPSIZE 0x00A0
3072#define ICH_FLASH_SECTOR_SIZE 4096
3073#define ICH_GFPREG_BASE_MASK 0x1FFF
3074#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
3075
3076/* Miscellaneous PHY bit definitions. */
3077#define PHY_PREAMBLE 0xFFFFFFFF
3078#define PHY_SOF 0x01
3079#define PHY_OP_READ 0x02
3080#define PHY_OP_WRITE 0x01
3081#define PHY_TURNAROUND 0x02
3082#define PHY_PREAMBLE_SIZE 32
3083#define MII_CR_SPEED_1000 0x0040
3084#define MII_CR_SPEED_100 0x2000
3085#define MII_CR_SPEED_10 0x0000
3086#define E1000_PHY_ADDRESS 0x01
3087#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
3088#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
3089#define PHY_REVISION_MASK 0xFFFFFFF0
3090#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */
3091#define REG4_SPEED_MASK 0x01E0
3092#define REG9_SPEED_MASK 0x0300
3093#define ADVERTISE_10_HALF 0x0001
3094#define ADVERTISE_10_FULL 0x0002
3095#define ADVERTISE_100_HALF 0x0004
3096#define ADVERTISE_100_FULL 0x0008
3097#define ADVERTISE_1000_HALF 0x0010
3098#define ADVERTISE_1000_FULL 0x0020
3099#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
3100#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds */
3101#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds */
3102
3103#endif /* _E1000_HW_H_ */
diff --git a/drivers/net/ethernet/intel/e1000/e1000_main.c b/drivers/net/ethernet/intel/e1000/e1000_main.c
new file mode 100644
index 000000000000..f97afda941d7
--- /dev/null
+++ b/drivers/net/ethernet/intel/e1000/e1000_main.c
@@ -0,0 +1,4974 @@
1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include "e1000.h"
30#include <net/ip6_checksum.h>
31#include <linux/io.h>
32#include <linux/prefetch.h>
33#include <linux/bitops.h>
34#include <linux/if_vlan.h>
35
36/* Intel Media SOC GbE MDIO physical base address */
37static unsigned long ce4100_gbe_mdio_base_phy;
38/* Intel Media SOC GbE MDIO virtual base address */
39void __iomem *ce4100_gbe_mdio_base_virt;
40
41char e1000_driver_name[] = "e1000";
42static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
43#define DRV_VERSION "7.3.21-k8-NAPI"
44const char e1000_driver_version[] = DRV_VERSION;
45static const char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation.";
46
47/* e1000_pci_tbl - PCI Device ID Table
48 *
49 * Last entry must be all 0s
50 *
51 * Macro expands to...
52 * {PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
53 */
54static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = {
55 INTEL_E1000_ETHERNET_DEVICE(0x1000),
56 INTEL_E1000_ETHERNET_DEVICE(0x1001),
57 INTEL_E1000_ETHERNET_DEVICE(0x1004),
58 INTEL_E1000_ETHERNET_DEVICE(0x1008),
59 INTEL_E1000_ETHERNET_DEVICE(0x1009),
60 INTEL_E1000_ETHERNET_DEVICE(0x100C),
61 INTEL_E1000_ETHERNET_DEVICE(0x100D),
62 INTEL_E1000_ETHERNET_DEVICE(0x100E),
63 INTEL_E1000_ETHERNET_DEVICE(0x100F),
64 INTEL_E1000_ETHERNET_DEVICE(0x1010),
65 INTEL_E1000_ETHERNET_DEVICE(0x1011),
66 INTEL_E1000_ETHERNET_DEVICE(0x1012),
67 INTEL_E1000_ETHERNET_DEVICE(0x1013),
68 INTEL_E1000_ETHERNET_DEVICE(0x1014),
69 INTEL_E1000_ETHERNET_DEVICE(0x1015),
70 INTEL_E1000_ETHERNET_DEVICE(0x1016),
71 INTEL_E1000_ETHERNET_DEVICE(0x1017),
72 INTEL_E1000_ETHERNET_DEVICE(0x1018),
73 INTEL_E1000_ETHERNET_DEVICE(0x1019),
74 INTEL_E1000_ETHERNET_DEVICE(0x101A),
75 INTEL_E1000_ETHERNET_DEVICE(0x101D),
76 INTEL_E1000_ETHERNET_DEVICE(0x101E),
77 INTEL_E1000_ETHERNET_DEVICE(0x1026),
78 INTEL_E1000_ETHERNET_DEVICE(0x1027),
79 INTEL_E1000_ETHERNET_DEVICE(0x1028),
80 INTEL_E1000_ETHERNET_DEVICE(0x1075),
81 INTEL_E1000_ETHERNET_DEVICE(0x1076),
82 INTEL_E1000_ETHERNET_DEVICE(0x1077),
83 INTEL_E1000_ETHERNET_DEVICE(0x1078),
84 INTEL_E1000_ETHERNET_DEVICE(0x1079),
85 INTEL_E1000_ETHERNET_DEVICE(0x107A),
86 INTEL_E1000_ETHERNET_DEVICE(0x107B),
87 INTEL_E1000_ETHERNET_DEVICE(0x107C),
88 INTEL_E1000_ETHERNET_DEVICE(0x108A),
89 INTEL_E1000_ETHERNET_DEVICE(0x1099),
90 INTEL_E1000_ETHERNET_DEVICE(0x10B5),
91 INTEL_E1000_ETHERNET_DEVICE(0x2E6E),
92 /* required last entry */
93 {0,}
94};
95
96MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
97
98int e1000_up(struct e1000_adapter *adapter);
99void e1000_down(struct e1000_adapter *adapter);
100void e1000_reinit_locked(struct e1000_adapter *adapter);
101void e1000_reset(struct e1000_adapter *adapter);
102int e1000_setup_all_tx_resources(struct e1000_adapter *adapter);
103int e1000_setup_all_rx_resources(struct e1000_adapter *adapter);
104void e1000_free_all_tx_resources(struct e1000_adapter *adapter);
105void e1000_free_all_rx_resources(struct e1000_adapter *adapter);
106static int e1000_setup_tx_resources(struct e1000_adapter *adapter,
107 struct e1000_tx_ring *txdr);
108static int e1000_setup_rx_resources(struct e1000_adapter *adapter,
109 struct e1000_rx_ring *rxdr);
110static void e1000_free_tx_resources(struct e1000_adapter *adapter,
111 struct e1000_tx_ring *tx_ring);
112static void e1000_free_rx_resources(struct e1000_adapter *adapter,
113 struct e1000_rx_ring *rx_ring);
114void e1000_update_stats(struct e1000_adapter *adapter);
115
116static int e1000_init_module(void);
117static void e1000_exit_module(void);
118static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
119static void __devexit e1000_remove(struct pci_dev *pdev);
120static int e1000_alloc_queues(struct e1000_adapter *adapter);
121static int e1000_sw_init(struct e1000_adapter *adapter);
122static int e1000_open(struct net_device *netdev);
123static int e1000_close(struct net_device *netdev);
124static void e1000_configure_tx(struct e1000_adapter *adapter);
125static void e1000_configure_rx(struct e1000_adapter *adapter);
126static void e1000_setup_rctl(struct e1000_adapter *adapter);
127static void e1000_clean_all_tx_rings(struct e1000_adapter *adapter);
128static void e1000_clean_all_rx_rings(struct e1000_adapter *adapter);
129static void e1000_clean_tx_ring(struct e1000_adapter *adapter,
130 struct e1000_tx_ring *tx_ring);
131static void e1000_clean_rx_ring(struct e1000_adapter *adapter,
132 struct e1000_rx_ring *rx_ring);
133static void e1000_set_rx_mode(struct net_device *netdev);
134static void e1000_update_phy_info(unsigned long data);
135static void e1000_update_phy_info_task(struct work_struct *work);
136static void e1000_watchdog(unsigned long data);
137static void e1000_82547_tx_fifo_stall(unsigned long data);
138static void e1000_82547_tx_fifo_stall_task(struct work_struct *work);
139static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
140 struct net_device *netdev);
141static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
142static int e1000_change_mtu(struct net_device *netdev, int new_mtu);
143static int e1000_set_mac(struct net_device *netdev, void *p);
144static irqreturn_t e1000_intr(int irq, void *data);
145static bool e1000_clean_tx_irq(struct e1000_adapter *adapter,
146 struct e1000_tx_ring *tx_ring);
147static int e1000_clean(struct napi_struct *napi, int budget);
148static bool e1000_clean_rx_irq(struct e1000_adapter *adapter,
149 struct e1000_rx_ring *rx_ring,
150 int *work_done, int work_to_do);
151static bool e1000_clean_jumbo_rx_irq(struct e1000_adapter *adapter,
152 struct e1000_rx_ring *rx_ring,
153 int *work_done, int work_to_do);
154static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
155 struct e1000_rx_ring *rx_ring,
156 int cleaned_count);
157static void e1000_alloc_jumbo_rx_buffers(struct e1000_adapter *adapter,
158 struct e1000_rx_ring *rx_ring,
159 int cleaned_count);
160static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
161static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
162 int cmd);
163static void e1000_enter_82542_rst(struct e1000_adapter *adapter);
164static void e1000_leave_82542_rst(struct e1000_adapter *adapter);
165static void e1000_tx_timeout(struct net_device *dev);
166static void e1000_reset_task(struct work_struct *work);
167static void e1000_smartspeed(struct e1000_adapter *adapter);
168static int e1000_82547_fifo_workaround(struct e1000_adapter *adapter,
169 struct sk_buff *skb);
170
171static bool e1000_vlan_used(struct e1000_adapter *adapter);
172static void e1000_vlan_mode(struct net_device *netdev, u32 features);
173static void e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid);
174static void e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid);
175static void e1000_restore_vlan(struct e1000_adapter *adapter);
176
177#ifdef CONFIG_PM
178static int e1000_suspend(struct pci_dev *pdev, pm_message_t state);
179static int e1000_resume(struct pci_dev *pdev);
180#endif
181static void e1000_shutdown(struct pci_dev *pdev);
182
183#ifdef CONFIG_NET_POLL_CONTROLLER
184/* for netdump / net console */
185static void e1000_netpoll (struct net_device *netdev);
186#endif
187
188#define COPYBREAK_DEFAULT 256
189static unsigned int copybreak __read_mostly = COPYBREAK_DEFAULT;
190module_param(copybreak, uint, 0644);
191MODULE_PARM_DESC(copybreak,
192 "Maximum size of packet that is copied to a new buffer on receive");
193
194static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
195 pci_channel_state_t state);
196static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev);
197static void e1000_io_resume(struct pci_dev *pdev);
198
199static struct pci_error_handlers e1000_err_handler = {
200 .error_detected = e1000_io_error_detected,
201 .slot_reset = e1000_io_slot_reset,
202 .resume = e1000_io_resume,
203};
204
205static struct pci_driver e1000_driver = {
206 .name = e1000_driver_name,
207 .id_table = e1000_pci_tbl,
208 .probe = e1000_probe,
209 .remove = __devexit_p(e1000_remove),
210#ifdef CONFIG_PM
211 /* Power Management Hooks */
212 .suspend = e1000_suspend,
213 .resume = e1000_resume,
214#endif
215 .shutdown = e1000_shutdown,
216 .err_handler = &e1000_err_handler
217};
218
219MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
220MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
221MODULE_LICENSE("GPL");
222MODULE_VERSION(DRV_VERSION);
223
224static int debug = NETIF_MSG_DRV | NETIF_MSG_PROBE;
225module_param(debug, int, 0);
226MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
227
228/**
229 * e1000_get_hw_dev - return device
230 * used by hardware layer to print debugging information
231 *
232 **/
233struct net_device *e1000_get_hw_dev(struct e1000_hw *hw)
234{
235 struct e1000_adapter *adapter = hw->back;
236 return adapter->netdev;
237}
238
239/**
240 * e1000_init_module - Driver Registration Routine
241 *
242 * e1000_init_module is the first routine called when the driver is
243 * loaded. All it does is register with the PCI subsystem.
244 **/
245
246static int __init e1000_init_module(void)
247{
248 int ret;
249 pr_info("%s - version %s\n", e1000_driver_string, e1000_driver_version);
250
251 pr_info("%s\n", e1000_copyright);
252
253 ret = pci_register_driver(&e1000_driver);
254 if (copybreak != COPYBREAK_DEFAULT) {
255 if (copybreak == 0)
256 pr_info("copybreak disabled\n");
257 else
258 pr_info("copybreak enabled for "
259 "packets <= %u bytes\n", copybreak);
260 }
261 return ret;
262}
263
264module_init(e1000_init_module);
265
266/**
267 * e1000_exit_module - Driver Exit Cleanup Routine
268 *
269 * e1000_exit_module is called just before the driver is removed
270 * from memory.
271 **/
272
273static void __exit e1000_exit_module(void)
274{
275 pci_unregister_driver(&e1000_driver);
276}
277
278module_exit(e1000_exit_module);
279
280static int e1000_request_irq(struct e1000_adapter *adapter)
281{
282 struct net_device *netdev = adapter->netdev;
283 irq_handler_t handler = e1000_intr;
284 int irq_flags = IRQF_SHARED;
285 int err;
286
287 err = request_irq(adapter->pdev->irq, handler, irq_flags, netdev->name,
288 netdev);
289 if (err) {
290 e_err(probe, "Unable to allocate interrupt Error: %d\n", err);
291 }
292
293 return err;
294}
295
296static void e1000_free_irq(struct e1000_adapter *adapter)
297{
298 struct net_device *netdev = adapter->netdev;
299
300 free_irq(adapter->pdev->irq, netdev);
301}
302
303/**
304 * e1000_irq_disable - Mask off interrupt generation on the NIC
305 * @adapter: board private structure
306 **/
307
308static void e1000_irq_disable(struct e1000_adapter *adapter)
309{
310 struct e1000_hw *hw = &adapter->hw;
311
312 ew32(IMC, ~0);
313 E1000_WRITE_FLUSH();
314 synchronize_irq(adapter->pdev->irq);
315}
316
317/**
318 * e1000_irq_enable - Enable default interrupt generation settings
319 * @adapter: board private structure
320 **/
321
322static void e1000_irq_enable(struct e1000_adapter *adapter)
323{
324 struct e1000_hw *hw = &adapter->hw;
325
326 ew32(IMS, IMS_ENABLE_MASK);
327 E1000_WRITE_FLUSH();
328}
329
330static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
331{
332 struct e1000_hw *hw = &adapter->hw;
333 struct net_device *netdev = adapter->netdev;
334 u16 vid = hw->mng_cookie.vlan_id;
335 u16 old_vid = adapter->mng_vlan_id;
336
337 if (!e1000_vlan_used(adapter))
338 return;
339
340 if (!test_bit(vid, adapter->active_vlans)) {
341 if (hw->mng_cookie.status &
342 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) {
343 e1000_vlan_rx_add_vid(netdev, vid);
344 adapter->mng_vlan_id = vid;
345 } else {
346 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
347 }
348 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) &&
349 (vid != old_vid) &&
350 !test_bit(old_vid, adapter->active_vlans))
351 e1000_vlan_rx_kill_vid(netdev, old_vid);
352 } else {
353 adapter->mng_vlan_id = vid;
354 }
355}
356
357static void e1000_init_manageability(struct e1000_adapter *adapter)
358{
359 struct e1000_hw *hw = &adapter->hw;
360
361 if (adapter->en_mng_pt) {
362 u32 manc = er32(MANC);
363
364 /* disable hardware interception of ARP */
365 manc &= ~(E1000_MANC_ARP_EN);
366
367 ew32(MANC, manc);
368 }
369}
370
371static void e1000_release_manageability(struct e1000_adapter *adapter)
372{
373 struct e1000_hw *hw = &adapter->hw;
374
375 if (adapter->en_mng_pt) {
376 u32 manc = er32(MANC);
377
378 /* re-enable hardware interception of ARP */
379 manc |= E1000_MANC_ARP_EN;
380
381 ew32(MANC, manc);
382 }
383}
384
385/**
386 * e1000_configure - configure the hardware for RX and TX
387 * @adapter = private board structure
388 **/
389static void e1000_configure(struct e1000_adapter *adapter)
390{
391 struct net_device *netdev = adapter->netdev;
392 int i;
393
394 e1000_set_rx_mode(netdev);
395
396 e1000_restore_vlan(adapter);
397 e1000_init_manageability(adapter);
398
399 e1000_configure_tx(adapter);
400 e1000_setup_rctl(adapter);
401 e1000_configure_rx(adapter);
402 /* call E1000_DESC_UNUSED which always leaves
403 * at least 1 descriptor unused to make sure
404 * next_to_use != next_to_clean */
405 for (i = 0; i < adapter->num_rx_queues; i++) {
406 struct e1000_rx_ring *ring = &adapter->rx_ring[i];
407 adapter->alloc_rx_buf(adapter, ring,
408 E1000_DESC_UNUSED(ring));
409 }
410}
411
412int e1000_up(struct e1000_adapter *adapter)
413{
414 struct e1000_hw *hw = &adapter->hw;
415
416 /* hardware has been reset, we need to reload some things */
417 e1000_configure(adapter);
418
419 clear_bit(__E1000_DOWN, &adapter->flags);
420
421 napi_enable(&adapter->napi);
422
423 e1000_irq_enable(adapter);
424
425 netif_wake_queue(adapter->netdev);
426
427 /* fire a link change interrupt to start the watchdog */
428 ew32(ICS, E1000_ICS_LSC);
429 return 0;
430}
431
432/**
433 * e1000_power_up_phy - restore link in case the phy was powered down
434 * @adapter: address of board private structure
435 *
436 * The phy may be powered down to save power and turn off link when the
437 * driver is unloaded and wake on lan is not enabled (among others)
438 * *** this routine MUST be followed by a call to e1000_reset ***
439 *
440 **/
441
442void e1000_power_up_phy(struct e1000_adapter *adapter)
443{
444 struct e1000_hw *hw = &adapter->hw;
445 u16 mii_reg = 0;
446
447 /* Just clear the power down bit to wake the phy back up */
448 if (hw->media_type == e1000_media_type_copper) {
449 /* according to the manual, the phy will retain its
450 * settings across a power-down/up cycle */
451 e1000_read_phy_reg(hw, PHY_CTRL, &mii_reg);
452 mii_reg &= ~MII_CR_POWER_DOWN;
453 e1000_write_phy_reg(hw, PHY_CTRL, mii_reg);
454 }
455}
456
457static void e1000_power_down_phy(struct e1000_adapter *adapter)
458{
459 struct e1000_hw *hw = &adapter->hw;
460
461 /* Power down the PHY so no link is implied when interface is down *
462 * The PHY cannot be powered down if any of the following is true *
463 * (a) WoL is enabled
464 * (b) AMT is active
465 * (c) SoL/IDER session is active */
466 if (!adapter->wol && hw->mac_type >= e1000_82540 &&
467 hw->media_type == e1000_media_type_copper) {
468 u16 mii_reg = 0;
469
470 switch (hw->mac_type) {
471 case e1000_82540:
472 case e1000_82545:
473 case e1000_82545_rev_3:
474 case e1000_82546:
475 case e1000_ce4100:
476 case e1000_82546_rev_3:
477 case e1000_82541:
478 case e1000_82541_rev_2:
479 case e1000_82547:
480 case e1000_82547_rev_2:
481 if (er32(MANC) & E1000_MANC_SMBUS_EN)
482 goto out;
483 break;
484 default:
485 goto out;
486 }
487 e1000_read_phy_reg(hw, PHY_CTRL, &mii_reg);
488 mii_reg |= MII_CR_POWER_DOWN;
489 e1000_write_phy_reg(hw, PHY_CTRL, mii_reg);
490 mdelay(1);
491 }
492out:
493 return;
494}
495
496void e1000_down(struct e1000_adapter *adapter)
497{
498 struct e1000_hw *hw = &adapter->hw;
499 struct net_device *netdev = adapter->netdev;
500 u32 rctl, tctl;
501
502
503 /* disable receives in the hardware */
504 rctl = er32(RCTL);
505 ew32(RCTL, rctl & ~E1000_RCTL_EN);
506 /* flush and sleep below */
507
508 netif_tx_disable(netdev);
509
510 /* disable transmits in the hardware */
511 tctl = er32(TCTL);
512 tctl &= ~E1000_TCTL_EN;
513 ew32(TCTL, tctl);
514 /* flush both disables and wait for them to finish */
515 E1000_WRITE_FLUSH();
516 msleep(10);
517
518 napi_disable(&adapter->napi);
519
520 e1000_irq_disable(adapter);
521
522 /*
523 * Setting DOWN must be after irq_disable to prevent
524 * a screaming interrupt. Setting DOWN also prevents
525 * timers and tasks from rescheduling.
526 */
527 set_bit(__E1000_DOWN, &adapter->flags);
528
529 del_timer_sync(&adapter->tx_fifo_stall_timer);
530 del_timer_sync(&adapter->watchdog_timer);
531 del_timer_sync(&adapter->phy_info_timer);
532
533 adapter->link_speed = 0;
534 adapter->link_duplex = 0;
535 netif_carrier_off(netdev);
536
537 e1000_reset(adapter);
538 e1000_clean_all_tx_rings(adapter);
539 e1000_clean_all_rx_rings(adapter);
540}
541
542static void e1000_reinit_safe(struct e1000_adapter *adapter)
543{
544 while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
545 msleep(1);
546 rtnl_lock();
547 e1000_down(adapter);
548 e1000_up(adapter);
549 rtnl_unlock();
550 clear_bit(__E1000_RESETTING, &adapter->flags);
551}
552
553void e1000_reinit_locked(struct e1000_adapter *adapter)
554{
555 /* if rtnl_lock is not held the call path is bogus */
556 ASSERT_RTNL();
557 WARN_ON(in_interrupt());
558 while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
559 msleep(1);
560 e1000_down(adapter);
561 e1000_up(adapter);
562 clear_bit(__E1000_RESETTING, &adapter->flags);
563}
564
565void e1000_reset(struct e1000_adapter *adapter)
566{
567 struct e1000_hw *hw = &adapter->hw;
568 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
569 bool legacy_pba_adjust = false;
570 u16 hwm;
571
572 /* Repartition Pba for greater than 9k mtu
573 * To take effect CTRL.RST is required.
574 */
575
576 switch (hw->mac_type) {
577 case e1000_82542_rev2_0:
578 case e1000_82542_rev2_1:
579 case e1000_82543:
580 case e1000_82544:
581 case e1000_82540:
582 case e1000_82541:
583 case e1000_82541_rev_2:
584 legacy_pba_adjust = true;
585 pba = E1000_PBA_48K;
586 break;
587 case e1000_82545:
588 case e1000_82545_rev_3:
589 case e1000_82546:
590 case e1000_ce4100:
591 case e1000_82546_rev_3:
592 pba = E1000_PBA_48K;
593 break;
594 case e1000_82547:
595 case e1000_82547_rev_2:
596 legacy_pba_adjust = true;
597 pba = E1000_PBA_30K;
598 break;
599 case e1000_undefined:
600 case e1000_num_macs:
601 break;
602 }
603
604 if (legacy_pba_adjust) {
605 if (hw->max_frame_size > E1000_RXBUFFER_8192)
606 pba -= 8; /* allocate more FIFO for Tx */
607
608 if (hw->mac_type == e1000_82547) {
609 adapter->tx_fifo_head = 0;
610 adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT;
611 adapter->tx_fifo_size =
612 (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT;
613 atomic_set(&adapter->tx_fifo_stall, 0);
614 }
615 } else if (hw->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
616 /* adjust PBA for jumbo frames */
617 ew32(PBA, pba);
618
619 /* To maintain wire speed transmits, the Tx FIFO should be
620 * large enough to accommodate two full transmit packets,
621 * rounded up to the next 1KB and expressed in KB. Likewise,
622 * the Rx FIFO should be large enough to accommodate at least
623 * one full receive packet and is similarly rounded up and
624 * expressed in KB. */
625 pba = er32(PBA);
626 /* upper 16 bits has Tx packet buffer allocation size in KB */
627 tx_space = pba >> 16;
628 /* lower 16 bits has Rx packet buffer allocation size in KB */
629 pba &= 0xffff;
630 /*
631 * the tx fifo also stores 16 bytes of information about the tx
632 * but don't include ethernet FCS because hardware appends it
633 */
634 min_tx_space = (hw->max_frame_size +
635 sizeof(struct e1000_tx_desc) -
636 ETH_FCS_LEN) * 2;
637 min_tx_space = ALIGN(min_tx_space, 1024);
638 min_tx_space >>= 10;
639 /* software strips receive CRC, so leave room for it */
640 min_rx_space = hw->max_frame_size;
641 min_rx_space = ALIGN(min_rx_space, 1024);
642 min_rx_space >>= 10;
643
644 /* If current Tx allocation is less than the min Tx FIFO size,
645 * and the min Tx FIFO size is less than the current Rx FIFO
646 * allocation, take space away from current Rx allocation */
647 if (tx_space < min_tx_space &&
648 ((min_tx_space - tx_space) < pba)) {
649 pba = pba - (min_tx_space - tx_space);
650
651 /* PCI/PCIx hardware has PBA alignment constraints */
652 switch (hw->mac_type) {
653 case e1000_82545 ... e1000_82546_rev_3:
654 pba &= ~(E1000_PBA_8K - 1);
655 break;
656 default:
657 break;
658 }
659
660 /* if short on rx space, rx wins and must trump tx
661 * adjustment or use Early Receive if available */
662 if (pba < min_rx_space)
663 pba = min_rx_space;
664 }
665 }
666
667 ew32(PBA, pba);
668
669 /*
670 * flow control settings:
671 * The high water mark must be low enough to fit one full frame
672 * (or the size used for early receive) above it in the Rx FIFO.
673 * Set it to the lower of:
674 * - 90% of the Rx FIFO size, and
675 * - the full Rx FIFO size minus the early receive size (for parts
676 * with ERT support assuming ERT set to E1000_ERT_2048), or
677 * - the full Rx FIFO size minus one full frame
678 */
679 hwm = min(((pba << 10) * 9 / 10),
680 ((pba << 10) - hw->max_frame_size));
681
682 hw->fc_high_water = hwm & 0xFFF8; /* 8-byte granularity */
683 hw->fc_low_water = hw->fc_high_water - 8;
684 hw->fc_pause_time = E1000_FC_PAUSE_TIME;
685 hw->fc_send_xon = 1;
686 hw->fc = hw->original_fc;
687
688 /* Allow time for pending master requests to run */
689 e1000_reset_hw(hw);
690 if (hw->mac_type >= e1000_82544)
691 ew32(WUC, 0);
692
693 if (e1000_init_hw(hw))
694 e_dev_err("Hardware Error\n");
695 e1000_update_mng_vlan(adapter);
696
697 /* if (adapter->hwflags & HWFLAGS_PHY_PWR_BIT) { */
698 if (hw->mac_type >= e1000_82544 &&
699 hw->autoneg == 1 &&
700 hw->autoneg_advertised == ADVERTISE_1000_FULL) {
701 u32 ctrl = er32(CTRL);
702 /* clear phy power management bit if we are in gig only mode,
703 * which if enabled will attempt negotiation to 100Mb, which
704 * can cause a loss of link at power off or driver unload */
705 ctrl &= ~E1000_CTRL_SWDPIN3;
706 ew32(CTRL, ctrl);
707 }
708
709 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
710 ew32(VET, ETHERNET_IEEE_VLAN_TYPE);
711
712 e1000_reset_adaptive(hw);
713 e1000_phy_get_info(hw, &adapter->phy_info);
714
715 e1000_release_manageability(adapter);
716}
717
718/**
719 * Dump the eeprom for users having checksum issues
720 **/
721static void e1000_dump_eeprom(struct e1000_adapter *adapter)
722{
723 struct net_device *netdev = adapter->netdev;
724 struct ethtool_eeprom eeprom;
725 const struct ethtool_ops *ops = netdev->ethtool_ops;
726 u8 *data;
727 int i;
728 u16 csum_old, csum_new = 0;
729
730 eeprom.len = ops->get_eeprom_len(netdev);
731 eeprom.offset = 0;
732
733 data = kmalloc(eeprom.len, GFP_KERNEL);
734 if (!data) {
735 pr_err("Unable to allocate memory to dump EEPROM data\n");
736 return;
737 }
738
739 ops->get_eeprom(netdev, &eeprom, data);
740
741 csum_old = (data[EEPROM_CHECKSUM_REG * 2]) +
742 (data[EEPROM_CHECKSUM_REG * 2 + 1] << 8);
743 for (i = 0; i < EEPROM_CHECKSUM_REG * 2; i += 2)
744 csum_new += data[i] + (data[i + 1] << 8);
745 csum_new = EEPROM_SUM - csum_new;
746
747 pr_err("/*********************/\n");
748 pr_err("Current EEPROM Checksum : 0x%04x\n", csum_old);
749 pr_err("Calculated : 0x%04x\n", csum_new);
750
751 pr_err("Offset Values\n");
752 pr_err("======== ======\n");
753 print_hex_dump(KERN_ERR, "", DUMP_PREFIX_OFFSET, 16, 1, data, 128, 0);
754
755 pr_err("Include this output when contacting your support provider.\n");
756 pr_err("This is not a software error! Something bad happened to\n");
757 pr_err("your hardware or EEPROM image. Ignoring this problem could\n");
758 pr_err("result in further problems, possibly loss of data,\n");
759 pr_err("corruption or system hangs!\n");
760 pr_err("The MAC Address will be reset to 00:00:00:00:00:00,\n");
761 pr_err("which is invalid and requires you to set the proper MAC\n");
762 pr_err("address manually before continuing to enable this network\n");
763 pr_err("device. Please inspect the EEPROM dump and report the\n");
764 pr_err("issue to your hardware vendor or Intel Customer Support.\n");
765 pr_err("/*********************/\n");
766
767 kfree(data);
768}
769
770/**
771 * e1000_is_need_ioport - determine if an adapter needs ioport resources or not
772 * @pdev: PCI device information struct
773 *
774 * Return true if an adapter needs ioport resources
775 **/
776static int e1000_is_need_ioport(struct pci_dev *pdev)
777{
778 switch (pdev->device) {
779 case E1000_DEV_ID_82540EM:
780 case E1000_DEV_ID_82540EM_LOM:
781 case E1000_DEV_ID_82540EP:
782 case E1000_DEV_ID_82540EP_LOM:
783 case E1000_DEV_ID_82540EP_LP:
784 case E1000_DEV_ID_82541EI:
785 case E1000_DEV_ID_82541EI_MOBILE:
786 case E1000_DEV_ID_82541ER:
787 case E1000_DEV_ID_82541ER_LOM:
788 case E1000_DEV_ID_82541GI:
789 case E1000_DEV_ID_82541GI_LF:
790 case E1000_DEV_ID_82541GI_MOBILE:
791 case E1000_DEV_ID_82544EI_COPPER:
792 case E1000_DEV_ID_82544EI_FIBER:
793 case E1000_DEV_ID_82544GC_COPPER:
794 case E1000_DEV_ID_82544GC_LOM:
795 case E1000_DEV_ID_82545EM_COPPER:
796 case E1000_DEV_ID_82545EM_FIBER:
797 case E1000_DEV_ID_82546EB_COPPER:
798 case E1000_DEV_ID_82546EB_FIBER:
799 case E1000_DEV_ID_82546EB_QUAD_COPPER:
800 return true;
801 default:
802 return false;
803 }
804}
805
806static u32 e1000_fix_features(struct net_device *netdev, u32 features)
807{
808 /*
809 * Since there is no support for separate rx/tx vlan accel
810 * enable/disable make sure tx flag is always in same state as rx.
811 */
812 if (features & NETIF_F_HW_VLAN_RX)
813 features |= NETIF_F_HW_VLAN_TX;
814 else
815 features &= ~NETIF_F_HW_VLAN_TX;
816
817 return features;
818}
819
820static int e1000_set_features(struct net_device *netdev, u32 features)
821{
822 struct e1000_adapter *adapter = netdev_priv(netdev);
823 u32 changed = features ^ netdev->features;
824
825 if (changed & NETIF_F_HW_VLAN_RX)
826 e1000_vlan_mode(netdev, features);
827
828 if (!(changed & NETIF_F_RXCSUM))
829 return 0;
830
831 adapter->rx_csum = !!(features & NETIF_F_RXCSUM);
832
833 if (netif_running(netdev))
834 e1000_reinit_locked(adapter);
835 else
836 e1000_reset(adapter);
837
838 return 0;
839}
840
841static const struct net_device_ops e1000_netdev_ops = {
842 .ndo_open = e1000_open,
843 .ndo_stop = e1000_close,
844 .ndo_start_xmit = e1000_xmit_frame,
845 .ndo_get_stats = e1000_get_stats,
846 .ndo_set_rx_mode = e1000_set_rx_mode,
847 .ndo_set_mac_address = e1000_set_mac,
848 .ndo_tx_timeout = e1000_tx_timeout,
849 .ndo_change_mtu = e1000_change_mtu,
850 .ndo_do_ioctl = e1000_ioctl,
851 .ndo_validate_addr = eth_validate_addr,
852 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
853 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
854#ifdef CONFIG_NET_POLL_CONTROLLER
855 .ndo_poll_controller = e1000_netpoll,
856#endif
857 .ndo_fix_features = e1000_fix_features,
858 .ndo_set_features = e1000_set_features,
859};
860
861/**
862 * e1000_init_hw_struct - initialize members of hw struct
863 * @adapter: board private struct
864 * @hw: structure used by e1000_hw.c
865 *
866 * Factors out initialization of the e1000_hw struct to its own function
867 * that can be called very early at init (just after struct allocation).
868 * Fields are initialized based on PCI device information and
869 * OS network device settings (MTU size).
870 * Returns negative error codes if MAC type setup fails.
871 */
872static int e1000_init_hw_struct(struct e1000_adapter *adapter,
873 struct e1000_hw *hw)
874{
875 struct pci_dev *pdev = adapter->pdev;
876
877 /* PCI config space info */
878 hw->vendor_id = pdev->vendor;
879 hw->device_id = pdev->device;
880 hw->subsystem_vendor_id = pdev->subsystem_vendor;
881 hw->subsystem_id = pdev->subsystem_device;
882 hw->revision_id = pdev->revision;
883
884 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
885
886 hw->max_frame_size = adapter->netdev->mtu +
887 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
888 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
889
890 /* identify the MAC */
891 if (e1000_set_mac_type(hw)) {
892 e_err(probe, "Unknown MAC Type\n");
893 return -EIO;
894 }
895
896 switch (hw->mac_type) {
897 default:
898 break;
899 case e1000_82541:
900 case e1000_82547:
901 case e1000_82541_rev_2:
902 case e1000_82547_rev_2:
903 hw->phy_init_script = 1;
904 break;
905 }
906
907 e1000_set_media_type(hw);
908 e1000_get_bus_info(hw);
909
910 hw->wait_autoneg_complete = false;
911 hw->tbi_compatibility_en = true;
912 hw->adaptive_ifs = true;
913
914 /* Copper options */
915
916 if (hw->media_type == e1000_media_type_copper) {
917 hw->mdix = AUTO_ALL_MODES;
918 hw->disable_polarity_correction = false;
919 hw->master_slave = E1000_MASTER_SLAVE;
920 }
921
922 return 0;
923}
924
925/**
926 * e1000_probe - Device Initialization Routine
927 * @pdev: PCI device information struct
928 * @ent: entry in e1000_pci_tbl
929 *
930 * Returns 0 on success, negative on failure
931 *
932 * e1000_probe initializes an adapter identified by a pci_dev structure.
933 * The OS initialization, configuring of the adapter private structure,
934 * and a hardware reset occur.
935 **/
936static int __devinit e1000_probe(struct pci_dev *pdev,
937 const struct pci_device_id *ent)
938{
939 struct net_device *netdev;
940 struct e1000_adapter *adapter;
941 struct e1000_hw *hw;
942
943 static int cards_found = 0;
944 static int global_quad_port_a = 0; /* global ksp3 port a indication */
945 int i, err, pci_using_dac;
946 u16 eeprom_data = 0;
947 u16 tmp = 0;
948 u16 eeprom_apme_mask = E1000_EEPROM_APME;
949 int bars, need_ioport;
950
951 /* do not allocate ioport bars when not needed */
952 need_ioport = e1000_is_need_ioport(pdev);
953 if (need_ioport) {
954 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
955 err = pci_enable_device(pdev);
956 } else {
957 bars = pci_select_bars(pdev, IORESOURCE_MEM);
958 err = pci_enable_device_mem(pdev);
959 }
960 if (err)
961 return err;
962
963 err = pci_request_selected_regions(pdev, bars, e1000_driver_name);
964 if (err)
965 goto err_pci_reg;
966
967 pci_set_master(pdev);
968 err = pci_save_state(pdev);
969 if (err)
970 goto err_alloc_etherdev;
971
972 err = -ENOMEM;
973 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
974 if (!netdev)
975 goto err_alloc_etherdev;
976
977 SET_NETDEV_DEV(netdev, &pdev->dev);
978
979 pci_set_drvdata(pdev, netdev);
980 adapter = netdev_priv(netdev);
981 adapter->netdev = netdev;
982 adapter->pdev = pdev;
983 adapter->msg_enable = (1 << debug) - 1;
984 adapter->bars = bars;
985 adapter->need_ioport = need_ioport;
986
987 hw = &adapter->hw;
988 hw->back = adapter;
989
990 err = -EIO;
991 hw->hw_addr = pci_ioremap_bar(pdev, BAR_0);
992 if (!hw->hw_addr)
993 goto err_ioremap;
994
995 if (adapter->need_ioport) {
996 for (i = BAR_1; i <= BAR_5; i++) {
997 if (pci_resource_len(pdev, i) == 0)
998 continue;
999 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
1000 hw->io_base = pci_resource_start(pdev, i);
1001 break;
1002 }
1003 }
1004 }
1005
1006 /* make ready for any if (hw->...) below */
1007 err = e1000_init_hw_struct(adapter, hw);
1008 if (err)
1009 goto err_sw_init;
1010
1011 /*
1012 * there is a workaround being applied below that limits
1013 * 64-bit DMA addresses to 64-bit hardware. There are some
1014 * 32-bit adapters that Tx hang when given 64-bit DMA addresses
1015 */
1016 pci_using_dac = 0;
1017 if ((hw->bus_type == e1000_bus_type_pcix) &&
1018 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
1019 /*
1020 * according to DMA-API-HOWTO, coherent calls will always
1021 * succeed if the set call did
1022 */
1023 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1024 pci_using_dac = 1;
1025 } else {
1026 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1027 if (err) {
1028 pr_err("No usable DMA config, aborting\n");
1029 goto err_dma;
1030 }
1031 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1032 }
1033
1034 netdev->netdev_ops = &e1000_netdev_ops;
1035 e1000_set_ethtool_ops(netdev);
1036 netdev->watchdog_timeo = 5 * HZ;
1037 netif_napi_add(netdev, &adapter->napi, e1000_clean, 64);
1038
1039 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1040
1041 adapter->bd_number = cards_found;
1042
1043 /* setup the private structure */
1044
1045 err = e1000_sw_init(adapter);
1046 if (err)
1047 goto err_sw_init;
1048
1049 err = -EIO;
1050 if (hw->mac_type == e1000_ce4100) {
1051 ce4100_gbe_mdio_base_phy = pci_resource_start(pdev, BAR_1);
1052 ce4100_gbe_mdio_base_virt = ioremap(ce4100_gbe_mdio_base_phy,
1053 pci_resource_len(pdev, BAR_1));
1054
1055 if (!ce4100_gbe_mdio_base_virt)
1056 goto err_mdio_ioremap;
1057 }
1058
1059 if (hw->mac_type >= e1000_82543) {
1060 netdev->hw_features = NETIF_F_SG |
1061 NETIF_F_HW_CSUM |
1062 NETIF_F_HW_VLAN_RX;
1063 netdev->features = NETIF_F_HW_VLAN_TX |
1064 NETIF_F_HW_VLAN_FILTER;
1065 }
1066
1067 if ((hw->mac_type >= e1000_82544) &&
1068 (hw->mac_type != e1000_82547))
1069 netdev->hw_features |= NETIF_F_TSO;
1070
1071 netdev->features |= netdev->hw_features;
1072 netdev->hw_features |= NETIF_F_RXCSUM;
1073
1074 if (pci_using_dac) {
1075 netdev->features |= NETIF_F_HIGHDMA;
1076 netdev->vlan_features |= NETIF_F_HIGHDMA;
1077 }
1078
1079 netdev->vlan_features |= NETIF_F_TSO;
1080 netdev->vlan_features |= NETIF_F_HW_CSUM;
1081 netdev->vlan_features |= NETIF_F_SG;
1082
1083 adapter->en_mng_pt = e1000_enable_mng_pass_thru(hw);
1084
1085 /* initialize eeprom parameters */
1086 if (e1000_init_eeprom_params(hw)) {
1087 e_err(probe, "EEPROM initialization failed\n");
1088 goto err_eeprom;
1089 }
1090
1091 /* before reading the EEPROM, reset the controller to
1092 * put the device in a known good starting state */
1093
1094 e1000_reset_hw(hw);
1095
1096 /* make sure the EEPROM is good */
1097 if (e1000_validate_eeprom_checksum(hw) < 0) {
1098 e_err(probe, "The EEPROM Checksum Is Not Valid\n");
1099 e1000_dump_eeprom(adapter);
1100 /*
1101 * set MAC address to all zeroes to invalidate and temporary
1102 * disable this device for the user. This blocks regular
1103 * traffic while still permitting ethtool ioctls from reaching
1104 * the hardware as well as allowing the user to run the
1105 * interface after manually setting a hw addr using
1106 * `ip set address`
1107 */
1108 memset(hw->mac_addr, 0, netdev->addr_len);
1109 } else {
1110 /* copy the MAC address out of the EEPROM */
1111 if (e1000_read_mac_addr(hw))
1112 e_err(probe, "EEPROM Read Error\n");
1113 }
1114 /* don't block initalization here due to bad MAC address */
1115 memcpy(netdev->dev_addr, hw->mac_addr, netdev->addr_len);
1116 memcpy(netdev->perm_addr, hw->mac_addr, netdev->addr_len);
1117
1118 if (!is_valid_ether_addr(netdev->perm_addr))
1119 e_err(probe, "Invalid MAC Address\n");
1120
1121 init_timer(&adapter->tx_fifo_stall_timer);
1122 adapter->tx_fifo_stall_timer.function = e1000_82547_tx_fifo_stall;
1123 adapter->tx_fifo_stall_timer.data = (unsigned long)adapter;
1124
1125 init_timer(&adapter->watchdog_timer);
1126 adapter->watchdog_timer.function = e1000_watchdog;
1127 adapter->watchdog_timer.data = (unsigned long) adapter;
1128
1129 init_timer(&adapter->phy_info_timer);
1130 adapter->phy_info_timer.function = e1000_update_phy_info;
1131 adapter->phy_info_timer.data = (unsigned long)adapter;
1132
1133 INIT_WORK(&adapter->fifo_stall_task, e1000_82547_tx_fifo_stall_task);
1134 INIT_WORK(&adapter->reset_task, e1000_reset_task);
1135 INIT_WORK(&adapter->phy_info_task, e1000_update_phy_info_task);
1136
1137 e1000_check_options(adapter);
1138
1139 /* Initial Wake on LAN setting
1140 * If APM wake is enabled in the EEPROM,
1141 * enable the ACPI Magic Packet filter
1142 */
1143
1144 switch (hw->mac_type) {
1145 case e1000_82542_rev2_0:
1146 case e1000_82542_rev2_1:
1147 case e1000_82543:
1148 break;
1149 case e1000_82544:
1150 e1000_read_eeprom(hw,
1151 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
1152 eeprom_apme_mask = E1000_EEPROM_82544_APM;
1153 break;
1154 case e1000_82546:
1155 case e1000_82546_rev_3:
1156 if (er32(STATUS) & E1000_STATUS_FUNC_1){
1157 e1000_read_eeprom(hw,
1158 EEPROM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
1159 break;
1160 }
1161 /* Fall Through */
1162 default:
1163 e1000_read_eeprom(hw,
1164 EEPROM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
1165 break;
1166 }
1167 if (eeprom_data & eeprom_apme_mask)
1168 adapter->eeprom_wol |= E1000_WUFC_MAG;
1169
1170 /* now that we have the eeprom settings, apply the special cases
1171 * where the eeprom may be wrong or the board simply won't support
1172 * wake on lan on a particular port */
1173 switch (pdev->device) {
1174 case E1000_DEV_ID_82546GB_PCIE:
1175 adapter->eeprom_wol = 0;
1176 break;
1177 case E1000_DEV_ID_82546EB_FIBER:
1178 case E1000_DEV_ID_82546GB_FIBER:
1179 /* Wake events only supported on port A for dual fiber
1180 * regardless of eeprom setting */
1181 if (er32(STATUS) & E1000_STATUS_FUNC_1)
1182 adapter->eeprom_wol = 0;
1183 break;
1184 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1185 /* if quad port adapter, disable WoL on all but port A */
1186 if (global_quad_port_a != 0)
1187 adapter->eeprom_wol = 0;
1188 else
1189 adapter->quad_port_a = 1;
1190 /* Reset for multiple quad port adapters */
1191 if (++global_quad_port_a == 4)
1192 global_quad_port_a = 0;
1193 break;
1194 }
1195
1196 /* initialize the wol settings based on the eeprom settings */
1197 adapter->wol = adapter->eeprom_wol;
1198 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1199
1200 /* Auto detect PHY address */
1201 if (hw->mac_type == e1000_ce4100) {
1202 for (i = 0; i < 32; i++) {
1203 hw->phy_addr = i;
1204 e1000_read_phy_reg(hw, PHY_ID2, &tmp);
1205 if (tmp == 0 || tmp == 0xFF) {
1206 if (i == 31)
1207 goto err_eeprom;
1208 continue;
1209 } else
1210 break;
1211 }
1212 }
1213
1214 /* reset the hardware with the new settings */
1215 e1000_reset(adapter);
1216
1217 strcpy(netdev->name, "eth%d");
1218 err = register_netdev(netdev);
1219 if (err)
1220 goto err_register;
1221
1222 e1000_vlan_mode(netdev, netdev->features);
1223
1224 /* print bus type/speed/width info */
1225 e_info(probe, "(PCI%s:%dMHz:%d-bit) %pM\n",
1226 ((hw->bus_type == e1000_bus_type_pcix) ? "-X" : ""),
1227 ((hw->bus_speed == e1000_bus_speed_133) ? 133 :
1228 (hw->bus_speed == e1000_bus_speed_120) ? 120 :
1229 (hw->bus_speed == e1000_bus_speed_100) ? 100 :
1230 (hw->bus_speed == e1000_bus_speed_66) ? 66 : 33),
1231 ((hw->bus_width == e1000_bus_width_64) ? 64 : 32),
1232 netdev->dev_addr);
1233
1234 /* carrier off reporting is important to ethtool even BEFORE open */
1235 netif_carrier_off(netdev);
1236
1237 e_info(probe, "Intel(R) PRO/1000 Network Connection\n");
1238
1239 cards_found++;
1240 return 0;
1241
1242err_register:
1243err_eeprom:
1244 e1000_phy_hw_reset(hw);
1245
1246 if (hw->flash_address)
1247 iounmap(hw->flash_address);
1248 kfree(adapter->tx_ring);
1249 kfree(adapter->rx_ring);
1250err_dma:
1251err_sw_init:
1252err_mdio_ioremap:
1253 iounmap(ce4100_gbe_mdio_base_virt);
1254 iounmap(hw->hw_addr);
1255err_ioremap:
1256 free_netdev(netdev);
1257err_alloc_etherdev:
1258 pci_release_selected_regions(pdev, bars);
1259err_pci_reg:
1260 pci_disable_device(pdev);
1261 return err;
1262}
1263
1264/**
1265 * e1000_remove - Device Removal Routine
1266 * @pdev: PCI device information struct
1267 *
1268 * e1000_remove is called by the PCI subsystem to alert the driver
1269 * that it should release a PCI device. The could be caused by a
1270 * Hot-Plug event, or because the driver is going to be removed from
1271 * memory.
1272 **/
1273
1274static void __devexit e1000_remove(struct pci_dev *pdev)
1275{
1276 struct net_device *netdev = pci_get_drvdata(pdev);
1277 struct e1000_adapter *adapter = netdev_priv(netdev);
1278 struct e1000_hw *hw = &adapter->hw;
1279
1280 set_bit(__E1000_DOWN, &adapter->flags);
1281 del_timer_sync(&adapter->tx_fifo_stall_timer);
1282 del_timer_sync(&adapter->watchdog_timer);
1283 del_timer_sync(&adapter->phy_info_timer);
1284
1285 cancel_work_sync(&adapter->reset_task);
1286
1287 e1000_release_manageability(adapter);
1288
1289 unregister_netdev(netdev);
1290
1291 e1000_phy_hw_reset(hw);
1292
1293 kfree(adapter->tx_ring);
1294 kfree(adapter->rx_ring);
1295
1296 iounmap(hw->hw_addr);
1297 if (hw->flash_address)
1298 iounmap(hw->flash_address);
1299 pci_release_selected_regions(pdev, adapter->bars);
1300
1301 free_netdev(netdev);
1302
1303 pci_disable_device(pdev);
1304}
1305
1306/**
1307 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
1308 * @adapter: board private structure to initialize
1309 *
1310 * e1000_sw_init initializes the Adapter private data structure.
1311 * e1000_init_hw_struct MUST be called before this function
1312 **/
1313
1314static int __devinit e1000_sw_init(struct e1000_adapter *adapter)
1315{
1316 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1317
1318 adapter->num_tx_queues = 1;
1319 adapter->num_rx_queues = 1;
1320
1321 if (e1000_alloc_queues(adapter)) {
1322 e_err(probe, "Unable to allocate memory for queues\n");
1323 return -ENOMEM;
1324 }
1325
1326 /* Explicitly disable IRQ since the NIC can be in any state. */
1327 e1000_irq_disable(adapter);
1328
1329 spin_lock_init(&adapter->stats_lock);
1330
1331 set_bit(__E1000_DOWN, &adapter->flags);
1332
1333 return 0;
1334}
1335
1336/**
1337 * e1000_alloc_queues - Allocate memory for all rings
1338 * @adapter: board private structure to initialize
1339 *
1340 * We allocate one ring per queue at run-time since we don't know the
1341 * number of queues at compile-time.
1342 **/
1343
1344static int __devinit e1000_alloc_queues(struct e1000_adapter *adapter)
1345{
1346 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
1347 sizeof(struct e1000_tx_ring), GFP_KERNEL);
1348 if (!adapter->tx_ring)
1349 return -ENOMEM;
1350
1351 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
1352 sizeof(struct e1000_rx_ring), GFP_KERNEL);
1353 if (!adapter->rx_ring) {
1354 kfree(adapter->tx_ring);
1355 return -ENOMEM;
1356 }
1357
1358 return E1000_SUCCESS;
1359}
1360
1361/**
1362 * e1000_open - Called when a network interface is made active
1363 * @netdev: network interface device structure
1364 *
1365 * Returns 0 on success, negative value on failure
1366 *
1367 * The open entry point is called when a network interface is made
1368 * active by the system (IFF_UP). At this point all resources needed
1369 * for transmit and receive operations are allocated, the interrupt
1370 * handler is registered with the OS, the watchdog timer is started,
1371 * and the stack is notified that the interface is ready.
1372 **/
1373
1374static int e1000_open(struct net_device *netdev)
1375{
1376 struct e1000_adapter *adapter = netdev_priv(netdev);
1377 struct e1000_hw *hw = &adapter->hw;
1378 int err;
1379
1380 /* disallow open during test */
1381 if (test_bit(__E1000_TESTING, &adapter->flags))
1382 return -EBUSY;
1383
1384 netif_carrier_off(netdev);
1385
1386 /* allocate transmit descriptors */
1387 err = e1000_setup_all_tx_resources(adapter);
1388 if (err)
1389 goto err_setup_tx;
1390
1391 /* allocate receive descriptors */
1392 err = e1000_setup_all_rx_resources(adapter);
1393 if (err)
1394 goto err_setup_rx;
1395
1396 e1000_power_up_phy(adapter);
1397
1398 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
1399 if ((hw->mng_cookie.status &
1400 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1401 e1000_update_mng_vlan(adapter);
1402 }
1403
1404 /* before we allocate an interrupt, we must be ready to handle it.
1405 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1406 * as soon as we call pci_request_irq, so we have to setup our
1407 * clean_rx handler before we do so. */
1408 e1000_configure(adapter);
1409
1410 err = e1000_request_irq(adapter);
1411 if (err)
1412 goto err_req_irq;
1413
1414 /* From here on the code is the same as e1000_up() */
1415 clear_bit(__E1000_DOWN, &adapter->flags);
1416
1417 napi_enable(&adapter->napi);
1418
1419 e1000_irq_enable(adapter);
1420
1421 netif_start_queue(netdev);
1422
1423 /* fire a link status change interrupt to start the watchdog */
1424 ew32(ICS, E1000_ICS_LSC);
1425
1426 return E1000_SUCCESS;
1427
1428err_req_irq:
1429 e1000_power_down_phy(adapter);
1430 e1000_free_all_rx_resources(adapter);
1431err_setup_rx:
1432 e1000_free_all_tx_resources(adapter);
1433err_setup_tx:
1434 e1000_reset(adapter);
1435
1436 return err;
1437}
1438
1439/**
1440 * e1000_close - Disables a network interface
1441 * @netdev: network interface device structure
1442 *
1443 * Returns 0, this is not allowed to fail
1444 *
1445 * The close entry point is called when an interface is de-activated
1446 * by the OS. The hardware is still under the drivers control, but
1447 * needs to be disabled. A global MAC reset is issued to stop the
1448 * hardware, and all transmit and receive resources are freed.
1449 **/
1450
1451static int e1000_close(struct net_device *netdev)
1452{
1453 struct e1000_adapter *adapter = netdev_priv(netdev);
1454 struct e1000_hw *hw = &adapter->hw;
1455
1456 WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags));
1457 e1000_down(adapter);
1458 e1000_power_down_phy(adapter);
1459 e1000_free_irq(adapter);
1460
1461 e1000_free_all_tx_resources(adapter);
1462 e1000_free_all_rx_resources(adapter);
1463
1464 /* kill manageability vlan ID if supported, but not if a vlan with
1465 * the same ID is registered on the host OS (let 8021q kill it) */
1466 if ((hw->mng_cookie.status &
1467 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
1468 !test_bit(adapter->mng_vlan_id, adapter->active_vlans)) {
1469 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1470 }
1471
1472 return 0;
1473}
1474
1475/**
1476 * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary
1477 * @adapter: address of board private structure
1478 * @start: address of beginning of memory
1479 * @len: length of memory
1480 **/
1481static bool e1000_check_64k_bound(struct e1000_adapter *adapter, void *start,
1482 unsigned long len)
1483{
1484 struct e1000_hw *hw = &adapter->hw;
1485 unsigned long begin = (unsigned long)start;
1486 unsigned long end = begin + len;
1487
1488 /* First rev 82545 and 82546 need to not allow any memory
1489 * write location to cross 64k boundary due to errata 23 */
1490 if (hw->mac_type == e1000_82545 ||
1491 hw->mac_type == e1000_ce4100 ||
1492 hw->mac_type == e1000_82546) {
1493 return ((begin ^ (end - 1)) >> 16) != 0 ? false : true;
1494 }
1495
1496 return true;
1497}
1498
1499/**
1500 * e1000_setup_tx_resources - allocate Tx resources (Descriptors)
1501 * @adapter: board private structure
1502 * @txdr: tx descriptor ring (for a specific queue) to setup
1503 *
1504 * Return 0 on success, negative on failure
1505 **/
1506
1507static int e1000_setup_tx_resources(struct e1000_adapter *adapter,
1508 struct e1000_tx_ring *txdr)
1509{
1510 struct pci_dev *pdev = adapter->pdev;
1511 int size;
1512
1513 size = sizeof(struct e1000_buffer) * txdr->count;
1514 txdr->buffer_info = vzalloc(size);
1515 if (!txdr->buffer_info) {
1516 e_err(probe, "Unable to allocate memory for the Tx descriptor "
1517 "ring\n");
1518 return -ENOMEM;
1519 }
1520
1521 /* round up to nearest 4K */
1522
1523 txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
1524 txdr->size = ALIGN(txdr->size, 4096);
1525
1526 txdr->desc = dma_alloc_coherent(&pdev->dev, txdr->size, &txdr->dma,
1527 GFP_KERNEL);
1528 if (!txdr->desc) {
1529setup_tx_desc_die:
1530 vfree(txdr->buffer_info);
1531 e_err(probe, "Unable to allocate memory for the Tx descriptor "
1532 "ring\n");
1533 return -ENOMEM;
1534 }
1535
1536 /* Fix for errata 23, can't cross 64kB boundary */
1537 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1538 void *olddesc = txdr->desc;
1539 dma_addr_t olddma = txdr->dma;
1540 e_err(tx_err, "txdr align check failed: %u bytes at %p\n",
1541 txdr->size, txdr->desc);
1542 /* Try again, without freeing the previous */
1543 txdr->desc = dma_alloc_coherent(&pdev->dev, txdr->size,
1544 &txdr->dma, GFP_KERNEL);
1545 /* Failed allocation, critical failure */
1546 if (!txdr->desc) {
1547 dma_free_coherent(&pdev->dev, txdr->size, olddesc,
1548 olddma);
1549 goto setup_tx_desc_die;
1550 }
1551
1552 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1553 /* give up */
1554 dma_free_coherent(&pdev->dev, txdr->size, txdr->desc,
1555 txdr->dma);
1556 dma_free_coherent(&pdev->dev, txdr->size, olddesc,
1557 olddma);
1558 e_err(probe, "Unable to allocate aligned memory "
1559 "for the transmit descriptor ring\n");
1560 vfree(txdr->buffer_info);
1561 return -ENOMEM;
1562 } else {
1563 /* Free old allocation, new allocation was successful */
1564 dma_free_coherent(&pdev->dev, txdr->size, olddesc,
1565 olddma);
1566 }
1567 }
1568 memset(txdr->desc, 0, txdr->size);
1569
1570 txdr->next_to_use = 0;
1571 txdr->next_to_clean = 0;
1572
1573 return 0;
1574}
1575
1576/**
1577 * e1000_setup_all_tx_resources - wrapper to allocate Tx resources
1578 * (Descriptors) for all queues
1579 * @adapter: board private structure
1580 *
1581 * Return 0 on success, negative on failure
1582 **/
1583
1584int e1000_setup_all_tx_resources(struct e1000_adapter *adapter)
1585{
1586 int i, err = 0;
1587
1588 for (i = 0; i < adapter->num_tx_queues; i++) {
1589 err = e1000_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1590 if (err) {
1591 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
1592 for (i-- ; i >= 0; i--)
1593 e1000_free_tx_resources(adapter,
1594 &adapter->tx_ring[i]);
1595 break;
1596 }
1597 }
1598
1599 return err;
1600}
1601
1602/**
1603 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
1604 * @adapter: board private structure
1605 *
1606 * Configure the Tx unit of the MAC after a reset.
1607 **/
1608
1609static void e1000_configure_tx(struct e1000_adapter *adapter)
1610{
1611 u64 tdba;
1612 struct e1000_hw *hw = &adapter->hw;
1613 u32 tdlen, tctl, tipg;
1614 u32 ipgr1, ipgr2;
1615
1616 /* Setup the HW Tx Head and Tail descriptor pointers */
1617
1618 switch (adapter->num_tx_queues) {
1619 case 1:
1620 default:
1621 tdba = adapter->tx_ring[0].dma;
1622 tdlen = adapter->tx_ring[0].count *
1623 sizeof(struct e1000_tx_desc);
1624 ew32(TDLEN, tdlen);
1625 ew32(TDBAH, (tdba >> 32));
1626 ew32(TDBAL, (tdba & 0x00000000ffffffffULL));
1627 ew32(TDT, 0);
1628 ew32(TDH, 0);
1629 adapter->tx_ring[0].tdh = ((hw->mac_type >= e1000_82543) ? E1000_TDH : E1000_82542_TDH);
1630 adapter->tx_ring[0].tdt = ((hw->mac_type >= e1000_82543) ? E1000_TDT : E1000_82542_TDT);
1631 break;
1632 }
1633
1634 /* Set the default values for the Tx Inter Packet Gap timer */
1635 if ((hw->media_type == e1000_media_type_fiber ||
1636 hw->media_type == e1000_media_type_internal_serdes))
1637 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
1638 else
1639 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
1640
1641 switch (hw->mac_type) {
1642 case e1000_82542_rev2_0:
1643 case e1000_82542_rev2_1:
1644 tipg = DEFAULT_82542_TIPG_IPGT;
1645 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
1646 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
1647 break;
1648 default:
1649 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
1650 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
1651 break;
1652 }
1653 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
1654 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
1655 ew32(TIPG, tipg);
1656
1657 /* Set the Tx Interrupt Delay register */
1658
1659 ew32(TIDV, adapter->tx_int_delay);
1660 if (hw->mac_type >= e1000_82540)
1661 ew32(TADV, adapter->tx_abs_int_delay);
1662
1663 /* Program the Transmit Control Register */
1664
1665 tctl = er32(TCTL);
1666 tctl &= ~E1000_TCTL_CT;
1667 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1668 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1669
1670 e1000_config_collision_dist(hw);
1671
1672 /* Setup Transmit Descriptor Settings for eop descriptor */
1673 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
1674
1675 /* only set IDE if we are delaying interrupts using the timers */
1676 if (adapter->tx_int_delay)
1677 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
1678
1679 if (hw->mac_type < e1000_82543)
1680 adapter->txd_cmd |= E1000_TXD_CMD_RPS;
1681 else
1682 adapter->txd_cmd |= E1000_TXD_CMD_RS;
1683
1684 /* Cache if we're 82544 running in PCI-X because we'll
1685 * need this to apply a workaround later in the send path. */
1686 if (hw->mac_type == e1000_82544 &&
1687 hw->bus_type == e1000_bus_type_pcix)
1688 adapter->pcix_82544 = 1;
1689
1690 ew32(TCTL, tctl);
1691
1692}
1693
1694/**
1695 * e1000_setup_rx_resources - allocate Rx resources (Descriptors)
1696 * @adapter: board private structure
1697 * @rxdr: rx descriptor ring (for a specific queue) to setup
1698 *
1699 * Returns 0 on success, negative on failure
1700 **/
1701
1702static int e1000_setup_rx_resources(struct e1000_adapter *adapter,
1703 struct e1000_rx_ring *rxdr)
1704{
1705 struct pci_dev *pdev = adapter->pdev;
1706 int size, desc_len;
1707
1708 size = sizeof(struct e1000_buffer) * rxdr->count;
1709 rxdr->buffer_info = vzalloc(size);
1710 if (!rxdr->buffer_info) {
1711 e_err(probe, "Unable to allocate memory for the Rx descriptor "
1712 "ring\n");
1713 return -ENOMEM;
1714 }
1715
1716 desc_len = sizeof(struct e1000_rx_desc);
1717
1718 /* Round up to nearest 4K */
1719
1720 rxdr->size = rxdr->count * desc_len;
1721 rxdr->size = ALIGN(rxdr->size, 4096);
1722
1723 rxdr->desc = dma_alloc_coherent(&pdev->dev, rxdr->size, &rxdr->dma,
1724 GFP_KERNEL);
1725
1726 if (!rxdr->desc) {
1727 e_err(probe, "Unable to allocate memory for the Rx descriptor "
1728 "ring\n");
1729setup_rx_desc_die:
1730 vfree(rxdr->buffer_info);
1731 return -ENOMEM;
1732 }
1733
1734 /* Fix for errata 23, can't cross 64kB boundary */
1735 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1736 void *olddesc = rxdr->desc;
1737 dma_addr_t olddma = rxdr->dma;
1738 e_err(rx_err, "rxdr align check failed: %u bytes at %p\n",
1739 rxdr->size, rxdr->desc);
1740 /* Try again, without freeing the previous */
1741 rxdr->desc = dma_alloc_coherent(&pdev->dev, rxdr->size,
1742 &rxdr->dma, GFP_KERNEL);
1743 /* Failed allocation, critical failure */
1744 if (!rxdr->desc) {
1745 dma_free_coherent(&pdev->dev, rxdr->size, olddesc,
1746 olddma);
1747 e_err(probe, "Unable to allocate memory for the Rx "
1748 "descriptor ring\n");
1749 goto setup_rx_desc_die;
1750 }
1751
1752 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1753 /* give up */
1754 dma_free_coherent(&pdev->dev, rxdr->size, rxdr->desc,
1755 rxdr->dma);
1756 dma_free_coherent(&pdev->dev, rxdr->size, olddesc,
1757 olddma);
1758 e_err(probe, "Unable to allocate aligned memory for "
1759 "the Rx descriptor ring\n");
1760 goto setup_rx_desc_die;
1761 } else {
1762 /* Free old allocation, new allocation was successful */
1763 dma_free_coherent(&pdev->dev, rxdr->size, olddesc,
1764 olddma);
1765 }
1766 }
1767 memset(rxdr->desc, 0, rxdr->size);
1768
1769 rxdr->next_to_clean = 0;
1770 rxdr->next_to_use = 0;
1771 rxdr->rx_skb_top = NULL;
1772
1773 return 0;
1774}
1775
1776/**
1777 * e1000_setup_all_rx_resources - wrapper to allocate Rx resources
1778 * (Descriptors) for all queues
1779 * @adapter: board private structure
1780 *
1781 * Return 0 on success, negative on failure
1782 **/
1783
1784int e1000_setup_all_rx_resources(struct e1000_adapter *adapter)
1785{
1786 int i, err = 0;
1787
1788 for (i = 0; i < adapter->num_rx_queues; i++) {
1789 err = e1000_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1790 if (err) {
1791 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
1792 for (i-- ; i >= 0; i--)
1793 e1000_free_rx_resources(adapter,
1794 &adapter->rx_ring[i]);
1795 break;
1796 }
1797 }
1798
1799 return err;
1800}
1801
1802/**
1803 * e1000_setup_rctl - configure the receive control registers
1804 * @adapter: Board private structure
1805 **/
1806static void e1000_setup_rctl(struct e1000_adapter *adapter)
1807{
1808 struct e1000_hw *hw = &adapter->hw;
1809 u32 rctl;
1810
1811 rctl = er32(RCTL);
1812
1813 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1814
1815 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1816 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1817 (hw->mc_filter_type << E1000_RCTL_MO_SHIFT);
1818
1819 if (hw->tbi_compatibility_on == 1)
1820 rctl |= E1000_RCTL_SBP;
1821 else
1822 rctl &= ~E1000_RCTL_SBP;
1823
1824 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1825 rctl &= ~E1000_RCTL_LPE;
1826 else
1827 rctl |= E1000_RCTL_LPE;
1828
1829 /* Setup buffer sizes */
1830 rctl &= ~E1000_RCTL_SZ_4096;
1831 rctl |= E1000_RCTL_BSEX;
1832 switch (adapter->rx_buffer_len) {
1833 case E1000_RXBUFFER_2048:
1834 default:
1835 rctl |= E1000_RCTL_SZ_2048;
1836 rctl &= ~E1000_RCTL_BSEX;
1837 break;
1838 case E1000_RXBUFFER_4096:
1839 rctl |= E1000_RCTL_SZ_4096;
1840 break;
1841 case E1000_RXBUFFER_8192:
1842 rctl |= E1000_RCTL_SZ_8192;
1843 break;
1844 case E1000_RXBUFFER_16384:
1845 rctl |= E1000_RCTL_SZ_16384;
1846 break;
1847 }
1848
1849 ew32(RCTL, rctl);
1850}
1851
1852/**
1853 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
1854 * @adapter: board private structure
1855 *
1856 * Configure the Rx unit of the MAC after a reset.
1857 **/
1858
1859static void e1000_configure_rx(struct e1000_adapter *adapter)
1860{
1861 u64 rdba;
1862 struct e1000_hw *hw = &adapter->hw;
1863 u32 rdlen, rctl, rxcsum;
1864
1865 if (adapter->netdev->mtu > ETH_DATA_LEN) {
1866 rdlen = adapter->rx_ring[0].count *
1867 sizeof(struct e1000_rx_desc);
1868 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
1869 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
1870 } else {
1871 rdlen = adapter->rx_ring[0].count *
1872 sizeof(struct e1000_rx_desc);
1873 adapter->clean_rx = e1000_clean_rx_irq;
1874 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
1875 }
1876
1877 /* disable receives while setting up the descriptors */
1878 rctl = er32(RCTL);
1879 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1880
1881 /* set the Receive Delay Timer Register */
1882 ew32(RDTR, adapter->rx_int_delay);
1883
1884 if (hw->mac_type >= e1000_82540) {
1885 ew32(RADV, adapter->rx_abs_int_delay);
1886 if (adapter->itr_setting != 0)
1887 ew32(ITR, 1000000000 / (adapter->itr * 256));
1888 }
1889
1890 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1891 * the Base and Length of the Rx Descriptor Ring */
1892 switch (adapter->num_rx_queues) {
1893 case 1:
1894 default:
1895 rdba = adapter->rx_ring[0].dma;
1896 ew32(RDLEN, rdlen);
1897 ew32(RDBAH, (rdba >> 32));
1898 ew32(RDBAL, (rdba & 0x00000000ffffffffULL));
1899 ew32(RDT, 0);
1900 ew32(RDH, 0);
1901 adapter->rx_ring[0].rdh = ((hw->mac_type >= e1000_82543) ? E1000_RDH : E1000_82542_RDH);
1902 adapter->rx_ring[0].rdt = ((hw->mac_type >= e1000_82543) ? E1000_RDT : E1000_82542_RDT);
1903 break;
1904 }
1905
1906 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
1907 if (hw->mac_type >= e1000_82543) {
1908 rxcsum = er32(RXCSUM);
1909 if (adapter->rx_csum)
1910 rxcsum |= E1000_RXCSUM_TUOFL;
1911 else
1912 /* don't need to clear IPPCSE as it defaults to 0 */
1913 rxcsum &= ~E1000_RXCSUM_TUOFL;
1914 ew32(RXCSUM, rxcsum);
1915 }
1916
1917 /* Enable Receives */
1918 ew32(RCTL, rctl);
1919}
1920
1921/**
1922 * e1000_free_tx_resources - Free Tx Resources per Queue
1923 * @adapter: board private structure
1924 * @tx_ring: Tx descriptor ring for a specific queue
1925 *
1926 * Free all transmit software resources
1927 **/
1928
1929static void e1000_free_tx_resources(struct e1000_adapter *adapter,
1930 struct e1000_tx_ring *tx_ring)
1931{
1932 struct pci_dev *pdev = adapter->pdev;
1933
1934 e1000_clean_tx_ring(adapter, tx_ring);
1935
1936 vfree(tx_ring->buffer_info);
1937 tx_ring->buffer_info = NULL;
1938
1939 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
1940 tx_ring->dma);
1941
1942 tx_ring->desc = NULL;
1943}
1944
1945/**
1946 * e1000_free_all_tx_resources - Free Tx Resources for All Queues
1947 * @adapter: board private structure
1948 *
1949 * Free all transmit software resources
1950 **/
1951
1952void e1000_free_all_tx_resources(struct e1000_adapter *adapter)
1953{
1954 int i;
1955
1956 for (i = 0; i < adapter->num_tx_queues; i++)
1957 e1000_free_tx_resources(adapter, &adapter->tx_ring[i]);
1958}
1959
1960static void e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter,
1961 struct e1000_buffer *buffer_info)
1962{
1963 if (buffer_info->dma) {
1964 if (buffer_info->mapped_as_page)
1965 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1966 buffer_info->length, DMA_TO_DEVICE);
1967 else
1968 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1969 buffer_info->length,
1970 DMA_TO_DEVICE);
1971 buffer_info->dma = 0;
1972 }
1973 if (buffer_info->skb) {
1974 dev_kfree_skb_any(buffer_info->skb);
1975 buffer_info->skb = NULL;
1976 }
1977 buffer_info->time_stamp = 0;
1978 /* buffer_info must be completely set up in the transmit path */
1979}
1980
1981/**
1982 * e1000_clean_tx_ring - Free Tx Buffers
1983 * @adapter: board private structure
1984 * @tx_ring: ring to be cleaned
1985 **/
1986
1987static void e1000_clean_tx_ring(struct e1000_adapter *adapter,
1988 struct e1000_tx_ring *tx_ring)
1989{
1990 struct e1000_hw *hw = &adapter->hw;
1991 struct e1000_buffer *buffer_info;
1992 unsigned long size;
1993 unsigned int i;
1994
1995 /* Free all the Tx ring sk_buffs */
1996
1997 for (i = 0; i < tx_ring->count; i++) {
1998 buffer_info = &tx_ring->buffer_info[i];
1999 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
2000 }
2001
2002 size = sizeof(struct e1000_buffer) * tx_ring->count;
2003 memset(tx_ring->buffer_info, 0, size);
2004
2005 /* Zero out the descriptor ring */
2006
2007 memset(tx_ring->desc, 0, tx_ring->size);
2008
2009 tx_ring->next_to_use = 0;
2010 tx_ring->next_to_clean = 0;
2011 tx_ring->last_tx_tso = 0;
2012
2013 writel(0, hw->hw_addr + tx_ring->tdh);
2014 writel(0, hw->hw_addr + tx_ring->tdt);
2015}
2016
2017/**
2018 * e1000_clean_all_tx_rings - Free Tx Buffers for all queues
2019 * @adapter: board private structure
2020 **/
2021
2022static void e1000_clean_all_tx_rings(struct e1000_adapter *adapter)
2023{
2024 int i;
2025
2026 for (i = 0; i < adapter->num_tx_queues; i++)
2027 e1000_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2028}
2029
2030/**
2031 * e1000_free_rx_resources - Free Rx Resources
2032 * @adapter: board private structure
2033 * @rx_ring: ring to clean the resources from
2034 *
2035 * Free all receive software resources
2036 **/
2037
2038static void e1000_free_rx_resources(struct e1000_adapter *adapter,
2039 struct e1000_rx_ring *rx_ring)
2040{
2041 struct pci_dev *pdev = adapter->pdev;
2042
2043 e1000_clean_rx_ring(adapter, rx_ring);
2044
2045 vfree(rx_ring->buffer_info);
2046 rx_ring->buffer_info = NULL;
2047
2048 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2049 rx_ring->dma);
2050
2051 rx_ring->desc = NULL;
2052}
2053
2054/**
2055 * e1000_free_all_rx_resources - Free Rx Resources for All Queues
2056 * @adapter: board private structure
2057 *
2058 * Free all receive software resources
2059 **/
2060
2061void e1000_free_all_rx_resources(struct e1000_adapter *adapter)
2062{
2063 int i;
2064
2065 for (i = 0; i < adapter->num_rx_queues; i++)
2066 e1000_free_rx_resources(adapter, &adapter->rx_ring[i]);
2067}
2068
2069/**
2070 * e1000_clean_rx_ring - Free Rx Buffers per Queue
2071 * @adapter: board private structure
2072 * @rx_ring: ring to free buffers from
2073 **/
2074
2075static void e1000_clean_rx_ring(struct e1000_adapter *adapter,
2076 struct e1000_rx_ring *rx_ring)
2077{
2078 struct e1000_hw *hw = &adapter->hw;
2079 struct e1000_buffer *buffer_info;
2080 struct pci_dev *pdev = adapter->pdev;
2081 unsigned long size;
2082 unsigned int i;
2083
2084 /* Free all the Rx ring sk_buffs */
2085 for (i = 0; i < rx_ring->count; i++) {
2086 buffer_info = &rx_ring->buffer_info[i];
2087 if (buffer_info->dma &&
2088 adapter->clean_rx == e1000_clean_rx_irq) {
2089 dma_unmap_single(&pdev->dev, buffer_info->dma,
2090 buffer_info->length,
2091 DMA_FROM_DEVICE);
2092 } else if (buffer_info->dma &&
2093 adapter->clean_rx == e1000_clean_jumbo_rx_irq) {
2094 dma_unmap_page(&pdev->dev, buffer_info->dma,
2095 buffer_info->length,
2096 DMA_FROM_DEVICE);
2097 }
2098
2099 buffer_info->dma = 0;
2100 if (buffer_info->page) {
2101 put_page(buffer_info->page);
2102 buffer_info->page = NULL;
2103 }
2104 if (buffer_info->skb) {
2105 dev_kfree_skb(buffer_info->skb);
2106 buffer_info->skb = NULL;
2107 }
2108 }
2109
2110 /* there also may be some cached data from a chained receive */
2111 if (rx_ring->rx_skb_top) {
2112 dev_kfree_skb(rx_ring->rx_skb_top);
2113 rx_ring->rx_skb_top = NULL;
2114 }
2115
2116 size = sizeof(struct e1000_buffer) * rx_ring->count;
2117 memset(rx_ring->buffer_info, 0, size);
2118
2119 /* Zero out the descriptor ring */
2120 memset(rx_ring->desc, 0, rx_ring->size);
2121
2122 rx_ring->next_to_clean = 0;
2123 rx_ring->next_to_use = 0;
2124
2125 writel(0, hw->hw_addr + rx_ring->rdh);
2126 writel(0, hw->hw_addr + rx_ring->rdt);
2127}
2128
2129/**
2130 * e1000_clean_all_rx_rings - Free Rx Buffers for all queues
2131 * @adapter: board private structure
2132 **/
2133
2134static void e1000_clean_all_rx_rings(struct e1000_adapter *adapter)
2135{
2136 int i;
2137
2138 for (i = 0; i < adapter->num_rx_queues; i++)
2139 e1000_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2140}
2141
2142/* The 82542 2.0 (revision 2) needs to have the receive unit in reset
2143 * and memory write and invalidate disabled for certain operations
2144 */
2145static void e1000_enter_82542_rst(struct e1000_adapter *adapter)
2146{
2147 struct e1000_hw *hw = &adapter->hw;
2148 struct net_device *netdev = adapter->netdev;
2149 u32 rctl;
2150
2151 e1000_pci_clear_mwi(hw);
2152
2153 rctl = er32(RCTL);
2154 rctl |= E1000_RCTL_RST;
2155 ew32(RCTL, rctl);
2156 E1000_WRITE_FLUSH();
2157 mdelay(5);
2158
2159 if (netif_running(netdev))
2160 e1000_clean_all_rx_rings(adapter);
2161}
2162
2163static void e1000_leave_82542_rst(struct e1000_adapter *adapter)
2164{
2165 struct e1000_hw *hw = &adapter->hw;
2166 struct net_device *netdev = adapter->netdev;
2167 u32 rctl;
2168
2169 rctl = er32(RCTL);
2170 rctl &= ~E1000_RCTL_RST;
2171 ew32(RCTL, rctl);
2172 E1000_WRITE_FLUSH();
2173 mdelay(5);
2174
2175 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
2176 e1000_pci_set_mwi(hw);
2177
2178 if (netif_running(netdev)) {
2179 /* No need to loop, because 82542 supports only 1 queue */
2180 struct e1000_rx_ring *ring = &adapter->rx_ring[0];
2181 e1000_configure_rx(adapter);
2182 adapter->alloc_rx_buf(adapter, ring, E1000_DESC_UNUSED(ring));
2183 }
2184}
2185
2186/**
2187 * e1000_set_mac - Change the Ethernet Address of the NIC
2188 * @netdev: network interface device structure
2189 * @p: pointer to an address structure
2190 *
2191 * Returns 0 on success, negative on failure
2192 **/
2193
2194static int e1000_set_mac(struct net_device *netdev, void *p)
2195{
2196 struct e1000_adapter *adapter = netdev_priv(netdev);
2197 struct e1000_hw *hw = &adapter->hw;
2198 struct sockaddr *addr = p;
2199
2200 if (!is_valid_ether_addr(addr->sa_data))
2201 return -EADDRNOTAVAIL;
2202
2203 /* 82542 2.0 needs to be in reset to write receive address registers */
2204
2205 if (hw->mac_type == e1000_82542_rev2_0)
2206 e1000_enter_82542_rst(adapter);
2207
2208 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2209 memcpy(hw->mac_addr, addr->sa_data, netdev->addr_len);
2210
2211 e1000_rar_set(hw, hw->mac_addr, 0);
2212
2213 if (hw->mac_type == e1000_82542_rev2_0)
2214 e1000_leave_82542_rst(adapter);
2215
2216 return 0;
2217}
2218
2219/**
2220 * e1000_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
2221 * @netdev: network interface device structure
2222 *
2223 * The set_rx_mode entry point is called whenever the unicast or multicast
2224 * address lists or the network interface flags are updated. This routine is
2225 * responsible for configuring the hardware for proper unicast, multicast,
2226 * promiscuous mode, and all-multi behavior.
2227 **/
2228
2229static void e1000_set_rx_mode(struct net_device *netdev)
2230{
2231 struct e1000_adapter *adapter = netdev_priv(netdev);
2232 struct e1000_hw *hw = &adapter->hw;
2233 struct netdev_hw_addr *ha;
2234 bool use_uc = false;
2235 u32 rctl;
2236 u32 hash_value;
2237 int i, rar_entries = E1000_RAR_ENTRIES;
2238 int mta_reg_count = E1000_NUM_MTA_REGISTERS;
2239 u32 *mcarray = kcalloc(mta_reg_count, sizeof(u32), GFP_ATOMIC);
2240
2241 if (!mcarray) {
2242 e_err(probe, "memory allocation failed\n");
2243 return;
2244 }
2245
2246 /* Check for Promiscuous and All Multicast modes */
2247
2248 rctl = er32(RCTL);
2249
2250 if (netdev->flags & IFF_PROMISC) {
2251 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2252 rctl &= ~E1000_RCTL_VFE;
2253 } else {
2254 if (netdev->flags & IFF_ALLMULTI)
2255 rctl |= E1000_RCTL_MPE;
2256 else
2257 rctl &= ~E1000_RCTL_MPE;
2258 /* Enable VLAN filter if there is a VLAN */
2259 if (e1000_vlan_used(adapter))
2260 rctl |= E1000_RCTL_VFE;
2261 }
2262
2263 if (netdev_uc_count(netdev) > rar_entries - 1) {
2264 rctl |= E1000_RCTL_UPE;
2265 } else if (!(netdev->flags & IFF_PROMISC)) {
2266 rctl &= ~E1000_RCTL_UPE;
2267 use_uc = true;
2268 }
2269
2270 ew32(RCTL, rctl);
2271
2272 /* 82542 2.0 needs to be in reset to write receive address registers */
2273
2274 if (hw->mac_type == e1000_82542_rev2_0)
2275 e1000_enter_82542_rst(adapter);
2276
2277 /* load the first 14 addresses into the exact filters 1-14. Unicast
2278 * addresses take precedence to avoid disabling unicast filtering
2279 * when possible.
2280 *
2281 * RAR 0 is used for the station MAC address
2282 * if there are not 14 addresses, go ahead and clear the filters
2283 */
2284 i = 1;
2285 if (use_uc)
2286 netdev_for_each_uc_addr(ha, netdev) {
2287 if (i == rar_entries)
2288 break;
2289 e1000_rar_set(hw, ha->addr, i++);
2290 }
2291
2292 netdev_for_each_mc_addr(ha, netdev) {
2293 if (i == rar_entries) {
2294 /* load any remaining addresses into the hash table */
2295 u32 hash_reg, hash_bit, mta;
2296 hash_value = e1000_hash_mc_addr(hw, ha->addr);
2297 hash_reg = (hash_value >> 5) & 0x7F;
2298 hash_bit = hash_value & 0x1F;
2299 mta = (1 << hash_bit);
2300 mcarray[hash_reg] |= mta;
2301 } else {
2302 e1000_rar_set(hw, ha->addr, i++);
2303 }
2304 }
2305
2306 for (; i < rar_entries; i++) {
2307 E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0);
2308 E1000_WRITE_FLUSH();
2309 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0);
2310 E1000_WRITE_FLUSH();
2311 }
2312
2313 /* write the hash table completely, write from bottom to avoid
2314 * both stupid write combining chipsets, and flushing each write */
2315 for (i = mta_reg_count - 1; i >= 0 ; i--) {
2316 /*
2317 * If we are on an 82544 has an errata where writing odd
2318 * offsets overwrites the previous even offset, but writing
2319 * backwards over the range solves the issue by always
2320 * writing the odd offset first
2321 */
2322 E1000_WRITE_REG_ARRAY(hw, MTA, i, mcarray[i]);
2323 }
2324 E1000_WRITE_FLUSH();
2325
2326 if (hw->mac_type == e1000_82542_rev2_0)
2327 e1000_leave_82542_rst(adapter);
2328
2329 kfree(mcarray);
2330}
2331
2332/* Need to wait a few seconds after link up to get diagnostic information from
2333 * the phy */
2334
2335static void e1000_update_phy_info(unsigned long data)
2336{
2337 struct e1000_adapter *adapter = (struct e1000_adapter *)data;
2338 schedule_work(&adapter->phy_info_task);
2339}
2340
2341static void e1000_update_phy_info_task(struct work_struct *work)
2342{
2343 struct e1000_adapter *adapter = container_of(work,
2344 struct e1000_adapter,
2345 phy_info_task);
2346 struct e1000_hw *hw = &adapter->hw;
2347
2348 rtnl_lock();
2349 e1000_phy_get_info(hw, &adapter->phy_info);
2350 rtnl_unlock();
2351}
2352
2353/**
2354 * e1000_82547_tx_fifo_stall - Timer Call-back
2355 * @data: pointer to adapter cast into an unsigned long
2356 **/
2357static void e1000_82547_tx_fifo_stall(unsigned long data)
2358{
2359 struct e1000_adapter *adapter = (struct e1000_adapter *)data;
2360 schedule_work(&adapter->fifo_stall_task);
2361}
2362
2363/**
2364 * e1000_82547_tx_fifo_stall_task - task to complete work
2365 * @work: work struct contained inside adapter struct
2366 **/
2367static void e1000_82547_tx_fifo_stall_task(struct work_struct *work)
2368{
2369 struct e1000_adapter *adapter = container_of(work,
2370 struct e1000_adapter,
2371 fifo_stall_task);
2372 struct e1000_hw *hw = &adapter->hw;
2373 struct net_device *netdev = adapter->netdev;
2374 u32 tctl;
2375
2376 rtnl_lock();
2377 if (atomic_read(&adapter->tx_fifo_stall)) {
2378 if ((er32(TDT) == er32(TDH)) &&
2379 (er32(TDFT) == er32(TDFH)) &&
2380 (er32(TDFTS) == er32(TDFHS))) {
2381 tctl = er32(TCTL);
2382 ew32(TCTL, tctl & ~E1000_TCTL_EN);
2383 ew32(TDFT, adapter->tx_head_addr);
2384 ew32(TDFH, adapter->tx_head_addr);
2385 ew32(TDFTS, adapter->tx_head_addr);
2386 ew32(TDFHS, adapter->tx_head_addr);
2387 ew32(TCTL, tctl);
2388 E1000_WRITE_FLUSH();
2389
2390 adapter->tx_fifo_head = 0;
2391 atomic_set(&adapter->tx_fifo_stall, 0);
2392 netif_wake_queue(netdev);
2393 } else if (!test_bit(__E1000_DOWN, &adapter->flags)) {
2394 mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
2395 }
2396 }
2397 rtnl_unlock();
2398}
2399
2400bool e1000_has_link(struct e1000_adapter *adapter)
2401{
2402 struct e1000_hw *hw = &adapter->hw;
2403 bool link_active = false;
2404
2405 /* get_link_status is set on LSC (link status) interrupt or rx
2406 * sequence error interrupt (except on intel ce4100).
2407 * get_link_status will stay false until the
2408 * e1000_check_for_link establishes link for copper adapters
2409 * ONLY
2410 */
2411 switch (hw->media_type) {
2412 case e1000_media_type_copper:
2413 if (hw->mac_type == e1000_ce4100)
2414 hw->get_link_status = 1;
2415 if (hw->get_link_status) {
2416 e1000_check_for_link(hw);
2417 link_active = !hw->get_link_status;
2418 } else {
2419 link_active = true;
2420 }
2421 break;
2422 case e1000_media_type_fiber:
2423 e1000_check_for_link(hw);
2424 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
2425 break;
2426 case e1000_media_type_internal_serdes:
2427 e1000_check_for_link(hw);
2428 link_active = hw->serdes_has_link;
2429 break;
2430 default:
2431 break;
2432 }
2433
2434 return link_active;
2435}
2436
2437/**
2438 * e1000_watchdog - Timer Call-back
2439 * @data: pointer to adapter cast into an unsigned long
2440 **/
2441static void e1000_watchdog(unsigned long data)
2442{
2443 struct e1000_adapter *adapter = (struct e1000_adapter *)data;
2444 struct e1000_hw *hw = &adapter->hw;
2445 struct net_device *netdev = adapter->netdev;
2446 struct e1000_tx_ring *txdr = adapter->tx_ring;
2447 u32 link, tctl;
2448
2449 link = e1000_has_link(adapter);
2450 if ((netif_carrier_ok(netdev)) && link)
2451 goto link_up;
2452
2453 if (link) {
2454 if (!netif_carrier_ok(netdev)) {
2455 u32 ctrl;
2456 bool txb2b = true;
2457 /* update snapshot of PHY registers on LSC */
2458 e1000_get_speed_and_duplex(hw,
2459 &adapter->link_speed,
2460 &adapter->link_duplex);
2461
2462 ctrl = er32(CTRL);
2463 pr_info("%s NIC Link is Up %d Mbps %s, "
2464 "Flow Control: %s\n",
2465 netdev->name,
2466 adapter->link_speed,
2467 adapter->link_duplex == FULL_DUPLEX ?
2468 "Full Duplex" : "Half Duplex",
2469 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2470 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2471 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2472 E1000_CTRL_TFCE) ? "TX" : "None")));
2473
2474 /* adjust timeout factor according to speed/duplex */
2475 adapter->tx_timeout_factor = 1;
2476 switch (adapter->link_speed) {
2477 case SPEED_10:
2478 txb2b = false;
2479 adapter->tx_timeout_factor = 16;
2480 break;
2481 case SPEED_100:
2482 txb2b = false;
2483 /* maybe add some timeout factor ? */
2484 break;
2485 }
2486
2487 /* enable transmits in the hardware */
2488 tctl = er32(TCTL);
2489 tctl |= E1000_TCTL_EN;
2490 ew32(TCTL, tctl);
2491
2492 netif_carrier_on(netdev);
2493 if (!test_bit(__E1000_DOWN, &adapter->flags))
2494 mod_timer(&adapter->phy_info_timer,
2495 round_jiffies(jiffies + 2 * HZ));
2496 adapter->smartspeed = 0;
2497 }
2498 } else {
2499 if (netif_carrier_ok(netdev)) {
2500 adapter->link_speed = 0;
2501 adapter->link_duplex = 0;
2502 pr_info("%s NIC Link is Down\n",
2503 netdev->name);
2504 netif_carrier_off(netdev);
2505
2506 if (!test_bit(__E1000_DOWN, &adapter->flags))
2507 mod_timer(&adapter->phy_info_timer,
2508 round_jiffies(jiffies + 2 * HZ));
2509 }
2510
2511 e1000_smartspeed(adapter);
2512 }
2513
2514link_up:
2515 e1000_update_stats(adapter);
2516
2517 hw->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2518 adapter->tpt_old = adapter->stats.tpt;
2519 hw->collision_delta = adapter->stats.colc - adapter->colc_old;
2520 adapter->colc_old = adapter->stats.colc;
2521
2522 adapter->gorcl = adapter->stats.gorcl - adapter->gorcl_old;
2523 adapter->gorcl_old = adapter->stats.gorcl;
2524 adapter->gotcl = adapter->stats.gotcl - adapter->gotcl_old;
2525 adapter->gotcl_old = adapter->stats.gotcl;
2526
2527 e1000_update_adaptive(hw);
2528
2529 if (!netif_carrier_ok(netdev)) {
2530 if (E1000_DESC_UNUSED(txdr) + 1 < txdr->count) {
2531 /* We've lost link, so the controller stops DMA,
2532 * but we've got queued Tx work that's never going
2533 * to get done, so reset controller to flush Tx.
2534 * (Do the reset outside of interrupt context). */
2535 adapter->tx_timeout_count++;
2536 schedule_work(&adapter->reset_task);
2537 /* return immediately since reset is imminent */
2538 return;
2539 }
2540 }
2541
2542 /* Simple mode for Interrupt Throttle Rate (ITR) */
2543 if (hw->mac_type >= e1000_82540 && adapter->itr_setting == 4) {
2544 /*
2545 * Symmetric Tx/Rx gets a reduced ITR=2000;
2546 * Total asymmetrical Tx or Rx gets ITR=8000;
2547 * everyone else is between 2000-8000.
2548 */
2549 u32 goc = (adapter->gotcl + adapter->gorcl) / 10000;
2550 u32 dif = (adapter->gotcl > adapter->gorcl ?
2551 adapter->gotcl - adapter->gorcl :
2552 adapter->gorcl - adapter->gotcl) / 10000;
2553 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
2554
2555 ew32(ITR, 1000000000 / (itr * 256));
2556 }
2557
2558 /* Cause software interrupt to ensure rx ring is cleaned */
2559 ew32(ICS, E1000_ICS_RXDMT0);
2560
2561 /* Force detection of hung controller every watchdog period */
2562 adapter->detect_tx_hung = true;
2563
2564 /* Reset the timer */
2565 if (!test_bit(__E1000_DOWN, &adapter->flags))
2566 mod_timer(&adapter->watchdog_timer,
2567 round_jiffies(jiffies + 2 * HZ));
2568}
2569
2570enum latency_range {
2571 lowest_latency = 0,
2572 low_latency = 1,
2573 bulk_latency = 2,
2574 latency_invalid = 255
2575};
2576
2577/**
2578 * e1000_update_itr - update the dynamic ITR value based on statistics
2579 * @adapter: pointer to adapter
2580 * @itr_setting: current adapter->itr
2581 * @packets: the number of packets during this measurement interval
2582 * @bytes: the number of bytes during this measurement interval
2583 *
2584 * Stores a new ITR value based on packets and byte
2585 * counts during the last interrupt. The advantage of per interrupt
2586 * computation is faster updates and more accurate ITR for the current
2587 * traffic pattern. Constants in this function were computed
2588 * based on theoretical maximum wire speed and thresholds were set based
2589 * on testing data as well as attempting to minimize response time
2590 * while increasing bulk throughput.
2591 * this functionality is controlled by the InterruptThrottleRate module
2592 * parameter (see e1000_param.c)
2593 **/
2594static unsigned int e1000_update_itr(struct e1000_adapter *adapter,
2595 u16 itr_setting, int packets, int bytes)
2596{
2597 unsigned int retval = itr_setting;
2598 struct e1000_hw *hw = &adapter->hw;
2599
2600 if (unlikely(hw->mac_type < e1000_82540))
2601 goto update_itr_done;
2602
2603 if (packets == 0)
2604 goto update_itr_done;
2605
2606 switch (itr_setting) {
2607 case lowest_latency:
2608 /* jumbo frames get bulk treatment*/
2609 if (bytes/packets > 8000)
2610 retval = bulk_latency;
2611 else if ((packets < 5) && (bytes > 512))
2612 retval = low_latency;
2613 break;
2614 case low_latency: /* 50 usec aka 20000 ints/s */
2615 if (bytes > 10000) {
2616 /* jumbo frames need bulk latency setting */
2617 if (bytes/packets > 8000)
2618 retval = bulk_latency;
2619 else if ((packets < 10) || ((bytes/packets) > 1200))
2620 retval = bulk_latency;
2621 else if ((packets > 35))
2622 retval = lowest_latency;
2623 } else if (bytes/packets > 2000)
2624 retval = bulk_latency;
2625 else if (packets <= 2 && bytes < 512)
2626 retval = lowest_latency;
2627 break;
2628 case bulk_latency: /* 250 usec aka 4000 ints/s */
2629 if (bytes > 25000) {
2630 if (packets > 35)
2631 retval = low_latency;
2632 } else if (bytes < 6000) {
2633 retval = low_latency;
2634 }
2635 break;
2636 }
2637
2638update_itr_done:
2639 return retval;
2640}
2641
2642static void e1000_set_itr(struct e1000_adapter *adapter)
2643{
2644 struct e1000_hw *hw = &adapter->hw;
2645 u16 current_itr;
2646 u32 new_itr = adapter->itr;
2647
2648 if (unlikely(hw->mac_type < e1000_82540))
2649 return;
2650
2651 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2652 if (unlikely(adapter->link_speed != SPEED_1000)) {
2653 current_itr = 0;
2654 new_itr = 4000;
2655 goto set_itr_now;
2656 }
2657
2658 adapter->tx_itr = e1000_update_itr(adapter,
2659 adapter->tx_itr,
2660 adapter->total_tx_packets,
2661 adapter->total_tx_bytes);
2662 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2663 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2664 adapter->tx_itr = low_latency;
2665
2666 adapter->rx_itr = e1000_update_itr(adapter,
2667 adapter->rx_itr,
2668 adapter->total_rx_packets,
2669 adapter->total_rx_bytes);
2670 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2671 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2672 adapter->rx_itr = low_latency;
2673
2674 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2675
2676 switch (current_itr) {
2677 /* counts and packets in update_itr are dependent on these numbers */
2678 case lowest_latency:
2679 new_itr = 70000;
2680 break;
2681 case low_latency:
2682 new_itr = 20000; /* aka hwitr = ~200 */
2683 break;
2684 case bulk_latency:
2685 new_itr = 4000;
2686 break;
2687 default:
2688 break;
2689 }
2690
2691set_itr_now:
2692 if (new_itr != adapter->itr) {
2693 /* this attempts to bias the interrupt rate towards Bulk
2694 * by adding intermediate steps when interrupt rate is
2695 * increasing */
2696 new_itr = new_itr > adapter->itr ?
2697 min(adapter->itr + (new_itr >> 2), new_itr) :
2698 new_itr;
2699 adapter->itr = new_itr;
2700 ew32(ITR, 1000000000 / (new_itr * 256));
2701 }
2702}
2703
2704#define E1000_TX_FLAGS_CSUM 0x00000001
2705#define E1000_TX_FLAGS_VLAN 0x00000002
2706#define E1000_TX_FLAGS_TSO 0x00000004
2707#define E1000_TX_FLAGS_IPV4 0x00000008
2708#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
2709#define E1000_TX_FLAGS_VLAN_SHIFT 16
2710
2711static int e1000_tso(struct e1000_adapter *adapter,
2712 struct e1000_tx_ring *tx_ring, struct sk_buff *skb)
2713{
2714 struct e1000_context_desc *context_desc;
2715 struct e1000_buffer *buffer_info;
2716 unsigned int i;
2717 u32 cmd_length = 0;
2718 u16 ipcse = 0, tucse, mss;
2719 u8 ipcss, ipcso, tucss, tucso, hdr_len;
2720 int err;
2721
2722 if (skb_is_gso(skb)) {
2723 if (skb_header_cloned(skb)) {
2724 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2725 if (err)
2726 return err;
2727 }
2728
2729 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2730 mss = skb_shinfo(skb)->gso_size;
2731 if (skb->protocol == htons(ETH_P_IP)) {
2732 struct iphdr *iph = ip_hdr(skb);
2733 iph->tot_len = 0;
2734 iph->check = 0;
2735 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2736 iph->daddr, 0,
2737 IPPROTO_TCP,
2738 0);
2739 cmd_length = E1000_TXD_CMD_IP;
2740 ipcse = skb_transport_offset(skb) - 1;
2741 } else if (skb->protocol == htons(ETH_P_IPV6)) {
2742 ipv6_hdr(skb)->payload_len = 0;
2743 tcp_hdr(skb)->check =
2744 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2745 &ipv6_hdr(skb)->daddr,
2746 0, IPPROTO_TCP, 0);
2747 ipcse = 0;
2748 }
2749 ipcss = skb_network_offset(skb);
2750 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
2751 tucss = skb_transport_offset(skb);
2752 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
2753 tucse = 0;
2754
2755 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
2756 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
2757
2758 i = tx_ring->next_to_use;
2759 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
2760 buffer_info = &tx_ring->buffer_info[i];
2761
2762 context_desc->lower_setup.ip_fields.ipcss = ipcss;
2763 context_desc->lower_setup.ip_fields.ipcso = ipcso;
2764 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
2765 context_desc->upper_setup.tcp_fields.tucss = tucss;
2766 context_desc->upper_setup.tcp_fields.tucso = tucso;
2767 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
2768 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
2769 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
2770 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
2771
2772 buffer_info->time_stamp = jiffies;
2773 buffer_info->next_to_watch = i;
2774
2775 if (++i == tx_ring->count) i = 0;
2776 tx_ring->next_to_use = i;
2777
2778 return true;
2779 }
2780 return false;
2781}
2782
2783static bool e1000_tx_csum(struct e1000_adapter *adapter,
2784 struct e1000_tx_ring *tx_ring, struct sk_buff *skb)
2785{
2786 struct e1000_context_desc *context_desc;
2787 struct e1000_buffer *buffer_info;
2788 unsigned int i;
2789 u8 css;
2790 u32 cmd_len = E1000_TXD_CMD_DEXT;
2791
2792 if (skb->ip_summed != CHECKSUM_PARTIAL)
2793 return false;
2794
2795 switch (skb->protocol) {
2796 case cpu_to_be16(ETH_P_IP):
2797 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2798 cmd_len |= E1000_TXD_CMD_TCP;
2799 break;
2800 case cpu_to_be16(ETH_P_IPV6):
2801 /* XXX not handling all IPV6 headers */
2802 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2803 cmd_len |= E1000_TXD_CMD_TCP;
2804 break;
2805 default:
2806 if (unlikely(net_ratelimit()))
2807 e_warn(drv, "checksum_partial proto=%x!\n",
2808 skb->protocol);
2809 break;
2810 }
2811
2812 css = skb_checksum_start_offset(skb);
2813
2814 i = tx_ring->next_to_use;
2815 buffer_info = &tx_ring->buffer_info[i];
2816 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
2817
2818 context_desc->lower_setup.ip_config = 0;
2819 context_desc->upper_setup.tcp_fields.tucss = css;
2820 context_desc->upper_setup.tcp_fields.tucso =
2821 css + skb->csum_offset;
2822 context_desc->upper_setup.tcp_fields.tucse = 0;
2823 context_desc->tcp_seg_setup.data = 0;
2824 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
2825
2826 buffer_info->time_stamp = jiffies;
2827 buffer_info->next_to_watch = i;
2828
2829 if (unlikely(++i == tx_ring->count)) i = 0;
2830 tx_ring->next_to_use = i;
2831
2832 return true;
2833}
2834
2835#define E1000_MAX_TXD_PWR 12
2836#define E1000_MAX_DATA_PER_TXD (1<<E1000_MAX_TXD_PWR)
2837
2838static int e1000_tx_map(struct e1000_adapter *adapter,
2839 struct e1000_tx_ring *tx_ring,
2840 struct sk_buff *skb, unsigned int first,
2841 unsigned int max_per_txd, unsigned int nr_frags,
2842 unsigned int mss)
2843{
2844 struct e1000_hw *hw = &adapter->hw;
2845 struct pci_dev *pdev = adapter->pdev;
2846 struct e1000_buffer *buffer_info;
2847 unsigned int len = skb_headlen(skb);
2848 unsigned int offset = 0, size, count = 0, i;
2849 unsigned int f;
2850
2851 i = tx_ring->next_to_use;
2852
2853 while (len) {
2854 buffer_info = &tx_ring->buffer_info[i];
2855 size = min(len, max_per_txd);
2856 /* Workaround for Controller erratum --
2857 * descriptor for non-tso packet in a linear SKB that follows a
2858 * tso gets written back prematurely before the data is fully
2859 * DMA'd to the controller */
2860 if (!skb->data_len && tx_ring->last_tx_tso &&
2861 !skb_is_gso(skb)) {
2862 tx_ring->last_tx_tso = 0;
2863 size -= 4;
2864 }
2865
2866 /* Workaround for premature desc write-backs
2867 * in TSO mode. Append 4-byte sentinel desc */
2868 if (unlikely(mss && !nr_frags && size == len && size > 8))
2869 size -= 4;
2870 /* work-around for errata 10 and it applies
2871 * to all controllers in PCI-X mode
2872 * The fix is to make sure that the first descriptor of a
2873 * packet is smaller than 2048 - 16 - 16 (or 2016) bytes
2874 */
2875 if (unlikely((hw->bus_type == e1000_bus_type_pcix) &&
2876 (size > 2015) && count == 0))
2877 size = 2015;
2878
2879 /* Workaround for potential 82544 hang in PCI-X. Avoid
2880 * terminating buffers within evenly-aligned dwords. */
2881 if (unlikely(adapter->pcix_82544 &&
2882 !((unsigned long)(skb->data + offset + size - 1) & 4) &&
2883 size > 4))
2884 size -= 4;
2885
2886 buffer_info->length = size;
2887 /* set time_stamp *before* dma to help avoid a possible race */
2888 buffer_info->time_stamp = jiffies;
2889 buffer_info->mapped_as_page = false;
2890 buffer_info->dma = dma_map_single(&pdev->dev,
2891 skb->data + offset,
2892 size, DMA_TO_DEVICE);
2893 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
2894 goto dma_error;
2895 buffer_info->next_to_watch = i;
2896
2897 len -= size;
2898 offset += size;
2899 count++;
2900 if (len) {
2901 i++;
2902 if (unlikely(i == tx_ring->count))
2903 i = 0;
2904 }
2905 }
2906
2907 for (f = 0; f < nr_frags; f++) {
2908 struct skb_frag_struct *frag;
2909
2910 frag = &skb_shinfo(skb)->frags[f];
2911 len = frag->size;
2912 offset = frag->page_offset;
2913
2914 while (len) {
2915 i++;
2916 if (unlikely(i == tx_ring->count))
2917 i = 0;
2918
2919 buffer_info = &tx_ring->buffer_info[i];
2920 size = min(len, max_per_txd);
2921 /* Workaround for premature desc write-backs
2922 * in TSO mode. Append 4-byte sentinel desc */
2923 if (unlikely(mss && f == (nr_frags-1) && size == len && size > 8))
2924 size -= 4;
2925 /* Workaround for potential 82544 hang in PCI-X.
2926 * Avoid terminating buffers within evenly-aligned
2927 * dwords. */
2928 if (unlikely(adapter->pcix_82544 &&
2929 !((unsigned long)(page_to_phys(frag->page) + offset
2930 + size - 1) & 4) &&
2931 size > 4))
2932 size -= 4;
2933
2934 buffer_info->length = size;
2935 buffer_info->time_stamp = jiffies;
2936 buffer_info->mapped_as_page = true;
2937 buffer_info->dma = dma_map_page(&pdev->dev, frag->page,
2938 offset, size,
2939 DMA_TO_DEVICE);
2940 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
2941 goto dma_error;
2942 buffer_info->next_to_watch = i;
2943
2944 len -= size;
2945 offset += size;
2946 count++;
2947 }
2948 }
2949
2950 tx_ring->buffer_info[i].skb = skb;
2951 tx_ring->buffer_info[first].next_to_watch = i;
2952
2953 return count;
2954
2955dma_error:
2956 dev_err(&pdev->dev, "TX DMA map failed\n");
2957 buffer_info->dma = 0;
2958 if (count)
2959 count--;
2960
2961 while (count--) {
2962 if (i==0)
2963 i += tx_ring->count;
2964 i--;
2965 buffer_info = &tx_ring->buffer_info[i];
2966 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
2967 }
2968
2969 return 0;
2970}
2971
2972static void e1000_tx_queue(struct e1000_adapter *adapter,
2973 struct e1000_tx_ring *tx_ring, int tx_flags,
2974 int count)
2975{
2976 struct e1000_hw *hw = &adapter->hw;
2977 struct e1000_tx_desc *tx_desc = NULL;
2978 struct e1000_buffer *buffer_info;
2979 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
2980 unsigned int i;
2981
2982 if (likely(tx_flags & E1000_TX_FLAGS_TSO)) {
2983 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
2984 E1000_TXD_CMD_TSE;
2985 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2986
2987 if (likely(tx_flags & E1000_TX_FLAGS_IPV4))
2988 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2989 }
2990
2991 if (likely(tx_flags & E1000_TX_FLAGS_CSUM)) {
2992 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
2993 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2994 }
2995
2996 if (unlikely(tx_flags & E1000_TX_FLAGS_VLAN)) {
2997 txd_lower |= E1000_TXD_CMD_VLE;
2998 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
2999 }
3000
3001 i = tx_ring->next_to_use;
3002
3003 while (count--) {
3004 buffer_info = &tx_ring->buffer_info[i];
3005 tx_desc = E1000_TX_DESC(*tx_ring, i);
3006 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
3007 tx_desc->lower.data =
3008 cpu_to_le32(txd_lower | buffer_info->length);
3009 tx_desc->upper.data = cpu_to_le32(txd_upper);
3010 if (unlikely(++i == tx_ring->count)) i = 0;
3011 }
3012
3013 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
3014
3015 /* Force memory writes to complete before letting h/w
3016 * know there are new descriptors to fetch. (Only
3017 * applicable for weak-ordered memory model archs,
3018 * such as IA-64). */
3019 wmb();
3020
3021 tx_ring->next_to_use = i;
3022 writel(i, hw->hw_addr + tx_ring->tdt);
3023 /* we need this if more than one processor can write to our tail
3024 * at a time, it syncronizes IO on IA64/Altix systems */
3025 mmiowb();
3026}
3027
3028/**
3029 * 82547 workaround to avoid controller hang in half-duplex environment.
3030 * The workaround is to avoid queuing a large packet that would span
3031 * the internal Tx FIFO ring boundary by notifying the stack to resend
3032 * the packet at a later time. This gives the Tx FIFO an opportunity to
3033 * flush all packets. When that occurs, we reset the Tx FIFO pointers
3034 * to the beginning of the Tx FIFO.
3035 **/
3036
3037#define E1000_FIFO_HDR 0x10
3038#define E1000_82547_PAD_LEN 0x3E0
3039
3040static int e1000_82547_fifo_workaround(struct e1000_adapter *adapter,
3041 struct sk_buff *skb)
3042{
3043 u32 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
3044 u32 skb_fifo_len = skb->len + E1000_FIFO_HDR;
3045
3046 skb_fifo_len = ALIGN(skb_fifo_len, E1000_FIFO_HDR);
3047
3048 if (adapter->link_duplex != HALF_DUPLEX)
3049 goto no_fifo_stall_required;
3050
3051 if (atomic_read(&adapter->tx_fifo_stall))
3052 return 1;
3053
3054 if (skb_fifo_len >= (E1000_82547_PAD_LEN + fifo_space)) {
3055 atomic_set(&adapter->tx_fifo_stall, 1);
3056 return 1;
3057 }
3058
3059no_fifo_stall_required:
3060 adapter->tx_fifo_head += skb_fifo_len;
3061 if (adapter->tx_fifo_head >= adapter->tx_fifo_size)
3062 adapter->tx_fifo_head -= adapter->tx_fifo_size;
3063 return 0;
3064}
3065
3066static int __e1000_maybe_stop_tx(struct net_device *netdev, int size)
3067{
3068 struct e1000_adapter *adapter = netdev_priv(netdev);
3069 struct e1000_tx_ring *tx_ring = adapter->tx_ring;
3070
3071 netif_stop_queue(netdev);
3072 /* Herbert's original patch had:
3073 * smp_mb__after_netif_stop_queue();
3074 * but since that doesn't exist yet, just open code it. */
3075 smp_mb();
3076
3077 /* We need to check again in a case another CPU has just
3078 * made room available. */
3079 if (likely(E1000_DESC_UNUSED(tx_ring) < size))
3080 return -EBUSY;
3081
3082 /* A reprieve! */
3083 netif_start_queue(netdev);
3084 ++adapter->restart_queue;
3085 return 0;
3086}
3087
3088static int e1000_maybe_stop_tx(struct net_device *netdev,
3089 struct e1000_tx_ring *tx_ring, int size)
3090{
3091 if (likely(E1000_DESC_UNUSED(tx_ring) >= size))
3092 return 0;
3093 return __e1000_maybe_stop_tx(netdev, size);
3094}
3095
3096#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
3097static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
3098 struct net_device *netdev)
3099{
3100 struct e1000_adapter *adapter = netdev_priv(netdev);
3101 struct e1000_hw *hw = &adapter->hw;
3102 struct e1000_tx_ring *tx_ring;
3103 unsigned int first, max_per_txd = E1000_MAX_DATA_PER_TXD;
3104 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
3105 unsigned int tx_flags = 0;
3106 unsigned int len = skb_headlen(skb);
3107 unsigned int nr_frags;
3108 unsigned int mss;
3109 int count = 0;
3110 int tso;
3111 unsigned int f;
3112
3113 /* This goes back to the question of how to logically map a tx queue
3114 * to a flow. Right now, performance is impacted slightly negatively
3115 * if using multiple tx queues. If the stack breaks away from a
3116 * single qdisc implementation, we can look at this again. */
3117 tx_ring = adapter->tx_ring;
3118
3119 if (unlikely(skb->len <= 0)) {
3120 dev_kfree_skb_any(skb);
3121 return NETDEV_TX_OK;
3122 }
3123
3124 mss = skb_shinfo(skb)->gso_size;
3125 /* The controller does a simple calculation to
3126 * make sure there is enough room in the FIFO before
3127 * initiating the DMA for each buffer. The calc is:
3128 * 4 = ceil(buffer len/mss). To make sure we don't
3129 * overrun the FIFO, adjust the max buffer len if mss
3130 * drops. */
3131 if (mss) {
3132 u8 hdr_len;
3133 max_per_txd = min(mss << 2, max_per_txd);
3134 max_txd_pwr = fls(max_per_txd) - 1;
3135
3136 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
3137 if (skb->data_len && hdr_len == len) {
3138 switch (hw->mac_type) {
3139 unsigned int pull_size;
3140 case e1000_82544:
3141 /* Make sure we have room to chop off 4 bytes,
3142 * and that the end alignment will work out to
3143 * this hardware's requirements
3144 * NOTE: this is a TSO only workaround
3145 * if end byte alignment not correct move us
3146 * into the next dword */
3147 if ((unsigned long)(skb_tail_pointer(skb) - 1) & 4)
3148 break;
3149 /* fall through */
3150 pull_size = min((unsigned int)4, skb->data_len);
3151 if (!__pskb_pull_tail(skb, pull_size)) {
3152 e_err(drv, "__pskb_pull_tail "
3153 "failed.\n");
3154 dev_kfree_skb_any(skb);
3155 return NETDEV_TX_OK;
3156 }
3157 len = skb_headlen(skb);
3158 break;
3159 default:
3160 /* do nothing */
3161 break;
3162 }
3163 }
3164 }
3165
3166 /* reserve a descriptor for the offload context */
3167 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
3168 count++;
3169 count++;
3170
3171 /* Controller Erratum workaround */
3172 if (!skb->data_len && tx_ring->last_tx_tso && !skb_is_gso(skb))
3173 count++;
3174
3175 count += TXD_USE_COUNT(len, max_txd_pwr);
3176
3177 if (adapter->pcix_82544)
3178 count++;
3179
3180 /* work-around for errata 10 and it applies to all controllers
3181 * in PCI-X mode, so add one more descriptor to the count
3182 */
3183 if (unlikely((hw->bus_type == e1000_bus_type_pcix) &&
3184 (len > 2015)))
3185 count++;
3186
3187 nr_frags = skb_shinfo(skb)->nr_frags;
3188 for (f = 0; f < nr_frags; f++)
3189 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
3190 max_txd_pwr);
3191 if (adapter->pcix_82544)
3192 count += nr_frags;
3193
3194 /* need: count + 2 desc gap to keep tail from touching
3195 * head, otherwise try next time */
3196 if (unlikely(e1000_maybe_stop_tx(netdev, tx_ring, count + 2)))
3197 return NETDEV_TX_BUSY;
3198
3199 if (unlikely(hw->mac_type == e1000_82547)) {
3200 if (unlikely(e1000_82547_fifo_workaround(adapter, skb))) {
3201 netif_stop_queue(netdev);
3202 if (!test_bit(__E1000_DOWN, &adapter->flags))
3203 mod_timer(&adapter->tx_fifo_stall_timer,
3204 jiffies + 1);
3205 return NETDEV_TX_BUSY;
3206 }
3207 }
3208
3209 if (vlan_tx_tag_present(skb)) {
3210 tx_flags |= E1000_TX_FLAGS_VLAN;
3211 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
3212 }
3213
3214 first = tx_ring->next_to_use;
3215
3216 tso = e1000_tso(adapter, tx_ring, skb);
3217 if (tso < 0) {
3218 dev_kfree_skb_any(skb);
3219 return NETDEV_TX_OK;
3220 }
3221
3222 if (likely(tso)) {
3223 if (likely(hw->mac_type != e1000_82544))
3224 tx_ring->last_tx_tso = 1;
3225 tx_flags |= E1000_TX_FLAGS_TSO;
3226 } else if (likely(e1000_tx_csum(adapter, tx_ring, skb)))
3227 tx_flags |= E1000_TX_FLAGS_CSUM;
3228
3229 if (likely(skb->protocol == htons(ETH_P_IP)))
3230 tx_flags |= E1000_TX_FLAGS_IPV4;
3231
3232 count = e1000_tx_map(adapter, tx_ring, skb, first, max_per_txd,
3233 nr_frags, mss);
3234
3235 if (count) {
3236 e1000_tx_queue(adapter, tx_ring, tx_flags, count);
3237 /* Make sure there is space in the ring for the next send. */
3238 e1000_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 2);
3239
3240 } else {
3241 dev_kfree_skb_any(skb);
3242 tx_ring->buffer_info[first].time_stamp = 0;
3243 tx_ring->next_to_use = first;
3244 }
3245
3246 return NETDEV_TX_OK;
3247}
3248
3249/**
3250 * e1000_tx_timeout - Respond to a Tx Hang
3251 * @netdev: network interface device structure
3252 **/
3253
3254static void e1000_tx_timeout(struct net_device *netdev)
3255{
3256 struct e1000_adapter *adapter = netdev_priv(netdev);
3257
3258 /* Do the reset outside of interrupt context */
3259 adapter->tx_timeout_count++;
3260 schedule_work(&adapter->reset_task);
3261}
3262
3263static void e1000_reset_task(struct work_struct *work)
3264{
3265 struct e1000_adapter *adapter =
3266 container_of(work, struct e1000_adapter, reset_task);
3267
3268 e1000_reinit_safe(adapter);
3269}
3270
3271/**
3272 * e1000_get_stats - Get System Network Statistics
3273 * @netdev: network interface device structure
3274 *
3275 * Returns the address of the device statistics structure.
3276 * The statistics are actually updated from the timer callback.
3277 **/
3278
3279static struct net_device_stats *e1000_get_stats(struct net_device *netdev)
3280{
3281 /* only return the current stats */
3282 return &netdev->stats;
3283}
3284
3285/**
3286 * e1000_change_mtu - Change the Maximum Transfer Unit
3287 * @netdev: network interface device structure
3288 * @new_mtu: new value for maximum frame size
3289 *
3290 * Returns 0 on success, negative on failure
3291 **/
3292
3293static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
3294{
3295 struct e1000_adapter *adapter = netdev_priv(netdev);
3296 struct e1000_hw *hw = &adapter->hw;
3297 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
3298
3299 if ((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
3300 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3301 e_err(probe, "Invalid MTU setting\n");
3302 return -EINVAL;
3303 }
3304
3305 /* Adapter-specific max frame size limits. */
3306 switch (hw->mac_type) {
3307 case e1000_undefined ... e1000_82542_rev2_1:
3308 if (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)) {
3309 e_err(probe, "Jumbo Frames not supported.\n");
3310 return -EINVAL;
3311 }
3312 break;
3313 default:
3314 /* Capable of supporting up to MAX_JUMBO_FRAME_SIZE limit. */
3315 break;
3316 }
3317
3318 while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
3319 msleep(1);
3320 /* e1000_down has a dependency on max_frame_size */
3321 hw->max_frame_size = max_frame;
3322 if (netif_running(netdev))
3323 e1000_down(adapter);
3324
3325 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3326 * means we reserve 2 more, this pushes us to allocate from the next
3327 * larger slab size.
3328 * i.e. RXBUFFER_2048 --> size-4096 slab
3329 * however with the new *_jumbo_rx* routines, jumbo receives will use
3330 * fragmented skbs */
3331
3332 if (max_frame <= E1000_RXBUFFER_2048)
3333 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
3334 else
3335#if (PAGE_SIZE >= E1000_RXBUFFER_16384)
3336 adapter->rx_buffer_len = E1000_RXBUFFER_16384;
3337#elif (PAGE_SIZE >= E1000_RXBUFFER_4096)
3338 adapter->rx_buffer_len = PAGE_SIZE;
3339#endif
3340
3341 /* adjust allocation if LPE protects us, and we aren't using SBP */
3342 if (!hw->tbi_compatibility_on &&
3343 ((max_frame == (ETH_FRAME_LEN + ETH_FCS_LEN)) ||
3344 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE)))
3345 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3346
3347 pr_info("%s changing MTU from %d to %d\n",
3348 netdev->name, netdev->mtu, new_mtu);
3349 netdev->mtu = new_mtu;
3350
3351 if (netif_running(netdev))
3352 e1000_up(adapter);
3353 else
3354 e1000_reset(adapter);
3355
3356 clear_bit(__E1000_RESETTING, &adapter->flags);
3357
3358 return 0;
3359}
3360
3361/**
3362 * e1000_update_stats - Update the board statistics counters
3363 * @adapter: board private structure
3364 **/
3365
3366void e1000_update_stats(struct e1000_adapter *adapter)
3367{
3368 struct net_device *netdev = adapter->netdev;
3369 struct e1000_hw *hw = &adapter->hw;
3370 struct pci_dev *pdev = adapter->pdev;
3371 unsigned long flags;
3372 u16 phy_tmp;
3373
3374#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3375
3376 /*
3377 * Prevent stats update while adapter is being reset, or if the pci
3378 * connection is down.
3379 */
3380 if (adapter->link_speed == 0)
3381 return;
3382 if (pci_channel_offline(pdev))
3383 return;
3384
3385 spin_lock_irqsave(&adapter->stats_lock, flags);
3386
3387 /* these counters are modified from e1000_tbi_adjust_stats,
3388 * called from the interrupt context, so they must only
3389 * be written while holding adapter->stats_lock
3390 */
3391
3392 adapter->stats.crcerrs += er32(CRCERRS);
3393 adapter->stats.gprc += er32(GPRC);
3394 adapter->stats.gorcl += er32(GORCL);
3395 adapter->stats.gorch += er32(GORCH);
3396 adapter->stats.bprc += er32(BPRC);
3397 adapter->stats.mprc += er32(MPRC);
3398 adapter->stats.roc += er32(ROC);
3399
3400 adapter->stats.prc64 += er32(PRC64);
3401 adapter->stats.prc127 += er32(PRC127);
3402 adapter->stats.prc255 += er32(PRC255);
3403 adapter->stats.prc511 += er32(PRC511);
3404 adapter->stats.prc1023 += er32(PRC1023);
3405 adapter->stats.prc1522 += er32(PRC1522);
3406
3407 adapter->stats.symerrs += er32(SYMERRS);
3408 adapter->stats.mpc += er32(MPC);
3409 adapter->stats.scc += er32(SCC);
3410 adapter->stats.ecol += er32(ECOL);
3411 adapter->stats.mcc += er32(MCC);
3412 adapter->stats.latecol += er32(LATECOL);
3413 adapter->stats.dc += er32(DC);
3414 adapter->stats.sec += er32(SEC);
3415 adapter->stats.rlec += er32(RLEC);
3416 adapter->stats.xonrxc += er32(XONRXC);
3417 adapter->stats.xontxc += er32(XONTXC);
3418 adapter->stats.xoffrxc += er32(XOFFRXC);
3419 adapter->stats.xofftxc += er32(XOFFTXC);
3420 adapter->stats.fcruc += er32(FCRUC);
3421 adapter->stats.gptc += er32(GPTC);
3422 adapter->stats.gotcl += er32(GOTCL);
3423 adapter->stats.gotch += er32(GOTCH);
3424 adapter->stats.rnbc += er32(RNBC);
3425 adapter->stats.ruc += er32(RUC);
3426 adapter->stats.rfc += er32(RFC);
3427 adapter->stats.rjc += er32(RJC);
3428 adapter->stats.torl += er32(TORL);
3429 adapter->stats.torh += er32(TORH);
3430 adapter->stats.totl += er32(TOTL);
3431 adapter->stats.toth += er32(TOTH);
3432 adapter->stats.tpr += er32(TPR);
3433
3434 adapter->stats.ptc64 += er32(PTC64);
3435 adapter->stats.ptc127 += er32(PTC127);
3436 adapter->stats.ptc255 += er32(PTC255);
3437 adapter->stats.ptc511 += er32(PTC511);
3438 adapter->stats.ptc1023 += er32(PTC1023);
3439 adapter->stats.ptc1522 += er32(PTC1522);
3440
3441 adapter->stats.mptc += er32(MPTC);
3442 adapter->stats.bptc += er32(BPTC);
3443
3444 /* used for adaptive IFS */
3445
3446 hw->tx_packet_delta = er32(TPT);
3447 adapter->stats.tpt += hw->tx_packet_delta;
3448 hw->collision_delta = er32(COLC);
3449 adapter->stats.colc += hw->collision_delta;
3450
3451 if (hw->mac_type >= e1000_82543) {
3452 adapter->stats.algnerrc += er32(ALGNERRC);
3453 adapter->stats.rxerrc += er32(RXERRC);
3454 adapter->stats.tncrs += er32(TNCRS);
3455 adapter->stats.cexterr += er32(CEXTERR);
3456 adapter->stats.tsctc += er32(TSCTC);
3457 adapter->stats.tsctfc += er32(TSCTFC);
3458 }
3459
3460 /* Fill out the OS statistics structure */
3461 netdev->stats.multicast = adapter->stats.mprc;
3462 netdev->stats.collisions = adapter->stats.colc;
3463
3464 /* Rx Errors */
3465
3466 /* RLEC on some newer hardware can be incorrect so build
3467 * our own version based on RUC and ROC */
3468 netdev->stats.rx_errors = adapter->stats.rxerrc +
3469 adapter->stats.crcerrs + adapter->stats.algnerrc +
3470 adapter->stats.ruc + adapter->stats.roc +
3471 adapter->stats.cexterr;
3472 adapter->stats.rlerrc = adapter->stats.ruc + adapter->stats.roc;
3473 netdev->stats.rx_length_errors = adapter->stats.rlerrc;
3474 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
3475 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
3476 netdev->stats.rx_missed_errors = adapter->stats.mpc;
3477
3478 /* Tx Errors */
3479 adapter->stats.txerrc = adapter->stats.ecol + adapter->stats.latecol;
3480 netdev->stats.tx_errors = adapter->stats.txerrc;
3481 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
3482 netdev->stats.tx_window_errors = adapter->stats.latecol;
3483 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
3484 if (hw->bad_tx_carr_stats_fd &&
3485 adapter->link_duplex == FULL_DUPLEX) {
3486 netdev->stats.tx_carrier_errors = 0;
3487 adapter->stats.tncrs = 0;
3488 }
3489
3490 /* Tx Dropped needs to be maintained elsewhere */
3491
3492 /* Phy Stats */
3493 if (hw->media_type == e1000_media_type_copper) {
3494 if ((adapter->link_speed == SPEED_1000) &&
3495 (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3496 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3497 adapter->phy_stats.idle_errors += phy_tmp;
3498 }
3499
3500 if ((hw->mac_type <= e1000_82546) &&
3501 (hw->phy_type == e1000_phy_m88) &&
3502 !e1000_read_phy_reg(hw, M88E1000_RX_ERR_CNTR, &phy_tmp))
3503 adapter->phy_stats.receive_errors += phy_tmp;
3504 }
3505
3506 /* Management Stats */
3507 if (hw->has_smbus) {
3508 adapter->stats.mgptc += er32(MGTPTC);
3509 adapter->stats.mgprc += er32(MGTPRC);
3510 adapter->stats.mgpdc += er32(MGTPDC);
3511 }
3512
3513 spin_unlock_irqrestore(&adapter->stats_lock, flags);
3514}
3515
3516/**
3517 * e1000_intr - Interrupt Handler
3518 * @irq: interrupt number
3519 * @data: pointer to a network interface device structure
3520 **/
3521
3522static irqreturn_t e1000_intr(int irq, void *data)
3523{
3524 struct net_device *netdev = data;
3525 struct e1000_adapter *adapter = netdev_priv(netdev);
3526 struct e1000_hw *hw = &adapter->hw;
3527 u32 icr = er32(ICR);
3528
3529 if (unlikely((!icr)))
3530 return IRQ_NONE; /* Not our interrupt */
3531
3532 /*
3533 * we might have caused the interrupt, but the above
3534 * read cleared it, and just in case the driver is
3535 * down there is nothing to do so return handled
3536 */
3537 if (unlikely(test_bit(__E1000_DOWN, &adapter->flags)))
3538 return IRQ_HANDLED;
3539
3540 if (unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) {
3541 hw->get_link_status = 1;
3542 /* guard against interrupt when we're going down */
3543 if (!test_bit(__E1000_DOWN, &adapter->flags))
3544 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3545 }
3546
3547 /* disable interrupts, without the synchronize_irq bit */
3548 ew32(IMC, ~0);
3549 E1000_WRITE_FLUSH();
3550
3551 if (likely(napi_schedule_prep(&adapter->napi))) {
3552 adapter->total_tx_bytes = 0;
3553 adapter->total_tx_packets = 0;
3554 adapter->total_rx_bytes = 0;
3555 adapter->total_rx_packets = 0;
3556 __napi_schedule(&adapter->napi);
3557 } else {
3558 /* this really should not happen! if it does it is basically a
3559 * bug, but not a hard error, so enable ints and continue */
3560 if (!test_bit(__E1000_DOWN, &adapter->flags))
3561 e1000_irq_enable(adapter);
3562 }
3563
3564 return IRQ_HANDLED;
3565}
3566
3567/**
3568 * e1000_clean - NAPI Rx polling callback
3569 * @adapter: board private structure
3570 **/
3571static int e1000_clean(struct napi_struct *napi, int budget)
3572{
3573 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, napi);
3574 int tx_clean_complete = 0, work_done = 0;
3575
3576 tx_clean_complete = e1000_clean_tx_irq(adapter, &adapter->tx_ring[0]);
3577
3578 adapter->clean_rx(adapter, &adapter->rx_ring[0], &work_done, budget);
3579
3580 if (!tx_clean_complete)
3581 work_done = budget;
3582
3583 /* If budget not fully consumed, exit the polling mode */
3584 if (work_done < budget) {
3585 if (likely(adapter->itr_setting & 3))
3586 e1000_set_itr(adapter);
3587 napi_complete(napi);
3588 if (!test_bit(__E1000_DOWN, &adapter->flags))
3589 e1000_irq_enable(adapter);
3590 }
3591
3592 return work_done;
3593}
3594
3595/**
3596 * e1000_clean_tx_irq - Reclaim resources after transmit completes
3597 * @adapter: board private structure
3598 **/
3599static bool e1000_clean_tx_irq(struct e1000_adapter *adapter,
3600 struct e1000_tx_ring *tx_ring)
3601{
3602 struct e1000_hw *hw = &adapter->hw;
3603 struct net_device *netdev = adapter->netdev;
3604 struct e1000_tx_desc *tx_desc, *eop_desc;
3605 struct e1000_buffer *buffer_info;
3606 unsigned int i, eop;
3607 unsigned int count = 0;
3608 unsigned int total_tx_bytes=0, total_tx_packets=0;
3609
3610 i = tx_ring->next_to_clean;
3611 eop = tx_ring->buffer_info[i].next_to_watch;
3612 eop_desc = E1000_TX_DESC(*tx_ring, eop);
3613
3614 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
3615 (count < tx_ring->count)) {
3616 bool cleaned = false;
3617 rmb(); /* read buffer_info after eop_desc */
3618 for ( ; !cleaned; count++) {
3619 tx_desc = E1000_TX_DESC(*tx_ring, i);
3620 buffer_info = &tx_ring->buffer_info[i];
3621 cleaned = (i == eop);
3622
3623 if (cleaned) {
3624 struct sk_buff *skb = buffer_info->skb;
3625 unsigned int segs, bytecount;
3626 segs = skb_shinfo(skb)->gso_segs ?: 1;
3627 /* multiply data chunks by size of headers */
3628 bytecount = ((segs - 1) * skb_headlen(skb)) +
3629 skb->len;
3630 total_tx_packets += segs;
3631 total_tx_bytes += bytecount;
3632 }
3633 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
3634 tx_desc->upper.data = 0;
3635
3636 if (unlikely(++i == tx_ring->count)) i = 0;
3637 }
3638
3639 eop = tx_ring->buffer_info[i].next_to_watch;
3640 eop_desc = E1000_TX_DESC(*tx_ring, eop);
3641 }
3642
3643 tx_ring->next_to_clean = i;
3644
3645#define TX_WAKE_THRESHOLD 32
3646 if (unlikely(count && netif_carrier_ok(netdev) &&
3647 E1000_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD)) {
3648 /* Make sure that anybody stopping the queue after this
3649 * sees the new next_to_clean.
3650 */
3651 smp_mb();
3652
3653 if (netif_queue_stopped(netdev) &&
3654 !(test_bit(__E1000_DOWN, &adapter->flags))) {
3655 netif_wake_queue(netdev);
3656 ++adapter->restart_queue;
3657 }
3658 }
3659
3660 if (adapter->detect_tx_hung) {
3661 /* Detect a transmit hang in hardware, this serializes the
3662 * check with the clearing of time_stamp and movement of i */
3663 adapter->detect_tx_hung = false;
3664 if (tx_ring->buffer_info[eop].time_stamp &&
3665 time_after(jiffies, tx_ring->buffer_info[eop].time_stamp +
3666 (adapter->tx_timeout_factor * HZ)) &&
3667 !(er32(STATUS) & E1000_STATUS_TXOFF)) {
3668
3669 /* detected Tx unit hang */
3670 e_err(drv, "Detected Tx Unit Hang\n"
3671 " Tx Queue <%lu>\n"
3672 " TDH <%x>\n"
3673 " TDT <%x>\n"
3674 " next_to_use <%x>\n"
3675 " next_to_clean <%x>\n"
3676 "buffer_info[next_to_clean]\n"
3677 " time_stamp <%lx>\n"
3678 " next_to_watch <%x>\n"
3679 " jiffies <%lx>\n"
3680 " next_to_watch.status <%x>\n",
3681 (unsigned long)((tx_ring - adapter->tx_ring) /
3682 sizeof(struct e1000_tx_ring)),
3683 readl(hw->hw_addr + tx_ring->tdh),
3684 readl(hw->hw_addr + tx_ring->tdt),
3685 tx_ring->next_to_use,
3686 tx_ring->next_to_clean,
3687 tx_ring->buffer_info[eop].time_stamp,
3688 eop,
3689 jiffies,
3690 eop_desc->upper.fields.status);
3691 netif_stop_queue(netdev);
3692 }
3693 }
3694 adapter->total_tx_bytes += total_tx_bytes;
3695 adapter->total_tx_packets += total_tx_packets;
3696 netdev->stats.tx_bytes += total_tx_bytes;
3697 netdev->stats.tx_packets += total_tx_packets;
3698 return count < tx_ring->count;
3699}
3700
3701/**
3702 * e1000_rx_checksum - Receive Checksum Offload for 82543
3703 * @adapter: board private structure
3704 * @status_err: receive descriptor status and error fields
3705 * @csum: receive descriptor csum field
3706 * @sk_buff: socket buffer with received data
3707 **/
3708
3709static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
3710 u32 csum, struct sk_buff *skb)
3711{
3712 struct e1000_hw *hw = &adapter->hw;
3713 u16 status = (u16)status_err;
3714 u8 errors = (u8)(status_err >> 24);
3715
3716 skb_checksum_none_assert(skb);
3717
3718 /* 82543 or newer only */
3719 if (unlikely(hw->mac_type < e1000_82543)) return;
3720 /* Ignore Checksum bit is set */
3721 if (unlikely(status & E1000_RXD_STAT_IXSM)) return;
3722 /* TCP/UDP checksum error bit is set */
3723 if (unlikely(errors & E1000_RXD_ERR_TCPE)) {
3724 /* let the stack verify checksum errors */
3725 adapter->hw_csum_err++;
3726 return;
3727 }
3728 /* TCP/UDP Checksum has not been calculated */
3729 if (!(status & E1000_RXD_STAT_TCPCS))
3730 return;
3731
3732 /* It must be a TCP or UDP packet with a valid checksum */
3733 if (likely(status & E1000_RXD_STAT_TCPCS)) {
3734 /* TCP checksum is good */
3735 skb->ip_summed = CHECKSUM_UNNECESSARY;
3736 }
3737 adapter->hw_csum_good++;
3738}
3739
3740/**
3741 * e1000_consume_page - helper function
3742 **/
3743static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
3744 u16 length)
3745{
3746 bi->page = NULL;
3747 skb->len += length;
3748 skb->data_len += length;
3749 skb->truesize += length;
3750}
3751
3752/**
3753 * e1000_receive_skb - helper function to handle rx indications
3754 * @adapter: board private structure
3755 * @status: descriptor status field as written by hardware
3756 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3757 * @skb: pointer to sk_buff to be indicated to stack
3758 */
3759static void e1000_receive_skb(struct e1000_adapter *adapter, u8 status,
3760 __le16 vlan, struct sk_buff *skb)
3761{
3762 skb->protocol = eth_type_trans(skb, adapter->netdev);
3763
3764 if (status & E1000_RXD_STAT_VP) {
3765 u16 vid = le16_to_cpu(vlan) & E1000_RXD_SPC_VLAN_MASK;
3766
3767 __vlan_hwaccel_put_tag(skb, vid);
3768 }
3769 napi_gro_receive(&adapter->napi, skb);
3770}
3771
3772/**
3773 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
3774 * @adapter: board private structure
3775 * @rx_ring: ring to clean
3776 * @work_done: amount of napi work completed this call
3777 * @work_to_do: max amount of work allowed for this call to do
3778 *
3779 * the return value indicates whether actual cleaning was done, there
3780 * is no guarantee that everything was cleaned
3781 */
3782static bool e1000_clean_jumbo_rx_irq(struct e1000_adapter *adapter,
3783 struct e1000_rx_ring *rx_ring,
3784 int *work_done, int work_to_do)
3785{
3786 struct e1000_hw *hw = &adapter->hw;
3787 struct net_device *netdev = adapter->netdev;
3788 struct pci_dev *pdev = adapter->pdev;
3789 struct e1000_rx_desc *rx_desc, *next_rxd;
3790 struct e1000_buffer *buffer_info, *next_buffer;
3791 unsigned long irq_flags;
3792 u32 length;
3793 unsigned int i;
3794 int cleaned_count = 0;
3795 bool cleaned = false;
3796 unsigned int total_rx_bytes=0, total_rx_packets=0;
3797
3798 i = rx_ring->next_to_clean;
3799 rx_desc = E1000_RX_DESC(*rx_ring, i);
3800 buffer_info = &rx_ring->buffer_info[i];
3801
3802 while (rx_desc->status & E1000_RXD_STAT_DD) {
3803 struct sk_buff *skb;
3804 u8 status;
3805
3806 if (*work_done >= work_to_do)
3807 break;
3808 (*work_done)++;
3809 rmb(); /* read descriptor and rx_buffer_info after status DD */
3810
3811 status = rx_desc->status;
3812 skb = buffer_info->skb;
3813 buffer_info->skb = NULL;
3814
3815 if (++i == rx_ring->count) i = 0;
3816 next_rxd = E1000_RX_DESC(*rx_ring, i);
3817 prefetch(next_rxd);
3818
3819 next_buffer = &rx_ring->buffer_info[i];
3820
3821 cleaned = true;
3822 cleaned_count++;
3823 dma_unmap_page(&pdev->dev, buffer_info->dma,
3824 buffer_info->length, DMA_FROM_DEVICE);
3825 buffer_info->dma = 0;
3826
3827 length = le16_to_cpu(rx_desc->length);
3828
3829 /* errors is only valid for DD + EOP descriptors */
3830 if (unlikely((status & E1000_RXD_STAT_EOP) &&
3831 (rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK))) {
3832 u8 last_byte = *(skb->data + length - 1);
3833 if (TBI_ACCEPT(hw, status, rx_desc->errors, length,
3834 last_byte)) {
3835 spin_lock_irqsave(&adapter->stats_lock,
3836 irq_flags);
3837 e1000_tbi_adjust_stats(hw, &adapter->stats,
3838 length, skb->data);
3839 spin_unlock_irqrestore(&adapter->stats_lock,
3840 irq_flags);
3841 length--;
3842 } else {
3843 /* recycle both page and skb */
3844 buffer_info->skb = skb;
3845 /* an error means any chain goes out the window
3846 * too */
3847 if (rx_ring->rx_skb_top)
3848 dev_kfree_skb(rx_ring->rx_skb_top);
3849 rx_ring->rx_skb_top = NULL;
3850 goto next_desc;
3851 }
3852 }
3853
3854#define rxtop rx_ring->rx_skb_top
3855 if (!(status & E1000_RXD_STAT_EOP)) {
3856 /* this descriptor is only the beginning (or middle) */
3857 if (!rxtop) {
3858 /* this is the beginning of a chain */
3859 rxtop = skb;
3860 skb_fill_page_desc(rxtop, 0, buffer_info->page,
3861 0, length);
3862 } else {
3863 /* this is the middle of a chain */
3864 skb_fill_page_desc(rxtop,
3865 skb_shinfo(rxtop)->nr_frags,
3866 buffer_info->page, 0, length);
3867 /* re-use the skb, only consumed the page */
3868 buffer_info->skb = skb;
3869 }
3870 e1000_consume_page(buffer_info, rxtop, length);
3871 goto next_desc;
3872 } else {
3873 if (rxtop) {
3874 /* end of the chain */
3875 skb_fill_page_desc(rxtop,
3876 skb_shinfo(rxtop)->nr_frags,
3877 buffer_info->page, 0, length);
3878 /* re-use the current skb, we only consumed the
3879 * page */
3880 buffer_info->skb = skb;
3881 skb = rxtop;
3882 rxtop = NULL;
3883 e1000_consume_page(buffer_info, skb, length);
3884 } else {
3885 /* no chain, got EOP, this buf is the packet
3886 * copybreak to save the put_page/alloc_page */
3887 if (length <= copybreak &&
3888 skb_tailroom(skb) >= length) {
3889 u8 *vaddr;
3890 vaddr = kmap_atomic(buffer_info->page,
3891 KM_SKB_DATA_SOFTIRQ);
3892 memcpy(skb_tail_pointer(skb), vaddr, length);
3893 kunmap_atomic(vaddr,
3894 KM_SKB_DATA_SOFTIRQ);
3895 /* re-use the page, so don't erase
3896 * buffer_info->page */
3897 skb_put(skb, length);
3898 } else {
3899 skb_fill_page_desc(skb, 0,
3900 buffer_info->page, 0,
3901 length);
3902 e1000_consume_page(buffer_info, skb,
3903 length);
3904 }
3905 }
3906 }
3907
3908 /* Receive Checksum Offload XXX recompute due to CRC strip? */
3909 e1000_rx_checksum(adapter,
3910 (u32)(status) |
3911 ((u32)(rx_desc->errors) << 24),
3912 le16_to_cpu(rx_desc->csum), skb);
3913
3914 pskb_trim(skb, skb->len - 4);
3915
3916 /* probably a little skewed due to removing CRC */
3917 total_rx_bytes += skb->len;
3918 total_rx_packets++;
3919
3920 /* eth type trans needs skb->data to point to something */
3921 if (!pskb_may_pull(skb, ETH_HLEN)) {
3922 e_err(drv, "pskb_may_pull failed.\n");
3923 dev_kfree_skb(skb);
3924 goto next_desc;
3925 }
3926
3927 e1000_receive_skb(adapter, status, rx_desc->special, skb);
3928
3929next_desc:
3930 rx_desc->status = 0;
3931
3932 /* return some buffers to hardware, one at a time is too slow */
3933 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
3934 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
3935 cleaned_count = 0;
3936 }
3937
3938 /* use prefetched values */
3939 rx_desc = next_rxd;
3940 buffer_info = next_buffer;
3941 }
3942 rx_ring->next_to_clean = i;
3943
3944 cleaned_count = E1000_DESC_UNUSED(rx_ring);
3945 if (cleaned_count)
3946 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
3947
3948 adapter->total_rx_packets += total_rx_packets;
3949 adapter->total_rx_bytes += total_rx_bytes;
3950 netdev->stats.rx_bytes += total_rx_bytes;
3951 netdev->stats.rx_packets += total_rx_packets;
3952 return cleaned;
3953}
3954
3955/*
3956 * this should improve performance for small packets with large amounts
3957 * of reassembly being done in the stack
3958 */
3959static void e1000_check_copybreak(struct net_device *netdev,
3960 struct e1000_buffer *buffer_info,
3961 u32 length, struct sk_buff **skb)
3962{
3963 struct sk_buff *new_skb;
3964
3965 if (length > copybreak)
3966 return;
3967
3968 new_skb = netdev_alloc_skb_ip_align(netdev, length);
3969 if (!new_skb)
3970 return;
3971
3972 skb_copy_to_linear_data_offset(new_skb, -NET_IP_ALIGN,
3973 (*skb)->data - NET_IP_ALIGN,
3974 length + NET_IP_ALIGN);
3975 /* save the skb in buffer_info as good */
3976 buffer_info->skb = *skb;
3977 *skb = new_skb;
3978}
3979
3980/**
3981 * e1000_clean_rx_irq - Send received data up the network stack; legacy
3982 * @adapter: board private structure
3983 * @rx_ring: ring to clean
3984 * @work_done: amount of napi work completed this call
3985 * @work_to_do: max amount of work allowed for this call to do
3986 */
3987static bool e1000_clean_rx_irq(struct e1000_adapter *adapter,
3988 struct e1000_rx_ring *rx_ring,
3989 int *work_done, int work_to_do)
3990{
3991 struct e1000_hw *hw = &adapter->hw;
3992 struct net_device *netdev = adapter->netdev;
3993 struct pci_dev *pdev = adapter->pdev;
3994 struct e1000_rx_desc *rx_desc, *next_rxd;
3995 struct e1000_buffer *buffer_info, *next_buffer;
3996 unsigned long flags;
3997 u32 length;
3998 unsigned int i;
3999 int cleaned_count = 0;
4000 bool cleaned = false;
4001 unsigned int total_rx_bytes=0, total_rx_packets=0;
4002
4003 i = rx_ring->next_to_clean;
4004 rx_desc = E1000_RX_DESC(*rx_ring, i);
4005 buffer_info = &rx_ring->buffer_info[i];
4006
4007 while (rx_desc->status & E1000_RXD_STAT_DD) {
4008 struct sk_buff *skb;
4009 u8 status;
4010
4011 if (*work_done >= work_to_do)
4012 break;
4013 (*work_done)++;
4014 rmb(); /* read descriptor and rx_buffer_info after status DD */
4015
4016 status = rx_desc->status;
4017 skb = buffer_info->skb;
4018 buffer_info->skb = NULL;
4019
4020 prefetch(skb->data - NET_IP_ALIGN);
4021
4022 if (++i == rx_ring->count) i = 0;
4023 next_rxd = E1000_RX_DESC(*rx_ring, i);
4024 prefetch(next_rxd);
4025
4026 next_buffer = &rx_ring->buffer_info[i];
4027
4028 cleaned = true;
4029 cleaned_count++;
4030 dma_unmap_single(&pdev->dev, buffer_info->dma,
4031 buffer_info->length, DMA_FROM_DEVICE);
4032 buffer_info->dma = 0;
4033
4034 length = le16_to_cpu(rx_desc->length);
4035 /* !EOP means multiple descriptors were used to store a single
4036 * packet, if thats the case we need to toss it. In fact, we
4037 * to toss every packet with the EOP bit clear and the next
4038 * frame that _does_ have the EOP bit set, as it is by
4039 * definition only a frame fragment
4040 */
4041 if (unlikely(!(status & E1000_RXD_STAT_EOP)))
4042 adapter->discarding = true;
4043
4044 if (adapter->discarding) {
4045 /* All receives must fit into a single buffer */
4046 e_dbg("Receive packet consumed multiple buffers\n");
4047 /* recycle */
4048 buffer_info->skb = skb;
4049 if (status & E1000_RXD_STAT_EOP)
4050 adapter->discarding = false;
4051 goto next_desc;
4052 }
4053
4054 if (unlikely(rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK)) {
4055 u8 last_byte = *(skb->data + length - 1);
4056 if (TBI_ACCEPT(hw, status, rx_desc->errors, length,
4057 last_byte)) {
4058 spin_lock_irqsave(&adapter->stats_lock, flags);
4059 e1000_tbi_adjust_stats(hw, &adapter->stats,
4060 length, skb->data);
4061 spin_unlock_irqrestore(&adapter->stats_lock,
4062 flags);
4063 length--;
4064 } else {
4065 /* recycle */
4066 buffer_info->skb = skb;
4067 goto next_desc;
4068 }
4069 }
4070
4071 /* adjust length to remove Ethernet CRC, this must be
4072 * done after the TBI_ACCEPT workaround above */
4073 length -= 4;
4074
4075 /* probably a little skewed due to removing CRC */
4076 total_rx_bytes += length;
4077 total_rx_packets++;
4078
4079 e1000_check_copybreak(netdev, buffer_info, length, &skb);
4080
4081 skb_put(skb, length);
4082
4083 /* Receive Checksum Offload */
4084 e1000_rx_checksum(adapter,
4085 (u32)(status) |
4086 ((u32)(rx_desc->errors) << 24),
4087 le16_to_cpu(rx_desc->csum), skb);
4088
4089 e1000_receive_skb(adapter, status, rx_desc->special, skb);
4090
4091next_desc:
4092 rx_desc->status = 0;
4093
4094 /* return some buffers to hardware, one at a time is too slow */
4095 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
4096 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
4097 cleaned_count = 0;
4098 }
4099
4100 /* use prefetched values */
4101 rx_desc = next_rxd;
4102 buffer_info = next_buffer;
4103 }
4104 rx_ring->next_to_clean = i;
4105
4106 cleaned_count = E1000_DESC_UNUSED(rx_ring);
4107 if (cleaned_count)
4108 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
4109
4110 adapter->total_rx_packets += total_rx_packets;
4111 adapter->total_rx_bytes += total_rx_bytes;
4112 netdev->stats.rx_bytes += total_rx_bytes;
4113 netdev->stats.rx_packets += total_rx_packets;
4114 return cleaned;
4115}
4116
4117/**
4118 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
4119 * @adapter: address of board private structure
4120 * @rx_ring: pointer to receive ring structure
4121 * @cleaned_count: number of buffers to allocate this pass
4122 **/
4123
4124static void
4125e1000_alloc_jumbo_rx_buffers(struct e1000_adapter *adapter,
4126 struct e1000_rx_ring *rx_ring, int cleaned_count)
4127{
4128 struct net_device *netdev = adapter->netdev;
4129 struct pci_dev *pdev = adapter->pdev;
4130 struct e1000_rx_desc *rx_desc;
4131 struct e1000_buffer *buffer_info;
4132 struct sk_buff *skb;
4133 unsigned int i;
4134 unsigned int bufsz = 256 - 16 /*for skb_reserve */ ;
4135
4136 i = rx_ring->next_to_use;
4137 buffer_info = &rx_ring->buffer_info[i];
4138
4139 while (cleaned_count--) {
4140 skb = buffer_info->skb;
4141 if (skb) {
4142 skb_trim(skb, 0);
4143 goto check_page;
4144 }
4145
4146 skb = netdev_alloc_skb_ip_align(netdev, bufsz);
4147 if (unlikely(!skb)) {
4148 /* Better luck next round */
4149 adapter->alloc_rx_buff_failed++;
4150 break;
4151 }
4152
4153 /* Fix for errata 23, can't cross 64kB boundary */
4154 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
4155 struct sk_buff *oldskb = skb;
4156 e_err(rx_err, "skb align check failed: %u bytes at "
4157 "%p\n", bufsz, skb->data);
4158 /* Try again, without freeing the previous */
4159 skb = netdev_alloc_skb_ip_align(netdev, bufsz);
4160 /* Failed allocation, critical failure */
4161 if (!skb) {
4162 dev_kfree_skb(oldskb);
4163 adapter->alloc_rx_buff_failed++;
4164 break;
4165 }
4166
4167 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
4168 /* give up */
4169 dev_kfree_skb(skb);
4170 dev_kfree_skb(oldskb);
4171 break; /* while (cleaned_count--) */
4172 }
4173
4174 /* Use new allocation */
4175 dev_kfree_skb(oldskb);
4176 }
4177 buffer_info->skb = skb;
4178 buffer_info->length = adapter->rx_buffer_len;
4179check_page:
4180 /* allocate a new page if necessary */
4181 if (!buffer_info->page) {
4182 buffer_info->page = alloc_page(GFP_ATOMIC);
4183 if (unlikely(!buffer_info->page)) {
4184 adapter->alloc_rx_buff_failed++;
4185 break;
4186 }
4187 }
4188
4189 if (!buffer_info->dma) {
4190 buffer_info->dma = dma_map_page(&pdev->dev,
4191 buffer_info->page, 0,
4192 buffer_info->length,
4193 DMA_FROM_DEVICE);
4194 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
4195 put_page(buffer_info->page);
4196 dev_kfree_skb(skb);
4197 buffer_info->page = NULL;
4198 buffer_info->skb = NULL;
4199 buffer_info->dma = 0;
4200 adapter->alloc_rx_buff_failed++;
4201 break; /* while !buffer_info->skb */
4202 }
4203 }
4204
4205 rx_desc = E1000_RX_DESC(*rx_ring, i);
4206 rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
4207
4208 if (unlikely(++i == rx_ring->count))
4209 i = 0;
4210 buffer_info = &rx_ring->buffer_info[i];
4211 }
4212
4213 if (likely(rx_ring->next_to_use != i)) {
4214 rx_ring->next_to_use = i;
4215 if (unlikely(i-- == 0))
4216 i = (rx_ring->count - 1);
4217
4218 /* Force memory writes to complete before letting h/w
4219 * know there are new descriptors to fetch. (Only
4220 * applicable for weak-ordered memory model archs,
4221 * such as IA-64). */
4222 wmb();
4223 writel(i, adapter->hw.hw_addr + rx_ring->rdt);
4224 }
4225}
4226
4227/**
4228 * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended
4229 * @adapter: address of board private structure
4230 **/
4231
4232static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
4233 struct e1000_rx_ring *rx_ring,
4234 int cleaned_count)
4235{
4236 struct e1000_hw *hw = &adapter->hw;
4237 struct net_device *netdev = adapter->netdev;
4238 struct pci_dev *pdev = adapter->pdev;
4239 struct e1000_rx_desc *rx_desc;
4240 struct e1000_buffer *buffer_info;
4241 struct sk_buff *skb;
4242 unsigned int i;
4243 unsigned int bufsz = adapter->rx_buffer_len;
4244
4245 i = rx_ring->next_to_use;
4246 buffer_info = &rx_ring->buffer_info[i];
4247
4248 while (cleaned_count--) {
4249 skb = buffer_info->skb;
4250 if (skb) {
4251 skb_trim(skb, 0);
4252 goto map_skb;
4253 }
4254
4255 skb = netdev_alloc_skb_ip_align(netdev, bufsz);
4256 if (unlikely(!skb)) {
4257 /* Better luck next round */
4258 adapter->alloc_rx_buff_failed++;
4259 break;
4260 }
4261
4262 /* Fix for errata 23, can't cross 64kB boundary */
4263 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
4264 struct sk_buff *oldskb = skb;
4265 e_err(rx_err, "skb align check failed: %u bytes at "
4266 "%p\n", bufsz, skb->data);
4267 /* Try again, without freeing the previous */
4268 skb = netdev_alloc_skb_ip_align(netdev, bufsz);
4269 /* Failed allocation, critical failure */
4270 if (!skb) {
4271 dev_kfree_skb(oldskb);
4272 adapter->alloc_rx_buff_failed++;
4273 break;
4274 }
4275
4276 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
4277 /* give up */
4278 dev_kfree_skb(skb);
4279 dev_kfree_skb(oldskb);
4280 adapter->alloc_rx_buff_failed++;
4281 break; /* while !buffer_info->skb */
4282 }
4283
4284 /* Use new allocation */
4285 dev_kfree_skb(oldskb);
4286 }
4287 buffer_info->skb = skb;
4288 buffer_info->length = adapter->rx_buffer_len;
4289map_skb:
4290 buffer_info->dma = dma_map_single(&pdev->dev,
4291 skb->data,
4292 buffer_info->length,
4293 DMA_FROM_DEVICE);
4294 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
4295 dev_kfree_skb(skb);
4296 buffer_info->skb = NULL;
4297 buffer_info->dma = 0;
4298 adapter->alloc_rx_buff_failed++;
4299 break; /* while !buffer_info->skb */
4300 }
4301
4302 /*
4303 * XXX if it was allocated cleanly it will never map to a
4304 * boundary crossing
4305 */
4306
4307 /* Fix for errata 23, can't cross 64kB boundary */
4308 if (!e1000_check_64k_bound(adapter,
4309 (void *)(unsigned long)buffer_info->dma,
4310 adapter->rx_buffer_len)) {
4311 e_err(rx_err, "dma align check failed: %u bytes at "
4312 "%p\n", adapter->rx_buffer_len,
4313 (void *)(unsigned long)buffer_info->dma);
4314 dev_kfree_skb(skb);
4315 buffer_info->skb = NULL;
4316
4317 dma_unmap_single(&pdev->dev, buffer_info->dma,
4318 adapter->rx_buffer_len,
4319 DMA_FROM_DEVICE);
4320 buffer_info->dma = 0;
4321
4322 adapter->alloc_rx_buff_failed++;
4323 break; /* while !buffer_info->skb */
4324 }
4325 rx_desc = E1000_RX_DESC(*rx_ring, i);
4326 rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
4327
4328 if (unlikely(++i == rx_ring->count))
4329 i = 0;
4330 buffer_info = &rx_ring->buffer_info[i];
4331 }
4332
4333 if (likely(rx_ring->next_to_use != i)) {
4334 rx_ring->next_to_use = i;
4335 if (unlikely(i-- == 0))
4336 i = (rx_ring->count - 1);
4337
4338 /* Force memory writes to complete before letting h/w
4339 * know there are new descriptors to fetch. (Only
4340 * applicable for weak-ordered memory model archs,
4341 * such as IA-64). */
4342 wmb();
4343 writel(i, hw->hw_addr + rx_ring->rdt);
4344 }
4345}
4346
4347/**
4348 * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers.
4349 * @adapter:
4350 **/
4351
4352static void e1000_smartspeed(struct e1000_adapter *adapter)
4353{
4354 struct e1000_hw *hw = &adapter->hw;
4355 u16 phy_status;
4356 u16 phy_ctrl;
4357
4358 if ((hw->phy_type != e1000_phy_igp) || !hw->autoneg ||
4359 !(hw->autoneg_advertised & ADVERTISE_1000_FULL))
4360 return;
4361
4362 if (adapter->smartspeed == 0) {
4363 /* If Master/Slave config fault is asserted twice,
4364 * we assume back-to-back */
4365 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status);
4366 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
4367 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status);
4368 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
4369 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl);
4370 if (phy_ctrl & CR_1000T_MS_ENABLE) {
4371 phy_ctrl &= ~CR_1000T_MS_ENABLE;
4372 e1000_write_phy_reg(hw, PHY_1000T_CTRL,
4373 phy_ctrl);
4374 adapter->smartspeed++;
4375 if (!e1000_phy_setup_autoneg(hw) &&
4376 !e1000_read_phy_reg(hw, PHY_CTRL,
4377 &phy_ctrl)) {
4378 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4379 MII_CR_RESTART_AUTO_NEG);
4380 e1000_write_phy_reg(hw, PHY_CTRL,
4381 phy_ctrl);
4382 }
4383 }
4384 return;
4385 } else if (adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) {
4386 /* If still no link, perhaps using 2/3 pair cable */
4387 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl);
4388 phy_ctrl |= CR_1000T_MS_ENABLE;
4389 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl);
4390 if (!e1000_phy_setup_autoneg(hw) &&
4391 !e1000_read_phy_reg(hw, PHY_CTRL, &phy_ctrl)) {
4392 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4393 MII_CR_RESTART_AUTO_NEG);
4394 e1000_write_phy_reg(hw, PHY_CTRL, phy_ctrl);
4395 }
4396 }
4397 /* Restart process after E1000_SMARTSPEED_MAX iterations */
4398 if (adapter->smartspeed++ == E1000_SMARTSPEED_MAX)
4399 adapter->smartspeed = 0;
4400}
4401
4402/**
4403 * e1000_ioctl -
4404 * @netdev:
4405 * @ifreq:
4406 * @cmd:
4407 **/
4408
4409static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4410{
4411 switch (cmd) {
4412 case SIOCGMIIPHY:
4413 case SIOCGMIIREG:
4414 case SIOCSMIIREG:
4415 return e1000_mii_ioctl(netdev, ifr, cmd);
4416 default:
4417 return -EOPNOTSUPP;
4418 }
4419}
4420
4421/**
4422 * e1000_mii_ioctl -
4423 * @netdev:
4424 * @ifreq:
4425 * @cmd:
4426 **/
4427
4428static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
4429 int cmd)
4430{
4431 struct e1000_adapter *adapter = netdev_priv(netdev);
4432 struct e1000_hw *hw = &adapter->hw;
4433 struct mii_ioctl_data *data = if_mii(ifr);
4434 int retval;
4435 u16 mii_reg;
4436 unsigned long flags;
4437
4438 if (hw->media_type != e1000_media_type_copper)
4439 return -EOPNOTSUPP;
4440
4441 switch (cmd) {
4442 case SIOCGMIIPHY:
4443 data->phy_id = hw->phy_addr;
4444 break;
4445 case SIOCGMIIREG:
4446 spin_lock_irqsave(&adapter->stats_lock, flags);
4447 if (e1000_read_phy_reg(hw, data->reg_num & 0x1F,
4448 &data->val_out)) {
4449 spin_unlock_irqrestore(&adapter->stats_lock, flags);
4450 return -EIO;
4451 }
4452 spin_unlock_irqrestore(&adapter->stats_lock, flags);
4453 break;
4454 case SIOCSMIIREG:
4455 if (data->reg_num & ~(0x1F))
4456 return -EFAULT;
4457 mii_reg = data->val_in;
4458 spin_lock_irqsave(&adapter->stats_lock, flags);
4459 if (e1000_write_phy_reg(hw, data->reg_num,
4460 mii_reg)) {
4461 spin_unlock_irqrestore(&adapter->stats_lock, flags);
4462 return -EIO;
4463 }
4464 spin_unlock_irqrestore(&adapter->stats_lock, flags);
4465 if (hw->media_type == e1000_media_type_copper) {
4466 switch (data->reg_num) {
4467 case PHY_CTRL:
4468 if (mii_reg & MII_CR_POWER_DOWN)
4469 break;
4470 if (mii_reg & MII_CR_AUTO_NEG_EN) {
4471 hw->autoneg = 1;
4472 hw->autoneg_advertised = 0x2F;
4473 } else {
4474 u32 speed;
4475 if (mii_reg & 0x40)
4476 speed = SPEED_1000;
4477 else if (mii_reg & 0x2000)
4478 speed = SPEED_100;
4479 else
4480 speed = SPEED_10;
4481 retval = e1000_set_spd_dplx(
4482 adapter, speed,
4483 ((mii_reg & 0x100)
4484 ? DUPLEX_FULL :
4485 DUPLEX_HALF));
4486 if (retval)
4487 return retval;
4488 }
4489 if (netif_running(adapter->netdev))
4490 e1000_reinit_locked(adapter);
4491 else
4492 e1000_reset(adapter);
4493 break;
4494 case M88E1000_PHY_SPEC_CTRL:
4495 case M88E1000_EXT_PHY_SPEC_CTRL:
4496 if (e1000_phy_reset(hw))
4497 return -EIO;
4498 break;
4499 }
4500 } else {
4501 switch (data->reg_num) {
4502 case PHY_CTRL:
4503 if (mii_reg & MII_CR_POWER_DOWN)
4504 break;
4505 if (netif_running(adapter->netdev))
4506 e1000_reinit_locked(adapter);
4507 else
4508 e1000_reset(adapter);
4509 break;
4510 }
4511 }
4512 break;
4513 default:
4514 return -EOPNOTSUPP;
4515 }
4516 return E1000_SUCCESS;
4517}
4518
4519void e1000_pci_set_mwi(struct e1000_hw *hw)
4520{
4521 struct e1000_adapter *adapter = hw->back;
4522 int ret_val = pci_set_mwi(adapter->pdev);
4523
4524 if (ret_val)
4525 e_err(probe, "Error in setting MWI\n");
4526}
4527
4528void e1000_pci_clear_mwi(struct e1000_hw *hw)
4529{
4530 struct e1000_adapter *adapter = hw->back;
4531
4532 pci_clear_mwi(adapter->pdev);
4533}
4534
4535int e1000_pcix_get_mmrbc(struct e1000_hw *hw)
4536{
4537 struct e1000_adapter *adapter = hw->back;
4538 return pcix_get_mmrbc(adapter->pdev);
4539}
4540
4541void e1000_pcix_set_mmrbc(struct e1000_hw *hw, int mmrbc)
4542{
4543 struct e1000_adapter *adapter = hw->back;
4544 pcix_set_mmrbc(adapter->pdev, mmrbc);
4545}
4546
4547void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value)
4548{
4549 outl(value, port);
4550}
4551
4552static bool e1000_vlan_used(struct e1000_adapter *adapter)
4553{
4554 u16 vid;
4555
4556 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
4557 return true;
4558 return false;
4559}
4560
4561static void e1000_vlan_filter_on_off(struct e1000_adapter *adapter,
4562 bool filter_on)
4563{
4564 struct e1000_hw *hw = &adapter->hw;
4565 u32 rctl;
4566
4567 if (!test_bit(__E1000_DOWN, &adapter->flags))
4568 e1000_irq_disable(adapter);
4569
4570 if (filter_on) {
4571 /* enable VLAN receive filtering */
4572 rctl = er32(RCTL);
4573 rctl &= ~E1000_RCTL_CFIEN;
4574 if (!(adapter->netdev->flags & IFF_PROMISC))
4575 rctl |= E1000_RCTL_VFE;
4576 ew32(RCTL, rctl);
4577 e1000_update_mng_vlan(adapter);
4578 } else {
4579 /* disable VLAN receive filtering */
4580 rctl = er32(RCTL);
4581 rctl &= ~E1000_RCTL_VFE;
4582 ew32(RCTL, rctl);
4583 }
4584
4585 if (!test_bit(__E1000_DOWN, &adapter->flags))
4586 e1000_irq_enable(adapter);
4587}
4588
4589static void e1000_vlan_mode(struct net_device *netdev, u32 features)
4590{
4591 struct e1000_adapter *adapter = netdev_priv(netdev);
4592 struct e1000_hw *hw = &adapter->hw;
4593 u32 ctrl;
4594
4595 if (!test_bit(__E1000_DOWN, &adapter->flags))
4596 e1000_irq_disable(adapter);
4597
4598 ctrl = er32(CTRL);
4599 if (features & NETIF_F_HW_VLAN_RX) {
4600 /* enable VLAN tag insert/strip */
4601 ctrl |= E1000_CTRL_VME;
4602 } else {
4603 /* disable VLAN tag insert/strip */
4604 ctrl &= ~E1000_CTRL_VME;
4605 }
4606 ew32(CTRL, ctrl);
4607
4608 if (!test_bit(__E1000_DOWN, &adapter->flags))
4609 e1000_irq_enable(adapter);
4610}
4611
4612static void e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4613{
4614 struct e1000_adapter *adapter = netdev_priv(netdev);
4615 struct e1000_hw *hw = &adapter->hw;
4616 u32 vfta, index;
4617
4618 if ((hw->mng_cookie.status &
4619 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
4620 (vid == adapter->mng_vlan_id))
4621 return;
4622
4623 if (!e1000_vlan_used(adapter))
4624 e1000_vlan_filter_on_off(adapter, true);
4625
4626 /* add VID to filter table */
4627 index = (vid >> 5) & 0x7F;
4628 vfta = E1000_READ_REG_ARRAY(hw, VFTA, index);
4629 vfta |= (1 << (vid & 0x1F));
4630 e1000_write_vfta(hw, index, vfta);
4631
4632 set_bit(vid, adapter->active_vlans);
4633}
4634
4635static void e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4636{
4637 struct e1000_adapter *adapter = netdev_priv(netdev);
4638 struct e1000_hw *hw = &adapter->hw;
4639 u32 vfta, index;
4640
4641 if (!test_bit(__E1000_DOWN, &adapter->flags))
4642 e1000_irq_disable(adapter);
4643 if (!test_bit(__E1000_DOWN, &adapter->flags))
4644 e1000_irq_enable(adapter);
4645
4646 /* remove VID from filter table */
4647 index = (vid >> 5) & 0x7F;
4648 vfta = E1000_READ_REG_ARRAY(hw, VFTA, index);
4649 vfta &= ~(1 << (vid & 0x1F));
4650 e1000_write_vfta(hw, index, vfta);
4651
4652 clear_bit(vid, adapter->active_vlans);
4653
4654 if (!e1000_vlan_used(adapter))
4655 e1000_vlan_filter_on_off(adapter, false);
4656}
4657
4658static void e1000_restore_vlan(struct e1000_adapter *adapter)
4659{
4660 u16 vid;
4661
4662 if (!e1000_vlan_used(adapter))
4663 return;
4664
4665 e1000_vlan_filter_on_off(adapter, true);
4666 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
4667 e1000_vlan_rx_add_vid(adapter->netdev, vid);
4668}
4669
4670int e1000_set_spd_dplx(struct e1000_adapter *adapter, u32 spd, u8 dplx)
4671{
4672 struct e1000_hw *hw = &adapter->hw;
4673
4674 hw->autoneg = 0;
4675
4676 /* Make sure dplx is at most 1 bit and lsb of speed is not set
4677 * for the switch() below to work */
4678 if ((spd & 1) || (dplx & ~1))
4679 goto err_inval;
4680
4681 /* Fiber NICs only allow 1000 gbps Full duplex */
4682 if ((hw->media_type == e1000_media_type_fiber) &&
4683 spd != SPEED_1000 &&
4684 dplx != DUPLEX_FULL)
4685 goto err_inval;
4686
4687 switch (spd + dplx) {
4688 case SPEED_10 + DUPLEX_HALF:
4689 hw->forced_speed_duplex = e1000_10_half;
4690 break;
4691 case SPEED_10 + DUPLEX_FULL:
4692 hw->forced_speed_duplex = e1000_10_full;
4693 break;
4694 case SPEED_100 + DUPLEX_HALF:
4695 hw->forced_speed_duplex = e1000_100_half;
4696 break;
4697 case SPEED_100 + DUPLEX_FULL:
4698 hw->forced_speed_duplex = e1000_100_full;
4699 break;
4700 case SPEED_1000 + DUPLEX_FULL:
4701 hw->autoneg = 1;
4702 hw->autoneg_advertised = ADVERTISE_1000_FULL;
4703 break;
4704 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4705 default:
4706 goto err_inval;
4707 }
4708 return 0;
4709
4710err_inval:
4711 e_err(probe, "Unsupported Speed/Duplex configuration\n");
4712 return -EINVAL;
4713}
4714
4715static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake)
4716{
4717 struct net_device *netdev = pci_get_drvdata(pdev);
4718 struct e1000_adapter *adapter = netdev_priv(netdev);
4719 struct e1000_hw *hw = &adapter->hw;
4720 u32 ctrl, ctrl_ext, rctl, status;
4721 u32 wufc = adapter->wol;
4722#ifdef CONFIG_PM
4723 int retval = 0;
4724#endif
4725
4726 netif_device_detach(netdev);
4727
4728 if (netif_running(netdev)) {
4729 WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags));
4730 e1000_down(adapter);
4731 }
4732
4733#ifdef CONFIG_PM
4734 retval = pci_save_state(pdev);
4735 if (retval)
4736 return retval;
4737#endif
4738
4739 status = er32(STATUS);
4740 if (status & E1000_STATUS_LU)
4741 wufc &= ~E1000_WUFC_LNKC;
4742
4743 if (wufc) {
4744 e1000_setup_rctl(adapter);
4745 e1000_set_rx_mode(netdev);
4746
4747 /* turn on all-multi mode if wake on multicast is enabled */
4748 if (wufc & E1000_WUFC_MC) {
4749 rctl = er32(RCTL);
4750 rctl |= E1000_RCTL_MPE;
4751 ew32(RCTL, rctl);
4752 }
4753
4754 if (hw->mac_type >= e1000_82540) {
4755 ctrl = er32(CTRL);
4756 /* advertise wake from D3Cold */
4757 #define E1000_CTRL_ADVD3WUC 0x00100000
4758 /* phy power management enable */
4759 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4760 ctrl |= E1000_CTRL_ADVD3WUC |
4761 E1000_CTRL_EN_PHY_PWR_MGMT;
4762 ew32(CTRL, ctrl);
4763 }
4764
4765 if (hw->media_type == e1000_media_type_fiber ||
4766 hw->media_type == e1000_media_type_internal_serdes) {
4767 /* keep the laser running in D3 */
4768 ctrl_ext = er32(CTRL_EXT);
4769 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
4770 ew32(CTRL_EXT, ctrl_ext);
4771 }
4772
4773 ew32(WUC, E1000_WUC_PME_EN);
4774 ew32(WUFC, wufc);
4775 } else {
4776 ew32(WUC, 0);
4777 ew32(WUFC, 0);
4778 }
4779
4780 e1000_release_manageability(adapter);
4781
4782 *enable_wake = !!wufc;
4783
4784 /* make sure adapter isn't asleep if manageability is enabled */
4785 if (adapter->en_mng_pt)
4786 *enable_wake = true;
4787
4788 if (netif_running(netdev))
4789 e1000_free_irq(adapter);
4790
4791 pci_disable_device(pdev);
4792
4793 return 0;
4794}
4795
4796#ifdef CONFIG_PM
4797static int e1000_suspend(struct pci_dev *pdev, pm_message_t state)
4798{
4799 int retval;
4800 bool wake;
4801
4802 retval = __e1000_shutdown(pdev, &wake);
4803 if (retval)
4804 return retval;
4805
4806 if (wake) {
4807 pci_prepare_to_sleep(pdev);
4808 } else {
4809 pci_wake_from_d3(pdev, false);
4810 pci_set_power_state(pdev, PCI_D3hot);
4811 }
4812
4813 return 0;
4814}
4815
4816static int e1000_resume(struct pci_dev *pdev)
4817{
4818 struct net_device *netdev = pci_get_drvdata(pdev);
4819 struct e1000_adapter *adapter = netdev_priv(netdev);
4820 struct e1000_hw *hw = &adapter->hw;
4821 u32 err;
4822
4823 pci_set_power_state(pdev, PCI_D0);
4824 pci_restore_state(pdev);
4825 pci_save_state(pdev);
4826
4827 if (adapter->need_ioport)
4828 err = pci_enable_device(pdev);
4829 else
4830 err = pci_enable_device_mem(pdev);
4831 if (err) {
4832 pr_err("Cannot enable PCI device from suspend\n");
4833 return err;
4834 }
4835 pci_set_master(pdev);
4836
4837 pci_enable_wake(pdev, PCI_D3hot, 0);
4838 pci_enable_wake(pdev, PCI_D3cold, 0);
4839
4840 if (netif_running(netdev)) {
4841 err = e1000_request_irq(adapter);
4842 if (err)
4843 return err;
4844 }
4845
4846 e1000_power_up_phy(adapter);
4847 e1000_reset(adapter);
4848 ew32(WUS, ~0);
4849
4850 e1000_init_manageability(adapter);
4851
4852 if (netif_running(netdev))
4853 e1000_up(adapter);
4854
4855 netif_device_attach(netdev);
4856
4857 return 0;
4858}
4859#endif
4860
4861static void e1000_shutdown(struct pci_dev *pdev)
4862{
4863 bool wake;
4864
4865 __e1000_shutdown(pdev, &wake);
4866
4867 if (system_state == SYSTEM_POWER_OFF) {
4868 pci_wake_from_d3(pdev, wake);
4869 pci_set_power_state(pdev, PCI_D3hot);
4870 }
4871}
4872
4873#ifdef CONFIG_NET_POLL_CONTROLLER
4874/*
4875 * Polling 'interrupt' - used by things like netconsole to send skbs
4876 * without having to re-enable interrupts. It's not called while
4877 * the interrupt routine is executing.
4878 */
4879static void e1000_netpoll(struct net_device *netdev)
4880{
4881 struct e1000_adapter *adapter = netdev_priv(netdev);
4882
4883 disable_irq(adapter->pdev->irq);
4884 e1000_intr(adapter->pdev->irq, netdev);
4885 enable_irq(adapter->pdev->irq);
4886}
4887#endif
4888
4889/**
4890 * e1000_io_error_detected - called when PCI error is detected
4891 * @pdev: Pointer to PCI device
4892 * @state: The current pci connection state
4893 *
4894 * This function is called after a PCI bus error affecting
4895 * this device has been detected.
4896 */
4897static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
4898 pci_channel_state_t state)
4899{
4900 struct net_device *netdev = pci_get_drvdata(pdev);
4901 struct e1000_adapter *adapter = netdev_priv(netdev);
4902
4903 netif_device_detach(netdev);
4904
4905 if (state == pci_channel_io_perm_failure)
4906 return PCI_ERS_RESULT_DISCONNECT;
4907
4908 if (netif_running(netdev))
4909 e1000_down(adapter);
4910 pci_disable_device(pdev);
4911
4912 /* Request a slot slot reset. */
4913 return PCI_ERS_RESULT_NEED_RESET;
4914}
4915
4916/**
4917 * e1000_io_slot_reset - called after the pci bus has been reset.
4918 * @pdev: Pointer to PCI device
4919 *
4920 * Restart the card from scratch, as if from a cold-boot. Implementation
4921 * resembles the first-half of the e1000_resume routine.
4922 */
4923static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
4924{
4925 struct net_device *netdev = pci_get_drvdata(pdev);
4926 struct e1000_adapter *adapter = netdev_priv(netdev);
4927 struct e1000_hw *hw = &adapter->hw;
4928 int err;
4929
4930 if (adapter->need_ioport)
4931 err = pci_enable_device(pdev);
4932 else
4933 err = pci_enable_device_mem(pdev);
4934 if (err) {
4935 pr_err("Cannot re-enable PCI device after reset.\n");
4936 return PCI_ERS_RESULT_DISCONNECT;
4937 }
4938 pci_set_master(pdev);
4939
4940 pci_enable_wake(pdev, PCI_D3hot, 0);
4941 pci_enable_wake(pdev, PCI_D3cold, 0);
4942
4943 e1000_reset(adapter);
4944 ew32(WUS, ~0);
4945
4946 return PCI_ERS_RESULT_RECOVERED;
4947}
4948
4949/**
4950 * e1000_io_resume - called when traffic can start flowing again.
4951 * @pdev: Pointer to PCI device
4952 *
4953 * This callback is called when the error recovery driver tells us that
4954 * its OK to resume normal operation. Implementation resembles the
4955 * second-half of the e1000_resume routine.
4956 */
4957static void e1000_io_resume(struct pci_dev *pdev)
4958{
4959 struct net_device *netdev = pci_get_drvdata(pdev);
4960 struct e1000_adapter *adapter = netdev_priv(netdev);
4961
4962 e1000_init_manageability(adapter);
4963
4964 if (netif_running(netdev)) {
4965 if (e1000_up(adapter)) {
4966 pr_info("can't bring device back up after reset\n");
4967 return;
4968 }
4969 }
4970
4971 netif_device_attach(netdev);
4972}
4973
4974/* e1000_main.c */
diff --git a/drivers/net/ethernet/intel/e1000/e1000_osdep.h b/drivers/net/ethernet/intel/e1000/e1000_osdep.h
new file mode 100644
index 000000000000..33e7c45a4fe4
--- /dev/null
+++ b/drivers/net/ethernet/intel/e1000/e1000_osdep.h
@@ -0,0 +1,109 @@
1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29
30/* glue for the OS independent part of e1000
31 * includes register access macros
32 */
33
34#ifndef _E1000_OSDEP_H_
35#define _E1000_OSDEP_H_
36
37#include <asm/io.h>
38
39#define CONFIG_RAM_BASE 0x60000
40#define GBE_CONFIG_OFFSET 0x0
41
42#define GBE_CONFIG_RAM_BASE \
43 ((unsigned int)(CONFIG_RAM_BASE + GBE_CONFIG_OFFSET))
44
45#define GBE_CONFIG_BASE_VIRT \
46 ((void __iomem *)phys_to_virt(GBE_CONFIG_RAM_BASE))
47
48#define GBE_CONFIG_FLASH_WRITE(base, offset, count, data) \
49 (iowrite16_rep(base + offset, data, count))
50
51#define GBE_CONFIG_FLASH_READ(base, offset, count, data) \
52 (ioread16_rep(base + (offset << 1), data, count))
53
54#define er32(reg) \
55 (readl(hw->hw_addr + ((hw->mac_type >= e1000_82543) \
56 ? E1000_##reg : E1000_82542_##reg)))
57
58#define ew32(reg, value) \
59 (writel((value), (hw->hw_addr + ((hw->mac_type >= e1000_82543) \
60 ? E1000_##reg : E1000_82542_##reg))))
61
62#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
63 writel((value), ((a)->hw_addr + \
64 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
65 ((offset) << 2))))
66
67#define E1000_READ_REG_ARRAY(a, reg, offset) ( \
68 readl((a)->hw_addr + \
69 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
70 ((offset) << 2)))
71
72#define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
73#define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
74
75#define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \
76 writew((value), ((a)->hw_addr + \
77 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
78 ((offset) << 1))))
79
80#define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \
81 readw((a)->hw_addr + \
82 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
83 ((offset) << 1)))
84
85#define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \
86 writeb((value), ((a)->hw_addr + \
87 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
88 (offset))))
89
90#define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \
91 readb((a)->hw_addr + \
92 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
93 (offset)))
94
95#define E1000_WRITE_FLUSH() er32(STATUS)
96
97#define E1000_WRITE_ICH_FLASH_REG(a, reg, value) ( \
98 writel((value), ((a)->flash_address + reg)))
99
100#define E1000_READ_ICH_FLASH_REG(a, reg) ( \
101 readl((a)->flash_address + reg))
102
103#define E1000_WRITE_ICH_FLASH_REG16(a, reg, value) ( \
104 writew((value), ((a)->flash_address + reg)))
105
106#define E1000_READ_ICH_FLASH_REG16(a, reg) ( \
107 readw((a)->flash_address + reg))
108
109#endif /* _E1000_OSDEP_H_ */
diff --git a/drivers/net/ethernet/intel/e1000/e1000_param.c b/drivers/net/ethernet/intel/e1000/e1000_param.c
new file mode 100644
index 000000000000..1301eba8b57a
--- /dev/null
+++ b/drivers/net/ethernet/intel/e1000/e1000_param.c
@@ -0,0 +1,755 @@
1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include "e1000.h"
30
31/* This is the only thing that needs to be changed to adjust the
32 * maximum number of ports that the driver can manage.
33 */
34
35#define E1000_MAX_NIC 32
36
37#define OPTION_UNSET -1
38#define OPTION_DISABLED 0
39#define OPTION_ENABLED 1
40
41/* All parameters are treated the same, as an integer array of values.
42 * This macro just reduces the need to repeat the same declaration code
43 * over and over (plus this helps to avoid typo bugs).
44 */
45
46#define E1000_PARAM_INIT { [0 ... E1000_MAX_NIC] = OPTION_UNSET }
47#define E1000_PARAM(X, desc) \
48 static int __devinitdata X[E1000_MAX_NIC+1] = E1000_PARAM_INIT; \
49 static unsigned int num_##X; \
50 module_param_array_named(X, X, int, &num_##X, 0); \
51 MODULE_PARM_DESC(X, desc);
52
53/* Transmit Descriptor Count
54 *
55 * Valid Range: 80-256 for 82542 and 82543 gigabit ethernet controllers
56 * Valid Range: 80-4096 for 82544 and newer
57 *
58 * Default Value: 256
59 */
60E1000_PARAM(TxDescriptors, "Number of transmit descriptors");
61
62/* Receive Descriptor Count
63 *
64 * Valid Range: 80-256 for 82542 and 82543 gigabit ethernet controllers
65 * Valid Range: 80-4096 for 82544 and newer
66 *
67 * Default Value: 256
68 */
69E1000_PARAM(RxDescriptors, "Number of receive descriptors");
70
71/* User Specified Speed Override
72 *
73 * Valid Range: 0, 10, 100, 1000
74 * - 0 - auto-negotiate at all supported speeds
75 * - 10 - only link at 10 Mbps
76 * - 100 - only link at 100 Mbps
77 * - 1000 - only link at 1000 Mbps
78 *
79 * Default Value: 0
80 */
81E1000_PARAM(Speed, "Speed setting");
82
83/* User Specified Duplex Override
84 *
85 * Valid Range: 0-2
86 * - 0 - auto-negotiate for duplex
87 * - 1 - only link at half duplex
88 * - 2 - only link at full duplex
89 *
90 * Default Value: 0
91 */
92E1000_PARAM(Duplex, "Duplex setting");
93
94/* Auto-negotiation Advertisement Override
95 *
96 * Valid Range: 0x01-0x0F, 0x20-0x2F (copper); 0x20 (fiber)
97 *
98 * The AutoNeg value is a bit mask describing which speed and duplex
99 * combinations should be advertised during auto-negotiation.
100 * The supported speed and duplex modes are listed below
101 *
102 * Bit 7 6 5 4 3 2 1 0
103 * Speed (Mbps) N/A N/A 1000 N/A 100 100 10 10
104 * Duplex Full Full Half Full Half
105 *
106 * Default Value: 0x2F (copper); 0x20 (fiber)
107 */
108E1000_PARAM(AutoNeg, "Advertised auto-negotiation setting");
109#define AUTONEG_ADV_DEFAULT 0x2F
110#define AUTONEG_ADV_MASK 0x2F
111
112/* User Specified Flow Control Override
113 *
114 * Valid Range: 0-3
115 * - 0 - No Flow Control
116 * - 1 - Rx only, respond to PAUSE frames but do not generate them
117 * - 2 - Tx only, generate PAUSE frames but ignore them on receive
118 * - 3 - Full Flow Control Support
119 *
120 * Default Value: Read flow control settings from the EEPROM
121 */
122E1000_PARAM(FlowControl, "Flow Control setting");
123#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
124
125/* XsumRX - Receive Checksum Offload Enable/Disable
126 *
127 * Valid Range: 0, 1
128 * - 0 - disables all checksum offload
129 * - 1 - enables receive IP/TCP/UDP checksum offload
130 * on 82543 and newer -based NICs
131 *
132 * Default Value: 1
133 */
134E1000_PARAM(XsumRX, "Disable or enable Receive Checksum offload");
135
136/* Transmit Interrupt Delay in units of 1.024 microseconds
137 * Tx interrupt delay needs to typically be set to something non zero
138 *
139 * Valid Range: 0-65535
140 */
141E1000_PARAM(TxIntDelay, "Transmit Interrupt Delay");
142#define DEFAULT_TIDV 8
143#define MAX_TXDELAY 0xFFFF
144#define MIN_TXDELAY 0
145
146/* Transmit Absolute Interrupt Delay in units of 1.024 microseconds
147 *
148 * Valid Range: 0-65535
149 */
150E1000_PARAM(TxAbsIntDelay, "Transmit Absolute Interrupt Delay");
151#define DEFAULT_TADV 32
152#define MAX_TXABSDELAY 0xFFFF
153#define MIN_TXABSDELAY 0
154
155/* Receive Interrupt Delay in units of 1.024 microseconds
156 * hardware will likely hang if you set this to anything but zero.
157 *
158 * Valid Range: 0-65535
159 */
160E1000_PARAM(RxIntDelay, "Receive Interrupt Delay");
161#define DEFAULT_RDTR 0
162#define MAX_RXDELAY 0xFFFF
163#define MIN_RXDELAY 0
164
165/* Receive Absolute Interrupt Delay in units of 1.024 microseconds
166 *
167 * Valid Range: 0-65535
168 */
169E1000_PARAM(RxAbsIntDelay, "Receive Absolute Interrupt Delay");
170#define DEFAULT_RADV 8
171#define MAX_RXABSDELAY 0xFFFF
172#define MIN_RXABSDELAY 0
173
174/* Interrupt Throttle Rate (interrupts/sec)
175 *
176 * Valid Range: 100-100000 (0=off, 1=dynamic, 3=dynamic conservative)
177 */
178E1000_PARAM(InterruptThrottleRate, "Interrupt Throttling Rate");
179#define DEFAULT_ITR 3
180#define MAX_ITR 100000
181#define MIN_ITR 100
182
183/* Enable Smart Power Down of the PHY
184 *
185 * Valid Range: 0, 1
186 *
187 * Default Value: 0 (disabled)
188 */
189E1000_PARAM(SmartPowerDownEnable, "Enable PHY smart power down");
190
191struct e1000_option {
192 enum { enable_option, range_option, list_option } type;
193 const char *name;
194 const char *err;
195 int def;
196 union {
197 struct { /* range_option info */
198 int min;
199 int max;
200 } r;
201 struct { /* list_option info */
202 int nr;
203 const struct e1000_opt_list { int i; char *str; } *p;
204 } l;
205 } arg;
206};
207
208static int __devinit e1000_validate_option(unsigned int *value,
209 const struct e1000_option *opt,
210 struct e1000_adapter *adapter)
211{
212 if (*value == OPTION_UNSET) {
213 *value = opt->def;
214 return 0;
215 }
216
217 switch (opt->type) {
218 case enable_option:
219 switch (*value) {
220 case OPTION_ENABLED:
221 e_dev_info("%s Enabled\n", opt->name);
222 return 0;
223 case OPTION_DISABLED:
224 e_dev_info("%s Disabled\n", opt->name);
225 return 0;
226 }
227 break;
228 case range_option:
229 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
230 e_dev_info("%s set to %i\n", opt->name, *value);
231 return 0;
232 }
233 break;
234 case list_option: {
235 int i;
236 const struct e1000_opt_list *ent;
237
238 for (i = 0; i < opt->arg.l.nr; i++) {
239 ent = &opt->arg.l.p[i];
240 if (*value == ent->i) {
241 if (ent->str[0] != '\0')
242 e_dev_info("%s\n", ent->str);
243 return 0;
244 }
245 }
246 }
247 break;
248 default:
249 BUG();
250 }
251
252 e_dev_info("Invalid %s value specified (%i) %s\n",
253 opt->name, *value, opt->err);
254 *value = opt->def;
255 return -1;
256}
257
258static void e1000_check_fiber_options(struct e1000_adapter *adapter);
259static void e1000_check_copper_options(struct e1000_adapter *adapter);
260
261/**
262 * e1000_check_options - Range Checking for Command Line Parameters
263 * @adapter: board private structure
264 *
265 * This routine checks all command line parameters for valid user
266 * input. If an invalid value is given, or if no user specified
267 * value exists, a default value is used. The final value is stored
268 * in a variable in the adapter structure.
269 **/
270
271void __devinit e1000_check_options(struct e1000_adapter *adapter)
272{
273 struct e1000_option opt;
274 int bd = adapter->bd_number;
275
276 if (bd >= E1000_MAX_NIC) {
277 e_dev_warn("Warning: no configuration for board #%i "
278 "using defaults for all values\n", bd);
279 }
280
281 { /* Transmit Descriptor Count */
282 struct e1000_tx_ring *tx_ring = adapter->tx_ring;
283 int i;
284 e1000_mac_type mac_type = adapter->hw.mac_type;
285
286 opt = (struct e1000_option) {
287 .type = range_option,
288 .name = "Transmit Descriptors",
289 .err = "using default of "
290 __MODULE_STRING(E1000_DEFAULT_TXD),
291 .def = E1000_DEFAULT_TXD,
292 .arg = { .r = {
293 .min = E1000_MIN_TXD,
294 .max = mac_type < e1000_82544 ? E1000_MAX_TXD : E1000_MAX_82544_TXD
295 }}
296 };
297
298 if (num_TxDescriptors > bd) {
299 tx_ring->count = TxDescriptors[bd];
300 e1000_validate_option(&tx_ring->count, &opt, adapter);
301 tx_ring->count = ALIGN(tx_ring->count,
302 REQ_TX_DESCRIPTOR_MULTIPLE);
303 } else {
304 tx_ring->count = opt.def;
305 }
306 for (i = 0; i < adapter->num_tx_queues; i++)
307 tx_ring[i].count = tx_ring->count;
308 }
309 { /* Receive Descriptor Count */
310 struct e1000_rx_ring *rx_ring = adapter->rx_ring;
311 int i;
312 e1000_mac_type mac_type = adapter->hw.mac_type;
313
314 opt = (struct e1000_option) {
315 .type = range_option,
316 .name = "Receive Descriptors",
317 .err = "using default of "
318 __MODULE_STRING(E1000_DEFAULT_RXD),
319 .def = E1000_DEFAULT_RXD,
320 .arg = { .r = {
321 .min = E1000_MIN_RXD,
322 .max = mac_type < e1000_82544 ? E1000_MAX_RXD : E1000_MAX_82544_RXD
323 }}
324 };
325
326 if (num_RxDescriptors > bd) {
327 rx_ring->count = RxDescriptors[bd];
328 e1000_validate_option(&rx_ring->count, &opt, adapter);
329 rx_ring->count = ALIGN(rx_ring->count,
330 REQ_RX_DESCRIPTOR_MULTIPLE);
331 } else {
332 rx_ring->count = opt.def;
333 }
334 for (i = 0; i < adapter->num_rx_queues; i++)
335 rx_ring[i].count = rx_ring->count;
336 }
337 { /* Checksum Offload Enable/Disable */
338 opt = (struct e1000_option) {
339 .type = enable_option,
340 .name = "Checksum Offload",
341 .err = "defaulting to Enabled",
342 .def = OPTION_ENABLED
343 };
344
345 if (num_XsumRX > bd) {
346 unsigned int rx_csum = XsumRX[bd];
347 e1000_validate_option(&rx_csum, &opt, adapter);
348 adapter->rx_csum = rx_csum;
349 } else {
350 adapter->rx_csum = opt.def;
351 }
352 }
353 { /* Flow Control */
354
355 static const struct e1000_opt_list fc_list[] = {
356 { E1000_FC_NONE, "Flow Control Disabled" },
357 { E1000_FC_RX_PAUSE, "Flow Control Receive Only" },
358 { E1000_FC_TX_PAUSE, "Flow Control Transmit Only" },
359 { E1000_FC_FULL, "Flow Control Enabled" },
360 { E1000_FC_DEFAULT, "Flow Control Hardware Default" }
361 };
362
363 opt = (struct e1000_option) {
364 .type = list_option,
365 .name = "Flow Control",
366 .err = "reading default settings from EEPROM",
367 .def = E1000_FC_DEFAULT,
368 .arg = { .l = { .nr = ARRAY_SIZE(fc_list),
369 .p = fc_list }}
370 };
371
372 if (num_FlowControl > bd) {
373 unsigned int fc = FlowControl[bd];
374 e1000_validate_option(&fc, &opt, adapter);
375 adapter->hw.fc = adapter->hw.original_fc = fc;
376 } else {
377 adapter->hw.fc = adapter->hw.original_fc = opt.def;
378 }
379 }
380 { /* Transmit Interrupt Delay */
381 opt = (struct e1000_option) {
382 .type = range_option,
383 .name = "Transmit Interrupt Delay",
384 .err = "using default of " __MODULE_STRING(DEFAULT_TIDV),
385 .def = DEFAULT_TIDV,
386 .arg = { .r = { .min = MIN_TXDELAY,
387 .max = MAX_TXDELAY }}
388 };
389
390 if (num_TxIntDelay > bd) {
391 adapter->tx_int_delay = TxIntDelay[bd];
392 e1000_validate_option(&adapter->tx_int_delay, &opt,
393 adapter);
394 } else {
395 adapter->tx_int_delay = opt.def;
396 }
397 }
398 { /* Transmit Absolute Interrupt Delay */
399 opt = (struct e1000_option) {
400 .type = range_option,
401 .name = "Transmit Absolute Interrupt Delay",
402 .err = "using default of " __MODULE_STRING(DEFAULT_TADV),
403 .def = DEFAULT_TADV,
404 .arg = { .r = { .min = MIN_TXABSDELAY,
405 .max = MAX_TXABSDELAY }}
406 };
407
408 if (num_TxAbsIntDelay > bd) {
409 adapter->tx_abs_int_delay = TxAbsIntDelay[bd];
410 e1000_validate_option(&adapter->tx_abs_int_delay, &opt,
411 adapter);
412 } else {
413 adapter->tx_abs_int_delay = opt.def;
414 }
415 }
416 { /* Receive Interrupt Delay */
417 opt = (struct e1000_option) {
418 .type = range_option,
419 .name = "Receive Interrupt Delay",
420 .err = "using default of " __MODULE_STRING(DEFAULT_RDTR),
421 .def = DEFAULT_RDTR,
422 .arg = { .r = { .min = MIN_RXDELAY,
423 .max = MAX_RXDELAY }}
424 };
425
426 if (num_RxIntDelay > bd) {
427 adapter->rx_int_delay = RxIntDelay[bd];
428 e1000_validate_option(&adapter->rx_int_delay, &opt,
429 adapter);
430 } else {
431 adapter->rx_int_delay = opt.def;
432 }
433 }
434 { /* Receive Absolute Interrupt Delay */
435 opt = (struct e1000_option) {
436 .type = range_option,
437 .name = "Receive Absolute Interrupt Delay",
438 .err = "using default of " __MODULE_STRING(DEFAULT_RADV),
439 .def = DEFAULT_RADV,
440 .arg = { .r = { .min = MIN_RXABSDELAY,
441 .max = MAX_RXABSDELAY }}
442 };
443
444 if (num_RxAbsIntDelay > bd) {
445 adapter->rx_abs_int_delay = RxAbsIntDelay[bd];
446 e1000_validate_option(&adapter->rx_abs_int_delay, &opt,
447 adapter);
448 } else {
449 adapter->rx_abs_int_delay = opt.def;
450 }
451 }
452 { /* Interrupt Throttling Rate */
453 opt = (struct e1000_option) {
454 .type = range_option,
455 .name = "Interrupt Throttling Rate (ints/sec)",
456 .err = "using default of " __MODULE_STRING(DEFAULT_ITR),
457 .def = DEFAULT_ITR,
458 .arg = { .r = { .min = MIN_ITR,
459 .max = MAX_ITR }}
460 };
461
462 if (num_InterruptThrottleRate > bd) {
463 adapter->itr = InterruptThrottleRate[bd];
464 switch (adapter->itr) {
465 case 0:
466 e_dev_info("%s turned off\n", opt.name);
467 break;
468 case 1:
469 e_dev_info("%s set to dynamic mode\n",
470 opt.name);
471 adapter->itr_setting = adapter->itr;
472 adapter->itr = 20000;
473 break;
474 case 3:
475 e_dev_info("%s set to dynamic conservative "
476 "mode\n", opt.name);
477 adapter->itr_setting = adapter->itr;
478 adapter->itr = 20000;
479 break;
480 case 4:
481 e_dev_info("%s set to simplified "
482 "(2000-8000) ints mode\n", opt.name);
483 adapter->itr_setting = adapter->itr;
484 break;
485 default:
486 e1000_validate_option(&adapter->itr, &opt,
487 adapter);
488 /* save the setting, because the dynamic bits
489 * change itr.
490 * clear the lower two bits because they are
491 * used as control */
492 adapter->itr_setting = adapter->itr & ~3;
493 break;
494 }
495 } else {
496 adapter->itr_setting = opt.def;
497 adapter->itr = 20000;
498 }
499 }
500 { /* Smart Power Down */
501 opt = (struct e1000_option) {
502 .type = enable_option,
503 .name = "PHY Smart Power Down",
504 .err = "defaulting to Disabled",
505 .def = OPTION_DISABLED
506 };
507
508 if (num_SmartPowerDownEnable > bd) {
509 unsigned int spd = SmartPowerDownEnable[bd];
510 e1000_validate_option(&spd, &opt, adapter);
511 adapter->smart_power_down = spd;
512 } else {
513 adapter->smart_power_down = opt.def;
514 }
515 }
516
517 switch (adapter->hw.media_type) {
518 case e1000_media_type_fiber:
519 case e1000_media_type_internal_serdes:
520 e1000_check_fiber_options(adapter);
521 break;
522 case e1000_media_type_copper:
523 e1000_check_copper_options(adapter);
524 break;
525 default:
526 BUG();
527 }
528}
529
530/**
531 * e1000_check_fiber_options - Range Checking for Link Options, Fiber Version
532 * @adapter: board private structure
533 *
534 * Handles speed and duplex options on fiber adapters
535 **/
536
537static void __devinit e1000_check_fiber_options(struct e1000_adapter *adapter)
538{
539 int bd = adapter->bd_number;
540 if (num_Speed > bd) {
541 e_dev_info("Speed not valid for fiber adapters, parameter "
542 "ignored\n");
543 }
544
545 if (num_Duplex > bd) {
546 e_dev_info("Duplex not valid for fiber adapters, parameter "
547 "ignored\n");
548 }
549
550 if ((num_AutoNeg > bd) && (AutoNeg[bd] != 0x20)) {
551 e_dev_info("AutoNeg other than 1000/Full is not valid for fiber"
552 "adapters, parameter ignored\n");
553 }
554}
555
556/**
557 * e1000_check_copper_options - Range Checking for Link Options, Copper Version
558 * @adapter: board private structure
559 *
560 * Handles speed and duplex options on copper adapters
561 **/
562
563static void __devinit e1000_check_copper_options(struct e1000_adapter *adapter)
564{
565 struct e1000_option opt;
566 unsigned int speed, dplx, an;
567 int bd = adapter->bd_number;
568
569 { /* Speed */
570 static const struct e1000_opt_list speed_list[] = {
571 { 0, "" },
572 { SPEED_10, "" },
573 { SPEED_100, "" },
574 { SPEED_1000, "" }};
575
576 opt = (struct e1000_option) {
577 .type = list_option,
578 .name = "Speed",
579 .err = "parameter ignored",
580 .def = 0,
581 .arg = { .l = { .nr = ARRAY_SIZE(speed_list),
582 .p = speed_list }}
583 };
584
585 if (num_Speed > bd) {
586 speed = Speed[bd];
587 e1000_validate_option(&speed, &opt, adapter);
588 } else {
589 speed = opt.def;
590 }
591 }
592 { /* Duplex */
593 static const struct e1000_opt_list dplx_list[] = {
594 { 0, "" },
595 { HALF_DUPLEX, "" },
596 { FULL_DUPLEX, "" }};
597
598 opt = (struct e1000_option) {
599 .type = list_option,
600 .name = "Duplex",
601 .err = "parameter ignored",
602 .def = 0,
603 .arg = { .l = { .nr = ARRAY_SIZE(dplx_list),
604 .p = dplx_list }}
605 };
606
607 if (num_Duplex > bd) {
608 dplx = Duplex[bd];
609 e1000_validate_option(&dplx, &opt, adapter);
610 } else {
611 dplx = opt.def;
612 }
613 }
614
615 if ((num_AutoNeg > bd) && (speed != 0 || dplx != 0)) {
616 e_dev_info("AutoNeg specified along with Speed or Duplex, "
617 "parameter ignored\n");
618 adapter->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT;
619 } else { /* Autoneg */
620 static const struct e1000_opt_list an_list[] =
621 #define AA "AutoNeg advertising "
622 {{ 0x01, AA "10/HD" },
623 { 0x02, AA "10/FD" },
624 { 0x03, AA "10/FD, 10/HD" },
625 { 0x04, AA "100/HD" },
626 { 0x05, AA "100/HD, 10/HD" },
627 { 0x06, AA "100/HD, 10/FD" },
628 { 0x07, AA "100/HD, 10/FD, 10/HD" },
629 { 0x08, AA "100/FD" },
630 { 0x09, AA "100/FD, 10/HD" },
631 { 0x0a, AA "100/FD, 10/FD" },
632 { 0x0b, AA "100/FD, 10/FD, 10/HD" },
633 { 0x0c, AA "100/FD, 100/HD" },
634 { 0x0d, AA "100/FD, 100/HD, 10/HD" },
635 { 0x0e, AA "100/FD, 100/HD, 10/FD" },
636 { 0x0f, AA "100/FD, 100/HD, 10/FD, 10/HD" },
637 { 0x20, AA "1000/FD" },
638 { 0x21, AA "1000/FD, 10/HD" },
639 { 0x22, AA "1000/FD, 10/FD" },
640 { 0x23, AA "1000/FD, 10/FD, 10/HD" },
641 { 0x24, AA "1000/FD, 100/HD" },
642 { 0x25, AA "1000/FD, 100/HD, 10/HD" },
643 { 0x26, AA "1000/FD, 100/HD, 10/FD" },
644 { 0x27, AA "1000/FD, 100/HD, 10/FD, 10/HD" },
645 { 0x28, AA "1000/FD, 100/FD" },
646 { 0x29, AA "1000/FD, 100/FD, 10/HD" },
647 { 0x2a, AA "1000/FD, 100/FD, 10/FD" },
648 { 0x2b, AA "1000/FD, 100/FD, 10/FD, 10/HD" },
649 { 0x2c, AA "1000/FD, 100/FD, 100/HD" },
650 { 0x2d, AA "1000/FD, 100/FD, 100/HD, 10/HD" },
651 { 0x2e, AA "1000/FD, 100/FD, 100/HD, 10/FD" },
652 { 0x2f, AA "1000/FD, 100/FD, 100/HD, 10/FD, 10/HD" }};
653
654 opt = (struct e1000_option) {
655 .type = list_option,
656 .name = "AutoNeg",
657 .err = "parameter ignored",
658 .def = AUTONEG_ADV_DEFAULT,
659 .arg = { .l = { .nr = ARRAY_SIZE(an_list),
660 .p = an_list }}
661 };
662
663 if (num_AutoNeg > bd) {
664 an = AutoNeg[bd];
665 e1000_validate_option(&an, &opt, adapter);
666 } else {
667 an = opt.def;
668 }
669 adapter->hw.autoneg_advertised = an;
670 }
671
672 switch (speed + dplx) {
673 case 0:
674 adapter->hw.autoneg = adapter->fc_autoneg = 1;
675 if ((num_Speed > bd) && (speed != 0 || dplx != 0))
676 e_dev_info("Speed and duplex autonegotiation "
677 "enabled\n");
678 break;
679 case HALF_DUPLEX:
680 e_dev_info("Half Duplex specified without Speed\n");
681 e_dev_info("Using Autonegotiation at Half Duplex only\n");
682 adapter->hw.autoneg = adapter->fc_autoneg = 1;
683 adapter->hw.autoneg_advertised = ADVERTISE_10_HALF |
684 ADVERTISE_100_HALF;
685 break;
686 case FULL_DUPLEX:
687 e_dev_info("Full Duplex specified without Speed\n");
688 e_dev_info("Using Autonegotiation at Full Duplex only\n");
689 adapter->hw.autoneg = adapter->fc_autoneg = 1;
690 adapter->hw.autoneg_advertised = ADVERTISE_10_FULL |
691 ADVERTISE_100_FULL |
692 ADVERTISE_1000_FULL;
693 break;
694 case SPEED_10:
695 e_dev_info("10 Mbps Speed specified without Duplex\n");
696 e_dev_info("Using Autonegotiation at 10 Mbps only\n");
697 adapter->hw.autoneg = adapter->fc_autoneg = 1;
698 adapter->hw.autoneg_advertised = ADVERTISE_10_HALF |
699 ADVERTISE_10_FULL;
700 break;
701 case SPEED_10 + HALF_DUPLEX:
702 e_dev_info("Forcing to 10 Mbps Half Duplex\n");
703 adapter->hw.autoneg = adapter->fc_autoneg = 0;
704 adapter->hw.forced_speed_duplex = e1000_10_half;
705 adapter->hw.autoneg_advertised = 0;
706 break;
707 case SPEED_10 + FULL_DUPLEX:
708 e_dev_info("Forcing to 10 Mbps Full Duplex\n");
709 adapter->hw.autoneg = adapter->fc_autoneg = 0;
710 adapter->hw.forced_speed_duplex = e1000_10_full;
711 adapter->hw.autoneg_advertised = 0;
712 break;
713 case SPEED_100:
714 e_dev_info("100 Mbps Speed specified without Duplex\n");
715 e_dev_info("Using Autonegotiation at 100 Mbps only\n");
716 adapter->hw.autoneg = adapter->fc_autoneg = 1;
717 adapter->hw.autoneg_advertised = ADVERTISE_100_HALF |
718 ADVERTISE_100_FULL;
719 break;
720 case SPEED_100 + HALF_DUPLEX:
721 e_dev_info("Forcing to 100 Mbps Half Duplex\n");
722 adapter->hw.autoneg = adapter->fc_autoneg = 0;
723 adapter->hw.forced_speed_duplex = e1000_100_half;
724 adapter->hw.autoneg_advertised = 0;
725 break;
726 case SPEED_100 + FULL_DUPLEX:
727 e_dev_info("Forcing to 100 Mbps Full Duplex\n");
728 adapter->hw.autoneg = adapter->fc_autoneg = 0;
729 adapter->hw.forced_speed_duplex = e1000_100_full;
730 adapter->hw.autoneg_advertised = 0;
731 break;
732 case SPEED_1000:
733 e_dev_info("1000 Mbps Speed specified without Duplex\n");
734 goto full_duplex_only;
735 case SPEED_1000 + HALF_DUPLEX:
736 e_dev_info("Half Duplex is not supported at 1000 Mbps\n");
737 /* fall through */
738 case SPEED_1000 + FULL_DUPLEX:
739full_duplex_only:
740 e_dev_info("Using Autonegotiation at 1000 Mbps Full Duplex "
741 "only\n");
742 adapter->hw.autoneg = adapter->fc_autoneg = 1;
743 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
744 break;
745 default:
746 BUG();
747 }
748
749 /* Speed, AutoNeg and MDI/MDI-X must all play nice */
750 if (e1000_validate_mdi_setting(&(adapter->hw)) < 0) {
751 e_dev_info("Speed, AutoNeg and MDI-X specs are incompatible. "
752 "Setting MDI-X to a compatible value.\n");
753 }
754}
755
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