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authorJeff Kirsher <jeffrey.t.kirsher@intel.com>2013-02-09 07:49:21 -0500
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2013-02-16 00:46:37 -0500
commit6cfbd97b3e891ed5a70b43b7a237341f4c09cbf1 (patch)
tree4e2188cb90fd4360d1850144b115d7b0f1d83a56 /drivers/net/ethernet/intel/e1000/e1000.h
parentefd9450e7e36717f24dff3bd584faa80a85231d6 (diff)
e1000: fix whitespace issues and multi-line comments
Fixes whitespace issues, such as lines exceeding 80 chars, needless blank lines and the use of spaces where tabs are needed. In addition, fix multi-line comments to align with the networking standard. Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel/e1000/e1000.h')
-rw-r--r--drivers/net/ethernet/intel/e1000/e1000.h65
1 files changed, 33 insertions, 32 deletions
diff --git a/drivers/net/ethernet/intel/e1000/e1000.h b/drivers/net/ethernet/intel/e1000/e1000.h
index 2b6cd02bfba0..26d9cd59ec75 100644
--- a/drivers/net/ethernet/intel/e1000/e1000.h
+++ b/drivers/net/ethernet/intel/e1000/e1000.h
@@ -81,68 +81,69 @@ struct e1000_adapter;
81 81
82#include "e1000_hw.h" 82#include "e1000_hw.h"
83 83
84#define E1000_MAX_INTR 10 84#define E1000_MAX_INTR 10
85 85
86/* TX/RX descriptor defines */ 86/* TX/RX descriptor defines */
87#define E1000_DEFAULT_TXD 256 87#define E1000_DEFAULT_TXD 256
88#define E1000_MAX_TXD 256 88#define E1000_MAX_TXD 256
89#define E1000_MIN_TXD 48 89#define E1000_MIN_TXD 48
90#define E1000_MAX_82544_TXD 4096 90#define E1000_MAX_82544_TXD 4096
91 91
92#define E1000_DEFAULT_RXD 256 92#define E1000_DEFAULT_RXD 256
93#define E1000_MAX_RXD 256 93#define E1000_MAX_RXD 256
94#define E1000_MIN_RXD 48 94#define E1000_MIN_RXD 48
95#define E1000_MAX_82544_RXD 4096 95#define E1000_MAX_82544_RXD 4096
96 96
97#define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */ 97#define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
98#define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */ 98#define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
99 99
100/* this is the size past which hardware will drop packets when setting LPE=0 */ 100/* this is the size past which hardware will drop packets when setting LPE=0 */
101#define MAXIMUM_ETHERNET_VLAN_SIZE 1522 101#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
102 102
103/* Supported Rx Buffer Sizes */ 103/* Supported Rx Buffer Sizes */
104#define E1000_RXBUFFER_128 128 /* Used for packet split */ 104#define E1000_RXBUFFER_128 128 /* Used for packet split */
105#define E1000_RXBUFFER_256 256 /* Used for packet split */ 105#define E1000_RXBUFFER_256 256 /* Used for packet split */
106#define E1000_RXBUFFER_512 512 106#define E1000_RXBUFFER_512 512
107#define E1000_RXBUFFER_1024 1024 107#define E1000_RXBUFFER_1024 1024
108#define E1000_RXBUFFER_2048 2048 108#define E1000_RXBUFFER_2048 2048
109#define E1000_RXBUFFER_4096 4096 109#define E1000_RXBUFFER_4096 4096
110#define E1000_RXBUFFER_8192 8192 110#define E1000_RXBUFFER_8192 8192
111#define E1000_RXBUFFER_16384 16384 111#define E1000_RXBUFFER_16384 16384
112 112
113/* SmartSpeed delimiters */ 113/* SmartSpeed delimiters */
114#define E1000_SMARTSPEED_DOWNSHIFT 3 114#define E1000_SMARTSPEED_DOWNSHIFT 3
115#define E1000_SMARTSPEED_MAX 15 115#define E1000_SMARTSPEED_MAX 15
116 116
117/* Packet Buffer allocations */ 117/* Packet Buffer allocations */
118#define E1000_PBA_BYTES_SHIFT 0xA 118#define E1000_PBA_BYTES_SHIFT 0xA
119#define E1000_TX_HEAD_ADDR_SHIFT 7 119#define E1000_TX_HEAD_ADDR_SHIFT 7
120#define E1000_PBA_TX_MASK 0xFFFF0000 120#define E1000_PBA_TX_MASK 0xFFFF0000
121 121
122/* Flow Control Watermarks */ 122/* Flow Control Watermarks */
123#define E1000_FC_HIGH_DIFF 0x1638 /* High: 5688 bytes below Rx FIFO size */ 123#define E1000_FC_HIGH_DIFF 0x1638 /* High: 5688 bytes below Rx FIFO size */
124#define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */ 124#define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */
125 125
126#define E1000_FC_PAUSE_TIME 0xFFFF /* pause for the max or until send xon */ 126#define E1000_FC_PAUSE_TIME 0xFFFF /* pause for the max or until send xon */
127 127
128/* How many Tx Descriptors do we need to call netif_wake_queue ? */ 128/* How many Tx Descriptors do we need to call netif_wake_queue ? */
129#define E1000_TX_QUEUE_WAKE 16 129#define E1000_TX_QUEUE_WAKE 16
130/* How many Rx Buffers do we bundle into one write to the hardware ? */ 130/* How many Rx Buffers do we bundle into one write to the hardware ? */
131#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 131#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
132 132
133#define AUTO_ALL_MODES 0 133#define AUTO_ALL_MODES 0
134#define E1000_EEPROM_82544_APM 0x0004 134#define E1000_EEPROM_82544_APM 0x0004
135#define E1000_EEPROM_APME 0x0400 135#define E1000_EEPROM_APME 0x0400
136 136
137#ifndef E1000_MASTER_SLAVE 137#ifndef E1000_MASTER_SLAVE
138/* Switch to override PHY master/slave setting */ 138/* Switch to override PHY master/slave setting */
139#define E1000_MASTER_SLAVE e1000_ms_hw_default 139#define E1000_MASTER_SLAVE e1000_ms_hw_default
140#endif 140#endif
141 141
142#define E1000_MNG_VLAN_NONE (-1) 142#define E1000_MNG_VLAN_NONE (-1)
143 143
144/* wrapper around a pointer to a socket buffer, 144/* wrapper around a pointer to a socket buffer,
145 * so a DMA handle can be stored along with the buffer */ 145 * so a DMA handle can be stored along with the buffer
146 */
146struct e1000_buffer { 147struct e1000_buffer {
147 struct sk_buff *skb; 148 struct sk_buff *skb;
148 dma_addr_t dma; 149 dma_addr_t dma;