aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/ethernet/freescale
diff options
context:
space:
mode:
authorFrank Li <Frank.Li@freescale.com>2012-10-30 14:24:49 -0400
committerDavid S. Miller <davem@davemloft.net>2012-11-01 12:28:05 -0400
commit405f257f46f66a800639532afd1dd8dfd5fa4861 (patch)
tree864751fe1566d4f77d24ca596926366c599b5291 /drivers/net/ethernet/freescale
parent23ea5a963768ff162a9ff8654589d7f7e1dfb780 (diff)
net: fec: move fec_enet_private to header file
A new file fec_ptp.c will use fec_enet_private to support 1588 PTP move such structure to common header file fec.h Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/freescale')
-rw-r--r--drivers/net/ethernet/freescale/fec.c73
-rw-r--r--drivers/net/ethernet/freescale/fec.h81
2 files changed, 81 insertions, 73 deletions
diff --git a/drivers/net/ethernet/freescale/fec.c b/drivers/net/ethernet/freescale/fec.c
index fffd20528b5d..d0e1b331e8e6 100644
--- a/drivers/net/ethernet/freescale/fec.c
+++ b/drivers/net/ethernet/freescale/fec.c
@@ -140,21 +140,6 @@ MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
140#endif 140#endif
141#endif /* CONFIG_M5272 */ 141#endif /* CONFIG_M5272 */
142 142
143/* The number of Tx and Rx buffers. These are allocated from the page
144 * pool. The code may assume these are power of two, so it it best
145 * to keep them that size.
146 * We don't need to allocate pages for the transmitter. We just use
147 * the skbuffer directly.
148 */
149#define FEC_ENET_RX_PAGES 8
150#define FEC_ENET_RX_FRSIZE 2048
151#define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
152#define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
153#define FEC_ENET_TX_FRSIZE 2048
154#define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
155#define TX_RING_SIZE 16 /* Must be power of two */
156#define TX_RING_MOD_MASK 15 /* for this to work */
157
158#if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE) 143#if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
159#error "FEC: descriptor ring size constants too large" 144#error "FEC: descriptor ring size constants too large"
160#endif 145#endif
@@ -179,9 +164,6 @@ MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
179#define PKT_MINBUF_SIZE 64 164#define PKT_MINBUF_SIZE 64
180#define PKT_MAXBLR_SIZE 1520 165#define PKT_MAXBLR_SIZE 1520
181 166
182/* This device has up to three irqs on some platforms */
183#define FEC_IRQ_NUM 3
184
185/* 167/*
186 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 168 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
187 * size bits. Other FEC hardware does not, so we need to take that into 169 * size bits. Other FEC hardware does not, so we need to take that into
@@ -194,61 +176,6 @@ MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
194#define OPT_FRAME_SIZE 0 176#define OPT_FRAME_SIZE 0
195#endif 177#endif
196 178
197/* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
198 * tx_bd_base always point to the base of the buffer descriptors. The
199 * cur_rx and cur_tx point to the currently available buffer.
200 * The dirty_tx tracks the current buffer that is being sent by the
201 * controller. The cur_tx and dirty_tx are equal under both completely
202 * empty and completely full conditions. The empty/ready indicator in
203 * the buffer descriptor determines the actual condition.
204 */
205struct fec_enet_private {
206 /* Hardware registers of the FEC device */
207 void __iomem *hwp;
208
209 struct net_device *netdev;
210
211 struct clk *clk_ipg;
212 struct clk *clk_ahb;
213
214 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
215 unsigned char *tx_bounce[TX_RING_SIZE];
216 struct sk_buff* tx_skbuff[TX_RING_SIZE];
217 struct sk_buff* rx_skbuff[RX_RING_SIZE];
218 ushort skb_cur;
219 ushort skb_dirty;
220
221 /* CPM dual port RAM relative addresses */
222 dma_addr_t bd_dma;
223 /* Address of Rx and Tx buffers */
224 struct bufdesc *rx_bd_base;
225 struct bufdesc *tx_bd_base;
226 /* The next free ring entry */
227 struct bufdesc *cur_rx, *cur_tx;
228 /* The ring entries to be free()ed */
229 struct bufdesc *dirty_tx;
230
231 uint tx_full;
232 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
233 spinlock_t hw_lock;
234
235 struct platform_device *pdev;
236
237 int opened;
238 int dev_id;
239
240 /* Phylib and MDIO interface */
241 struct mii_bus *mii_bus;
242 struct phy_device *phy_dev;
243 int mii_timeout;
244 uint phy_speed;
245 phy_interface_t phy_interface;
246 int link;
247 int full_duplex;
248 struct completion mdio_done;
249 int irq[FEC_IRQ_NUM];
250};
251
252/* FEC MII MMFR bits definition */ 179/* FEC MII MMFR bits definition */
253#define FEC_MMFR_ST (1 << 30) 180#define FEC_MMFR_ST (1 << 30)
254#define FEC_MMFR_OP_READ (2 << 28) 181#define FEC_MMFR_OP_READ (2 << 28)
diff --git a/drivers/net/ethernet/freescale/fec.h b/drivers/net/ethernet/freescale/fec.h
index 8408c627b195..e803812975df 100644
--- a/drivers/net/ethernet/freescale/fec.h
+++ b/drivers/net/ethernet/freescale/fec.h
@@ -147,6 +147,87 @@ struct bufdesc {
147#define BD_ENET_TX_CSL ((ushort)0x0001) 147#define BD_ENET_TX_CSL ((ushort)0x0001)
148#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ 148#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
149 149
150/*enhanced buffer desciptor control/status used by Ethernet transmit*/
151#define BD_ENET_TX_INT 0x40000000
152#define BD_ENET_TX_TS 0x20000000
153
154
155/* This device has up to three irqs on some platforms */
156#define FEC_IRQ_NUM 3
157
158/* The number of Tx and Rx buffers. These are allocated from the page
159 * pool. The code may assume these are power of two, so it it best
160 * to keep them that size.
161 * We don't need to allocate pages for the transmitter. We just use
162 * the skbuffer directly.
163 */
164
165#define FEC_ENET_RX_PAGES 8
166#define FEC_ENET_RX_FRSIZE 2048
167#define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
168#define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
169#define FEC_ENET_TX_FRSIZE 2048
170#define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
171#define TX_RING_SIZE 16 /* Must be power of two */
172#define TX_RING_MOD_MASK 15 /* for this to work */
173
174#define BD_ENET_RX_INT 0x00800000
175#define BD_ENET_RX_PTP ((ushort)0x0400)
176
177/* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
178 * tx_bd_base always point to the base of the buffer descriptors. The
179 * cur_rx and cur_tx point to the currently available buffer.
180 * The dirty_tx tracks the current buffer that is being sent by the
181 * controller. The cur_tx and dirty_tx are equal under both completely
182 * empty and completely full conditions. The empty/ready indicator in
183 * the buffer descriptor determines the actual condition.
184 */
185struct fec_enet_private {
186 /* Hardware registers of the FEC device */
187 void __iomem *hwp;
188
189 struct net_device *netdev;
190
191 struct clk *clk_ipg;
192 struct clk *clk_ahb;
193
194 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
195 unsigned char *tx_bounce[TX_RING_SIZE];
196 struct sk_buff *tx_skbuff[TX_RING_SIZE];
197 struct sk_buff *rx_skbuff[RX_RING_SIZE];
198 ushort skb_cur;
199 ushort skb_dirty;
200
201 /* CPM dual port RAM relative addresses */
202 dma_addr_t bd_dma;
203 /* Address of Rx and Tx buffers */
204 struct bufdesc *rx_bd_base;
205 struct bufdesc *tx_bd_base;
206 /* The next free ring entry */
207 struct bufdesc *cur_rx, *cur_tx;
208 /* The ring entries to be free()ed */
209 struct bufdesc *dirty_tx;
210
211 uint tx_full;
212 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
213 spinlock_t hw_lock;
214
215 struct platform_device *pdev;
216
217 int opened;
218 int dev_id;
219
220 /* Phylib and MDIO interface */
221 struct mii_bus *mii_bus;
222 struct phy_device *phy_dev;
223 int mii_timeout;
224 uint phy_speed;
225 phy_interface_t phy_interface;
226 int link;
227 int full_duplex;
228 struct completion mdio_done;
229 int irq[FEC_IRQ_NUM];
230};
150 231
151/****************************************************************************/ 232/****************************************************************************/
152#endif /* FEC_H */ 233#endif /* FEC_H */