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authorLuwei Zhou <b45643@freescale.com>2014-10-10 01:15:28 -0400
committerDavid S. Miller <davem@davemloft.net>2014-10-14 14:45:08 -0400
commitf28460b229919387b2f97f3a688d0dd86cc819c9 (patch)
treebbe3281c2842f1544f1292da34d69f7201dacea4 /drivers/net/ethernet/freescale
parent02ea80741a25435123e8a5ca40cac6a0bcf0c9f1 (diff)
net: fec: ptp: Use the 31-bit ptp timer.
When ptp switches from software adjustment to hardware ajustment, linux ptp can't converge. It is caused by the IP limit. Hardware adjustment logcial have issue when ptp counter runs over 0x80000000(31 bit counter). The internal IP reference manual already remove 32bit free-running count support. This patch replace the 32-bit PTP timer with 31-bit. Signed-off-by: Luwei Zhou <b45643@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/freescale')
-rw-r--r--drivers/net/ethernet/freescale/fec_ptp.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/net/ethernet/freescale/fec_ptp.c b/drivers/net/ethernet/freescale/fec_ptp.c
index cca3617a2321..8016bdd1995f 100644
--- a/drivers/net/ethernet/freescale/fec_ptp.c
+++ b/drivers/net/ethernet/freescale/fec_ptp.c
@@ -70,6 +70,7 @@
70#define FEC_TS_TIMESTAMP 0x418 70#define FEC_TS_TIMESTAMP 0x418
71 71
72#define FEC_CC_MULT (1 << 31) 72#define FEC_CC_MULT (1 << 31)
73#define FEC_COUNTER_PERIOD (1 << 31)
73/** 74/**
74 * fec_ptp_read - read raw cycle counter (to be used by time counter) 75 * fec_ptp_read - read raw cycle counter (to be used by time counter)
75 * @cc: the cyclecounter structure 76 * @cc: the cyclecounter structure
@@ -113,14 +114,15 @@ void fec_ptp_start_cyclecounter(struct net_device *ndev)
113 /* 1ns counter */ 114 /* 1ns counter */
114 writel(inc << FEC_T_INC_OFFSET, fep->hwp + FEC_ATIME_INC); 115 writel(inc << FEC_T_INC_OFFSET, fep->hwp + FEC_ATIME_INC);
115 116
116 /* use free running count */ 117 /* use 31-bit timer counter */
117 writel(0, fep->hwp + FEC_ATIME_EVT_PERIOD); 118 writel(FEC_COUNTER_PERIOD, fep->hwp + FEC_ATIME_EVT_PERIOD);
118 119
119 writel(FEC_T_CTRL_ENABLE, fep->hwp + FEC_ATIME_CTRL); 120 writel(FEC_T_CTRL_ENABLE | FEC_T_CTRL_PERIOD_RST,
121 fep->hwp + FEC_ATIME_CTRL);
120 122
121 memset(&fep->cc, 0, sizeof(fep->cc)); 123 memset(&fep->cc, 0, sizeof(fep->cc));
122 fep->cc.read = fec_ptp_read; 124 fep->cc.read = fec_ptp_read;
123 fep->cc.mask = CLOCKSOURCE_MASK(32); 125 fep->cc.mask = CLOCKSOURCE_MASK(31);
124 fep->cc.shift = 31; 126 fep->cc.shift = 31;
125 fep->cc.mult = FEC_CC_MULT; 127 fep->cc.mult = FEC_CC_MULT;
126 128