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authorFrancois Romieu <romieu@fr.zoreil.com>2012-03-09 17:26:32 -0500
committerFrancois Romieu <romieu@fr.zoreil.com>2012-04-07 05:47:18 -0400
commit5820e97a299e502e71dd5587ed2bf63a75d4f4f7 (patch)
tree703397725834485adae5a0e5fcc85b607873a47a /drivers/net/ethernet/dec
parentaae9bc302de493ad62102e7cdb1e123648057b66 (diff)
dmfe: stop using net_device.{base_addr, irq} and convert to __iomem.
This is a pure PCI driver, no ISA here. Signed-off-by: Francois Romieu <romieu@fr.zoreil.com> Acked-by: Grant Grundler <grundler@parisc-linux.org>
Diffstat (limited to 'drivers/net/ethernet/dec')
-rw-r--r--drivers/net/ethernet/dec/tulip/dmfe.c295
1 files changed, 153 insertions, 142 deletions
diff --git a/drivers/net/ethernet/dec/tulip/dmfe.c b/drivers/net/ethernet/dec/tulip/dmfe.c
index 1eccf4945485..0ef5b68acd05 100644
--- a/drivers/net/ethernet/dec/tulip/dmfe.c
+++ b/drivers/net/ethernet/dec/tulip/dmfe.c
@@ -150,6 +150,12 @@
150#define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */ 150#define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
151#define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */ 151#define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */
152 152
153#define dw32(reg, val) iowrite32(val, ioaddr + (reg))
154#define dw16(reg, val) iowrite16(val, ioaddr + (reg))
155#define dr32(reg) ioread32(ioaddr + (reg))
156#define dr16(reg) ioread16(ioaddr + (reg))
157#define dr8(reg) ioread8(ioaddr + (reg))
158
153#define DMFE_DBUG(dbug_now, msg, value) \ 159#define DMFE_DBUG(dbug_now, msg, value) \
154 do { \ 160 do { \
155 if (dmfe_debug || (dbug_now)) \ 161 if (dmfe_debug || (dbug_now)) \
@@ -178,14 +184,6 @@
178 184
179#define SROM_V41_CODE 0x14 185#define SROM_V41_CODE 0x14
180 186
181#define SROM_CLK_WRITE(data, ioaddr) \
182 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
183 udelay(5); \
184 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
185 udelay(5); \
186 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
187 udelay(5);
188
189#define __CHK_IO_SIZE(pci_id, dev_rev) \ 187#define __CHK_IO_SIZE(pci_id, dev_rev) \
190 (( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x30) ) ? \ 188 (( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x30) ) ? \
191 DM9102A_IO_SIZE: DM9102_IO_SIZE) 189 DM9102A_IO_SIZE: DM9102_IO_SIZE)
@@ -213,11 +211,11 @@ struct rx_desc {
213struct dmfe_board_info { 211struct dmfe_board_info {
214 u32 chip_id; /* Chip vendor/Device ID */ 212 u32 chip_id; /* Chip vendor/Device ID */
215 u8 chip_revision; /* Chip revision */ 213 u8 chip_revision; /* Chip revision */
216 struct DEVICE *next_dev; /* next device */ 214 struct net_device *next_dev; /* next device */
217 struct pci_dev *pdev; /* PCI device */ 215 struct pci_dev *pdev; /* PCI device */
218 spinlock_t lock; 216 spinlock_t lock;
219 217
220 long ioaddr; /* I/O base address */ 218 void __iomem *ioaddr; /* I/O base address */
221 u32 cr0_data; 219 u32 cr0_data;
222 u32 cr5_data; 220 u32 cr5_data;
223 u32 cr6_data; 221 u32 cr6_data;
@@ -320,20 +318,20 @@ static netdev_tx_t dmfe_start_xmit(struct sk_buff *, struct DEVICE *);
320static int dmfe_stop(struct DEVICE *); 318static int dmfe_stop(struct DEVICE *);
321static void dmfe_set_filter_mode(struct DEVICE *); 319static void dmfe_set_filter_mode(struct DEVICE *);
322static const struct ethtool_ops netdev_ethtool_ops; 320static const struct ethtool_ops netdev_ethtool_ops;
323static u16 read_srom_word(long ,int); 321static u16 read_srom_word(void __iomem *, int);
324static irqreturn_t dmfe_interrupt(int , void *); 322static irqreturn_t dmfe_interrupt(int , void *);
325#ifdef CONFIG_NET_POLL_CONTROLLER 323#ifdef CONFIG_NET_POLL_CONTROLLER
326static void poll_dmfe (struct net_device *dev); 324static void poll_dmfe (struct net_device *dev);
327#endif 325#endif
328static void dmfe_descriptor_init(struct net_device *, unsigned long); 326static void dmfe_descriptor_init(struct net_device *);
329static void allocate_rx_buffer(struct net_device *); 327static void allocate_rx_buffer(struct net_device *);
330static void update_cr6(u32, unsigned long); 328static void update_cr6(u32, void __iomem *);
331static void send_filter_frame(struct DEVICE *); 329static void send_filter_frame(struct DEVICE *);
332static void dm9132_id_table(struct DEVICE *); 330static void dm9132_id_table(struct DEVICE *);
333static u16 phy_read(unsigned long, u8, u8, u32); 331static u16 phy_read(void __iomem *, u8, u8, u32);
334static void phy_write(unsigned long, u8, u8, u16, u32); 332static void phy_write(void __iomem *, u8, u8, u16, u32);
335static void phy_write_1bit(unsigned long, u32); 333static void phy_write_1bit(void __iomem *, u32);
336static u16 phy_read_1bit(unsigned long); 334static u16 phy_read_1bit(void __iomem *);
337static u8 dmfe_sense_speed(struct dmfe_board_info *); 335static u8 dmfe_sense_speed(struct dmfe_board_info *);
338static void dmfe_process_mode(struct dmfe_board_info *); 336static void dmfe_process_mode(struct dmfe_board_info *);
339static void dmfe_timer(unsigned long); 337static void dmfe_timer(unsigned long);
@@ -462,14 +460,16 @@ static int __devinit dmfe_init_one (struct pci_dev *pdev,
462 db->buf_pool_dma_start = db->buf_pool_dma_ptr; 460 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
463 461
464 db->chip_id = ent->driver_data; 462 db->chip_id = ent->driver_data;
465 db->ioaddr = pci_resource_start(pdev, 0); 463 /* IO type range. */
464 db->ioaddr = pci_iomap(pdev, 0, 0);
465 if (!db->ioaddr)
466 goto err_out_free_buf;
467
466 db->chip_revision = pdev->revision; 468 db->chip_revision = pdev->revision;
467 db->wol_mode = 0; 469 db->wol_mode = 0;
468 470
469 db->pdev = pdev; 471 db->pdev = pdev;
470 472
471 dev->base_addr = db->ioaddr;
472 dev->irq = pdev->irq;
473 pci_set_drvdata(pdev, dev); 473 pci_set_drvdata(pdev, dev);
474 dev->netdev_ops = &netdev_ops; 474 dev->netdev_ops = &netdev_ops;
475 dev->ethtool_ops = &netdev_ethtool_ops; 475 dev->ethtool_ops = &netdev_ethtool_ops;
@@ -484,9 +484,10 @@ static int __devinit dmfe_init_one (struct pci_dev *pdev,
484 db->chip_type = 0; 484 db->chip_type = 0;
485 485
486 /* read 64 word srom data */ 486 /* read 64 word srom data */
487 for (i = 0; i < 64; i++) 487 for (i = 0; i < 64; i++) {
488 ((__le16 *) db->srom)[i] = 488 ((__le16 *) db->srom)[i] =
489 cpu_to_le16(read_srom_word(db->ioaddr, i)); 489 cpu_to_le16(read_srom_word(db->ioaddr, i));
490 }
490 491
491 /* Set Node address */ 492 /* Set Node address */
492 for (i = 0; i < 6; i++) 493 for (i = 0; i < 6; i++)
@@ -494,16 +495,18 @@ static int __devinit dmfe_init_one (struct pci_dev *pdev,
494 495
495 err = register_netdev (dev); 496 err = register_netdev (dev);
496 if (err) 497 if (err)
497 goto err_out_free_buf; 498 goto err_out_unmap;
498 499
499 dev_info(&dev->dev, "Davicom DM%04lx at pci%s, %pM, irq %d\n", 500 dev_info(&dev->dev, "Davicom DM%04lx at pci%s, %pM, irq %d\n",
500 ent->driver_data >> 16, 501 ent->driver_data >> 16,
501 pci_name(pdev), dev->dev_addr, dev->irq); 502 pci_name(pdev), dev->dev_addr, pdev->irq);
502 503
503 pci_set_master(pdev); 504 pci_set_master(pdev);
504 505
505 return 0; 506 return 0;
506 507
508err_out_unmap:
509 pci_iounmap(pdev, db->ioaddr);
507err_out_free_buf: 510err_out_free_buf:
508 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, 511 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
509 db->buf_pool_ptr, db->buf_pool_dma_ptr); 512 db->buf_pool_ptr, db->buf_pool_dma_ptr);
@@ -532,7 +535,7 @@ static void __devexit dmfe_remove_one (struct pci_dev *pdev)
532 if (dev) { 535 if (dev) {
533 536
534 unregister_netdev(dev); 537 unregister_netdev(dev);
535 538 pci_iounmap(db->pdev, db->ioaddr);
536 pci_free_consistent(db->pdev, sizeof(struct tx_desc) * 539 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
537 DESC_ALL_CNT + 0x20, db->desc_pool_ptr, 540 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
538 db->desc_pool_dma_ptr); 541 db->desc_pool_dma_ptr);
@@ -555,13 +558,13 @@ static void __devexit dmfe_remove_one (struct pci_dev *pdev)
555 558
556static int dmfe_open(struct DEVICE *dev) 559static int dmfe_open(struct DEVICE *dev)
557{ 560{
558 int ret;
559 struct dmfe_board_info *db = netdev_priv(dev); 561 struct dmfe_board_info *db = netdev_priv(dev);
562 const int irq = db->pdev->irq;
563 int ret;
560 564
561 DMFE_DBUG(0, "dmfe_open", 0); 565 DMFE_DBUG(0, "dmfe_open", 0);
562 566
563 ret = request_irq(dev->irq, dmfe_interrupt, 567 ret = request_irq(irq, dmfe_interrupt, IRQF_SHARED, dev->name, dev);
564 IRQF_SHARED, dev->name, dev);
565 if (ret) 568 if (ret)
566 return ret; 569 return ret;
567 570
@@ -615,14 +618,14 @@ static int dmfe_open(struct DEVICE *dev)
615static void dmfe_init_dm910x(struct DEVICE *dev) 618static void dmfe_init_dm910x(struct DEVICE *dev)
616{ 619{
617 struct dmfe_board_info *db = netdev_priv(dev); 620 struct dmfe_board_info *db = netdev_priv(dev);
618 unsigned long ioaddr = db->ioaddr; 621 void __iomem *ioaddr = db->ioaddr;
619 622
620 DMFE_DBUG(0, "dmfe_init_dm910x()", 0); 623 DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
621 624
622 /* Reset DM910x MAC controller */ 625 /* Reset DM910x MAC controller */
623 outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */ 626 dw32(DCR0, DM910X_RESET); /* RESET MAC */
624 udelay(100); 627 udelay(100);
625 outl(db->cr0_data, ioaddr + DCR0); 628 dw32(DCR0, db->cr0_data);
626 udelay(5); 629 udelay(5);
627 630
628 /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */ 631 /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
@@ -633,12 +636,12 @@ static void dmfe_init_dm910x(struct DEVICE *dev)
633 db->media_mode = dmfe_media_mode; 636 db->media_mode = dmfe_media_mode;
634 637
635 /* RESET Phyxcer Chip by GPR port bit 7 */ 638 /* RESET Phyxcer Chip by GPR port bit 7 */
636 outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */ 639 dw32(DCR12, 0x180); /* Let bit 7 output port */
637 if (db->chip_id == PCI_DM9009_ID) { 640 if (db->chip_id == PCI_DM9009_ID) {
638 outl(0x80, ioaddr + DCR12); /* Issue RESET signal */ 641 dw32(DCR12, 0x80); /* Issue RESET signal */
639 mdelay(300); /* Delay 300 ms */ 642 mdelay(300); /* Delay 300 ms */
640 } 643 }
641 outl(0x0, ioaddr + DCR12); /* Clear RESET signal */ 644 dw32(DCR12, 0x0); /* Clear RESET signal */
642 645
643 /* Process Phyxcer Media Mode */ 646 /* Process Phyxcer Media Mode */
644 if ( !(db->media_mode & 0x10) ) /* Force 1M mode */ 647 if ( !(db->media_mode & 0x10) ) /* Force 1M mode */
@@ -649,7 +652,7 @@ static void dmfe_init_dm910x(struct DEVICE *dev)
649 db->op_mode = db->media_mode; /* Force Mode */ 652 db->op_mode = db->media_mode; /* Force Mode */
650 653
651 /* Initialize Transmit/Receive decriptor and CR3/4 */ 654 /* Initialize Transmit/Receive decriptor and CR3/4 */
652 dmfe_descriptor_init(dev, ioaddr); 655 dmfe_descriptor_init(dev);
653 656
654 /* Init CR6 to program DM910x operation */ 657 /* Init CR6 to program DM910x operation */
655 update_cr6(db->cr6_data, ioaddr); 658 update_cr6(db->cr6_data, ioaddr);
@@ -662,10 +665,10 @@ static void dmfe_init_dm910x(struct DEVICE *dev)
662 665
663 /* Init CR7, interrupt active bit */ 666 /* Init CR7, interrupt active bit */
664 db->cr7_data = CR7_DEFAULT; 667 db->cr7_data = CR7_DEFAULT;
665 outl(db->cr7_data, ioaddr + DCR7); 668 dw32(DCR7, db->cr7_data);
666 669
667 /* Init CR15, Tx jabber and Rx watchdog timer */ 670 /* Init CR15, Tx jabber and Rx watchdog timer */
668 outl(db->cr15_data, ioaddr + DCR15); 671 dw32(DCR15, db->cr15_data);
669 672
670 /* Enable DM910X Tx/Rx function */ 673 /* Enable DM910X Tx/Rx function */
671 db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000; 674 db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
@@ -682,6 +685,7 @@ static netdev_tx_t dmfe_start_xmit(struct sk_buff *skb,
682 struct DEVICE *dev) 685 struct DEVICE *dev)
683{ 686{
684 struct dmfe_board_info *db = netdev_priv(dev); 687 struct dmfe_board_info *db = netdev_priv(dev);
688 void __iomem *ioaddr = db->ioaddr;
685 struct tx_desc *txptr; 689 struct tx_desc *txptr;
686 unsigned long flags; 690 unsigned long flags;
687 691
@@ -707,7 +711,7 @@ static netdev_tx_t dmfe_start_xmit(struct sk_buff *skb,
707 } 711 }
708 712
709 /* Disable NIC interrupt */ 713 /* Disable NIC interrupt */
710 outl(0, dev->base_addr + DCR7); 714 dw32(DCR7, 0);
711 715
712 /* transmit this packet */ 716 /* transmit this packet */
713 txptr = db->tx_insert_ptr; 717 txptr = db->tx_insert_ptr;
@@ -721,11 +725,11 @@ static netdev_tx_t dmfe_start_xmit(struct sk_buff *skb,
721 if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) { 725 if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) {
722 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */ 726 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
723 db->tx_packet_cnt++; /* Ready to send */ 727 db->tx_packet_cnt++; /* Ready to send */
724 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */ 728 dw32(DCR1, 0x1); /* Issue Tx polling */
725 dev->trans_start = jiffies; /* saved time stamp */ 729 dev->trans_start = jiffies; /* saved time stamp */
726 } else { 730 } else {
727 db->tx_queue_cnt++; /* queue TX packet */ 731 db->tx_queue_cnt++; /* queue TX packet */
728 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */ 732 dw32(DCR1, 0x1); /* Issue Tx polling */
729 } 733 }
730 734
731 /* Tx resource check */ 735 /* Tx resource check */
@@ -734,7 +738,7 @@ static netdev_tx_t dmfe_start_xmit(struct sk_buff *skb,
734 738
735 /* Restore CR7 to enable interrupt */ 739 /* Restore CR7 to enable interrupt */
736 spin_unlock_irqrestore(&db->lock, flags); 740 spin_unlock_irqrestore(&db->lock, flags);
737 outl(db->cr7_data, dev->base_addr + DCR7); 741 dw32(DCR7, db->cr7_data);
738 742
739 /* free this SKB */ 743 /* free this SKB */
740 dev_kfree_skb(skb); 744 dev_kfree_skb(skb);
@@ -751,7 +755,7 @@ static netdev_tx_t dmfe_start_xmit(struct sk_buff *skb,
751static int dmfe_stop(struct DEVICE *dev) 755static int dmfe_stop(struct DEVICE *dev)
752{ 756{
753 struct dmfe_board_info *db = netdev_priv(dev); 757 struct dmfe_board_info *db = netdev_priv(dev);
754 unsigned long ioaddr = dev->base_addr; 758 void __iomem *ioaddr = db->ioaddr;
755 759
756 DMFE_DBUG(0, "dmfe_stop", 0); 760 DMFE_DBUG(0, "dmfe_stop", 0);
757 761
@@ -762,12 +766,12 @@ static int dmfe_stop(struct DEVICE *dev)
762 del_timer_sync(&db->timer); 766 del_timer_sync(&db->timer);
763 767
764 /* Reset & stop DM910X board */ 768 /* Reset & stop DM910X board */
765 outl(DM910X_RESET, ioaddr + DCR0); 769 dw32(DCR0, DM910X_RESET);
766 udelay(5); 770 udelay(5);
767 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id); 771 phy_write(ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
768 772
769 /* free interrupt */ 773 /* free interrupt */
770 free_irq(dev->irq, dev); 774 free_irq(db->pdev->irq, dev);
771 775
772 /* free allocated rx buffer */ 776 /* free allocated rx buffer */
773 dmfe_free_rxbuffer(db); 777 dmfe_free_rxbuffer(db);
@@ -794,7 +798,7 @@ static irqreturn_t dmfe_interrupt(int irq, void *dev_id)
794{ 798{
795 struct DEVICE *dev = dev_id; 799 struct DEVICE *dev = dev_id;
796 struct dmfe_board_info *db = netdev_priv(dev); 800 struct dmfe_board_info *db = netdev_priv(dev);
797 unsigned long ioaddr = dev->base_addr; 801 void __iomem *ioaddr = db->ioaddr;
798 unsigned long flags; 802 unsigned long flags;
799 803
800 DMFE_DBUG(0, "dmfe_interrupt()", 0); 804 DMFE_DBUG(0, "dmfe_interrupt()", 0);
@@ -802,15 +806,15 @@ static irqreturn_t dmfe_interrupt(int irq, void *dev_id)
802 spin_lock_irqsave(&db->lock, flags); 806 spin_lock_irqsave(&db->lock, flags);
803 807
804 /* Got DM910X status */ 808 /* Got DM910X status */
805 db->cr5_data = inl(ioaddr + DCR5); 809 db->cr5_data = dr32(DCR5);
806 outl(db->cr5_data, ioaddr + DCR5); 810 dw32(DCR5, db->cr5_data);
807 if ( !(db->cr5_data & 0xc1) ) { 811 if ( !(db->cr5_data & 0xc1) ) {
808 spin_unlock_irqrestore(&db->lock, flags); 812 spin_unlock_irqrestore(&db->lock, flags);
809 return IRQ_HANDLED; 813 return IRQ_HANDLED;
810 } 814 }
811 815
812 /* Disable all interrupt in CR7 to solve the interrupt edge problem */ 816 /* Disable all interrupt in CR7 to solve the interrupt edge problem */
813 outl(0, ioaddr + DCR7); 817 dw32(DCR7, 0);
814 818
815 /* Check system status */ 819 /* Check system status */
816 if (db->cr5_data & 0x2000) { 820 if (db->cr5_data & 0x2000) {
@@ -838,11 +842,11 @@ static irqreturn_t dmfe_interrupt(int irq, void *dev_id)
838 if (db->dm910x_chk_mode & 0x2) { 842 if (db->dm910x_chk_mode & 0x2) {
839 db->dm910x_chk_mode = 0x4; 843 db->dm910x_chk_mode = 0x4;
840 db->cr6_data |= 0x100; 844 db->cr6_data |= 0x100;
841 update_cr6(db->cr6_data, db->ioaddr); 845 update_cr6(db->cr6_data, ioaddr);
842 } 846 }
843 847
844 /* Restore CR7 to enable interrupt mask */ 848 /* Restore CR7 to enable interrupt mask */
845 outl(db->cr7_data, ioaddr + DCR7); 849 dw32(DCR7, db->cr7_data);
846 850
847 spin_unlock_irqrestore(&db->lock, flags); 851 spin_unlock_irqrestore(&db->lock, flags);
848 return IRQ_HANDLED; 852 return IRQ_HANDLED;
@@ -858,11 +862,14 @@ static irqreturn_t dmfe_interrupt(int irq, void *dev_id)
858 862
859static void poll_dmfe (struct net_device *dev) 863static void poll_dmfe (struct net_device *dev)
860{ 864{
865 struct dmfe_board_info *db = netdev_priv(dev);
866 const int irq = db->pdev->irq;
867
861 /* disable_irq here is not very nice, but with the lockless 868 /* disable_irq here is not very nice, but with the lockless
862 interrupt handler we have no other choice. */ 869 interrupt handler we have no other choice. */
863 disable_irq(dev->irq); 870 disable_irq(irq);
864 dmfe_interrupt (dev->irq, dev); 871 dmfe_interrupt (irq, dev);
865 enable_irq(dev->irq); 872 enable_irq(irq);
866} 873}
867#endif 874#endif
868 875
@@ -873,7 +880,7 @@ static void poll_dmfe (struct net_device *dev)
873static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db) 880static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db)
874{ 881{
875 struct tx_desc *txptr; 882 struct tx_desc *txptr;
876 unsigned long ioaddr = dev->base_addr; 883 void __iomem *ioaddr = db->ioaddr;
877 u32 tdes0; 884 u32 tdes0;
878 885
879 txptr = db->tx_remove_ptr; 886 txptr = db->tx_remove_ptr;
@@ -897,7 +904,7 @@ static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db)
897 db->tx_fifo_underrun++; 904 db->tx_fifo_underrun++;
898 if ( !(db->cr6_data & CR6_SFT) ) { 905 if ( !(db->cr6_data & CR6_SFT) ) {
899 db->cr6_data = db->cr6_data | CR6_SFT; 906 db->cr6_data = db->cr6_data | CR6_SFT;
900 update_cr6(db->cr6_data, db->ioaddr); 907 update_cr6(db->cr6_data, ioaddr);
901 } 908 }
902 } 909 }
903 if (tdes0 & 0x0100) 910 if (tdes0 & 0x0100)
@@ -924,7 +931,7 @@ static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db)
924 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */ 931 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
925 db->tx_packet_cnt++; /* Ready to send */ 932 db->tx_packet_cnt++; /* Ready to send */
926 db->tx_queue_cnt--; 933 db->tx_queue_cnt--;
927 outl(0x1, ioaddr + DCR1); /* Issue Tx polling */ 934 dw32(DCR1, 0x1); /* Issue Tx polling */
928 dev->trans_start = jiffies; /* saved time stamp */ 935 dev->trans_start = jiffies; /* saved time stamp */
929 } 936 }
930 937
@@ -1087,12 +1094,7 @@ static void dmfe_ethtool_get_drvinfo(struct net_device *dev,
1087 1094
1088 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 1095 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1089 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 1096 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1090 if (np->pdev) 1097 strlcpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
1091 strlcpy(info->bus_info, pci_name(np->pdev),
1092 sizeof(info->bus_info));
1093 else
1094 sprintf(info->bus_info, "EISA 0x%lx %d",
1095 dev->base_addr, dev->irq);
1096} 1098}
1097 1099
1098static int dmfe_ethtool_set_wol(struct net_device *dev, 1100static int dmfe_ethtool_set_wol(struct net_device *dev,
@@ -1132,10 +1134,11 @@ static const struct ethtool_ops netdev_ethtool_ops = {
1132 1134
1133static void dmfe_timer(unsigned long data) 1135static void dmfe_timer(unsigned long data)
1134{ 1136{
1137 struct net_device *dev = (struct net_device *)data;
1138 struct dmfe_board_info *db = netdev_priv(dev);
1139 void __iomem *ioaddr = db->ioaddr;
1135 u32 tmp_cr8; 1140 u32 tmp_cr8;
1136 unsigned char tmp_cr12; 1141 unsigned char tmp_cr12;
1137 struct DEVICE *dev = (struct DEVICE *) data;
1138 struct dmfe_board_info *db = netdev_priv(dev);
1139 unsigned long flags; 1142 unsigned long flags;
1140 1143
1141 int link_ok, link_ok_phy; 1144 int link_ok, link_ok_phy;
@@ -1148,11 +1151,10 @@ static void dmfe_timer(unsigned long data)
1148 db->first_in_callback = 1; 1151 db->first_in_callback = 1;
1149 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) { 1152 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
1150 db->cr6_data &= ~0x40000; 1153 db->cr6_data &= ~0x40000;
1151 update_cr6(db->cr6_data, db->ioaddr); 1154 update_cr6(db->cr6_data, ioaddr);
1152 phy_write(db->ioaddr, 1155 phy_write(ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1153 db->phy_addr, 0, 0x1000, db->chip_id);
1154 db->cr6_data |= 0x40000; 1156 db->cr6_data |= 0x40000;
1155 update_cr6(db->cr6_data, db->ioaddr); 1157 update_cr6(db->cr6_data, ioaddr);
1156 db->timer.expires = DMFE_TIMER_WUT + HZ * 2; 1158 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
1157 add_timer(&db->timer); 1159 add_timer(&db->timer);
1158 spin_unlock_irqrestore(&db->lock, flags); 1160 spin_unlock_irqrestore(&db->lock, flags);
@@ -1167,7 +1169,7 @@ static void dmfe_timer(unsigned long data)
1167 db->dm910x_chk_mode = 0x4; 1169 db->dm910x_chk_mode = 0x4;
1168 1170
1169 /* Dynamic reset DM910X : system error or transmit time-out */ 1171 /* Dynamic reset DM910X : system error or transmit time-out */
1170 tmp_cr8 = inl(db->ioaddr + DCR8); 1172 tmp_cr8 = dr32(DCR8);
1171 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) { 1173 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1172 db->reset_cr8++; 1174 db->reset_cr8++;
1173 db->wait_reset = 1; 1175 db->wait_reset = 1;
@@ -1177,7 +1179,7 @@ static void dmfe_timer(unsigned long data)
1177 /* TX polling kick monitor */ 1179 /* TX polling kick monitor */
1178 if ( db->tx_packet_cnt && 1180 if ( db->tx_packet_cnt &&
1179 time_after(jiffies, dev_trans_start(dev) + DMFE_TX_KICK) ) { 1181 time_after(jiffies, dev_trans_start(dev) + DMFE_TX_KICK) ) {
1180 outl(0x1, dev->base_addr + DCR1); /* Tx polling again */ 1182 dw32(DCR1, 0x1); /* Tx polling again */
1181 1183
1182 /* TX Timeout */ 1184 /* TX Timeout */
1183 if (time_after(jiffies, dev_trans_start(dev) + DMFE_TX_TIMEOUT) ) { 1185 if (time_after(jiffies, dev_trans_start(dev) + DMFE_TX_TIMEOUT) ) {
@@ -1200,9 +1202,9 @@ static void dmfe_timer(unsigned long data)
1200 1202
1201 /* Link status check, Dynamic media type change */ 1203 /* Link status check, Dynamic media type change */
1202 if (db->chip_id == PCI_DM9132_ID) 1204 if (db->chip_id == PCI_DM9132_ID)
1203 tmp_cr12 = inb(db->ioaddr + DCR9 + 3); /* DM9132 */ 1205 tmp_cr12 = dr8(DCR9 + 3); /* DM9132 */
1204 else 1206 else
1205 tmp_cr12 = inb(db->ioaddr + DCR12); /* DM9102/DM9102A */ 1207 tmp_cr12 = dr8(DCR12); /* DM9102/DM9102A */
1206 1208
1207 if ( ((db->chip_id == PCI_DM9102_ID) && 1209 if ( ((db->chip_id == PCI_DM9102_ID) &&
1208 (db->chip_revision == 0x30)) || 1210 (db->chip_revision == 0x30)) ||
@@ -1251,7 +1253,7 @@ static void dmfe_timer(unsigned long data)
1251 /* 10/100M link failed, used 1M Home-Net */ 1253 /* 10/100M link failed, used 1M Home-Net */
1252 db->cr6_data|=0x00040000; /* bit18=1, MII */ 1254 db->cr6_data|=0x00040000; /* bit18=1, MII */
1253 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */ 1255 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1254 update_cr6(db->cr6_data, db->ioaddr); 1256 update_cr6(db->cr6_data, ioaddr);
1255 } 1257 }
1256 } else if (!netif_carrier_ok(dev)) { 1258 } else if (!netif_carrier_ok(dev)) {
1257 1259
@@ -1288,17 +1290,18 @@ static void dmfe_timer(unsigned long data)
1288 * Re-initialize DM910X board 1290 * Re-initialize DM910X board
1289 */ 1291 */
1290 1292
1291static void dmfe_dynamic_reset(struct DEVICE *dev) 1293static void dmfe_dynamic_reset(struct net_device *dev)
1292{ 1294{
1293 struct dmfe_board_info *db = netdev_priv(dev); 1295 struct dmfe_board_info *db = netdev_priv(dev);
1296 void __iomem *ioaddr = db->ioaddr;
1294 1297
1295 DMFE_DBUG(0, "dmfe_dynamic_reset()", 0); 1298 DMFE_DBUG(0, "dmfe_dynamic_reset()", 0);
1296 1299
1297 /* Sopt MAC controller */ 1300 /* Sopt MAC controller */
1298 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */ 1301 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1299 update_cr6(db->cr6_data, dev->base_addr); 1302 update_cr6(db->cr6_data, ioaddr);
1300 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */ 1303 dw32(DCR7, 0); /* Disable Interrupt */
1301 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5); 1304 dw32(DCR5, dr32(DCR5));
1302 1305
1303 /* Disable upper layer interface */ 1306 /* Disable upper layer interface */
1304 netif_stop_queue(dev); 1307 netif_stop_queue(dev);
@@ -1364,9 +1367,10 @@ static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb)
1364 * Using Chain structure, and allocate Tx/Rx buffer 1367 * Using Chain structure, and allocate Tx/Rx buffer
1365 */ 1368 */
1366 1369
1367static void dmfe_descriptor_init(struct net_device *dev, unsigned long ioaddr) 1370static void dmfe_descriptor_init(struct net_device *dev)
1368{ 1371{
1369 struct dmfe_board_info *db = netdev_priv(dev); 1372 struct dmfe_board_info *db = netdev_priv(dev);
1373 void __iomem *ioaddr = db->ioaddr;
1370 struct tx_desc *tmp_tx; 1374 struct tx_desc *tmp_tx;
1371 struct rx_desc *tmp_rx; 1375 struct rx_desc *tmp_rx;
1372 unsigned char *tmp_buf; 1376 unsigned char *tmp_buf;
@@ -1379,7 +1383,7 @@ static void dmfe_descriptor_init(struct net_device *dev, unsigned long ioaddr)
1379 /* tx descriptor start pointer */ 1383 /* tx descriptor start pointer */
1380 db->tx_insert_ptr = db->first_tx_desc; 1384 db->tx_insert_ptr = db->first_tx_desc;
1381 db->tx_remove_ptr = db->first_tx_desc; 1385 db->tx_remove_ptr = db->first_tx_desc;
1382 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */ 1386 dw32(DCR4, db->first_tx_desc_dma); /* TX DESC address */
1383 1387
1384 /* rx descriptor start pointer */ 1388 /* rx descriptor start pointer */
1385 db->first_rx_desc = (void *)db->first_tx_desc + 1389 db->first_rx_desc = (void *)db->first_tx_desc +
@@ -1389,7 +1393,7 @@ static void dmfe_descriptor_init(struct net_device *dev, unsigned long ioaddr)
1389 sizeof(struct tx_desc) * TX_DESC_CNT; 1393 sizeof(struct tx_desc) * TX_DESC_CNT;
1390 db->rx_insert_ptr = db->first_rx_desc; 1394 db->rx_insert_ptr = db->first_rx_desc;
1391 db->rx_ready_ptr = db->first_rx_desc; 1395 db->rx_ready_ptr = db->first_rx_desc;
1392 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */ 1396 dw32(DCR3, db->first_rx_desc_dma); /* RX DESC address */
1393 1397
1394 /* Init Transmit chain */ 1398 /* Init Transmit chain */
1395 tmp_buf = db->buf_pool_start; 1399 tmp_buf = db->buf_pool_start;
@@ -1431,14 +1435,14 @@ static void dmfe_descriptor_init(struct net_device *dev, unsigned long ioaddr)
1431 * Firstly stop DM910X , then written value and start 1435 * Firstly stop DM910X , then written value and start
1432 */ 1436 */
1433 1437
1434static void update_cr6(u32 cr6_data, unsigned long ioaddr) 1438static void update_cr6(u32 cr6_data, void __iomem *ioaddr)
1435{ 1439{
1436 u32 cr6_tmp; 1440 u32 cr6_tmp;
1437 1441
1438 cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */ 1442 cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
1439 outl(cr6_tmp, ioaddr + DCR6); 1443 dw32(DCR6, cr6_tmp);
1440 udelay(5); 1444 udelay(5);
1441 outl(cr6_data, ioaddr + DCR6); 1445 dw32(DCR6, cr6_data);
1442 udelay(5); 1446 udelay(5);
1443} 1447}
1444 1448
@@ -1448,24 +1452,19 @@ static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1448 * This setup frame initialize DM910X address filter mode 1452 * This setup frame initialize DM910X address filter mode
1449*/ 1453*/
1450 1454
1451static void dm9132_id_table(struct DEVICE *dev) 1455static void dm9132_id_table(struct net_device *dev)
1452{ 1456{
1457 struct dmfe_board_info *db = netdev_priv(dev);
1458 void __iomem *ioaddr = db->ioaddr + 0xc0;
1459 u16 *addrptr = (u16 *)dev->dev_addr;
1453 struct netdev_hw_addr *ha; 1460 struct netdev_hw_addr *ha;
1454 u16 * addrptr;
1455 unsigned long ioaddr = dev->base_addr+0xc0; /* ID Table */
1456 u32 hash_val;
1457 u16 i, hash_table[4]; 1461 u16 i, hash_table[4];
1458 1462
1459 DMFE_DBUG(0, "dm9132_id_table()", 0);
1460
1461 /* Node address */ 1463 /* Node address */
1462 addrptr = (u16 *) dev->dev_addr; 1464 for (i = 0; i < 3; i++) {
1463 outw(addrptr[0], ioaddr); 1465 dw16(0, addrptr[i]);
1464 ioaddr += 4; 1466 ioaddr += 4;
1465 outw(addrptr[1], ioaddr); 1467 }
1466 ioaddr += 4;
1467 outw(addrptr[2], ioaddr);
1468 ioaddr += 4;
1469 1468
1470 /* Clear Hash Table */ 1469 /* Clear Hash Table */
1471 memset(hash_table, 0, sizeof(hash_table)); 1470 memset(hash_table, 0, sizeof(hash_table));
@@ -1475,13 +1474,14 @@ static void dm9132_id_table(struct DEVICE *dev)
1475 1474
1476 /* the multicast address in Hash Table : 64 bits */ 1475 /* the multicast address in Hash Table : 64 bits */
1477 netdev_for_each_mc_addr(ha, dev) { 1476 netdev_for_each_mc_addr(ha, dev) {
1478 hash_val = cal_CRC((char *) ha->addr, 6, 0) & 0x3f; 1477 u32 hash_val = cal_CRC((char *)ha->addr, 6, 0) & 0x3f;
1478
1479 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16); 1479 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
1480 } 1480 }
1481 1481
1482 /* Write the hash table to MAC MD table */ 1482 /* Write the hash table to MAC MD table */
1483 for (i = 0; i < 4; i++, ioaddr += 4) 1483 for (i = 0; i < 4; i++, ioaddr += 4)
1484 outw(hash_table[i], ioaddr); 1484 dw16(0, hash_table[i]);
1485} 1485}
1486 1486
1487 1487
@@ -1490,7 +1490,7 @@ static void dm9132_id_table(struct DEVICE *dev)
1490 * This setup frame initialize DM910X address filter mode 1490 * This setup frame initialize DM910X address filter mode
1491 */ 1491 */
1492 1492
1493static void send_filter_frame(struct DEVICE *dev) 1493static void send_filter_frame(struct net_device *dev)
1494{ 1494{
1495 struct dmfe_board_info *db = netdev_priv(dev); 1495 struct dmfe_board_info *db = netdev_priv(dev);
1496 struct netdev_hw_addr *ha; 1496 struct netdev_hw_addr *ha;
@@ -1535,12 +1535,14 @@ static void send_filter_frame(struct DEVICE *dev)
1535 1535
1536 /* Resource Check and Send the setup packet */ 1536 /* Resource Check and Send the setup packet */
1537 if (!db->tx_packet_cnt) { 1537 if (!db->tx_packet_cnt) {
1538 void __iomem *ioaddr = db->ioaddr;
1539
1538 /* Resource Empty */ 1540 /* Resource Empty */
1539 db->tx_packet_cnt++; 1541 db->tx_packet_cnt++;
1540 txptr->tdes0 = cpu_to_le32(0x80000000); 1542 txptr->tdes0 = cpu_to_le32(0x80000000);
1541 update_cr6(db->cr6_data | 0x2000, dev->base_addr); 1543 update_cr6(db->cr6_data | 0x2000, ioaddr);
1542 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */ 1544 dw32(DCR1, 0x1); /* Issue Tx polling */
1543 update_cr6(db->cr6_data, dev->base_addr); 1545 update_cr6(db->cr6_data, ioaddr);
1544 dev->trans_start = jiffies; 1546 dev->trans_start = jiffies;
1545 } else 1547 } else
1546 db->tx_queue_cnt++; /* Put in TX queue */ 1548 db->tx_queue_cnt++; /* Put in TX queue */
@@ -1575,43 +1577,55 @@ static void allocate_rx_buffer(struct net_device *dev)
1575 db->rx_insert_ptr = rxptr; 1577 db->rx_insert_ptr = rxptr;
1576} 1578}
1577 1579
1580static void srom_clk_write(void __iomem *ioaddr, u32 data)
1581{
1582 static const u32 cmd[] = {
1583 CR9_SROM_READ | CR9_SRCS,
1584 CR9_SROM_READ | CR9_SRCS | CR9_SRCLK,
1585 CR9_SROM_READ | CR9_SRCS
1586 };
1587 int i;
1588
1589 for (i = 0; i < ARRAY_SIZE(cmd); i++) {
1590 dw32(DCR9, data | cmd[i]);
1591 udelay(5);
1592 }
1593}
1578 1594
1579/* 1595/*
1580 * Read one word data from the serial ROM 1596 * Read one word data from the serial ROM
1581 */ 1597 */
1582 1598static u16 read_srom_word(void __iomem *ioaddr, int offset)
1583static u16 read_srom_word(long ioaddr, int offset)
1584{ 1599{
1600 u16 srom_data;
1585 int i; 1601 int i;
1586 u16 srom_data = 0;
1587 long cr9_ioaddr = ioaddr + DCR9;
1588 1602
1589 outl(CR9_SROM_READ, cr9_ioaddr); 1603 dw32(DCR9, CR9_SROM_READ);
1590 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); 1604 dw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1591 1605
1592 /* Send the Read Command 110b */ 1606 /* Send the Read Command 110b */
1593 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr); 1607 srom_clk_write(ioaddr, SROM_DATA_1);
1594 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr); 1608 srom_clk_write(ioaddr, SROM_DATA_1);
1595 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr); 1609 srom_clk_write(ioaddr, SROM_DATA_0);
1596 1610
1597 /* Send the offset */ 1611 /* Send the offset */
1598 for (i = 5; i >= 0; i--) { 1612 for (i = 5; i >= 0; i--) {
1599 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0; 1613 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1600 SROM_CLK_WRITE(srom_data, cr9_ioaddr); 1614 srom_clk_write(ioaddr, srom_data);
1601 } 1615 }
1602 1616
1603 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); 1617 dw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1604 1618
1605 for (i = 16; i > 0; i--) { 1619 for (i = 16; i > 0; i--) {
1606 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr); 1620 dw32(DCR9, CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
1607 udelay(5); 1621 udelay(5);
1608 srom_data = (srom_data << 1) | 1622 srom_data = (srom_data << 1) |
1609 ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0); 1623 ((dr32(DCR9) & CR9_CRDOUT) ? 1 : 0);
1610 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); 1624 dw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1611 udelay(5); 1625 udelay(5);
1612 } 1626 }
1613 1627
1614 outl(CR9_SROM_READ, cr9_ioaddr); 1628 dw32(DCR9, CR9_SROM_READ);
1615 return srom_data; 1629 return srom_data;
1616} 1630}
1617 1631
@@ -1620,13 +1634,14 @@ static u16 read_srom_word(long ioaddr, int offset)
1620 * Auto sense the media mode 1634 * Auto sense the media mode
1621 */ 1635 */
1622 1636
1623static u8 dmfe_sense_speed(struct dmfe_board_info * db) 1637static u8 dmfe_sense_speed(struct dmfe_board_info *db)
1624{ 1638{
1639 void __iomem *ioaddr = db->ioaddr;
1625 u8 ErrFlag = 0; 1640 u8 ErrFlag = 0;
1626 u16 phy_mode; 1641 u16 phy_mode;
1627 1642
1628 /* CR6 bit18=0, select 10/100M */ 1643 /* CR6 bit18=0, select 10/100M */
1629 update_cr6( (db->cr6_data & ~0x40000), db->ioaddr); 1644 update_cr6(db->cr6_data & ~0x40000, ioaddr);
1630 1645
1631 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id); 1646 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1632 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id); 1647 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
@@ -1665,11 +1680,12 @@ static u8 dmfe_sense_speed(struct dmfe_board_info * db)
1665 1680
1666static void dmfe_set_phyxcer(struct dmfe_board_info *db) 1681static void dmfe_set_phyxcer(struct dmfe_board_info *db)
1667{ 1682{
1683 void __iomem *ioaddr = db->ioaddr;
1668 u16 phy_reg; 1684 u16 phy_reg;
1669 1685
1670 /* Select 10/100M phyxcer */ 1686 /* Select 10/100M phyxcer */
1671 db->cr6_data &= ~0x40000; 1687 db->cr6_data &= ~0x40000;
1672 update_cr6(db->cr6_data, db->ioaddr); 1688 update_cr6(db->cr6_data, ioaddr);
1673 1689
1674 /* DM9009 Chip: Phyxcer reg18 bit12=0 */ 1690 /* DM9009 Chip: Phyxcer reg18 bit12=0 */
1675 if (db->chip_id == PCI_DM9009_ID) { 1691 if (db->chip_id == PCI_DM9009_ID) {
@@ -1765,18 +1781,15 @@ static void dmfe_process_mode(struct dmfe_board_info *db)
1765 * Write a word to Phy register 1781 * Write a word to Phy register
1766 */ 1782 */
1767 1783
1768static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, 1784static void phy_write(void __iomem *ioaddr, u8 phy_addr, u8 offset,
1769 u16 phy_data, u32 chip_id) 1785 u16 phy_data, u32 chip_id)
1770{ 1786{
1771 u16 i; 1787 u16 i;
1772 unsigned long ioaddr;
1773 1788
1774 if (chip_id == PCI_DM9132_ID) { 1789 if (chip_id == PCI_DM9132_ID) {
1775 ioaddr = iobase + 0x80 + offset * 4; 1790 dw16(0x80 + offset * 4, phy_data);
1776 outw(phy_data, ioaddr);
1777 } else { 1791 } else {
1778 /* DM9102/DM9102A Chip */ 1792 /* DM9102/DM9102A Chip */
1779 ioaddr = iobase + DCR9;
1780 1793
1781 /* Send 33 synchronization clock to Phy controller */ 1794 /* Send 33 synchronization clock to Phy controller */
1782 for (i = 0; i < 35; i++) 1795 for (i = 0; i < 35; i++)
@@ -1816,19 +1829,16 @@ static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
1816 * Read a word data from phy register 1829 * Read a word data from phy register
1817 */ 1830 */
1818 1831
1819static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id) 1832static u16 phy_read(void __iomem *ioaddr, u8 phy_addr, u8 offset, u32 chip_id)
1820{ 1833{
1821 int i; 1834 int i;
1822 u16 phy_data; 1835 u16 phy_data;
1823 unsigned long ioaddr;
1824 1836
1825 if (chip_id == PCI_DM9132_ID) { 1837 if (chip_id == PCI_DM9132_ID) {
1826 /* DM9132 Chip */ 1838 /* DM9132 Chip */
1827 ioaddr = iobase + 0x80 + offset * 4; 1839 phy_data = dr16(0x80 + offset * 4);
1828 phy_data = inw(ioaddr);
1829 } else { 1840 } else {
1830 /* DM9102/DM9102A Chip */ 1841 /* DM9102/DM9102A Chip */
1831 ioaddr = iobase + DCR9;
1832 1842
1833 /* Send 33 synchronization clock to Phy controller */ 1843 /* Send 33 synchronization clock to Phy controller */
1834 for (i = 0; i < 35; i++) 1844 for (i = 0; i < 35; i++)
@@ -1870,13 +1880,13 @@ static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1870 * Write one bit data to Phy Controller 1880 * Write one bit data to Phy Controller
1871 */ 1881 */
1872 1882
1873static void phy_write_1bit(unsigned long ioaddr, u32 phy_data) 1883static void phy_write_1bit(void __iomem *ioaddr, u32 phy_data)
1874{ 1884{
1875 outl(phy_data, ioaddr); /* MII Clock Low */ 1885 dw32(DCR9, phy_data); /* MII Clock Low */
1876 udelay(1); 1886 udelay(1);
1877 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */ 1887 dw32(DCR9, phy_data | MDCLKH); /* MII Clock High */
1878 udelay(1); 1888 udelay(1);
1879 outl(phy_data, ioaddr); /* MII Clock Low */ 1889 dw32(DCR9, phy_data); /* MII Clock Low */
1880 udelay(1); 1890 udelay(1);
1881} 1891}
1882 1892
@@ -1885,14 +1895,14 @@ static void phy_write_1bit(unsigned long ioaddr, u32 phy_data)
1885 * Read one bit phy data from PHY controller 1895 * Read one bit phy data from PHY controller
1886 */ 1896 */
1887 1897
1888static u16 phy_read_1bit(unsigned long ioaddr) 1898static u16 phy_read_1bit(void __iomem *ioaddr)
1889{ 1899{
1890 u16 phy_data; 1900 u16 phy_data;
1891 1901
1892 outl(0x50000, ioaddr); 1902 dw32(DCR9, 0x50000);
1893 udelay(1); 1903 udelay(1);
1894 phy_data = ( inl(ioaddr) >> 19 ) & 0x1; 1904 phy_data = (dr32(DCR9) >> 19) & 0x1;
1895 outl(0x40000, ioaddr); 1905 dw32(DCR9, 0x40000);
1896 udelay(1); 1906 udelay(1);
1897 1907
1898 return phy_data; 1908 return phy_data;
@@ -1978,7 +1988,7 @@ static void dmfe_parse_srom(struct dmfe_board_info * db)
1978 1988
1979 /* Check DM9801 or DM9802 present or not */ 1989 /* Check DM9801 or DM9802 present or not */
1980 db->HPNA_present = 0; 1990 db->HPNA_present = 0;
1981 update_cr6(db->cr6_data|0x40000, db->ioaddr); 1991 update_cr6(db->cr6_data | 0x40000, db->ioaddr);
1982 tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id); 1992 tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
1983 if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) { 1993 if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) {
1984 /* DM9801 or DM9802 present */ 1994 /* DM9801 or DM9802 present */
@@ -2095,6 +2105,7 @@ static int dmfe_suspend(struct pci_dev *pci_dev, pm_message_t state)
2095{ 2105{
2096 struct net_device *dev = pci_get_drvdata(pci_dev); 2106 struct net_device *dev = pci_get_drvdata(pci_dev);
2097 struct dmfe_board_info *db = netdev_priv(dev); 2107 struct dmfe_board_info *db = netdev_priv(dev);
2108 void __iomem *ioaddr = db->ioaddr;
2098 u32 tmp; 2109 u32 tmp;
2099 2110
2100 /* Disable upper layer interface */ 2111 /* Disable upper layer interface */
@@ -2102,11 +2113,11 @@ static int dmfe_suspend(struct pci_dev *pci_dev, pm_message_t state)
2102 2113
2103 /* Disable Tx/Rx */ 2114 /* Disable Tx/Rx */
2104 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); 2115 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC);
2105 update_cr6(db->cr6_data, dev->base_addr); 2116 update_cr6(db->cr6_data, ioaddr);
2106 2117
2107 /* Disable Interrupt */ 2118 /* Disable Interrupt */
2108 outl(0, dev->base_addr + DCR7); 2119 dw32(DCR7, 0);
2109 outl(inl (dev->base_addr + DCR5), dev->base_addr + DCR5); 2120 dw32(DCR5, dr32(DCR5));
2110 2121
2111 /* Fre RX buffers */ 2122 /* Fre RX buffers */
2112 dmfe_free_rxbuffer(db); 2123 dmfe_free_rxbuffer(db);