net/macb: fix ISR clear-on-write behavior only for some SoC

Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using the Design Configuration Register 1 information and a capability
property to actually activate this clear-on-write behavior on ISR.

Reported-by: Hein Tibosch <hein_tibosch@yahoo.es>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Tested-by: Hein Tibosch <hein_tibosch@yahoo.es>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 7 insertions, 0 deletions

diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 993d70380688..548c0ecae869 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -300,6 +300,8 @@
 #define MACB_REV_SIZE                           16
 
 /* Bitfields in DCFG1. */
+#define GEM_IRQCOR_OFFSET                       23
+#define GEM_IRQCOR_SIZE                         1
 #define GEM_DBWDEF_OFFSET                       25
 #define GEM_DBWDEF_SIZE                         3
 
@@ -323,6 +325,9 @@
 #define MACB_MAN_READ                           2
 #define MACB_MAN_CODE                           2
 
+/* Capability mask bits */
+#define MACB_CAPS_ISR_CLEAR_ON_WRITE            0x1
+
 /* Bit manipulation macros */
 #define MACB_BIT(name)                                  \
         (1 << MACB_##name##_OFFSET)
@@ -574,6 +579,8 @@ struct macb {
         unsigned int            speed;
         unsigned int            duplex;
 
+        u32                     caps;
+
         phy_interface_t         phy_interface;
 
         /* AT91RM9200 transmit */