diff options
author | Arun Chandran <achandran@mvista.com> | 2015-02-18 06:29:35 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2015-02-20 15:51:31 -0500 |
commit | a50dad355a5314da64586da36804b86fbebb7c2a (patch) | |
tree | e0b41be8f30ee85291d349454b32989bc7602e06 /drivers/net/ethernet/cadence/macb.c | |
parent | 931c471af51565a6290d9fabbe14ed7c8fa4a317 (diff) |
net: macb: Add big endian CPU support
This patch converts all __raw_readl and __raw_writel function calls
to their corresponding readl_relaxed and writel_relaxed variants.
It also tells the driver to set ahb_endian_swp_mgmt_en bit in dma_cfg
when the CPU is configured in big endian mode.
Signed-off-by: Arun Chandran <achandran@mvista.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/cadence/macb.c')
-rw-r--r-- | drivers/net/ethernet/cadence/macb.c | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c index ad76b8e35a00..05fb36da0cff 100644 --- a/drivers/net/ethernet/cadence/macb.c +++ b/drivers/net/ethernet/cadence/macb.c | |||
@@ -449,7 +449,7 @@ static void macb_update_stats(struct macb *bp) | |||
449 | WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4); | 449 | WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4); |
450 | 450 | ||
451 | for(; p < end; p++, reg++) | 451 | for(; p < end; p++, reg++) |
452 | *p += __raw_readl(reg); | 452 | *p += readl_relaxed(reg); |
453 | } | 453 | } |
454 | 454 | ||
455 | static int macb_halt_tx(struct macb *bp) | 455 | static int macb_halt_tx(struct macb *bp) |
@@ -1585,7 +1585,11 @@ static void macb_configure_dma(struct macb *bp) | |||
1585 | if (bp->dma_burst_length) | 1585 | if (bp->dma_burst_length) |
1586 | dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg); | 1586 | dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg); |
1587 | dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L); | 1587 | dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L); |
1588 | dmacfg &= ~GEM_BIT(ENDIA); | 1588 | dmacfg &= ~GEM_BIT(ENDIA_PKT); |
1589 | /* Tell the chip to byteswap descriptors on big-endian hosts */ | ||
1590 | #ifdef __BIG_ENDIAN | ||
1591 | dmacfg |= GEM_BIT(ENDIA_DESC); | ||
1592 | #endif | ||
1589 | if (bp->dev->features & NETIF_F_HW_CSUM) | 1593 | if (bp->dev->features & NETIF_F_HW_CSUM) |
1590 | dmacfg |= GEM_BIT(TXCOEN); | 1594 | dmacfg |= GEM_BIT(TXCOEN); |
1591 | else | 1595 | else |
@@ -1832,14 +1836,14 @@ static void gem_update_stats(struct macb *bp) | |||
1832 | 1836 | ||
1833 | for (i = 0; i < GEM_STATS_LEN; ++i, ++p) { | 1837 | for (i = 0; i < GEM_STATS_LEN; ++i, ++p) { |
1834 | u32 offset = gem_statistics[i].offset; | 1838 | u32 offset = gem_statistics[i].offset; |
1835 | u64 val = __raw_readl(bp->regs + offset); | 1839 | u64 val = readl_relaxed(bp->regs + offset); |
1836 | 1840 | ||
1837 | bp->ethtool_stats[i] += val; | 1841 | bp->ethtool_stats[i] += val; |
1838 | *p += val; | 1842 | *p += val; |
1839 | 1843 | ||
1840 | if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) { | 1844 | if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) { |
1841 | /* Add GEM_OCTTXH, GEM_OCTRXH */ | 1845 | /* Add GEM_OCTTXH, GEM_OCTRXH */ |
1842 | val = __raw_readl(bp->regs + offset + 4); | 1846 | val = readl_relaxed(bp->regs + offset + 4); |
1843 | bp->ethtool_stats[i] += ((u64)val) << 32; | 1847 | bp->ethtool_stats[i] += ((u64)val) << 32; |
1844 | *(++p) += val; | 1848 | *(++p) += val; |
1845 | } | 1849 | } |
@@ -2191,12 +2195,14 @@ static void macb_probe_queues(void __iomem *mem, | |||
2191 | *num_queues = 1; | 2195 | *num_queues = 1; |
2192 | 2196 | ||
2193 | /* is it macb or gem ? */ | 2197 | /* is it macb or gem ? */ |
2194 | mid = __raw_readl(mem + MACB_MID); | 2198 | mid = readl_relaxed(mem + MACB_MID); |
2199 | |||
2195 | if (MACB_BFEXT(IDNUM, mid) != 0x2) | 2200 | if (MACB_BFEXT(IDNUM, mid) != 0x2) |
2196 | return; | 2201 | return; |
2197 | 2202 | ||
2198 | /* bit 0 is never set but queue 0 always exists */ | 2203 | /* bit 0 is never set but queue 0 always exists */ |
2199 | *queue_mask = __raw_readl(mem + GEM_DCFG6) & 0xff; | 2204 | *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff; |
2205 | |||
2200 | *queue_mask |= 0x1; | 2206 | *queue_mask |= 0x1; |
2201 | 2207 | ||
2202 | for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q) | 2208 | for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q) |