diff options
author | Nithin Sujir <nsujir@broadcom.com> | 2013-09-20 19:46:55 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2013-09-21 14:04:51 -0400 |
commit | 3ab7107133289324b77c466bb40617c5fdd24f0c (patch) | |
tree | 7ab1d3c84c1c04049a68c5c591ab269ea4ef4753 /drivers/net/ethernet/broadcom | |
parent | 8dda204164131ff56fffc5443c475d8ed57d5ebd (diff) |
tg3: Add function tg3_phy_shdw_write()
For consistency with other register access functions, add shadow
register access function of the type (register/val).
Signed-off-by: Nithin Nayak Sujir <nsujir@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/broadcom')
-rw-r--r-- | drivers/net/ethernet/broadcom/tg3.c | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c index 12d961c4ebca..bcb92d497b44 100644 --- a/drivers/net/ethernet/broadcom/tg3.c +++ b/drivers/net/ethernet/broadcom/tg3.c | |||
@@ -1326,6 +1326,12 @@ static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable) | |||
1326 | return err; | 1326 | return err; |
1327 | } | 1327 | } |
1328 | 1328 | ||
1329 | static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val) | ||
1330 | { | ||
1331 | return tg3_writephy(tp, MII_TG3_MISC_SHDW, | ||
1332 | reg | val | MII_TG3_MISC_SHDW_WREN); | ||
1333 | } | ||
1334 | |||
1329 | static int tg3_bmcr_reset(struct tg3 *tp) | 1335 | static int tg3_bmcr_reset(struct tg3 *tp) |
1330 | { | 1336 | { |
1331 | u32 phy_control; | 1337 | u32 phy_control; |
@@ -2218,25 +2224,21 @@ static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) | |||
2218 | return; | 2224 | return; |
2219 | } | 2225 | } |
2220 | 2226 | ||
2221 | reg = MII_TG3_MISC_SHDW_WREN | | 2227 | reg = MII_TG3_MISC_SHDW_SCR5_LPED | |
2222 | MII_TG3_MISC_SHDW_SCR5_SEL | | ||
2223 | MII_TG3_MISC_SHDW_SCR5_LPED | | ||
2224 | MII_TG3_MISC_SHDW_SCR5_DLPTLM | | 2228 | MII_TG3_MISC_SHDW_SCR5_DLPTLM | |
2225 | MII_TG3_MISC_SHDW_SCR5_SDTL | | 2229 | MII_TG3_MISC_SHDW_SCR5_SDTL | |
2226 | MII_TG3_MISC_SHDW_SCR5_C125OE; | 2230 | MII_TG3_MISC_SHDW_SCR5_C125OE; |
2227 | if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable) | 2231 | if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable) |
2228 | reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD; | 2232 | reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD; |
2229 | 2233 | ||
2230 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | 2234 | tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg); |
2231 | 2235 | ||
2232 | 2236 | ||
2233 | reg = MII_TG3_MISC_SHDW_WREN | | 2237 | reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS; |
2234 | MII_TG3_MISC_SHDW_APD_SEL | | ||
2235 | MII_TG3_MISC_SHDW_APD_WKTM_84MS; | ||
2236 | if (enable) | 2238 | if (enable) |
2237 | reg |= MII_TG3_MISC_SHDW_APD_ENABLE; | 2239 | reg |= MII_TG3_MISC_SHDW_APD_ENABLE; |
2238 | 2240 | ||
2239 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | 2241 | tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg); |
2240 | } | 2242 | } |
2241 | 2243 | ||
2242 | static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable) | 2244 | static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable) |