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authorMatt Carlson <mcarlson@broadcom.com>2011-12-14 06:09:59 -0500
committerDavid S. Miller <davem@davemloft.net>2011-12-15 13:09:11 -0500
commit55086ad95d740577def0b4e6ecc2c0ae9b0d6dec (patch)
treee8a838935811370991a509178f14b6849d64974f /drivers/net/ethernet/broadcom/tg3.c
parenta4cb428d31e11af1662e19c6fab9133c0f7a0eda (diff)
tg3: Add 57766 ASIC rev support
This patch adds support for the 57766 ASIC revision. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Reviewed-by: Benjamin Li <benli@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/broadcom/tg3.c')
-rw-r--r--drivers/net/ethernet/broadcom/tg3.c58
1 files changed, 41 insertions, 17 deletions
diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
index 9c9a4b4a9f69..90ef94292a9c 100644
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
@@ -199,6 +199,7 @@ static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
199 199
200/* minimum number of free TX descriptors required to wake up TX process */ 200/* minimum number of free TX descriptors required to wake up TX process */
201#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4) 201#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
202#define TG3_TX_BD_DMA_MAX_2K 2048
202#define TG3_TX_BD_DMA_MAX_4K 4096 203#define TG3_TX_BD_DMA_MAX_4K 4096
203 204
204#define TG3_RAW_IP_ALIGN 2 205#define TG3_RAW_IP_ALIGN 2
@@ -2154,7 +2155,7 @@ static void tg3_phy_eee_enable(struct tg3 *tp)
2154 if (tp->link_config.active_speed == SPEED_1000 && 2155 if (tp->link_config.active_speed == SPEED_1000 &&
2155 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || 2156 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2156 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || 2157 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2157 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) && 2158 tg3_flag(tp, 57765_CLASS)) &&
2158 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { 2159 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2159 val = MII_TG3_DSP_TAP26_ALNOKO | 2160 val = MII_TG3_DSP_TAP26_ALNOKO |
2160 MII_TG3_DSP_TAP26_RMRXSTO; 2161 MII_TG3_DSP_TAP26_RMRXSTO;
@@ -2673,8 +2674,7 @@ static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2673 bool need_vaux = false; 2674 bool need_vaux = false;
2674 2675
2675 /* The GPIOs do something completely different on 57765. */ 2676 /* The GPIOs do something completely different on 57765. */
2676 if (!tg3_flag(tp, IS_NIC) || 2677 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2677 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2678 return; 2678 return;
2679 2679
2680 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || 2680 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
@@ -3631,6 +3631,7 @@ static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
3631 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) { 3631 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
3632 case ASIC_REV_5717: 3632 case ASIC_REV_5717:
3633 case ASIC_REV_57765: 3633 case ASIC_REV_57765:
3634 case ASIC_REV_57766:
3634 case ASIC_REV_5719: 3635 case ASIC_REV_5719:
3635 /* If we advertised any eee advertisements above... */ 3636 /* If we advertised any eee advertisements above... */
3636 if (val) 3637 if (val)
@@ -8081,7 +8082,7 @@ static void tg3_rings_reset(struct tg3 *tp)
8081 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; 8082 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
8082 else if (tg3_flag(tp, 5717_PLUS)) 8083 else if (tg3_flag(tp, 5717_PLUS))
8083 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; 8084 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
8084 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) 8085 else if (tg3_flag(tp, 57765_CLASS))
8085 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; 8086 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
8086 else 8087 else
8087 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; 8088 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
@@ -8098,7 +8099,7 @@ static void tg3_rings_reset(struct tg3 *tp)
8098 else if (!tg3_flag(tp, 5705_PLUS)) 8099 else if (!tg3_flag(tp, 5705_PLUS))
8099 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16; 8100 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
8100 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || 8101 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8101 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) 8102 tg3_flag(tp, 57765_CLASS))
8102 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; 8103 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
8103 else 8104 else
8104 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; 8105 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
@@ -8342,7 +8343,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8342 tw32(GRC_MODE, grc_mode); 8343 tw32(GRC_MODE, grc_mode);
8343 } 8344 }
8344 8345
8345 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { 8346 if (tg3_flag(tp, 57765_CLASS)) {
8346 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { 8347 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
8347 u32 grc_mode = tr32(GRC_MODE); 8348 u32 grc_mode = tr32(GRC_MODE);
8348 8349
@@ -8430,7 +8431,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8430 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT; 8431 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
8431 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) 8432 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
8432 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK; 8433 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
8433 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 && 8434 if (!tg3_flag(tp, 57765_CLASS) &&
8434 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) 8435 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8435 val |= DMA_RWCTRL_TAGGED_STAT_WA; 8436 val |= DMA_RWCTRL_TAGGED_STAT_WA;
8436 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); 8437 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
@@ -8577,7 +8578,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8577 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, 8578 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8578 val | BDINFO_FLAGS_USE_EXT_RECV); 8579 val | BDINFO_FLAGS_USE_EXT_RECV);
8579 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) || 8580 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
8580 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) 8581 tg3_flag(tp, 57765_CLASS))
8581 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR, 8582 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8582 NIC_SRAM_RX_JUMBO_BUFFER_DESC); 8583 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
8583 } else { 8584 } else {
@@ -8663,6 +8664,9 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8663 if (tg3_flag(tp, PCI_EXPRESS)) 8664 if (tg3_flag(tp, PCI_EXPRESS))
8664 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; 8665 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8665 8666
8667 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766)
8668 rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
8669
8666 if (tg3_flag(tp, HW_TSO_1) || 8670 if (tg3_flag(tp, HW_TSO_1) ||
8667 tg3_flag(tp, HW_TSO_2) || 8671 tg3_flag(tp, HW_TSO_2) ||
8668 tg3_flag(tp, HW_TSO_3)) 8672 tg3_flag(tp, HW_TSO_3))
@@ -9004,7 +9008,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
9004 /* Prevent chip from dropping frames when flow control 9008 /* Prevent chip from dropping frames when flow control
9005 * is enabled. 9009 * is enabled.
9006 */ 9010 */
9007 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) 9011 if (tg3_flag(tp, 57765_CLASS))
9008 val = 1; 9012 val = 1;
9009 else 9013 else
9010 val = 2; 9014 val = 2;
@@ -9219,7 +9223,7 @@ static void tg3_timer(unsigned long __opaque)
9219 spin_lock(&tp->lock); 9223 spin_lock(&tp->lock);
9220 9224
9221 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || 9225 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
9222 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) 9226 tg3_flag(tp, 57765_CLASS))
9223 tg3_chk_missed_msi(tp); 9227 tg3_chk_missed_msi(tp);
9224 9228
9225 if (!tg3_flag(tp, TAGGED_STATUS)) { 9229 if (!tg3_flag(tp, TAGGED_STATUS)) {
@@ -9702,8 +9706,8 @@ static int tg3_open(struct net_device *dev)
9702 tg3_free_rings(tp); 9706 tg3_free_rings(tp);
9703 } else { 9707 } else {
9704 if (tg3_flag(tp, TAGGED_STATUS) && 9708 if (tg3_flag(tp, TAGGED_STATUS) &&
9705 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && 9709 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
9706 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) 9710 !tg3_flag(tp, 57765_CLASS))
9707 tp->timer_offset = HZ; 9711 tp->timer_offset = HZ;
9708 else 9712 else
9709 tp->timer_offset = HZ / 10; 9713 tp->timer_offset = HZ / 10;
@@ -11358,7 +11362,7 @@ static int tg3_test_memory(struct tg3 *tp)
11358 11362
11359 if (tg3_flag(tp, 5717_PLUS)) 11363 if (tg3_flag(tp, 5717_PLUS))
11360 mem_tbl = mem_tbl_5717; 11364 mem_tbl = mem_tbl_5717;
11361 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) 11365 else if (tg3_flag(tp, 57765_CLASS))
11362 mem_tbl = mem_tbl_57765; 11366 mem_tbl = mem_tbl_57765;
11363 else if (tg3_flag(tp, 5755_PLUS)) 11367 else if (tg3_flag(tp, 5755_PLUS))
11364 mem_tbl = mem_tbl_5755; 11368 mem_tbl = mem_tbl_5755;
@@ -12619,7 +12623,7 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
12619 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) 12623 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12620 tg3_get_5906_nvram_info(tp); 12624 tg3_get_5906_nvram_info(tp);
12621 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || 12625 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12622 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) 12626 tg3_flag(tp, 57765_CLASS))
12623 tg3_get_57780_nvram_info(tp); 12627 tg3_get_57780_nvram_info(tp);
12624 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || 12628 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12625 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) 12629 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
@@ -13463,6 +13467,17 @@ out_no_vpd:
13463 strcpy(tp->board_part_number, "BCM57795"); 13467 strcpy(tp->board_part_number, "BCM57795");
13464 else 13468 else
13465 goto nomatch; 13469 goto nomatch;
13470 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) {
13471 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
13472 strcpy(tp->board_part_number, "BCM57762");
13473 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
13474 strcpy(tp->board_part_number, "BCM57766");
13475 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
13476 strcpy(tp->board_part_number, "BCM57782");
13477 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
13478 strcpy(tp->board_part_number, "BCM57786");
13479 else
13480 goto nomatch;
13466 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { 13481 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13467 strcpy(tp->board_part_number, "BCM95906"); 13482 strcpy(tp->board_part_number, "BCM95906");
13468 } else { 13483 } else {
@@ -13801,7 +13816,11 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13801 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || 13816 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13802 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || 13817 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13803 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || 13818 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13804 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) 13819 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13820 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
13821 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
13822 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
13823 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
13805 pci_read_config_dword(tp->pdev, 13824 pci_read_config_dword(tp->pdev,
13806 TG3PCI_GEN15_PRODID_ASICREV, 13825 TG3PCI_GEN15_PRODID_ASICREV,
13807 &prod_id_asic_rev); 13826 &prod_id_asic_rev);
@@ -13948,7 +13967,10 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13948 tg3_flag_set(tp, 5717_PLUS); 13967 tg3_flag_set(tp, 5717_PLUS);
13949 13968
13950 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 || 13969 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
13951 tg3_flag(tp, 5717_PLUS)) 13970 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766)
13971 tg3_flag_set(tp, 57765_CLASS);
13972
13973 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS))
13952 tg3_flag_set(tp, 57765_PLUS); 13974 tg3_flag_set(tp, 57765_PLUS);
13953 13975
13954 /* Intentionally exclude ASIC_REV_5906 */ 13976 /* Intentionally exclude ASIC_REV_5906 */
@@ -14042,6 +14064,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
14042 14064
14043 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) 14065 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
14044 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K; 14066 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
14067 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766)
14068 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
14045 14069
14046 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || 14070 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14047 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || 14071 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
@@ -14325,7 +14349,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
14325 14349
14326 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || 14350 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14327 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || 14351 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14328 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) 14352 tg3_flag(tp, 57765_CLASS))
14329 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; 14353 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
14330 14354
14331 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || 14355 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||