enic: Add support for multiple hardware receive queues

Add support for multiple hardware receive queues. The ingress traffic is hashed into one of the receive queues based on IP or TCP or both headers. The max no. of receive queues supported is 8.

Signed-off-by: Vasanthy Kolluri <vkolluri@cisco.com>
Signed-off-by: Roopa Prabhu <roprabhu@cisco.com>
Signed-off-by: David Wang <dwang2@cisco.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 30 insertions, 19 deletions

diff --git a/drivers/net/enic/enic_res.c b/drivers/net/enic/enic_res.c
index 19a276cf7681..f111a37419ce 100644
--- a/drivers/net/enic/enic_res.c
+++ b/drivers/net/enic/enic_res.c
@@ -35,6 +35,7 @@
 #include "vnic_intr.h"
 #include "vnic_stats.h"
 #include "vnic_nic.h"
+#include "vnic_rss.h"
 #include "enic_res.h"
 #include "enic.h"
 
@@ -93,13 +94,14 @@ int enic_get_vnic_config(struct enic *enic)
                 INTR_COALESCE_HW_TO_USEC(VNIC_INTR_TIMER_MAX),
                 c->intr_timer_usec);
 
-        dev_info(enic_get_dev(enic), "vNIC MAC addr %pM wq/rq %d/%d\n",
-                enic->mac_addr, c->wq_desc_count, c->rq_desc_count);
-        dev_info(enic_get_dev(enic), "vNIC mtu %d csum tx/rx %d/%d "
-                "tso/lro %d/%d intr timer %d usec\n",
-                c->mtu, ENIC_SETTING(enic, TXCSUM),
-                ENIC_SETTING(enic, RXCSUM), ENIC_SETTING(enic, TSO),
-                ENIC_SETTING(enic, LRO), c->intr_timer_usec);
+        dev_info(enic_get_dev(enic),
+                "vNIC MAC addr %pM wq/rq %d/%d mtu %d\n",
+                enic->mac_addr, c->wq_desc_count, c->rq_desc_count, c->mtu);
+        dev_info(enic_get_dev(enic), "vNIC csum tx/rx %d/%d "
+                "tso/lro %d/%d intr timer %d usec rss %d\n",
+                ENIC_SETTING(enic, TXCSUM), ENIC_SETTING(enic, RXCSUM),
+                ENIC_SETTING(enic, TSO), ENIC_SETTING(enic, LRO),
+                c->intr_timer_usec, ENIC_SETTING(enic, RSS));
 
         return 0;
 }
@@ -148,6 +150,22 @@ int enic_set_nic_cfg(struct enic *enic, u8 rss_default_cpu, u8 rss_hash_type,
         return vnic_dev_cmd(enic->vdev, CMD_NIC_CFG, &a0, &a1, wait);
 }
 
+int enic_set_rss_key(struct enic *enic, dma_addr_t key_pa, u64 len)
+{
+        u64 a0 = (u64)key_pa, a1 = len;
+        int wait = 1000;
+
+        return vnic_dev_cmd(enic->vdev, CMD_RSS_KEY, &a0, &a1, wait);
+}
+
+int enic_set_rss_cpu(struct enic *enic, dma_addr_t cpu_pa, u64 len)
+{
+        u64 a0 = (u64)cpu_pa, a1 = len;
+        int wait = 1000;
+
+        return vnic_dev_cmd(enic->vdev, CMD_RSS_CPU, &a0, &a1, wait);
+}
+
 void enic_free_vnic_resources(struct enic *enic)
 {
         unsigned int i;
@@ -164,18 +182,11 @@ void enic_free_vnic_resources(struct enic *enic)
 
 void enic_get_res_counts(struct enic *enic)
 {
-        enic->wq_count = min_t(int,
-                vnic_dev_get_res_count(enic->vdev, RES_TYPE_WQ),
-                ENIC_WQ_MAX);
-        enic->rq_count = min_t(int,
-                vnic_dev_get_res_count(enic->vdev, RES_TYPE_RQ),
-                ENIC_RQ_MAX);
-        enic->cq_count = min_t(int,
-                vnic_dev_get_res_count(enic->vdev, RES_TYPE_CQ),
-                ENIC_CQ_MAX);
-        enic->intr_count = min_t(int,
-                vnic_dev_get_res_count(enic->vdev, RES_TYPE_INTR_CTRL),
-                ENIC_INTR_MAX);
+        enic->wq_count = vnic_dev_get_res_count(enic->vdev, RES_TYPE_WQ);
+        enic->rq_count = vnic_dev_get_res_count(enic->vdev, RES_TYPE_RQ);
+        enic->cq_count = vnic_dev_get_res_count(enic->vdev, RES_TYPE_CQ);
+        enic->intr_count = vnic_dev_get_res_count(enic->vdev,
+                RES_TYPE_INTR_CTRL);
 
         dev_info(enic_get_dev(enic),
                 "vNIC resources avail: wq %d rq %d cq %d intr %d\n",