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authorVasanthy Kolluri <vkolluri@cisco.com>2010-10-20 06:16:59 -0400
committerDavid S. Miller <davem@davemloft.net>2010-10-21 04:26:47 -0400
commit717258ba4b3ecca9c7c0ef2b76d7aa5800242bad (patch)
treed82deb82352401aa9b3877c2b99fec348e3b583d /drivers/net/enic/enic.h
parente0e8ab596012d8c2147beb3c8b70d2d6ab90acda (diff)
enic: Add support for multiple hardware receive queues
Add support for multiple hardware receive queues. The ingress traffic is hashed into one of the receive queues based on IP or TCP or both headers. The max no. of receive queues supported is 8. Signed-off-by: Vasanthy Kolluri <vkolluri@cisco.com> Signed-off-by: Roopa Prabhu <roprabhu@cisco.com> Signed-off-by: David Wang <dwang2@cisco.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/enic/enic.h')
-rw-r--r--drivers/net/enic/enic.h28
1 files changed, 5 insertions, 23 deletions
diff --git a/drivers/net/enic/enic.h b/drivers/net/enic/enic.h
index ae623206f180..c91d364c5527 100644
--- a/drivers/net/enic/enic.h
+++ b/drivers/net/enic/enic.h
@@ -28,10 +28,11 @@
28#include "vnic_intr.h" 28#include "vnic_intr.h"
29#include "vnic_stats.h" 29#include "vnic_stats.h"
30#include "vnic_nic.h" 30#include "vnic_nic.h"
31#include "vnic_rss.h"
31 32
32#define DRV_NAME "enic" 33#define DRV_NAME "enic"
33#define DRV_DESCRIPTION "Cisco VIC Ethernet NIC Driver" 34#define DRV_DESCRIPTION "Cisco VIC Ethernet NIC Driver"
34#define DRV_VERSION "1.4.1.2a" 35#define DRV_VERSION "1.4.1.6"
35#define DRV_COPYRIGHT "Copyright 2008-2010 Cisco Systems, Inc" 36#define DRV_COPYRIGHT "Copyright 2008-2010 Cisco Systems, Inc"
36 37
37#define ENIC_BARS_MAX 6 38#define ENIC_BARS_MAX 6
@@ -41,25 +42,6 @@
41#define ENIC_CQ_MAX (ENIC_WQ_MAX + ENIC_RQ_MAX) 42#define ENIC_CQ_MAX (ENIC_WQ_MAX + ENIC_RQ_MAX)
42#define ENIC_INTR_MAX (ENIC_CQ_MAX + 2) 43#define ENIC_INTR_MAX (ENIC_CQ_MAX + 2)
43 44
44enum enic_cq_index {
45 ENIC_CQ_RQ,
46 ENIC_CQ_WQ,
47};
48
49enum enic_intx_intr_index {
50 ENIC_INTX_WQ_RQ,
51 ENIC_INTX_ERR,
52 ENIC_INTX_NOTIFY,
53};
54
55enum enic_msix_intr_index {
56 ENIC_MSIX_RQ,
57 ENIC_MSIX_WQ,
58 ENIC_MSIX_ERR,
59 ENIC_MSIX_NOTIFY,
60 ENIC_MSIX_MAX,
61};
62
63struct enic_msix_entry { 45struct enic_msix_entry {
64 int requested; 46 int requested;
65 char devname[IFNAMSIZ]; 47 char devname[IFNAMSIZ];
@@ -90,8 +72,8 @@ struct enic {
90 struct vnic_dev *vdev; 72 struct vnic_dev *vdev;
91 struct timer_list notify_timer; 73 struct timer_list notify_timer;
92 struct work_struct reset; 74 struct work_struct reset;
93 struct msix_entry msix_entry[ENIC_MSIX_MAX]; 75 struct msix_entry msix_entry[ENIC_INTR_MAX];
94 struct enic_msix_entry msix[ENIC_MSIX_MAX]; 76 struct enic_msix_entry msix[ENIC_INTR_MAX];
95 u32 msg_enable; 77 u32 msg_enable;
96 spinlock_t devcmd_lock; 78 spinlock_t devcmd_lock;
97 u8 mac_addr[ETH_ALEN]; 79 u8 mac_addr[ETH_ALEN];
@@ -118,7 +100,7 @@ struct enic {
118 int (*rq_alloc_buf)(struct vnic_rq *rq); 100 int (*rq_alloc_buf)(struct vnic_rq *rq);
119 u64 rq_truncated_pkts; 101 u64 rq_truncated_pkts;
120 u64 rq_bad_fcs; 102 u64 rq_bad_fcs;
121 struct napi_struct napi; 103 struct napi_struct napi[ENIC_RQ_MAX];
122 104
123 /* interrupt resource cache line section */ 105 /* interrupt resource cache line section */
124 ____cacheline_aligned struct vnic_intr intr[ENIC_INTR_MAX]; 106 ____cacheline_aligned struct vnic_intr intr[ENIC_INTR_MAX];