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authorBruce Allan <bruce.w.allan@intel.com>2010-06-17 14:59:48 -0400
committerDavid S. Miller <davem@davemloft.net>2010-06-23 15:58:40 -0400
commit17f085df92ba74a4dc88744cbc7a699c231f8728 (patch)
treeb76afd6210f027cdce6b50cf3cf862c68feff7ff /drivers/net/e1000e
parentdbcb9fec5c79780152e32282297de6ddb1f6a43b (diff)
e1000e: disable gig speed when in S0->Sx transition
Most of this workaround is necessary for all ICHx/PCH parts so one of the two MAC-type checks can be removed. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/e1000e')
-rw-r--r--drivers/net/e1000e/ich8lan.c19
1 files changed, 5 insertions, 14 deletions
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c
index c7292a1a81ef..6b5e108bb51f 100644
--- a/drivers/net/e1000e/ich8lan.c
+++ b/drivers/net/e1000e/ich8lan.c
@@ -3457,21 +3457,12 @@ void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3457{ 3457{
3458 u32 phy_ctrl; 3458 u32 phy_ctrl;
3459 3459
3460 switch (hw->mac.type) { 3460 phy_ctrl = er32(PHY_CTRL);
3461 case e1000_ich8lan: 3461 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
3462 case e1000_ich9lan: 3462 ew32(PHY_CTRL, phy_ctrl);
3463 case e1000_ich10lan:
3464 case e1000_pchlan:
3465 phy_ctrl = er32(PHY_CTRL);
3466 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
3467 E1000_PHY_CTRL_GBE_DISABLE;
3468 ew32(PHY_CTRL, phy_ctrl);
3469 3463
3470 if (hw->mac.type == e1000_pchlan) 3464 if (hw->mac.type >= e1000_pchlan)
3471 e1000_phy_hw_reset_ich8lan(hw); 3465 e1000_phy_hw_reset_ich8lan(hw);
3472 default:
3473 break;
3474 }
3475} 3466}
3476 3467
3477/** 3468/**