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authorBruce Allan <bruce.w.allan@intel.com>2009-12-01 10:51:11 -0500
committerDavid S. Miller <davem@davemloft.net>2009-12-02 03:35:54 -0500
commit5ff5b664351a94754031c1e5783f0cea6b3000ed (patch)
tree09ff7ddacd94175b78879548179f108c1593efc1 /drivers/net/e1000e
parent9e135a2e6266eba276f33c404a2478499bc07ff5 (diff)
e1000e: comment corrections
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/e1000e')
-rw-r--r--drivers/net/e1000e/82571.c2
-rw-r--r--drivers/net/e1000e/ich8lan.c5
-rw-r--r--drivers/net/e1000e/lib.c5
-rw-r--r--drivers/net/e1000e/phy.c14
4 files changed, 11 insertions, 15 deletions
diff --git a/drivers/net/e1000e/82571.c b/drivers/net/e1000e/82571.c
index 227f3d03ba2a..f6f3a2289e03 100644
--- a/drivers/net/e1000e/82571.c
+++ b/drivers/net/e1000e/82571.c
@@ -1551,7 +1551,7 @@ bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1551 * @hw: pointer to the HW structure 1551 * @hw: pointer to the HW structure
1552 * @state: enable/disable locally administered address 1552 * @state: enable/disable locally administered address
1553 * 1553 *
1554 * Enable/Disable the current locally administers address state. 1554 * Enable/Disable the current locally administered address state.
1555 **/ 1555 **/
1556void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state) 1556void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1557{ 1557{
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c
index fbbc6ddfde80..1ce2bf97fa37 100644
--- a/drivers/net/e1000e/ich8lan.c
+++ b/drivers/net/e1000e/ich8lan.c
@@ -1747,7 +1747,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1747 if (hsfsts.hsf_status.flcinprog == 0) { 1747 if (hsfsts.hsf_status.flcinprog == 0) {
1748 /* 1748 /*
1749 * There is no cycle running at present, 1749 * There is no cycle running at present,
1750 * so we can start a cycle 1750 * so we can start a cycle.
1751 * Begin by setting Flash Cycle Done. 1751 * Begin by setting Flash Cycle Done.
1752 */ 1752 */
1753 hsfsts.hsf_status.flcdone = 1; 1753 hsfsts.hsf_status.flcdone = 1;
@@ -1755,7 +1755,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1755 ret_val = 0; 1755 ret_val = 0;
1756 } else { 1756 } else {
1757 /* 1757 /*
1758 * otherwise poll for sometime so the current 1758 * Otherwise poll for sometime so the current
1759 * cycle has a chance to end before giving up. 1759 * cycle has a chance to end before giving up.
1760 */ 1760 */
1761 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 1761 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
@@ -2645,7 +2645,6 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2645 ctrl |= E1000_CTRL_PHY_RST; 2645 ctrl |= E1000_CTRL_PHY_RST;
2646 } 2646 }
2647 ret_val = e1000_acquire_swflag_ich8lan(hw); 2647 ret_val = e1000_acquire_swflag_ich8lan(hw);
2648 /* Whether or not the swflag was acquired, we need to reset the part */
2649 e_dbg("Issuing a global reset to ich8lan\n"); 2648 e_dbg("Issuing a global reset to ich8lan\n");
2650 ew32(CTRL, (ctrl | E1000_CTRL_RST)); 2649 ew32(CTRL, (ctrl | E1000_CTRL_RST));
2651 msleep(20); 2650 msleep(20);
diff --git a/drivers/net/e1000e/lib.c b/drivers/net/e1000e/lib.c
index e3976ea668d0..a86c17548c1e 100644
--- a/drivers/net/e1000e/lib.c
+++ b/drivers/net/e1000e/lib.c
@@ -1086,7 +1086,6 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1086 * 1 | 1 | 0 | 0 | e1000_fc_none 1086 * 1 | 1 | 0 | 0 | e1000_fc_none
1087 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1087 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1088 * 1088 *
1089 *
1090 * Are both PAUSE bits set to 1? If so, this implies 1089 * Are both PAUSE bits set to 1? If so, this implies
1091 * Symmetric Flow Control is enabled at both ends. The 1090 * Symmetric Flow Control is enabled at both ends. The
1092 * ASM_DIR bits are irrelevant per the spec. 1091 * ASM_DIR bits are irrelevant per the spec.
@@ -1124,7 +1123,6 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1124 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1123 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1125 *-------|---------|-------|---------|-------------------- 1124 *-------|---------|-------|---------|--------------------
1126 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1125 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1127 *
1128 */ 1126 */
1129 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1127 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1130 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1128 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
@@ -1140,7 +1138,6 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1140 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1138 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1141 *-------|---------|-------|---------|-------------------- 1139 *-------|---------|-------|---------|--------------------
1142 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1140 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1143 *
1144 */ 1141 */
1145 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1142 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1146 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1143 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
@@ -2363,7 +2360,7 @@ static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
2363} 2360}
2364 2361
2365/** 2362/**
2366 * e1000_mng_host_if_write - Writes to the manageability host interface 2363 * e1000_mng_host_if_write - Write to the manageability host interface
2367 * @hw: pointer to the HW structure 2364 * @hw: pointer to the HW structure
2368 * @buffer: pointer to the host interface buffer 2365 * @buffer: pointer to the host interface buffer
2369 * @length: size of the buffer 2366 * @length: size of the buffer
diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c
index 140b23b320fd..1bc09b240e62 100644
--- a/drivers/net/e1000e/phy.c
+++ b/drivers/net/e1000e/phy.c
@@ -153,10 +153,10 @@ s32 e1000e_get_phy_id(struct e1000_hw *hw)
153 goto out; 153 goto out;
154 154
155 /* 155 /*
156 * If the PHY ID is still unknown, we may have an 82577i 156 * If the PHY ID is still unknown, we may have an 82577
157 * without link. We will try again after setting Slow 157 * without link. We will try again after setting Slow MDIC
158 * MDIC mode. No harm in trying again in this case since 158 * mode. No harm in trying again in this case since the PHY
159 * the PHY ID is unknown at this point anyway 159 * ID is unknown at this point anyway.
160 */ 160 */
161 ret_val = phy->ops.acquire(hw); 161 ret_val = phy->ops.acquire(hw);
162 if (ret_val) 162 if (ret_val)
@@ -1744,7 +1744,7 @@ out:
1744 * The automatic gain control (agc) normalizes the amplitude of the 1744 * The automatic gain control (agc) normalizes the amplitude of the
1745 * received signal, adjusting for the attenuation produced by the 1745 * received signal, adjusting for the attenuation produced by the
1746 * cable. By reading the AGC registers, which represent the 1746 * cable. By reading the AGC registers, which represent the
1747 * combination of course and fine gain value, the value can be put 1747 * combination of coarse and fine gain value, the value can be put
1748 * into a lookup table to obtain the approximate cable length 1748 * into a lookup table to obtain the approximate cable length
1749 * for each channel. 1749 * for each channel.
1750 **/ 1750 **/
@@ -1769,7 +1769,7 @@ s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1769 1769
1770 /* 1770 /*
1771 * Getting bits 15:9, which represent the combination of 1771 * Getting bits 15:9, which represent the combination of
1772 * course and fine gain values. The result is a number 1772 * coarse and fine gain values. The result is a number
1773 * that can be put into the lookup table to obtain the 1773 * that can be put into the lookup table to obtain the
1774 * approximate cable length. 1774 * approximate cable length.
1775 */ 1775 */
@@ -2511,7 +2511,7 @@ static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2511 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 2511 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2512 data); 2512 data);
2513 } else { 2513 } else {
2514 /* Read the page 800 value using opcode 0x12 */ 2514 /* Write the page 800 value using opcode 0x12 */
2515 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 2515 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2516 *data); 2516 *data);
2517 } 2517 }