diff options
author | Bruce Allan <bruce.w.allan@intel.com> | 2008-08-26 21:36:50 -0400 |
---|---|---|
committer | Jeff Garzik <jgarzik@redhat.com> | 2008-09-03 10:06:47 -0400 |
commit | f4187b56e1f8a05dd110875d5094b21b51ebd79b (patch) | |
tree | 7c3f97f98c808b6f6ab8ea6acdfb2f324e8a3c09 /drivers/net/e1000e | |
parent | 2f15f9d60190a62bc8ac50fa84fea31fc0b00ecf (diff) |
e1000e: add support for 82567LM-3 and 82567LF-3 (ICH10D) parts
Add support for new LOM devices on the latest generation ICHx platforms.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/net/e1000e')
-rw-r--r-- | drivers/net/e1000e/defines.h | 2 | ||||
-rw-r--r-- | drivers/net/e1000e/e1000.h | 3 | ||||
-rw-r--r-- | drivers/net/e1000e/ethtool.c | 22 | ||||
-rw-r--r-- | drivers/net/e1000e/hw.h | 3 | ||||
-rw-r--r-- | drivers/net/e1000e/ich8lan.c | 154 | ||||
-rw-r--r-- | drivers/net/e1000e/netdev.c | 25 | ||||
-rw-r--r-- | drivers/net/e1000e/phy.c | 85 |
7 files changed, 280 insertions, 14 deletions
diff --git a/drivers/net/e1000e/defines.h b/drivers/net/e1000e/defines.h index 14b0e6cd3b8d..4b21fa99d68e 100644 --- a/drivers/net/e1000e/defines.h +++ b/drivers/net/e1000e/defines.h | |||
@@ -505,6 +505,7 @@ | |||
505 | #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ | 505 | #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ |
506 | 506 | ||
507 | /* Autoneg Expansion Register */ | 507 | /* Autoneg Expansion Register */ |
508 | #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ | ||
508 | 509 | ||
509 | /* 1000BASE-T Control Register */ | 510 | /* 1000BASE-T Control Register */ |
510 | #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ | 511 | #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ |
@@ -540,6 +541,7 @@ | |||
540 | #define E1000_EECD_DO 0x00000008 /* NVM Data Out */ | 541 | #define E1000_EECD_DO 0x00000008 /* NVM Data Out */ |
541 | #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ | 542 | #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ |
542 | #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ | 543 | #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ |
544 | #define E1000_EECD_PRES 0x00000100 /* NVM Present */ | ||
543 | #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ | 545 | #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ |
544 | /* NVM Addressing bits based on type (0-small, 1-large) */ | 546 | /* NVM Addressing bits based on type (0-small, 1-large) */ |
545 | #define E1000_EECD_ADDR_BITS 0x00000400 | 547 | #define E1000_EECD_ADDR_BITS 0x00000400 |
diff --git a/drivers/net/e1000e/e1000.h b/drivers/net/e1000e/e1000.h index ac4e506b4f88..ef66dc44fae6 100644 --- a/drivers/net/e1000e/e1000.h +++ b/drivers/net/e1000e/e1000.h | |||
@@ -98,6 +98,7 @@ enum e1000_boards { | |||
98 | board_80003es2lan, | 98 | board_80003es2lan, |
99 | board_ich8lan, | 99 | board_ich8lan, |
100 | board_ich9lan, | 100 | board_ich9lan, |
101 | board_ich10lan, | ||
101 | }; | 102 | }; |
102 | 103 | ||
103 | struct e1000_queue_stats { | 104 | struct e1000_queue_stats { |
@@ -374,6 +375,7 @@ extern struct e1000_info e1000_82572_info; | |||
374 | extern struct e1000_info e1000_82573_info; | 375 | extern struct e1000_info e1000_82573_info; |
375 | extern struct e1000_info e1000_ich8_info; | 376 | extern struct e1000_info e1000_ich8_info; |
376 | extern struct e1000_info e1000_ich9_info; | 377 | extern struct e1000_info e1000_ich9_info; |
378 | extern struct e1000_info e1000_ich10_info; | ||
377 | extern struct e1000_info e1000_es2_info; | 379 | extern struct e1000_info e1000_es2_info; |
378 | 380 | ||
379 | extern s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num); | 381 | extern s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num); |
@@ -446,6 +448,7 @@ extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw); | |||
446 | extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw); | 448 | extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw); |
447 | extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); | 449 | extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); |
448 | extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); | 450 | extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); |
451 | extern s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw); | ||
449 | extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id); | 452 | extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id); |
450 | extern s32 e1000e_determine_phy_address(struct e1000_hw *hw); | 453 | extern s32 e1000e_determine_phy_address(struct e1000_hw *hw); |
451 | extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data); | 454 | extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data); |
diff --git a/drivers/net/e1000e/ethtool.c b/drivers/net/e1000e/ethtool.c index e21c9e0f3738..a89498dcb636 100644 --- a/drivers/net/e1000e/ethtool.c +++ b/drivers/net/e1000e/ethtool.c | |||
@@ -781,6 +781,7 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data) | |||
781 | case e1000_82573: | 781 | case e1000_82573: |
782 | case e1000_ich8lan: | 782 | case e1000_ich8lan: |
783 | case e1000_ich9lan: | 783 | case e1000_ich9lan: |
784 | case e1000_ich10lan: | ||
784 | toggle = 0x7FFFF033; | 785 | toggle = 0x7FFFF033; |
785 | break; | 786 | break; |
786 | default: | 787 | default: |
@@ -833,7 +834,9 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data) | |||
833 | REG_PATTERN_TEST(E1000_TIDV, 0x0000FFFF, 0x0000FFFF); | 834 | REG_PATTERN_TEST(E1000_TIDV, 0x0000FFFF, 0x0000FFFF); |
834 | for (i = 0; i < mac->rar_entry_count; i++) | 835 | for (i = 0; i < mac->rar_entry_count; i++) |
835 | REG_PATTERN_TEST_ARRAY(E1000_RA, ((i << 1) + 1), | 836 | REG_PATTERN_TEST_ARRAY(E1000_RA, ((i << 1) + 1), |
836 | 0x8003FFFF, 0xFFFFFFFF); | 837 | ((mac->type == e1000_ich10lan) ? |
838 | 0x8007FFFF : 0x8003FFFF), | ||
839 | 0xFFFFFFFF); | ||
837 | 840 | ||
838 | for (i = 0; i < mac->mta_reg_count; i++) | 841 | for (i = 0; i < mac->mta_reg_count; i++) |
839 | REG_PATTERN_TEST_ARRAY(E1000_MTA, i, 0xFFFFFFFF, 0xFFFFFFFF); | 842 | REG_PATTERN_TEST_ARRAY(E1000_MTA, i, 0xFFFFFFFF, 0xFFFFFFFF); |
@@ -905,12 +908,23 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data) | |||
905 | 908 | ||
906 | /* Test each interrupt */ | 909 | /* Test each interrupt */ |
907 | for (i = 0; i < 10; i++) { | 910 | for (i = 0; i < 10; i++) { |
908 | if ((adapter->flags & FLAG_IS_ICH) && (i == 8)) | ||
909 | continue; | ||
910 | |||
911 | /* Interrupt to test */ | 911 | /* Interrupt to test */ |
912 | mask = 1 << i; | 912 | mask = 1 << i; |
913 | 913 | ||
914 | if (adapter->flags & FLAG_IS_ICH) { | ||
915 | switch (mask) { | ||
916 | case E1000_ICR_RXSEQ: | ||
917 | continue; | ||
918 | case 0x00000100: | ||
919 | if (adapter->hw.mac.type == e1000_ich8lan || | ||
920 | adapter->hw.mac.type == e1000_ich9lan) | ||
921 | continue; | ||
922 | break; | ||
923 | default: | ||
924 | break; | ||
925 | } | ||
926 | } | ||
927 | |||
914 | if (!shared_int) { | 928 | if (!shared_int) { |
915 | /* | 929 | /* |
916 | * Disable the interrupt to be reported in | 930 | * Disable the interrupt to be reported in |
diff --git a/drivers/net/e1000e/hw.h b/drivers/net/e1000e/hw.h index d0e7b461aaf7..5d2acc531b5c 100644 --- a/drivers/net/e1000e/hw.h +++ b/drivers/net/e1000e/hw.h | |||
@@ -357,6 +357,8 @@ enum e1e_registers { | |||
357 | #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC | 357 | #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC |
358 | #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD | 358 | #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD |
359 | #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE | 359 | #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE |
360 | #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE | ||
361 | #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF | ||
360 | 362 | ||
361 | #define E1000_FUNC_1 1 | 363 | #define E1000_FUNC_1 1 |
362 | 364 | ||
@@ -367,6 +369,7 @@ enum e1000_mac_type { | |||
367 | e1000_80003es2lan, | 369 | e1000_80003es2lan, |
368 | e1000_ich8lan, | 370 | e1000_ich8lan, |
369 | e1000_ich9lan, | 371 | e1000_ich9lan, |
372 | e1000_ich10lan, | ||
370 | }; | 373 | }; |
371 | 374 | ||
372 | enum e1000_media_type { | 375 | enum e1000_media_type { |
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c index b5fc2c903044..0e76bb0378fd 100644 --- a/drivers/net/e1000e/ich8lan.c +++ b/drivers/net/e1000e/ich8lan.c | |||
@@ -43,7 +43,8 @@ | |||
43 | * 82567LM-2 Gigabit Network Connection | 43 | * 82567LM-2 Gigabit Network Connection |
44 | * 82567LF-2 Gigabit Network Connection | 44 | * 82567LF-2 Gigabit Network Connection |
45 | * 82567V-2 Gigabit Network Connection | 45 | * 82567V-2 Gigabit Network Connection |
46 | * 82562GT-3 10/100 Network Connection | 46 | * 82567LF-3 Gigabit Network Connection |
47 | * 82567LM-3 Gigabit Network Connection | ||
47 | * 82567LM-4 Gigabit Network Connection | 48 | * 82567LM-4 Gigabit Network Connection |
48 | */ | 49 | */ |
49 | 50 | ||
@@ -158,12 +159,15 @@ static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw); | |||
158 | static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); | 159 | static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); |
159 | static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, | 160 | static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, |
160 | u32 offset, u8 byte); | 161 | u32 offset, u8 byte); |
162 | static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, | ||
163 | u8 *data); | ||
161 | static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, | 164 | static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, |
162 | u16 *data); | 165 | u16 *data); |
163 | static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, | 166 | static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, |
164 | u8 size, u16 *data); | 167 | u8 size, u16 *data); |
165 | static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); | 168 | static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); |
166 | static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); | 169 | static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); |
170 | static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); | ||
167 | 171 | ||
168 | static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) | 172 | static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) |
169 | { | 173 | { |
@@ -898,6 +902,56 @@ static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) | |||
898 | } | 902 | } |
899 | 903 | ||
900 | /** | 904 | /** |
905 | * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 | ||
906 | * @hw: pointer to the HW structure | ||
907 | * @bank: pointer to the variable that returns the active bank | ||
908 | * | ||
909 | * Reads signature byte from the NVM using the flash access registers. | ||
910 | **/ | ||
911 | static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) | ||
912 | { | ||
913 | struct e1000_nvm_info *nvm = &hw->nvm; | ||
914 | /* flash bank size is in words */ | ||
915 | u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); | ||
916 | u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; | ||
917 | u8 bank_high_byte = 0; | ||
918 | |||
919 | if (hw->mac.type != e1000_ich10lan) { | ||
920 | if (er32(EECD) & E1000_EECD_SEC1VAL) | ||
921 | *bank = 1; | ||
922 | else | ||
923 | *bank = 0; | ||
924 | } else { | ||
925 | /* | ||
926 | * Make sure the signature for bank 0 is valid, | ||
927 | * if not check for bank1 | ||
928 | */ | ||
929 | e1000_read_flash_byte_ich8lan(hw, act_offset, &bank_high_byte); | ||
930 | if ((bank_high_byte & 0xC0) == 0x80) { | ||
931 | *bank = 0; | ||
932 | } else { | ||
933 | /* | ||
934 | * find if segment 1 is valid by verifying | ||
935 | * bit 15:14 = 10b in word 0x13 | ||
936 | */ | ||
937 | e1000_read_flash_byte_ich8lan(hw, | ||
938 | act_offset + bank1_offset, | ||
939 | &bank_high_byte); | ||
940 | |||
941 | /* bank1 has a valid signature equivalent to SEC1V */ | ||
942 | if ((bank_high_byte & 0xC0) == 0x80) { | ||
943 | *bank = 1; | ||
944 | } else { | ||
945 | hw_dbg(hw, "ERROR: EEPROM not present\n"); | ||
946 | return -E1000_ERR_NVM; | ||
947 | } | ||
948 | } | ||
949 | } | ||
950 | |||
951 | return 0; | ||
952 | } | ||
953 | |||
954 | /** | ||
901 | * e1000_read_nvm_ich8lan - Read word(s) from the NVM | 955 | * e1000_read_nvm_ich8lan - Read word(s) from the NVM |
902 | * @hw: pointer to the HW structure | 956 | * @hw: pointer to the HW structure |
903 | * @offset: The offset (in bytes) of the word(s) to read. | 957 | * @offset: The offset (in bytes) of the word(s) to read. |
@@ -913,6 +967,7 @@ static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, | |||
913 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | 967 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
914 | u32 act_offset; | 968 | u32 act_offset; |
915 | s32 ret_val; | 969 | s32 ret_val; |
970 | u32 bank = 0; | ||
916 | u16 i, word; | 971 | u16 i, word; |
917 | 972 | ||
918 | if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || | 973 | if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || |
@@ -925,10 +980,11 @@ static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, | |||
925 | if (ret_val) | 980 | if (ret_val) |
926 | return ret_val; | 981 | return ret_val; |
927 | 982 | ||
928 | /* Start with the bank offset, then add the relative offset. */ | 983 | ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); |
929 | act_offset = (er32(EECD) & E1000_EECD_SEC1VAL) | 984 | if (ret_val) |
930 | ? nvm->flash_bank_size | 985 | return ret_val; |
931 | : 0; | 986 | |
987 | act_offset = (bank) ? nvm->flash_bank_size : 0; | ||
932 | act_offset += offset; | 988 | act_offset += offset; |
933 | 989 | ||
934 | for (i = 0; i < words; i++) { | 990 | for (i = 0; i < words; i++) { |
@@ -1076,6 +1132,29 @@ static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, | |||
1076 | } | 1132 | } |
1077 | 1133 | ||
1078 | /** | 1134 | /** |
1135 | * e1000_read_flash_byte_ich8lan - Read byte from flash | ||
1136 | * @hw: pointer to the HW structure | ||
1137 | * @offset: The offset of the byte to read. | ||
1138 | * @data: Pointer to a byte to store the value read. | ||
1139 | * | ||
1140 | * Reads a single byte from the NVM using the flash access registers. | ||
1141 | **/ | ||
1142 | static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, | ||
1143 | u8 *data) | ||
1144 | { | ||
1145 | s32 ret_val; | ||
1146 | u16 word = 0; | ||
1147 | |||
1148 | ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); | ||
1149 | if (ret_val) | ||
1150 | return ret_val; | ||
1151 | |||
1152 | *data = (u8)word; | ||
1153 | |||
1154 | return 0; | ||
1155 | } | ||
1156 | |||
1157 | /** | ||
1079 | * e1000_read_flash_data_ich8lan - Read byte or word from NVM | 1158 | * e1000_read_flash_data_ich8lan - Read byte or word from NVM |
1080 | * @hw: pointer to the HW structure | 1159 | * @hw: pointer to the HW structure |
1081 | * @offset: The offset (in bytes) of the byte or word to read. | 1160 | * @offset: The offset (in bytes) of the byte or word to read. |
@@ -1206,7 +1285,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) | |||
1206 | { | 1285 | { |
1207 | struct e1000_nvm_info *nvm = &hw->nvm; | 1286 | struct e1000_nvm_info *nvm = &hw->nvm; |
1208 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | 1287 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
1209 | u32 i, act_offset, new_bank_offset, old_bank_offset; | 1288 | u32 i, act_offset, new_bank_offset, old_bank_offset, bank; |
1210 | s32 ret_val; | 1289 | s32 ret_val; |
1211 | u16 data; | 1290 | u16 data; |
1212 | 1291 | ||
@@ -1226,7 +1305,11 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) | |||
1226 | * write to bank 0 etc. We also need to erase the segment that | 1305 | * write to bank 0 etc. We also need to erase the segment that |
1227 | * is going to be written | 1306 | * is going to be written |
1228 | */ | 1307 | */ |
1229 | if (!(er32(EECD) & E1000_EECD_SEC1VAL)) { | 1308 | ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); |
1309 | if (ret_val) | ||
1310 | return ret_val; | ||
1311 | |||
1312 | if (bank == 0) { | ||
1230 | new_bank_offset = nvm->flash_bank_size; | 1313 | new_bank_offset = nvm->flash_bank_size; |
1231 | old_bank_offset = 0; | 1314 | old_bank_offset = 0; |
1232 | e1000_erase_flash_bank_ich8lan(hw, 1); | 1315 | e1000_erase_flash_bank_ich8lan(hw, 1); |
@@ -2190,13 +2273,14 @@ void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) | |||
2190 | * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation | 2273 | * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation |
2191 | * to a lower speed. | 2274 | * to a lower speed. |
2192 | * | 2275 | * |
2193 | * Should only be called for ICH9 devices. | 2276 | * Should only be called for ICH9 and ICH10 devices. |
2194 | **/ | 2277 | **/ |
2195 | void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw) | 2278 | void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw) |
2196 | { | 2279 | { |
2197 | u32 phy_ctrl; | 2280 | u32 phy_ctrl; |
2198 | 2281 | ||
2199 | if (hw->mac.type == e1000_ich9lan) { | 2282 | if ((hw->mac.type == e1000_ich10lan) || |
2283 | (hw->mac.type == e1000_ich9lan)) { | ||
2200 | phy_ctrl = er32(PHY_CTRL); | 2284 | phy_ctrl = er32(PHY_CTRL); |
2201 | phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | | 2285 | phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | |
2202 | E1000_PHY_CTRL_GBE_DISABLE; | 2286 | E1000_PHY_CTRL_GBE_DISABLE; |
@@ -2254,6 +2338,39 @@ static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) | |||
2254 | } | 2338 | } |
2255 | 2339 | ||
2256 | /** | 2340 | /** |
2341 | * e1000_get_cfg_done_ich8lan - Read config done bit | ||
2342 | * @hw: pointer to the HW structure | ||
2343 | * | ||
2344 | * Read the management control register for the config done bit for | ||
2345 | * completion status. NOTE: silicon which is EEPROM-less will fail trying | ||
2346 | * to read the config done bit, so an error is *ONLY* logged and returns | ||
2347 | * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon | ||
2348 | * would not be able to be reset or change link. | ||
2349 | **/ | ||
2350 | static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) | ||
2351 | { | ||
2352 | u32 bank = 0; | ||
2353 | |||
2354 | e1000e_get_cfg_done(hw); | ||
2355 | |||
2356 | /* If EEPROM is not marked present, init the IGP 3 PHY manually */ | ||
2357 | if (hw->mac.type != e1000_ich10lan) { | ||
2358 | if (((er32(EECD) & E1000_EECD_PRES) == 0) && | ||
2359 | (hw->phy.type == e1000_phy_igp_3)) { | ||
2360 | e1000e_phy_init_script_igp3(hw); | ||
2361 | } | ||
2362 | } else { | ||
2363 | if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { | ||
2364 | /* Maybe we should do a basic PHY config */ | ||
2365 | hw_dbg(hw, "EEPROM not present\n"); | ||
2366 | return -E1000_ERR_CONFIG; | ||
2367 | } | ||
2368 | } | ||
2369 | |||
2370 | return 0; | ||
2371 | } | ||
2372 | |||
2373 | /** | ||
2257 | * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters | 2374 | * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters |
2258 | * @hw: pointer to the HW structure | 2375 | * @hw: pointer to the HW structure |
2259 | * | 2376 | * |
@@ -2303,7 +2420,7 @@ static struct e1000_phy_operations ich8_phy_ops = { | |||
2303 | .check_reset_block = e1000_check_reset_block_ich8lan, | 2420 | .check_reset_block = e1000_check_reset_block_ich8lan, |
2304 | .commit_phy = NULL, | 2421 | .commit_phy = NULL, |
2305 | .force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan, | 2422 | .force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan, |
2306 | .get_cfg_done = e1000e_get_cfg_done, | 2423 | .get_cfg_done = e1000_get_cfg_done_ich8lan, |
2307 | .get_cable_length = e1000e_get_cable_length_igp_2, | 2424 | .get_cable_length = e1000e_get_cable_length_igp_2, |
2308 | .get_phy_info = e1000_get_phy_info_ich8lan, | 2425 | .get_phy_info = e1000_get_phy_info_ich8lan, |
2309 | .read_phy_reg = e1000e_read_phy_reg_igp, | 2426 | .read_phy_reg = e1000e_read_phy_reg_igp, |
@@ -2358,3 +2475,20 @@ struct e1000_info e1000_ich9_info = { | |||
2358 | .nvm_ops = &ich8_nvm_ops, | 2475 | .nvm_ops = &ich8_nvm_ops, |
2359 | }; | 2476 | }; |
2360 | 2477 | ||
2478 | struct e1000_info e1000_ich10_info = { | ||
2479 | .mac = e1000_ich10lan, | ||
2480 | .flags = FLAG_HAS_JUMBO_FRAMES | ||
2481 | | FLAG_IS_ICH | ||
2482 | | FLAG_HAS_WOL | ||
2483 | | FLAG_RX_CSUM_ENABLED | ||
2484 | | FLAG_HAS_CTRLEXT_ON_LOAD | ||
2485 | | FLAG_HAS_AMT | ||
2486 | | FLAG_HAS_ERT | ||
2487 | | FLAG_HAS_FLASH | ||
2488 | | FLAG_APME_IN_WUC, | ||
2489 | .pba = 10, | ||
2490 | .get_variants = e1000_get_variants_ich8lan, | ||
2491 | .mac_ops = &ich8_mac_ops, | ||
2492 | .phy_ops = &ich8_phy_ops, | ||
2493 | .nvm_ops = &ich8_nvm_ops, | ||
2494 | }; | ||
diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c index c3d74115a6b9..2d9bcb02d093 100644 --- a/drivers/net/e1000e/netdev.c +++ b/drivers/net/e1000e/netdev.c | |||
@@ -58,6 +58,7 @@ static const struct e1000_info *e1000_info_tbl[] = { | |||
58 | [board_80003es2lan] = &e1000_es2_info, | 58 | [board_80003es2lan] = &e1000_es2_info, |
59 | [board_ich8lan] = &e1000_ich8_info, | 59 | [board_ich8lan] = &e1000_ich8_info, |
60 | [board_ich9lan] = &e1000_ich9_info, | 60 | [board_ich9lan] = &e1000_ich9_info, |
61 | [board_ich10lan] = &e1000_ich10_info, | ||
61 | }; | 62 | }; |
62 | 63 | ||
63 | #ifdef DEBUG | 64 | #ifdef DEBUG |
@@ -3201,6 +3202,27 @@ static void e1000_watchdog_task(struct work_struct *work) | |||
3201 | &adapter->link_duplex); | 3202 | &adapter->link_duplex); |
3202 | e1000_print_link_info(adapter); | 3203 | e1000_print_link_info(adapter); |
3203 | /* | 3204 | /* |
3205 | * On supported PHYs, check for duplex mismatch only | ||
3206 | * if link has autonegotiated at 10/100 half | ||
3207 | */ | ||
3208 | if ((hw->phy.type == e1000_phy_igp_3 || | ||
3209 | hw->phy.type == e1000_phy_bm) && | ||
3210 | (hw->mac.autoneg == true) && | ||
3211 | (adapter->link_speed == SPEED_10 || | ||
3212 | adapter->link_speed == SPEED_100) && | ||
3213 | (adapter->link_duplex == HALF_DUPLEX)) { | ||
3214 | u16 autoneg_exp; | ||
3215 | |||
3216 | e1e_rphy(hw, PHY_AUTONEG_EXP, &autoneg_exp); | ||
3217 | |||
3218 | if (!(autoneg_exp & NWAY_ER_LP_NWAY_CAPS)) | ||
3219 | e_info("Autonegotiated half duplex but" | ||
3220 | " link partner cannot autoneg. " | ||
3221 | " Try forcing full duplex if " | ||
3222 | "link gets many collisions.\n"); | ||
3223 | } | ||
3224 | |||
3225 | /* | ||
3204 | * tweak tx_queue_len according to speed/duplex | 3226 | * tweak tx_queue_len according to speed/duplex |
3205 | * and adjust the timeout factor | 3227 | * and adjust the timeout factor |
3206 | */ | 3228 | */ |
@@ -4776,6 +4798,9 @@ static struct pci_device_id e1000_pci_tbl[] = { | |||
4776 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan }, | 4798 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan }, |
4777 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan }, | 4799 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan }, |
4778 | 4800 | ||
4801 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan }, | ||
4802 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan }, | ||
4803 | |||
4779 | { } /* terminate list */ | 4804 | { } /* terminate list */ |
4780 | }; | 4805 | }; |
4781 | MODULE_DEVICE_TABLE(pci, e1000_pci_tbl); | 4806 | MODULE_DEVICE_TABLE(pci, e1000_pci_tbl); |
diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c index b133dcf0e950..16724f84d5ce 100644 --- a/drivers/net/e1000e/phy.c +++ b/drivers/net/e1000e/phy.c | |||
@@ -1720,6 +1720,91 @@ s32 e1000e_get_cfg_done(struct e1000_hw *hw) | |||
1720 | return 0; | 1720 | return 0; |
1721 | } | 1721 | } |
1722 | 1722 | ||
1723 | /** | ||
1724 | * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY | ||
1725 | * @hw: pointer to the HW structure | ||
1726 | * | ||
1727 | * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. | ||
1728 | **/ | ||
1729 | s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw) | ||
1730 | { | ||
1731 | hw_dbg(hw, "Running IGP 3 PHY init script\n"); | ||
1732 | |||
1733 | /* PHY init IGP 3 */ | ||
1734 | /* Enable rise/fall, 10-mode work in class-A */ | ||
1735 | e1e_wphy(hw, 0x2F5B, 0x9018); | ||
1736 | /* Remove all caps from Replica path filter */ | ||
1737 | e1e_wphy(hw, 0x2F52, 0x0000); | ||
1738 | /* Bias trimming for ADC, AFE and Driver (Default) */ | ||
1739 | e1e_wphy(hw, 0x2FB1, 0x8B24); | ||
1740 | /* Increase Hybrid poly bias */ | ||
1741 | e1e_wphy(hw, 0x2FB2, 0xF8F0); | ||
1742 | /* Add 4% to Tx amplitude in Gig mode */ | ||
1743 | e1e_wphy(hw, 0x2010, 0x10B0); | ||
1744 | /* Disable trimming (TTT) */ | ||
1745 | e1e_wphy(hw, 0x2011, 0x0000); | ||
1746 | /* Poly DC correction to 94.6% + 2% for all channels */ | ||
1747 | e1e_wphy(hw, 0x20DD, 0x249A); | ||
1748 | /* ABS DC correction to 95.9% */ | ||
1749 | e1e_wphy(hw, 0x20DE, 0x00D3); | ||
1750 | /* BG temp curve trim */ | ||
1751 | e1e_wphy(hw, 0x28B4, 0x04CE); | ||
1752 | /* Increasing ADC OPAMP stage 1 currents to max */ | ||
1753 | e1e_wphy(hw, 0x2F70, 0x29E4); | ||
1754 | /* Force 1000 ( required for enabling PHY regs configuration) */ | ||
1755 | e1e_wphy(hw, 0x0000, 0x0140); | ||
1756 | /* Set upd_freq to 6 */ | ||
1757 | e1e_wphy(hw, 0x1F30, 0x1606); | ||
1758 | /* Disable NPDFE */ | ||
1759 | e1e_wphy(hw, 0x1F31, 0xB814); | ||
1760 | /* Disable adaptive fixed FFE (Default) */ | ||
1761 | e1e_wphy(hw, 0x1F35, 0x002A); | ||
1762 | /* Enable FFE hysteresis */ | ||
1763 | e1e_wphy(hw, 0x1F3E, 0x0067); | ||
1764 | /* Fixed FFE for short cable lengths */ | ||
1765 | e1e_wphy(hw, 0x1F54, 0x0065); | ||
1766 | /* Fixed FFE for medium cable lengths */ | ||
1767 | e1e_wphy(hw, 0x1F55, 0x002A); | ||
1768 | /* Fixed FFE for long cable lengths */ | ||
1769 | e1e_wphy(hw, 0x1F56, 0x002A); | ||
1770 | /* Enable Adaptive Clip Threshold */ | ||
1771 | e1e_wphy(hw, 0x1F72, 0x3FB0); | ||
1772 | /* AHT reset limit to 1 */ | ||
1773 | e1e_wphy(hw, 0x1F76, 0xC0FF); | ||
1774 | /* Set AHT master delay to 127 msec */ | ||
1775 | e1e_wphy(hw, 0x1F77, 0x1DEC); | ||
1776 | /* Set scan bits for AHT */ | ||
1777 | e1e_wphy(hw, 0x1F78, 0xF9EF); | ||
1778 | /* Set AHT Preset bits */ | ||
1779 | e1e_wphy(hw, 0x1F79, 0x0210); | ||
1780 | /* Change integ_factor of channel A to 3 */ | ||
1781 | e1e_wphy(hw, 0x1895, 0x0003); | ||
1782 | /* Change prop_factor of channels BCD to 8 */ | ||
1783 | e1e_wphy(hw, 0x1796, 0x0008); | ||
1784 | /* Change cg_icount + enable integbp for channels BCD */ | ||
1785 | e1e_wphy(hw, 0x1798, 0xD008); | ||
1786 | /* | ||
1787 | * Change cg_icount + enable integbp + change prop_factor_master | ||
1788 | * to 8 for channel A | ||
1789 | */ | ||
1790 | e1e_wphy(hw, 0x1898, 0xD918); | ||
1791 | /* Disable AHT in Slave mode on channel A */ | ||
1792 | e1e_wphy(hw, 0x187A, 0x0800); | ||
1793 | /* | ||
1794 | * Enable LPLU and disable AN to 1000 in non-D0a states, | ||
1795 | * Enable SPD+B2B | ||
1796 | */ | ||
1797 | e1e_wphy(hw, 0x0019, 0x008D); | ||
1798 | /* Enable restart AN on an1000_dis change */ | ||
1799 | e1e_wphy(hw, 0x001B, 0x2080); | ||
1800 | /* Enable wh_fifo read clock in 10/100 modes */ | ||
1801 | e1e_wphy(hw, 0x0014, 0x0045); | ||
1802 | /* Restart AN, Speed selection is 1000 */ | ||
1803 | e1e_wphy(hw, 0x0000, 0x1340); | ||
1804 | |||
1805 | return 0; | ||
1806 | } | ||
1807 | |||
1723 | /* Internal function pointers */ | 1808 | /* Internal function pointers */ |
1724 | 1809 | ||
1725 | /** | 1810 | /** |