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authorAuke Kok <auke-jan.h.kok@intel.com>2007-09-17 15:30:59 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2007-10-10 19:50:40 -0400
commitbc7f75fa97884d41efbfde1397b621fefb2550b4 (patch)
tree037910bdb72ae1c1fc179f47beb1f9d00803dbf5 /drivers/net/e1000e/phy.c
parentcbdb9e43d1fc50cfa509b1006e7252dc4ea53aa0 (diff)
[E1000E]: New pci-express e1000 driver (currently for ICH9 devices only)
This driver implements support for the ICH9 on-board LAN ethernet device. The device is similar to ICH8. The driver encompasses code to support 82571/2/3, es2lan and ICH8 devices as well, but those device IDs are disabled and will be "lifted" from the e1000 driver over one at a time once this driver receives some more live time. Changes to the last snapshot posted are exclusively in the internal hardware API organization. Many thanks to Jeff Garzik for jumping in and getting this organized with a keen eye on the future layout. [ Integrated napi_struct patch from Auke as well... -DaveM ] Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> Signed-off-by: Jeff Garzik <jeff@garzik.org> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/e1000e/phy.c')
-rw-r--r--drivers/net/e1000e/phy.c1773
1 files changed, 1773 insertions, 0 deletions
diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c
new file mode 100644
index 000000000000..793231810ae0
--- /dev/null
+++ b/drivers/net/e1000e/phy.c
@@ -0,0 +1,1773 @@
1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/delay.h>
30
31#include "e1000.h"
32
33static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
34static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
35static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
36static s32 e1000_wait_autoneg(struct e1000_hw *hw);
37
38/* Cable length tables */
39static const u16 e1000_m88_cable_length_table[] =
40 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
41
42static const u16 e1000_igp_2_cable_length_table[] =
43 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
44 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
45 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
46 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
47 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
48 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
49 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
50 124};
51#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
52 (sizeof(e1000_igp_2_cable_length_table) / \
53 sizeof(e1000_igp_2_cable_length_table[0]))
54
55/**
56 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
57 * @hw: pointer to the HW structure
58 *
59 * Read the PHY management control register and check whether a PHY reset
60 * is blocked. If a reset is not blocked return 0, otherwise
61 * return E1000_BLK_PHY_RESET (12).
62 **/
63s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
64{
65 u32 manc;
66
67 manc = er32(MANC);
68
69 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
70 E1000_BLK_PHY_RESET : 0;
71}
72
73/**
74 * e1000e_get_phy_id - Retrieve the PHY ID and revision
75 * @hw: pointer to the HW structure
76 *
77 * Reads the PHY registers and stores the PHY ID and possibly the PHY
78 * revision in the hardware structure.
79 **/
80s32 e1000e_get_phy_id(struct e1000_hw *hw)
81{
82 struct e1000_phy_info *phy = &hw->phy;
83 s32 ret_val;
84 u16 phy_id;
85
86 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
87 if (ret_val)
88 return ret_val;
89
90 phy->id = (u32)(phy_id << 16);
91 udelay(20);
92 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
93 if (ret_val)
94 return ret_val;
95
96 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
97 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
98
99 return 0;
100}
101
102/**
103 * e1000e_phy_reset_dsp - Reset PHY DSP
104 * @hw: pointer to the HW structure
105 *
106 * Reset the digital signal processor.
107 **/
108s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
109{
110 s32 ret_val;
111
112 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
113 if (ret_val)
114 return ret_val;
115
116 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
117}
118
119/**
120 * e1000_read_phy_reg_mdic - Read MDI control register
121 * @hw: pointer to the HW structure
122 * @offset: register offset to be read
123 * @data: pointer to the read data
124 *
125 * Reads the MDI control regsiter in the PHY at offset and stores the
126 * information read to data.
127 **/
128static s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
129{
130 struct e1000_phy_info *phy = &hw->phy;
131 u32 i, mdic = 0;
132
133 if (offset > MAX_PHY_REG_ADDRESS) {
134 hw_dbg(hw, "PHY Address %d is out of range\n", offset);
135 return -E1000_ERR_PARAM;
136 }
137
138 /* Set up Op-code, Phy Address, and register offset in the MDI
139 * Control register. The MAC will take care of interfacing with the
140 * PHY to retrieve the desired data.
141 */
142 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
143 (phy->addr << E1000_MDIC_PHY_SHIFT) |
144 (E1000_MDIC_OP_READ));
145
146 ew32(MDIC, mdic);
147
148 /* Poll the ready bit to see if the MDI read completed */
149 for (i = 0; i < 64; i++) {
150 udelay(50);
151 mdic = er32(MDIC);
152 if (mdic & E1000_MDIC_READY)
153 break;
154 }
155 if (!(mdic & E1000_MDIC_READY)) {
156 hw_dbg(hw, "MDI Read did not complete\n");
157 return -E1000_ERR_PHY;
158 }
159 if (mdic & E1000_MDIC_ERROR) {
160 hw_dbg(hw, "MDI Error\n");
161 return -E1000_ERR_PHY;
162 }
163 *data = (u16) mdic;
164
165 return 0;
166}
167
168/**
169 * e1000_write_phy_reg_mdic - Write MDI control register
170 * @hw: pointer to the HW structure
171 * @offset: register offset to write to
172 * @data: data to write to register at offset
173 *
174 * Writes data to MDI control register in the PHY at offset.
175 **/
176static s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
177{
178 struct e1000_phy_info *phy = &hw->phy;
179 u32 i, mdic = 0;
180
181 if (offset > MAX_PHY_REG_ADDRESS) {
182 hw_dbg(hw, "PHY Address %d is out of range\n", offset);
183 return -E1000_ERR_PARAM;
184 }
185
186 /* Set up Op-code, Phy Address, and register offset in the MDI
187 * Control register. The MAC will take care of interfacing with the
188 * PHY to retrieve the desired data.
189 */
190 mdic = (((u32)data) |
191 (offset << E1000_MDIC_REG_SHIFT) |
192 (phy->addr << E1000_MDIC_PHY_SHIFT) |
193 (E1000_MDIC_OP_WRITE));
194
195 ew32(MDIC, mdic);
196
197 /* Poll the ready bit to see if the MDI read completed */
198 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
199 udelay(5);
200 mdic = er32(MDIC);
201 if (mdic & E1000_MDIC_READY)
202 break;
203 }
204 if (!(mdic & E1000_MDIC_READY)) {
205 hw_dbg(hw, "MDI Write did not complete\n");
206 return -E1000_ERR_PHY;
207 }
208
209 return 0;
210}
211
212/**
213 * e1000e_read_phy_reg_m88 - Read m88 PHY register
214 * @hw: pointer to the HW structure
215 * @offset: register offset to be read
216 * @data: pointer to the read data
217 *
218 * Acquires semaphore, if necessary, then reads the PHY register at offset
219 * and storing the retrieved information in data. Release any acquired
220 * semaphores before exiting.
221 **/
222s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
223{
224 s32 ret_val;
225
226 ret_val = hw->phy.ops.acquire_phy(hw);
227 if (ret_val)
228 return ret_val;
229
230 ret_val = e1000_read_phy_reg_mdic(hw,
231 MAX_PHY_REG_ADDRESS & offset,
232 data);
233
234 hw->phy.ops.release_phy(hw);
235
236 return ret_val;
237}
238
239/**
240 * e1000e_write_phy_reg_m88 - Write m88 PHY register
241 * @hw: pointer to the HW structure
242 * @offset: register offset to write to
243 * @data: data to write at register offset
244 *
245 * Acquires semaphore, if necessary, then writes the data to PHY register
246 * at the offset. Release any acquired semaphores before exiting.
247 **/
248s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
249{
250 s32 ret_val;
251
252 ret_val = hw->phy.ops.acquire_phy(hw);
253 if (ret_val)
254 return ret_val;
255
256 ret_val = e1000_write_phy_reg_mdic(hw,
257 MAX_PHY_REG_ADDRESS & offset,
258 data);
259
260 hw->phy.ops.release_phy(hw);
261
262 return ret_val;
263}
264
265/**
266 * e1000e_read_phy_reg_igp - Read igp PHY register
267 * @hw: pointer to the HW structure
268 * @offset: register offset to be read
269 * @data: pointer to the read data
270 *
271 * Acquires semaphore, if necessary, then reads the PHY register at offset
272 * and storing the retrieved information in data. Release any acquired
273 * semaphores before exiting.
274 **/
275s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
276{
277 s32 ret_val;
278
279 ret_val = hw->phy.ops.acquire_phy(hw);
280 if (ret_val)
281 return ret_val;
282
283 if (offset > MAX_PHY_MULTI_PAGE_REG) {
284 ret_val = e1000_write_phy_reg_mdic(hw,
285 IGP01E1000_PHY_PAGE_SELECT,
286 (u16)offset);
287 if (ret_val) {
288 hw->phy.ops.release_phy(hw);
289 return ret_val;
290 }
291 }
292
293 ret_val = e1000_read_phy_reg_mdic(hw,
294 MAX_PHY_REG_ADDRESS & offset,
295 data);
296
297 hw->phy.ops.release_phy(hw);
298
299 return ret_val;
300}
301
302/**
303 * e1000e_write_phy_reg_igp - Write igp PHY register
304 * @hw: pointer to the HW structure
305 * @offset: register offset to write to
306 * @data: data to write at register offset
307 *
308 * Acquires semaphore, if necessary, then writes the data to PHY register
309 * at the offset. Release any acquired semaphores before exiting.
310 **/
311s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
312{
313 s32 ret_val;
314
315 ret_val = hw->phy.ops.acquire_phy(hw);
316 if (ret_val)
317 return ret_val;
318
319 if (offset > MAX_PHY_MULTI_PAGE_REG) {
320 ret_val = e1000_write_phy_reg_mdic(hw,
321 IGP01E1000_PHY_PAGE_SELECT,
322 (u16)offset);
323 if (ret_val) {
324 hw->phy.ops.release_phy(hw);
325 return ret_val;
326 }
327 }
328
329 ret_val = e1000_write_phy_reg_mdic(hw,
330 MAX_PHY_REG_ADDRESS & offset,
331 data);
332
333 hw->phy.ops.release_phy(hw);
334
335 return ret_val;
336}
337
338/**
339 * e1000e_read_kmrn_reg - Read kumeran register
340 * @hw: pointer to the HW structure
341 * @offset: register offset to be read
342 * @data: pointer to the read data
343 *
344 * Acquires semaphore, if necessary. Then reads the PHY register at offset
345 * using the kumeran interface. The information retrieved is stored in data.
346 * Release any acquired semaphores before exiting.
347 **/
348s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
349{
350 u32 kmrnctrlsta;
351 s32 ret_val;
352
353 ret_val = hw->phy.ops.acquire_phy(hw);
354 if (ret_val)
355 return ret_val;
356
357 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
358 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
359 ew32(KMRNCTRLSTA, kmrnctrlsta);
360
361 udelay(2);
362
363 kmrnctrlsta = er32(KMRNCTRLSTA);
364 *data = (u16)kmrnctrlsta;
365
366 hw->phy.ops.release_phy(hw);
367
368 return ret_val;
369}
370
371/**
372 * e1000e_write_kmrn_reg - Write kumeran register
373 * @hw: pointer to the HW structure
374 * @offset: register offset to write to
375 * @data: data to write at register offset
376 *
377 * Acquires semaphore, if necessary. Then write the data to PHY register
378 * at the offset using the kumeran interface. Release any acquired semaphores
379 * before exiting.
380 **/
381s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
382{
383 u32 kmrnctrlsta;
384 s32 ret_val;
385
386 ret_val = hw->phy.ops.acquire_phy(hw);
387 if (ret_val)
388 return ret_val;
389
390 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
391 E1000_KMRNCTRLSTA_OFFSET) | data;
392 ew32(KMRNCTRLSTA, kmrnctrlsta);
393
394 udelay(2);
395 hw->phy.ops.release_phy(hw);
396
397 return ret_val;
398}
399
400/**
401 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
402 * @hw: pointer to the HW structure
403 *
404 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
405 * and downshift values are set also.
406 **/
407s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
408{
409 struct e1000_phy_info *phy = &hw->phy;
410 s32 ret_val;
411 u16 phy_data;
412
413 /* Enable CRS on TX. This must be set for half-duplex operation. */
414 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
415 if (ret_val)
416 return ret_val;
417
418 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
419
420 /* Options:
421 * MDI/MDI-X = 0 (default)
422 * 0 - Auto for all speeds
423 * 1 - MDI mode
424 * 2 - MDI-X mode
425 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
426 */
427 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
428
429 switch (phy->mdix) {
430 case 1:
431 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
432 break;
433 case 2:
434 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
435 break;
436 case 3:
437 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
438 break;
439 case 0:
440 default:
441 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
442 break;
443 }
444
445 /* Options:
446 * disable_polarity_correction = 0 (default)
447 * Automatic Correction for Reversed Cable Polarity
448 * 0 - Disabled
449 * 1 - Enabled
450 */
451 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
452 if (phy->disable_polarity_correction == 1)
453 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
454
455 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
456 if (ret_val)
457 return ret_val;
458
459 if (phy->revision < 4) {
460 /* Force TX_CLK in the Extended PHY Specific Control Register
461 * to 25MHz clock.
462 */
463 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
464 if (ret_val)
465 return ret_val;
466
467 phy_data |= M88E1000_EPSCR_TX_CLK_25;
468
469 if ((phy->revision == 2) &&
470 (phy->id == M88E1111_I_PHY_ID)) {
471 /* 82573L PHY - set the downshift counter to 5x. */
472 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
473 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
474 } else {
475 /* Configure Master and Slave downshift values */
476 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
477 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
478 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
479 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
480 }
481 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
482 if (ret_val)
483 return ret_val;
484 }
485
486 /* Commit the changes. */
487 ret_val = e1000e_commit_phy(hw);
488 if (ret_val)
489 hw_dbg(hw, "Error committing the PHY changes\n");
490
491 return ret_val;
492}
493
494/**
495 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
496 * @hw: pointer to the HW structure
497 *
498 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
499 * igp PHY's.
500 **/
501s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
502{
503 struct e1000_phy_info *phy = &hw->phy;
504 s32 ret_val;
505 u16 data;
506
507 ret_val = e1000_phy_hw_reset(hw);
508 if (ret_val) {
509 hw_dbg(hw, "Error resetting the PHY.\n");
510 return ret_val;
511 }
512
513 /* Wait 15ms for MAC to configure PHY from NVM settings. */
514 msleep(15);
515
516 /* disable lplu d0 during driver init */
517 ret_val = e1000_set_d0_lplu_state(hw, 0);
518 if (ret_val) {
519 hw_dbg(hw, "Error Disabling LPLU D0\n");
520 return ret_val;
521 }
522 /* Configure mdi-mdix settings */
523 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
524 if (ret_val)
525 return ret_val;
526
527 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
528
529 switch (phy->mdix) {
530 case 1:
531 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
532 break;
533 case 2:
534 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
535 break;
536 case 0:
537 default:
538 data |= IGP01E1000_PSCR_AUTO_MDIX;
539 break;
540 }
541 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
542 if (ret_val)
543 return ret_val;
544
545 /* set auto-master slave resolution settings */
546 if (hw->mac.autoneg) {
547 /* when autonegotiation advertisement is only 1000Mbps then we
548 * should disable SmartSpeed and enable Auto MasterSlave
549 * resolution as hardware default. */
550 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
551 /* Disable SmartSpeed */
552 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
553 &data);
554 if (ret_val)
555 return ret_val;
556
557 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
558 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
559 data);
560 if (ret_val)
561 return ret_val;
562
563 /* Set auto Master/Slave resolution process */
564 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
565 if (ret_val)
566 return ret_val;
567
568 data &= ~CR_1000T_MS_ENABLE;
569 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
570 if (ret_val)
571 return ret_val;
572 }
573
574 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
575 if (ret_val)
576 return ret_val;
577
578 /* load defaults for future use */
579 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
580 ((data & CR_1000T_MS_VALUE) ?
581 e1000_ms_force_master :
582 e1000_ms_force_slave) :
583 e1000_ms_auto;
584
585 switch (phy->ms_type) {
586 case e1000_ms_force_master:
587 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
588 break;
589 case e1000_ms_force_slave:
590 data |= CR_1000T_MS_ENABLE;
591 data &= ~(CR_1000T_MS_VALUE);
592 break;
593 case e1000_ms_auto:
594 data &= ~CR_1000T_MS_ENABLE;
595 default:
596 break;
597 }
598 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
599 }
600
601 return ret_val;
602}
603
604/**
605 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
606 * @hw: pointer to the HW structure
607 *
608 * Reads the MII auto-neg advertisement register and/or the 1000T control
609 * register and if the PHY is already setup for auto-negotiation, then
610 * return successful. Otherwise, setup advertisement and flow control to
611 * the appropriate values for the wanted auto-negotiation.
612 **/
613static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
614{
615 struct e1000_phy_info *phy = &hw->phy;
616 s32 ret_val;
617 u16 mii_autoneg_adv_reg;
618 u16 mii_1000t_ctrl_reg = 0;
619
620 phy->autoneg_advertised &= phy->autoneg_mask;
621
622 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
623 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
624 if (ret_val)
625 return ret_val;
626
627 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
628 /* Read the MII 1000Base-T Control Register (Address 9). */
629 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
630 if (ret_val)
631 return ret_val;
632 }
633
634 /* Need to parse both autoneg_advertised and fc and set up
635 * the appropriate PHY registers. First we will parse for
636 * autoneg_advertised software override. Since we can advertise
637 * a plethora of combinations, we need to check each bit
638 * individually.
639 */
640
641 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
642 * Advertisement Register (Address 4) and the 1000 mb speed bits in
643 * the 1000Base-T Control Register (Address 9).
644 */
645 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
646 NWAY_AR_100TX_HD_CAPS |
647 NWAY_AR_10T_FD_CAPS |
648 NWAY_AR_10T_HD_CAPS);
649 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
650
651 hw_dbg(hw, "autoneg_advertised %x\n", phy->autoneg_advertised);
652
653 /* Do we want to advertise 10 Mb Half Duplex? */
654 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
655 hw_dbg(hw, "Advertise 10mb Half duplex\n");
656 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
657 }
658
659 /* Do we want to advertise 10 Mb Full Duplex? */
660 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
661 hw_dbg(hw, "Advertise 10mb Full duplex\n");
662 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
663 }
664
665 /* Do we want to advertise 100 Mb Half Duplex? */
666 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
667 hw_dbg(hw, "Advertise 100mb Half duplex\n");
668 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
669 }
670
671 /* Do we want to advertise 100 Mb Full Duplex? */
672 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
673 hw_dbg(hw, "Advertise 100mb Full duplex\n");
674 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
675 }
676
677 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
678 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
679 hw_dbg(hw, "Advertise 1000mb Half duplex request denied!\n");
680
681 /* Do we want to advertise 1000 Mb Full Duplex? */
682 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
683 hw_dbg(hw, "Advertise 1000mb Full duplex\n");
684 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
685 }
686
687 /* Check for a software override of the flow control settings, and
688 * setup the PHY advertisement registers accordingly. If
689 * auto-negotiation is enabled, then software will have to set the
690 * "PAUSE" bits to the correct value in the Auto-Negotiation
691 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
692 * negotiation.
693 *
694 * The possible values of the "fc" parameter are:
695 * 0: Flow control is completely disabled
696 * 1: Rx flow control is enabled (we can receive pause frames
697 * but not send pause frames).
698 * 2: Tx flow control is enabled (we can send pause frames
699 * but we do not support receiving pause frames).
700 * 3: Both Rx and TX flow control (symmetric) are enabled.
701 * other: No software override. The flow control configuration
702 * in the EEPROM is used.
703 */
704 switch (hw->mac.fc) {
705 case e1000_fc_none:
706 /* Flow control (RX & TX) is completely disabled by a
707 * software over-ride.
708 */
709 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
710 break;
711 case e1000_fc_rx_pause:
712 /* RX Flow control is enabled, and TX Flow control is
713 * disabled, by a software over-ride.
714 */
715 /* Since there really isn't a way to advertise that we are
716 * capable of RX Pause ONLY, we will advertise that we
717 * support both symmetric and asymmetric RX PAUSE. Later
718 * (in e1000e_config_fc_after_link_up) we will disable the
719 * hw's ability to send PAUSE frames.
720 */
721 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
722 break;
723 case e1000_fc_tx_pause:
724 /* TX Flow control is enabled, and RX Flow control is
725 * disabled, by a software over-ride.
726 */
727 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
728 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
729 break;
730 case e1000_fc_full:
731 /* Flow control (both RX and TX) is enabled by a software
732 * over-ride.
733 */
734 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
735 break;
736 default:
737 hw_dbg(hw, "Flow control param set incorrectly\n");
738 ret_val = -E1000_ERR_CONFIG;
739 return ret_val;
740 }
741
742 ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
743 if (ret_val)
744 return ret_val;
745
746 hw_dbg(hw, "Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
747
748 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
749 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
750 }
751
752 return ret_val;
753}
754
755/**
756 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
757 * @hw: pointer to the HW structure
758 *
759 * Performs initial bounds checking on autoneg advertisement parameter, then
760 * configure to advertise the full capability. Setup the PHY to autoneg
761 * and restart the negotiation process between the link partner. If
762 * wait_for_link, then wait for autoneg to complete before exiting.
763 **/
764static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
765{
766 struct e1000_phy_info *phy = &hw->phy;
767 s32 ret_val;
768 u16 phy_ctrl;
769
770 /* Perform some bounds checking on the autoneg advertisement
771 * parameter.
772 */
773 phy->autoneg_advertised &= phy->autoneg_mask;
774
775 /* If autoneg_advertised is zero, we assume it was not defaulted
776 * by the calling code so we set to advertise full capability.
777 */
778 if (phy->autoneg_advertised == 0)
779 phy->autoneg_advertised = phy->autoneg_mask;
780
781 hw_dbg(hw, "Reconfiguring auto-neg advertisement params\n");
782 ret_val = e1000_phy_setup_autoneg(hw);
783 if (ret_val) {
784 hw_dbg(hw, "Error Setting up Auto-Negotiation\n");
785 return ret_val;
786 }
787 hw_dbg(hw, "Restarting Auto-Neg\n");
788
789 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
790 * the Auto Neg Restart bit in the PHY control register.
791 */
792 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
793 if (ret_val)
794 return ret_val;
795
796 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
797 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
798 if (ret_val)
799 return ret_val;
800
801 /* Does the user want to wait for Auto-Neg to complete here, or
802 * check at a later time (for example, callback routine).
803 */
804 if (phy->wait_for_link) {
805 ret_val = e1000_wait_autoneg(hw);
806 if (ret_val) {
807 hw_dbg(hw, "Error while waiting for "
808 "autoneg to complete\n");
809 return ret_val;
810 }
811 }
812
813 hw->mac.get_link_status = 1;
814
815 return ret_val;
816}
817
818/**
819 * e1000e_setup_copper_link - Configure copper link settings
820 * @hw: pointer to the HW structure
821 *
822 * Calls the appropriate function to configure the link for auto-neg or forced
823 * speed and duplex. Then we check for link, once link is established calls
824 * to configure collision distance and flow control are called. If link is
825 * not established, we return -E1000_ERR_PHY (-2).
826 **/
827s32 e1000e_setup_copper_link(struct e1000_hw *hw)
828{
829 s32 ret_val;
830 bool link;
831
832 if (hw->mac.autoneg) {
833 /* Setup autoneg and flow control advertisement and perform
834 * autonegotiation. */
835 ret_val = e1000_copper_link_autoneg(hw);
836 if (ret_val)
837 return ret_val;
838 } else {
839 /* PHY will be set to 10H, 10F, 100H or 100F
840 * depending on user settings. */
841 hw_dbg(hw, "Forcing Speed and Duplex\n");
842 ret_val = e1000_phy_force_speed_duplex(hw);
843 if (ret_val) {
844 hw_dbg(hw, "Error Forcing Speed and Duplex\n");
845 return ret_val;
846 }
847 }
848
849 /* Check link status. Wait up to 100 microseconds for link to become
850 * valid.
851 */
852 ret_val = e1000e_phy_has_link_generic(hw,
853 COPPER_LINK_UP_LIMIT,
854 10,
855 &link);
856 if (ret_val)
857 return ret_val;
858
859 if (link) {
860 hw_dbg(hw, "Valid link established!!!\n");
861 e1000e_config_collision_dist(hw);
862 ret_val = e1000e_config_fc_after_link_up(hw);
863 } else {
864 hw_dbg(hw, "Unable to establish link!!!\n");
865 }
866
867 return ret_val;
868}
869
870/**
871 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
872 * @hw: pointer to the HW structure
873 *
874 * Calls the PHY setup function to force speed and duplex. Clears the
875 * auto-crossover to force MDI manually. Waits for link and returns
876 * successful if link up is successful, else -E1000_ERR_PHY (-2).
877 **/
878s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
879{
880 struct e1000_phy_info *phy = &hw->phy;
881 s32 ret_val;
882 u16 phy_data;
883 bool link;
884
885 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
886 if (ret_val)
887 return ret_val;
888
889 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
890
891 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
892 if (ret_val)
893 return ret_val;
894
895 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
896 * forced whenever speed and duplex are forced.
897 */
898 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
899 if (ret_val)
900 return ret_val;
901
902 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
903 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
904
905 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
906 if (ret_val)
907 return ret_val;
908
909 hw_dbg(hw, "IGP PSCR: %X\n", phy_data);
910
911 udelay(1);
912
913 if (phy->wait_for_link) {
914 hw_dbg(hw, "Waiting for forced speed/duplex link on IGP phy.\n");
915
916 ret_val = e1000e_phy_has_link_generic(hw,
917 PHY_FORCE_LIMIT,
918 100000,
919 &link);
920 if (ret_val)
921 return ret_val;
922
923 if (!link)
924 hw_dbg(hw, "Link taking longer than expected.\n");
925
926 /* Try once more */
927 ret_val = e1000e_phy_has_link_generic(hw,
928 PHY_FORCE_LIMIT,
929 100000,
930 &link);
931 if (ret_val)
932 return ret_val;
933 }
934
935 return ret_val;
936}
937
938/**
939 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
940 * @hw: pointer to the HW structure
941 *
942 * Calls the PHY setup function to force speed and duplex. Clears the
943 * auto-crossover to force MDI manually. Resets the PHY to commit the
944 * changes. If time expires while waiting for link up, we reset the DSP.
945 * After reset, TX_CLK and CRS on TX must be set. Return successful upon
946 * successful completion, else return corresponding error code.
947 **/
948s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
949{
950 struct e1000_phy_info *phy = &hw->phy;
951 s32 ret_val;
952 u16 phy_data;
953 bool link;
954
955 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
956 * forced whenever speed and duplex are forced.
957 */
958 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
959 if (ret_val)
960 return ret_val;
961
962 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
963 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
964 if (ret_val)
965 return ret_val;
966
967 hw_dbg(hw, "M88E1000 PSCR: %X\n", phy_data);
968
969 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
970 if (ret_val)
971 return ret_val;
972
973 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
974
975 /* Reset the phy to commit changes. */
976 phy_data |= MII_CR_RESET;
977
978 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
979 if (ret_val)
980 return ret_val;
981
982 udelay(1);
983
984 if (phy->wait_for_link) {
985 hw_dbg(hw, "Waiting for forced speed/duplex link on M88 phy.\n");
986
987 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
988 100000, &link);
989 if (ret_val)
990 return ret_val;
991
992 if (!link) {
993 /* We didn't get link.
994 * Reset the DSP and cross our fingers.
995 */
996 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT, 0x001d);
997 if (ret_val)
998 return ret_val;
999 ret_val = e1000e_phy_reset_dsp(hw);
1000 if (ret_val)
1001 return ret_val;
1002 }
1003
1004 /* Try once more */
1005 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1006 100000, &link);
1007 if (ret_val)
1008 return ret_val;
1009 }
1010
1011 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1012 if (ret_val)
1013 return ret_val;
1014
1015 /* Resetting the phy means we need to re-force TX_CLK in the
1016 * Extended PHY Specific Control Register to 25MHz clock from
1017 * the reset value of 2.5MHz.
1018 */
1019 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1020 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1021 if (ret_val)
1022 return ret_val;
1023
1024 /* In addition, we must re-enable CRS on Tx for both half and full
1025 * duplex.
1026 */
1027 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1028 if (ret_val)
1029 return ret_val;
1030
1031 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1032 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1033
1034 return ret_val;
1035}
1036
1037/**
1038 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1039 * @hw: pointer to the HW structure
1040 * @phy_ctrl: pointer to current value of PHY_CONTROL
1041 *
1042 * Forces speed and duplex on the PHY by doing the following: disable flow
1043 * control, force speed/duplex on the MAC, disable auto speed detection,
1044 * disable auto-negotiation, configure duplex, configure speed, configure
1045 * the collision distance, write configuration to CTRL register. The
1046 * caller must write to the PHY_CONTROL register for these settings to
1047 * take affect.
1048 **/
1049void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1050{
1051 struct e1000_mac_info *mac = &hw->mac;
1052 u32 ctrl;
1053
1054 /* Turn off flow control when forcing speed/duplex */
1055 mac->fc = e1000_fc_none;
1056
1057 /* Force speed/duplex on the mac */
1058 ctrl = er32(CTRL);
1059 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1060 ctrl &= ~E1000_CTRL_SPD_SEL;
1061
1062 /* Disable Auto Speed Detection */
1063 ctrl &= ~E1000_CTRL_ASDE;
1064
1065 /* Disable autoneg on the phy */
1066 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1067
1068 /* Forcing Full or Half Duplex? */
1069 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1070 ctrl &= ~E1000_CTRL_FD;
1071 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1072 hw_dbg(hw, "Half Duplex\n");
1073 } else {
1074 ctrl |= E1000_CTRL_FD;
1075 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1076 hw_dbg(hw, "Full Duplex\n");
1077 }
1078
1079 /* Forcing 10mb or 100mb? */
1080 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1081 ctrl |= E1000_CTRL_SPD_100;
1082 *phy_ctrl |= MII_CR_SPEED_100;
1083 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1084 hw_dbg(hw, "Forcing 100mb\n");
1085 } else {
1086 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1087 *phy_ctrl |= MII_CR_SPEED_10;
1088 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1089 hw_dbg(hw, "Forcing 10mb\n");
1090 }
1091
1092 e1000e_config_collision_dist(hw);
1093
1094 ew32(CTRL, ctrl);
1095}
1096
1097/**
1098 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1099 * @hw: pointer to the HW structure
1100 * @active: boolean used to enable/disable lplu
1101 *
1102 * Success returns 0, Failure returns 1
1103 *
1104 * The low power link up (lplu) state is set to the power management level D3
1105 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1106 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1107 * is used during Dx states where the power conservation is most important.
1108 * During driver activity, SmartSpeed should be enabled so performance is
1109 * maintained.
1110 **/
1111s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1112{
1113 struct e1000_phy_info *phy = &hw->phy;
1114 s32 ret_val;
1115 u16 data;
1116
1117 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1118 if (ret_val)
1119 return ret_val;
1120
1121 if (!active) {
1122 data &= ~IGP02E1000_PM_D3_LPLU;
1123 ret_val = e1e_wphy(hw,
1124 IGP02E1000_PHY_POWER_MGMT,
1125 data);
1126 if (ret_val)
1127 return ret_val;
1128 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1129 * during Dx states where the power conservation is most
1130 * important. During driver activity we should enable
1131 * SmartSpeed, so performance is maintained. */
1132 if (phy->smart_speed == e1000_smart_speed_on) {
1133 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1134 &data);
1135 if (ret_val)
1136 return ret_val;
1137
1138 data |= IGP01E1000_PSCFR_SMART_SPEED;
1139 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1140 data);
1141 if (ret_val)
1142 return ret_val;
1143 } else if (phy->smart_speed == e1000_smart_speed_off) {
1144 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1145 &data);
1146 if (ret_val)
1147 return ret_val;
1148
1149 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1150 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1151 data);
1152 if (ret_val)
1153 return ret_val;
1154 }
1155 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1156 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1157 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1158 data |= IGP02E1000_PM_D3_LPLU;
1159 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1160 if (ret_val)
1161 return ret_val;
1162
1163 /* When LPLU is enabled, we should disable SmartSpeed */
1164 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1165 if (ret_val)
1166 return ret_val;
1167
1168 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1169 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1170 }
1171
1172 return ret_val;
1173}
1174
1175/**
1176 * e1000e_check_downshift - Checks whether a downshift in speed occured
1177 * @hw: pointer to the HW structure
1178 *
1179 * Success returns 0, Failure returns 1
1180 *
1181 * A downshift is detected by querying the PHY link health.
1182 **/
1183s32 e1000e_check_downshift(struct e1000_hw *hw)
1184{
1185 struct e1000_phy_info *phy = &hw->phy;
1186 s32 ret_val;
1187 u16 phy_data, offset, mask;
1188
1189 switch (phy->type) {
1190 case e1000_phy_m88:
1191 case e1000_phy_gg82563:
1192 offset = M88E1000_PHY_SPEC_STATUS;
1193 mask = M88E1000_PSSR_DOWNSHIFT;
1194 break;
1195 case e1000_phy_igp_2:
1196 case e1000_phy_igp_3:
1197 offset = IGP01E1000_PHY_LINK_HEALTH;
1198 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1199 break;
1200 default:
1201 /* speed downshift not supported */
1202 phy->speed_downgraded = 0;
1203 return 0;
1204 }
1205
1206 ret_val = e1e_rphy(hw, offset, &phy_data);
1207
1208 if (!ret_val)
1209 phy->speed_downgraded = (phy_data & mask);
1210
1211 return ret_val;
1212}
1213
1214/**
1215 * e1000_check_polarity_m88 - Checks the polarity.
1216 * @hw: pointer to the HW structure
1217 *
1218 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1219 *
1220 * Polarity is determined based on the PHY specific status register.
1221 **/
1222static s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1223{
1224 struct e1000_phy_info *phy = &hw->phy;
1225 s32 ret_val;
1226 u16 data;
1227
1228 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1229
1230 if (!ret_val)
1231 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1232 ? e1000_rev_polarity_reversed
1233 : e1000_rev_polarity_normal;
1234
1235 return ret_val;
1236}
1237
1238/**
1239 * e1000_check_polarity_igp - Checks the polarity.
1240 * @hw: pointer to the HW structure
1241 *
1242 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1243 *
1244 * Polarity is determined based on the PHY port status register, and the
1245 * current speed (since there is no polarity at 100Mbps).
1246 **/
1247static s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1248{
1249 struct e1000_phy_info *phy = &hw->phy;
1250 s32 ret_val;
1251 u16 data, offset, mask;
1252
1253 /* Polarity is determined based on the speed of
1254 * our connection. */
1255 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1256 if (ret_val)
1257 return ret_val;
1258
1259 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1260 IGP01E1000_PSSR_SPEED_1000MBPS) {
1261 offset = IGP01E1000_PHY_PCS_INIT_REG;
1262 mask = IGP01E1000_PHY_POLARITY_MASK;
1263 } else {
1264 /* This really only applies to 10Mbps since
1265 * there is no polarity for 100Mbps (always 0).
1266 */
1267 offset = IGP01E1000_PHY_PORT_STATUS;
1268 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1269 }
1270
1271 ret_val = e1e_rphy(hw, offset, &data);
1272
1273 if (!ret_val)
1274 phy->cable_polarity = (data & mask)
1275 ? e1000_rev_polarity_reversed
1276 : e1000_rev_polarity_normal;
1277
1278 return ret_val;
1279}
1280
1281/**
1282 * e1000_wait_autoneg - Wait for auto-neg compeletion
1283 * @hw: pointer to the HW structure
1284 *
1285 * Waits for auto-negotiation to complete or for the auto-negotiation time
1286 * limit to expire, which ever happens first.
1287 **/
1288static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1289{
1290 s32 ret_val = 0;
1291 u16 i, phy_status;
1292
1293 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1294 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1295 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1296 if (ret_val)
1297 break;
1298 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1299 if (ret_val)
1300 break;
1301 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1302 break;
1303 msleep(100);
1304 }
1305
1306 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1307 * has completed.
1308 */
1309 return ret_val;
1310}
1311
1312/**
1313 * e1000e_phy_has_link_generic - Polls PHY for link
1314 * @hw: pointer to the HW structure
1315 * @iterations: number of times to poll for link
1316 * @usec_interval: delay between polling attempts
1317 * @success: pointer to whether polling was successful or not
1318 *
1319 * Polls the PHY status register for link, 'iterations' number of times.
1320 **/
1321s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1322 u32 usec_interval, bool *success)
1323{
1324 s32 ret_val = 0;
1325 u16 i, phy_status;
1326
1327 for (i = 0; i < iterations; i++) {
1328 /* Some PHYs require the PHY_STATUS register to be read
1329 * twice due to the link bit being sticky. No harm doing
1330 * it across the board.
1331 */
1332 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1333 if (ret_val)
1334 break;
1335 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1336 if (ret_val)
1337 break;
1338 if (phy_status & MII_SR_LINK_STATUS)
1339 break;
1340 if (usec_interval >= 1000)
1341 mdelay(usec_interval/1000);
1342 else
1343 udelay(usec_interval);
1344 }
1345
1346 *success = (i < iterations);
1347
1348 return ret_val;
1349}
1350
1351/**
1352 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1353 * @hw: pointer to the HW structure
1354 *
1355 * Reads the PHY specific status register to retrieve the cable length
1356 * information. The cable length is determined by averaging the minimum and
1357 * maximum values to get the "average" cable length. The m88 PHY has four
1358 * possible cable length values, which are:
1359 * Register Value Cable Length
1360 * 0 < 50 meters
1361 * 1 50 - 80 meters
1362 * 2 80 - 110 meters
1363 * 3 110 - 140 meters
1364 * 4 > 140 meters
1365 **/
1366s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1367{
1368 struct e1000_phy_info *phy = &hw->phy;
1369 s32 ret_val;
1370 u16 phy_data, index;
1371
1372 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1373 if (ret_val)
1374 return ret_val;
1375
1376 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1377 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1378 phy->min_cable_length = e1000_m88_cable_length_table[index];
1379 phy->max_cable_length = e1000_m88_cable_length_table[index+1];
1380
1381 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1382
1383 return ret_val;
1384}
1385
1386/**
1387 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1388 * @hw: pointer to the HW structure
1389 *
1390 * The automatic gain control (agc) normalizes the amplitude of the
1391 * received signal, adjusting for the attenuation produced by the
1392 * cable. By reading the AGC registers, which reperesent the
1393 * cobination of course and fine gain value, the value can be put
1394 * into a lookup table to obtain the approximate cable length
1395 * for each channel.
1396 **/
1397s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1398{
1399 struct e1000_phy_info *phy = &hw->phy;
1400 s32 ret_val;
1401 u16 phy_data, i, agc_value = 0;
1402 u16 cur_agc_index, max_agc_index = 0;
1403 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1404 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
1405 {IGP02E1000_PHY_AGC_A,
1406 IGP02E1000_PHY_AGC_B,
1407 IGP02E1000_PHY_AGC_C,
1408 IGP02E1000_PHY_AGC_D};
1409
1410 /* Read the AGC registers for all channels */
1411 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1412 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1413 if (ret_val)
1414 return ret_val;
1415
1416 /* Getting bits 15:9, which represent the combination of
1417 * course and fine gain values. The result is a number
1418 * that can be put into the lookup table to obtain the
1419 * approximate cable length. */
1420 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1421 IGP02E1000_AGC_LENGTH_MASK;
1422
1423 /* Array index bound check. */
1424 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1425 (cur_agc_index == 0))
1426 return -E1000_ERR_PHY;
1427
1428 /* Remove min & max AGC values from calculation. */
1429 if (e1000_igp_2_cable_length_table[min_agc_index] >
1430 e1000_igp_2_cable_length_table[cur_agc_index])
1431 min_agc_index = cur_agc_index;
1432 if (e1000_igp_2_cable_length_table[max_agc_index] <
1433 e1000_igp_2_cable_length_table[cur_agc_index])
1434 max_agc_index = cur_agc_index;
1435
1436 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1437 }
1438
1439 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1440 e1000_igp_2_cable_length_table[max_agc_index]);
1441 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1442
1443 /* Calculate cable length with the error range of +/- 10 meters. */
1444 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1445 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1446 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1447
1448 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1449
1450 return ret_val;
1451}
1452
1453/**
1454 * e1000e_get_phy_info_m88 - Retrieve PHY information
1455 * @hw: pointer to the HW structure
1456 *
1457 * Valid for only copper links. Read the PHY status register (sticky read)
1458 * to verify that link is up. Read the PHY special control register to
1459 * determine the polarity and 10base-T extended distance. Read the PHY
1460 * special status register to determine MDI/MDIx and current speed. If
1461 * speed is 1000, then determine cable length, local and remote receiver.
1462 **/
1463s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1464{
1465 struct e1000_phy_info *phy = &hw->phy;
1466 s32 ret_val;
1467 u16 phy_data;
1468 bool link;
1469
1470 if (hw->media_type != e1000_media_type_copper) {
1471 hw_dbg(hw, "Phy info is only valid for copper media\n");
1472 return -E1000_ERR_CONFIG;
1473 }
1474
1475 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1476 if (ret_val)
1477 return ret_val;
1478
1479 if (!link) {
1480 hw_dbg(hw, "Phy info is only valid if link is up\n");
1481 return -E1000_ERR_CONFIG;
1482 }
1483
1484 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1485 if (ret_val)
1486 return ret_val;
1487
1488 phy->polarity_correction = (phy_data &
1489 M88E1000_PSCR_POLARITY_REVERSAL);
1490
1491 ret_val = e1000_check_polarity_m88(hw);
1492 if (ret_val)
1493 return ret_val;
1494
1495 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1496 if (ret_val)
1497 return ret_val;
1498
1499 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX);
1500
1501 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1502 ret_val = e1000_get_cable_length(hw);
1503 if (ret_val)
1504 return ret_val;
1505
1506 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data);
1507 if (ret_val)
1508 return ret_val;
1509
1510 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1511 ? e1000_1000t_rx_status_ok
1512 : e1000_1000t_rx_status_not_ok;
1513
1514 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1515 ? e1000_1000t_rx_status_ok
1516 : e1000_1000t_rx_status_not_ok;
1517 } else {
1518 /* Set values to "undefined" */
1519 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1520 phy->local_rx = e1000_1000t_rx_status_undefined;
1521 phy->remote_rx = e1000_1000t_rx_status_undefined;
1522 }
1523
1524 return ret_val;
1525}
1526
1527/**
1528 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1529 * @hw: pointer to the HW structure
1530 *
1531 * Read PHY status to determine if link is up. If link is up, then
1532 * set/determine 10base-T extended distance and polarity correction. Read
1533 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1534 * determine on the cable length, local and remote receiver.
1535 **/
1536s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
1537{
1538 struct e1000_phy_info *phy = &hw->phy;
1539 s32 ret_val;
1540 u16 data;
1541 bool link;
1542
1543 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1544 if (ret_val)
1545 return ret_val;
1546
1547 if (!link) {
1548 hw_dbg(hw, "Phy info is only valid if link is up\n");
1549 return -E1000_ERR_CONFIG;
1550 }
1551
1552 phy->polarity_correction = 1;
1553
1554 ret_val = e1000_check_polarity_igp(hw);
1555 if (ret_val)
1556 return ret_val;
1557
1558 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1559 if (ret_val)
1560 return ret_val;
1561
1562 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX);
1563
1564 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1565 IGP01E1000_PSSR_SPEED_1000MBPS) {
1566 ret_val = e1000_get_cable_length(hw);
1567 if (ret_val)
1568 return ret_val;
1569
1570 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
1571 if (ret_val)
1572 return ret_val;
1573
1574 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
1575 ? e1000_1000t_rx_status_ok
1576 : e1000_1000t_rx_status_not_ok;
1577
1578 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
1579 ? e1000_1000t_rx_status_ok
1580 : e1000_1000t_rx_status_not_ok;
1581 } else {
1582 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1583 phy->local_rx = e1000_1000t_rx_status_undefined;
1584 phy->remote_rx = e1000_1000t_rx_status_undefined;
1585 }
1586
1587 return ret_val;
1588}
1589
1590/**
1591 * e1000e_phy_sw_reset - PHY software reset
1592 * @hw: pointer to the HW structure
1593 *
1594 * Does a software reset of the PHY by reading the PHY control register and
1595 * setting/write the control register reset bit to the PHY.
1596 **/
1597s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
1598{
1599 s32 ret_val;
1600 u16 phy_ctrl;
1601
1602 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
1603 if (ret_val)
1604 return ret_val;
1605
1606 phy_ctrl |= MII_CR_RESET;
1607 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
1608 if (ret_val)
1609 return ret_val;
1610
1611 udelay(1);
1612
1613 return ret_val;
1614}
1615
1616/**
1617 * e1000e_phy_hw_reset_generic - PHY hardware reset
1618 * @hw: pointer to the HW structure
1619 *
1620 * Verify the reset block is not blocking us from resetting. Acquire
1621 * semaphore (if necessary) and read/set/write the device control reset
1622 * bit in the PHY. Wait the appropriate delay time for the device to
1623 * reset and relase the semaphore (if necessary).
1624 **/
1625s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
1626{
1627 struct e1000_phy_info *phy = &hw->phy;
1628 s32 ret_val;
1629 u32 ctrl;
1630
1631 ret_val = e1000_check_reset_block(hw);
1632 if (ret_val)
1633 return 0;
1634
1635 ret_val = phy->ops.acquire_phy(hw);
1636 if (ret_val)
1637 return ret_val;
1638
1639 ctrl = er32(CTRL);
1640 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
1641 e1e_flush();
1642
1643 udelay(phy->reset_delay_us);
1644
1645 ew32(CTRL, ctrl);
1646 e1e_flush();
1647
1648 udelay(150);
1649
1650 phy->ops.release_phy(hw);
1651
1652 return e1000_get_phy_cfg_done(hw);
1653}
1654
1655/**
1656 * e1000e_get_cfg_done - Generic configuration done
1657 * @hw: pointer to the HW structure
1658 *
1659 * Generic function to wait 10 milli-seconds for configuration to complete
1660 * and return success.
1661 **/
1662s32 e1000e_get_cfg_done(struct e1000_hw *hw)
1663{
1664 mdelay(10);
1665 return 0;
1666}
1667
1668/* Internal function pointers */
1669
1670/**
1671 * e1000_get_phy_cfg_done - Generic PHY configuration done
1672 * @hw: pointer to the HW structure
1673 *
1674 * Return success if silicon family did not implement a family specific
1675 * get_cfg_done function.
1676 **/
1677static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
1678{
1679 if (hw->phy.ops.get_cfg_done)
1680 return hw->phy.ops.get_cfg_done(hw);
1681
1682 return 0;
1683}
1684
1685/**
1686 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
1687 * @hw: pointer to the HW structure
1688 *
1689 * When the silicon family has not implemented a forced speed/duplex
1690 * function for the PHY, simply return 0.
1691 **/
1692static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1693{
1694 if (hw->phy.ops.force_speed_duplex)
1695 return hw->phy.ops.force_speed_duplex(hw);
1696
1697 return 0;
1698}
1699
1700/**
1701 * e1000e_get_phy_type_from_id - Get PHY type from id
1702 * @phy_id: phy_id read from the phy
1703 *
1704 * Returns the phy type from the id.
1705 **/
1706enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
1707{
1708 enum e1000_phy_type phy_type = e1000_phy_unknown;
1709
1710 switch (phy_id) {
1711 case M88E1000_I_PHY_ID:
1712 case M88E1000_E_PHY_ID:
1713 case M88E1111_I_PHY_ID:
1714 case M88E1011_I_PHY_ID:
1715 phy_type = e1000_phy_m88;
1716 break;
1717 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
1718 phy_type = e1000_phy_igp_2;
1719 break;
1720 case GG82563_E_PHY_ID:
1721 phy_type = e1000_phy_gg82563;
1722 break;
1723 case IGP03E1000_E_PHY_ID:
1724 phy_type = e1000_phy_igp_3;
1725 break;
1726 case IFE_E_PHY_ID:
1727 case IFE_PLUS_E_PHY_ID:
1728 case IFE_C_E_PHY_ID:
1729 phy_type = e1000_phy_ife;
1730 break;
1731 default:
1732 phy_type = e1000_phy_unknown;
1733 break;
1734 }
1735 return phy_type;
1736}
1737
1738/**
1739 * e1000e_commit_phy - Soft PHY reset
1740 * @hw: pointer to the HW structure
1741 *
1742 * Performs a soft PHY reset on those that apply. This is a function pointer
1743 * entry point called by drivers.
1744 **/
1745s32 e1000e_commit_phy(struct e1000_hw *hw)
1746{
1747 if (hw->phy.ops.commit_phy)
1748 return hw->phy.ops.commit_phy(hw);
1749
1750 return 0;
1751}
1752
1753/**
1754 * e1000_set_d0_lplu_state - Sets low power link up state for D0
1755 * @hw: pointer to the HW structure
1756 * @active: boolean used to enable/disable lplu
1757 *
1758 * Success returns 0, Failure returns 1
1759 *
1760 * The low power link up (lplu) state is set to the power management level D0
1761 * and SmartSpeed is disabled when active is true, else clear lplu for D0
1762 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1763 * is used during Dx states where the power conservation is most important.
1764 * During driver activity, SmartSpeed should be enabled so performance is
1765 * maintained. This is a function pointer entry point called by drivers.
1766 **/
1767static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
1768{
1769 if (hw->phy.ops.set_d0_lplu_state)
1770 return hw->phy.ops.set_d0_lplu_state(hw, active);
1771
1772 return 0;
1773}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-13 06:09:38 -0500