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authorDavid S. Miller <davem@davemloft.net>2009-11-29 03:57:15 -0500
committerDavid S. Miller <davem@davemloft.net>2009-11-29 03:57:15 -0500
commit9b963e5d0e01461099a40117b05480f24b63381f (patch)
tree4756d554e37bf4ab7202f2c564cbe629af98b576 /drivers/net/e1000e/phy.c
parent3b8626ba01a8a745a3fdf22dd347edd708b0af13 (diff)
parent5fdd4baef6195a1f2960e901c8877e2105f832ca (diff)
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
Conflicts: drivers/ieee802154/fakehard.c drivers/net/e1000e/ich8lan.c drivers/net/e1000e/phy.c drivers/net/netxen/netxen_nic_init.c drivers/net/wireless/ath/ath9k/main.c
Diffstat (limited to 'drivers/net/e1000e/phy.c')
-rw-r--r--drivers/net/e1000e/phy.c56
1 files changed, 22 insertions, 34 deletions
diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c
index 99d53fae4307..5cd01c691c53 100644
--- a/drivers/net/e1000e/phy.c
+++ b/drivers/net/e1000e/phy.c
@@ -71,7 +71,6 @@ static const u16 e1000_igp_2_cable_length_table[] =
71#define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15) 71#define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
72#define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */ 72#define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */
73#define I82577_CTRL_REG 23 73#define I82577_CTRL_REG 23
74#define I82577_CTRL_DOWNSHIFT_MASK (7 << 10)
75 74
76/* 82577 specific PHY registers */ 75/* 82577 specific PHY registers */
77#define I82577_PHY_CTRL_2 18 76#define I82577_PHY_CTRL_2 18
@@ -660,15 +659,6 @@ s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
660 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; 659 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
661 660
662 ret_val = phy->ops.write_reg(hw, I82577_CFG_REG, phy_data); 661 ret_val = phy->ops.write_reg(hw, I82577_CFG_REG, phy_data);
663 if (ret_val)
664 goto out;
665
666 /* Set number of link attempts before downshift */
667 ret_val = phy->ops.read_reg(hw, I82577_CTRL_REG, &phy_data);
668 if (ret_val)
669 goto out;
670 phy_data &= ~I82577_CTRL_DOWNSHIFT_MASK;
671 ret_val = phy->ops.write_reg(hw, I82577_CTRL_REG, phy_data);
672 662
673out: 663out:
674 return ret_val; 664 return ret_val;
@@ -2658,19 +2648,18 @@ static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2658 page = 0; 2648 page = 0;
2659 2649
2660 if (reg > MAX_PHY_MULTI_PAGE_REG) { 2650 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2661 if ((hw->phy.type != e1000_phy_82578) || 2651 u32 phy_addr = hw->phy.addr;
2662 ((reg != I82578_ADDR_REG) &&
2663 (reg != I82578_ADDR_REG + 1))) {
2664 u32 phy_addr = hw->phy.addr;
2665 2652
2666 hw->phy.addr = 1; 2653 hw->phy.addr = 1;
2667 2654
2668 /* Page is shifted left, PHY expects (page x 32) */ 2655 /* Page is shifted left, PHY expects (page x 32) */
2669 ret_val = e1000e_write_phy_reg_mdic(hw, 2656 ret_val = e1000e_write_phy_reg_mdic(hw,
2670 IGP01E1000_PHY_PAGE_SELECT, 2657 IGP01E1000_PHY_PAGE_SELECT,
2671 (page << IGP_PAGE_SHIFT)); 2658 (page << IGP_PAGE_SHIFT));
2672 hw->phy.addr = phy_addr; 2659 hw->phy.addr = phy_addr;
2673 } 2660
2661 if (ret_val)
2662 goto out;
2674 } 2663 }
2675 2664
2676 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 2665 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
@@ -2678,7 +2667,7 @@ static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2678out: 2667out:
2679 /* Revert to MDIO fast mode, if applicable */ 2668 /* Revert to MDIO fast mode, if applicable */
2680 if ((hw->phy.type == e1000_phy_82577) && in_slow_mode) 2669 if ((hw->phy.type == e1000_phy_82577) && in_slow_mode)
2681 ret_val = e1000_set_mdio_slow_mode_hv(hw, false); 2670 ret_val |= e1000_set_mdio_slow_mode_hv(hw, false);
2682 2671
2683 if (!locked) 2672 if (!locked)
2684 hw->phy.ops.release(hw); 2673 hw->phy.ops.release(hw);
@@ -2784,19 +2773,18 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2784 } 2773 }
2785 2774
2786 if (reg > MAX_PHY_MULTI_PAGE_REG) { 2775 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2787 if ((hw->phy.type != e1000_phy_82578) || 2776 u32 phy_addr = hw->phy.addr;
2788 ((reg != I82578_ADDR_REG) &&
2789 (reg != I82578_ADDR_REG + 1))) {
2790 u32 phy_addr = hw->phy.addr;
2791 2777
2792 hw->phy.addr = 1; 2778 hw->phy.addr = 1;
2793 2779
2794 /* Page is shifted left, PHY expects (page x 32) */ 2780 /* Page is shifted left, PHY expects (page x 32) */
2795 ret_val = e1000e_write_phy_reg_mdic(hw, 2781 ret_val = e1000e_write_phy_reg_mdic(hw,
2796 IGP01E1000_PHY_PAGE_SELECT, 2782 IGP01E1000_PHY_PAGE_SELECT,
2797 (page << IGP_PAGE_SHIFT)); 2783 (page << IGP_PAGE_SHIFT));
2798 hw->phy.addr = phy_addr; 2784 hw->phy.addr = phy_addr;
2799 } 2785
2786 if (ret_val)
2787 goto out;
2800 } 2788 }
2801 2789
2802 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 2790 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
@@ -2805,7 +2793,7 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2805out: 2793out:
2806 /* Revert to MDIO fast mode, if applicable */ 2794 /* Revert to MDIO fast mode, if applicable */
2807 if ((hw->phy.type == e1000_phy_82577) && in_slow_mode) 2795 if ((hw->phy.type == e1000_phy_82577) && in_slow_mode)
2808 ret_val = e1000_set_mdio_slow_mode_hv(hw, false); 2796 ret_val |= e1000_set_mdio_slow_mode_hv(hw, false);
2809 2797
2810 if (!locked) 2798 if (!locked)
2811 hw->phy.ops.release(hw); 2799 hw->phy.ops.release(hw);