diff options
author | Bruce Allan <bruce.w.allan@intel.com> | 2010-06-16 09:27:28 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2010-06-19 01:12:16 -0400 |
commit | d3738bb8203acf8552c3ec8b3447133fc0938ddd (patch) | |
tree | c466411e6dce52ca422ad524ace68301c6b0d169 /drivers/net/e1000e/netdev.c | |
parent | eb7700dc0344564b0b9857d1f5e331a0dd629e92 (diff) |
e1000e: initial support for 82579 LOMs
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/e1000e/netdev.c')
-rw-r--r-- | drivers/net/e1000e/netdev.c | 70 |
1 files changed, 43 insertions, 27 deletions
diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c index b4c431d84516..f296f6f32a36 100644 --- a/drivers/net/e1000e/netdev.c +++ b/drivers/net/e1000e/netdev.c | |||
@@ -67,6 +67,7 @@ static const struct e1000_info *e1000_info_tbl[] = { | |||
67 | [board_ich9lan] = &e1000_ich9_info, | 67 | [board_ich9lan] = &e1000_ich9_info, |
68 | [board_ich10lan] = &e1000_ich10_info, | 68 | [board_ich10lan] = &e1000_ich10_info, |
69 | [board_pchlan] = &e1000_pch_info, | 69 | [board_pchlan] = &e1000_pch_info, |
70 | [board_pch2lan] = &e1000_pch2_info, | ||
70 | }; | 71 | }; |
71 | 72 | ||
72 | struct e1000_reg_info { | 73 | struct e1000_reg_info { |
@@ -2723,6 +2724,16 @@ static void e1000_setup_rctl(struct e1000_adapter *adapter) | |||
2723 | e1e_wphy(hw, 22, phy_data); | 2724 | e1e_wphy(hw, 22, phy_data); |
2724 | } | 2725 | } |
2725 | 2726 | ||
2727 | /* Workaround Si errata on 82579 - configure jumbo frame flow */ | ||
2728 | if (hw->mac.type == e1000_pch2lan) { | ||
2729 | s32 ret_val; | ||
2730 | |||
2731 | if (rctl & E1000_RCTL_LPE) | ||
2732 | ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true); | ||
2733 | else | ||
2734 | ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false); | ||
2735 | } | ||
2736 | |||
2726 | /* Setup buffer sizes */ | 2737 | /* Setup buffer sizes */ |
2727 | rctl &= ~E1000_RCTL_SZ_4096; | 2738 | rctl &= ~E1000_RCTL_SZ_4096; |
2728 | rctl |= E1000_RCTL_BSEX; | 2739 | rctl |= E1000_RCTL_BSEX; |
@@ -3118,7 +3129,27 @@ void e1000e_reset(struct e1000_adapter *adapter) | |||
3118 | * with ERT support assuming ERT set to E1000_ERT_2048), or | 3129 | * with ERT support assuming ERT set to E1000_ERT_2048), or |
3119 | * - the full Rx FIFO size minus one full frame | 3130 | * - the full Rx FIFO size minus one full frame |
3120 | */ | 3131 | */ |
3121 | if (hw->mac.type == e1000_pchlan) { | 3132 | if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME) |
3133 | fc->pause_time = 0xFFFF; | ||
3134 | else | ||
3135 | fc->pause_time = E1000_FC_PAUSE_TIME; | ||
3136 | fc->send_xon = 1; | ||
3137 | fc->current_mode = fc->requested_mode; | ||
3138 | |||
3139 | switch (hw->mac.type) { | ||
3140 | default: | ||
3141 | if ((adapter->flags & FLAG_HAS_ERT) && | ||
3142 | (adapter->netdev->mtu > ETH_DATA_LEN)) | ||
3143 | hwm = min(((pba << 10) * 9 / 10), | ||
3144 | ((pba << 10) - (E1000_ERT_2048 << 3))); | ||
3145 | else | ||
3146 | hwm = min(((pba << 10) * 9 / 10), | ||
3147 | ((pba << 10) - adapter->max_frame_size)); | ||
3148 | |||
3149 | fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */ | ||
3150 | fc->low_water = fc->high_water - 8; | ||
3151 | break; | ||
3152 | case e1000_pchlan: | ||
3122 | /* | 3153 | /* |
3123 | * Workaround PCH LOM adapter hangs with certain network | 3154 | * Workaround PCH LOM adapter hangs with certain network |
3124 | * loads. If hangs persist, try disabling Tx flow control. | 3155 | * loads. If hangs persist, try disabling Tx flow control. |
@@ -3131,26 +3162,15 @@ void e1000e_reset(struct e1000_adapter *adapter) | |||
3131 | fc->low_water = 0x3000; | 3162 | fc->low_water = 0x3000; |
3132 | } | 3163 | } |
3133 | fc->refresh_time = 0x1000; | 3164 | fc->refresh_time = 0x1000; |
3134 | } else { | 3165 | break; |
3135 | if ((adapter->flags & FLAG_HAS_ERT) && | 3166 | case e1000_pch2lan: |
3136 | (adapter->netdev->mtu > ETH_DATA_LEN)) | 3167 | fc->high_water = 0x05C20; |
3137 | hwm = min(((pba << 10) * 9 / 10), | 3168 | fc->low_water = 0x05048; |
3138 | ((pba << 10) - (E1000_ERT_2048 << 3))); | 3169 | fc->pause_time = 0x0650; |
3139 | else | 3170 | fc->refresh_time = 0x0400; |
3140 | hwm = min(((pba << 10) * 9 / 10), | 3171 | break; |
3141 | ((pba << 10) - adapter->max_frame_size)); | ||
3142 | |||
3143 | fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */ | ||
3144 | fc->low_water = fc->high_water - 8; | ||
3145 | } | 3172 | } |
3146 | 3173 | ||
3147 | if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME) | ||
3148 | fc->pause_time = 0xFFFF; | ||
3149 | else | ||
3150 | fc->pause_time = E1000_FC_PAUSE_TIME; | ||
3151 | fc->send_xon = 1; | ||
3152 | fc->current_mode = fc->requested_mode; | ||
3153 | |||
3154 | /* Allow time for pending master requests to run */ | 3174 | /* Allow time for pending master requests to run */ |
3155 | mac->ops.reset_hw(hw); | 3175 | mac->ops.reset_hw(hw); |
3156 | 3176 | ||
@@ -4918,14 +4938,7 @@ static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc) | |||
4918 | int retval = 0; | 4938 | int retval = 0; |
4919 | 4939 | ||
4920 | /* copy MAC RARs to PHY RARs */ | 4940 | /* copy MAC RARs to PHY RARs */ |
4921 | for (i = 0; i < adapter->hw.mac.rar_entry_count; i++) { | 4941 | e1000_copy_rx_addrs_to_phy_ich8lan(hw); |
4922 | mac_reg = er32(RAL(i)); | ||
4923 | e1e_wphy(hw, BM_RAR_L(i), (u16)(mac_reg & 0xFFFF)); | ||
4924 | e1e_wphy(hw, BM_RAR_M(i), (u16)((mac_reg >> 16) & 0xFFFF)); | ||
4925 | mac_reg = er32(RAH(i)); | ||
4926 | e1e_wphy(hw, BM_RAR_H(i), (u16)(mac_reg & 0xFFFF)); | ||
4927 | e1e_wphy(hw, BM_RAR_CTRL(i), (u16)((mac_reg >> 16) & 0xFFFF)); | ||
4928 | } | ||
4929 | 4942 | ||
4930 | /* copy MAC MTA to PHY MTA */ | 4943 | /* copy MAC MTA to PHY MTA */ |
4931 | for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) { | 4944 | for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) { |
@@ -5976,6 +5989,9 @@ static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = { | |||
5976 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan }, | 5989 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan }, |
5977 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan }, | 5990 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan }, |
5978 | 5991 | ||
5992 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan }, | ||
5993 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan }, | ||
5994 | |||
5979 | { } /* terminate list */ | 5995 | { } /* terminate list */ |
5980 | }; | 5996 | }; |
5981 | MODULE_DEVICE_TABLE(pci, e1000_pci_tbl); | 5997 | MODULE_DEVICE_TABLE(pci, e1000_pci_tbl); |