diff options
author | Jesse Brandeburg <jesse.brandeburg@intel.com> | 2011-07-19 20:56:21 -0400 |
---|---|---|
committer | Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2011-08-04 07:59:07 -0400 |
commit | 945a51517cc0bd9e461f2018624dfc1faef9ddee (patch) | |
tree | 5782ffe27f3fb8f5b4cbc19ffe7b74bff36c6a05 /drivers/net/e1000e/ich8lan.c | |
parent | d3e614577198757d5854caa912e88f2d4296479b (diff) |
intel drivers: repair missing flush operations
after review of all intel drivers, found several instances where
drivers had the incorrect pattern of:
memory mapped write();
delay();
which should always be:
memory mapped write();
write flush(); /* aka memory mapped read */
delay();
explanation:
The reason for including the flush is that writes can be held
(posted) in PCI/PCIe bridges, but the read always has to complete
synchronously and therefore has to flush all pending writes to a
device. If a write is held and followed by a delay, the delay
means nothing because the write may not have reached hardware
(maybe even not until the next read)
Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/e1000e/ich8lan.c')
-rw-r--r-- | drivers/net/e1000e/ich8lan.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c index c1752124f3cd..f7a75c1531ad 100644 --- a/drivers/net/e1000e/ich8lan.c +++ b/drivers/net/e1000e/ich8lan.c | |||
@@ -283,6 +283,7 @@ static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw *hw) | |||
283 | ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE; | 283 | ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE; |
284 | ctrl &= ~E1000_CTRL_LANPHYPC_VALUE; | 284 | ctrl &= ~E1000_CTRL_LANPHYPC_VALUE; |
285 | ew32(CTRL, ctrl); | 285 | ew32(CTRL, ctrl); |
286 | e1e_flush(); | ||
286 | udelay(10); | 287 | udelay(10); |
287 | ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE; | 288 | ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE; |
288 | ew32(CTRL, ctrl); | 289 | ew32(CTRL, ctrl); |
@@ -1230,9 +1231,11 @@ s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) | |||
1230 | ew32(CTRL, reg); | 1231 | ew32(CTRL, reg); |
1231 | 1232 | ||
1232 | ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); | 1233 | ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); |
1234 | e1e_flush(); | ||
1233 | udelay(20); | 1235 | udelay(20); |
1234 | ew32(CTRL, ctrl_reg); | 1236 | ew32(CTRL, ctrl_reg); |
1235 | ew32(CTRL_EXT, ctrl_ext); | 1237 | ew32(CTRL_EXT, ctrl_ext); |
1238 | e1e_flush(); | ||
1236 | udelay(20); | 1239 | udelay(20); |
1237 | 1240 | ||
1238 | out: | 1241 | out: |
@@ -3090,6 +3093,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) | |||
3090 | ret_val = e1000_acquire_swflag_ich8lan(hw); | 3093 | ret_val = e1000_acquire_swflag_ich8lan(hw); |
3091 | e_dbg("Issuing a global reset to ich8lan\n"); | 3094 | e_dbg("Issuing a global reset to ich8lan\n"); |
3092 | ew32(CTRL, (ctrl | E1000_CTRL_RST)); | 3095 | ew32(CTRL, (ctrl | E1000_CTRL_RST)); |
3096 | /* cannot issue a flush here because it hangs the hardware */ | ||
3093 | msleep(20); | 3097 | msleep(20); |
3094 | 3098 | ||
3095 | if (!ret_val) | 3099 | if (!ret_val) |