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authorBruce Allan <bruce.w.allan@intel.com>2011-02-25 01:25:18 -0500
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-03-11 05:14:56 -0500
commit6cc7aaed70c96c3933fbacbad582fc79b7d6e335 (patch)
treeb01610d2eb974637e20d96364bb6bc513f0a3da4 /drivers/net/e1000e/ich8lan.c
parent1effb45cca29e22e4b2209bb567770b7e20a3a2b (diff)
e1000e: do not toggle LANPHYPC value bit when PHY reset is blocked
When PHY reset is intentionally blocked on 82577/8/9, do not toggle the LANPHYPC value bit (essentially performing a hard power reset of the device) otherwise the PHY can be put into an unknown state. Cleanup whitespace in the same function. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/e1000e/ich8lan.c')
-rw-r--r--drivers/net/e1000e/ich8lan.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c
index cf18d65417e6..9b434c0cbc9f 100644
--- a/drivers/net/e1000e/ich8lan.c
+++ b/drivers/net/e1000e/ich8lan.c
@@ -307,9 +307,9 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
307 * the interconnect to PCIe mode. 307 * the interconnect to PCIe mode.
308 */ 308 */
309 fwsm = er32(FWSM); 309 fwsm = er32(FWSM);
310 if (!(fwsm & E1000_ICH_FWSM_FW_VALID)) { 310 if (!(fwsm & E1000_ICH_FWSM_FW_VALID) && !e1000_check_reset_block(hw)) {
311 ctrl = er32(CTRL); 311 ctrl = er32(CTRL);
312 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE; 312 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
313 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE; 313 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
314 ew32(CTRL, ctrl); 314 ew32(CTRL, ctrl);
315 udelay(10); 315 udelay(10);
@@ -336,7 +336,7 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
336 goto out; 336 goto out;
337 337
338 /* Ungate automatic PHY configuration on non-managed 82579 */ 338 /* Ungate automatic PHY configuration on non-managed 82579 */
339 if ((hw->mac.type == e1000_pch2lan) && 339 if ((hw->mac.type == e1000_pch2lan) &&
340 !(fwsm & E1000_ICH_FWSM_FW_VALID)) { 340 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
341 msleep(10); 341 msleep(10);
342 e1000_gate_hw_phy_config_ich8lan(hw, false); 342 e1000_gate_hw_phy_config_ich8lan(hw, false);
@@ -371,7 +371,7 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
371 case e1000_phy_82579: 371 case e1000_phy_82579:
372 phy->ops.check_polarity = e1000_check_polarity_82577; 372 phy->ops.check_polarity = e1000_check_polarity_82577;
373 phy->ops.force_speed_duplex = 373 phy->ops.force_speed_duplex =
374 e1000_phy_force_speed_duplex_82577; 374 e1000_phy_force_speed_duplex_82577;
375 phy->ops.get_cable_length = e1000_get_cable_length_82577; 375 phy->ops.get_cable_length = e1000_get_cable_length_82577;
376 phy->ops.get_info = e1000_get_phy_info_82577; 376 phy->ops.get_info = e1000_get_phy_info_82577;
377 phy->ops.commit = e1000e_phy_sw_reset; 377 phy->ops.commit = e1000e_phy_sw_reset;