diff options
author | Bruce Allan <bruce.w.allan@intel.com> | 2009-11-20 18:25:07 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-11-21 14:34:05 -0500 |
commit | 3bb99fe226ead584a4db674dab546689f705201f (patch) | |
tree | 3b49aaef9f4b798b7930a76f62e754eefe0ddb91 /drivers/net/e1000e/ich8lan.c | |
parent | d8014dbca7f5d2d6f0fdb47e5286bd2d887f7065 (diff) |
e1000e: consolidate two dbug macros into one simpler one
This patch depends on a previous one that cleans up redundant #includes.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/e1000e/ich8lan.c')
-rw-r--r-- | drivers/net/e1000e/ich8lan.c | 69 |
1 files changed, 34 insertions, 35 deletions
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c index bef5e3333f2a..101a2714467e 100644 --- a/drivers/net/e1000e/ich8lan.c +++ b/drivers/net/e1000e/ich8lan.c | |||
@@ -368,7 +368,7 @@ static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) | |||
368 | 368 | ||
369 | /* Can't read flash registers if the register set isn't mapped. */ | 369 | /* Can't read flash registers if the register set isn't mapped. */ |
370 | if (!hw->flash_address) { | 370 | if (!hw->flash_address) { |
371 | hw_dbg(hw, "ERROR: Flash registers not mapped\n"); | 371 | e_dbg("ERROR: Flash registers not mapped\n"); |
372 | return -E1000_ERR_CONFIG; | 372 | return -E1000_ERR_CONFIG; |
373 | } | 373 | } |
374 | 374 | ||
@@ -550,7 +550,7 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) | |||
550 | */ | 550 | */ |
551 | ret_val = e1000e_config_fc_after_link_up(hw); | 551 | ret_val = e1000e_config_fc_after_link_up(hw); |
552 | if (ret_val) | 552 | if (ret_val) |
553 | hw_dbg(hw, "Error configuring flow control\n"); | 553 | e_dbg("Error configuring flow control\n"); |
554 | 554 | ||
555 | out: | 555 | out: |
556 | return ret_val; | 556 | return ret_val; |
@@ -644,7 +644,7 @@ static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) | |||
644 | } | 644 | } |
645 | 645 | ||
646 | if (!timeout) { | 646 | if (!timeout) { |
647 | hw_dbg(hw, "SW/FW/HW has locked the resource for too long.\n"); | 647 | e_dbg("SW/FW/HW has locked the resource for too long.\n"); |
648 | ret_val = -E1000_ERR_CONFIG; | 648 | ret_val = -E1000_ERR_CONFIG; |
649 | goto out; | 649 | goto out; |
650 | } | 650 | } |
@@ -664,7 +664,7 @@ static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) | |||
664 | } | 664 | } |
665 | 665 | ||
666 | if (!timeout) { | 666 | if (!timeout) { |
667 | hw_dbg(hw, "Failed to acquire the semaphore.\n"); | 667 | e_dbg("Failed to acquire the semaphore.\n"); |
668 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; | 668 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; |
669 | ew32(EXTCNF_CTRL, extcnf_ctrl); | 669 | ew32(EXTCNF_CTRL, extcnf_ctrl); |
670 | ret_val = -E1000_ERR_CONFIG; | 670 | ret_val = -E1000_ERR_CONFIG; |
@@ -773,12 +773,12 @@ static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw) | |||
773 | if (ret_val) | 773 | if (ret_val) |
774 | return ret_val; | 774 | return ret_val; |
775 | 775 | ||
776 | hw_dbg(hw, "IFE PMC: %X\n", data); | 776 | e_dbg("IFE PMC: %X\n", data); |
777 | 777 | ||
778 | udelay(1); | 778 | udelay(1); |
779 | 779 | ||
780 | if (phy->autoneg_wait_to_complete) { | 780 | if (phy->autoneg_wait_to_complete) { |
781 | hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n"); | 781 | e_dbg("Waiting for forced speed/duplex link on IFE phy.\n"); |
782 | 782 | ||
783 | ret_val = e1000e_phy_has_link_generic(hw, | 783 | ret_val = e1000e_phy_has_link_generic(hw, |
784 | PHY_FORCE_LIMIT, | 784 | PHY_FORCE_LIMIT, |
@@ -788,7 +788,7 @@ static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw) | |||
788 | return ret_val; | 788 | return ret_val; |
789 | 789 | ||
790 | if (!link) | 790 | if (!link) |
791 | hw_dbg(hw, "Link taking longer than expected.\n"); | 791 | e_dbg("Link taking longer than expected.\n"); |
792 | 792 | ||
793 | /* Try once more */ | 793 | /* Try once more */ |
794 | ret_val = e1000e_phy_has_link_generic(hw, | 794 | ret_val = e1000e_phy_has_link_generic(hw, |
@@ -1203,7 +1203,7 @@ static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) | |||
1203 | * leave the PHY in a bad state possibly resulting in no link. | 1203 | * leave the PHY in a bad state possibly resulting in no link. |
1204 | */ | 1204 | */ |
1205 | if (loop == 0) | 1205 | if (loop == 0) |
1206 | hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n"); | 1206 | e_dbg("LAN_INIT_DONE not set, increase timeout\n"); |
1207 | 1207 | ||
1208 | /* Clear the Init Done bit for the next init event */ | 1208 | /* Clear the Init Done bit for the next init event */ |
1209 | data = er32(STATUS); | 1209 | data = er32(STATUS); |
@@ -1274,7 +1274,7 @@ static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw) | |||
1274 | return ret_val; | 1274 | return ret_val; |
1275 | 1275 | ||
1276 | if (!link) { | 1276 | if (!link) { |
1277 | hw_dbg(hw, "Phy info is only valid if link is up\n"); | 1277 | e_dbg("Phy info is only valid if link is up\n"); |
1278 | return -E1000_ERR_CONFIG; | 1278 | return -E1000_ERR_CONFIG; |
1279 | } | 1279 | } |
1280 | 1280 | ||
@@ -1604,7 +1604,7 @@ static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) | |||
1604 | 1604 | ||
1605 | return 0; | 1605 | return 0; |
1606 | } | 1606 | } |
1607 | hw_dbg(hw, "Unable to determine valid NVM bank via EEC - " | 1607 | e_dbg("Unable to determine valid NVM bank via EEC - " |
1608 | "reading flash signature\n"); | 1608 | "reading flash signature\n"); |
1609 | /* fall-thru */ | 1609 | /* fall-thru */ |
1610 | default: | 1610 | default: |
@@ -1634,7 +1634,7 @@ static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) | |||
1634 | return 0; | 1634 | return 0; |
1635 | } | 1635 | } |
1636 | 1636 | ||
1637 | hw_dbg(hw, "ERROR: No valid NVM bank present\n"); | 1637 | e_dbg("ERROR: No valid NVM bank present\n"); |
1638 | return -E1000_ERR_NVM; | 1638 | return -E1000_ERR_NVM; |
1639 | } | 1639 | } |
1640 | 1640 | ||
@@ -1662,7 +1662,7 @@ static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, | |||
1662 | 1662 | ||
1663 | if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || | 1663 | if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || |
1664 | (words == 0)) { | 1664 | (words == 0)) { |
1665 | hw_dbg(hw, "nvm parameter(s) out of bounds\n"); | 1665 | e_dbg("nvm parameter(s) out of bounds\n"); |
1666 | ret_val = -E1000_ERR_NVM; | 1666 | ret_val = -E1000_ERR_NVM; |
1667 | goto out; | 1667 | goto out; |
1668 | } | 1668 | } |
@@ -1671,7 +1671,7 @@ static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, | |||
1671 | 1671 | ||
1672 | ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); | 1672 | ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); |
1673 | if (ret_val) { | 1673 | if (ret_val) { |
1674 | hw_dbg(hw, "Could not detect valid bank, assuming bank 0\n"); | 1674 | e_dbg("Could not detect valid bank, assuming bank 0\n"); |
1675 | bank = 0; | 1675 | bank = 0; |
1676 | } | 1676 | } |
1677 | 1677 | ||
@@ -1697,7 +1697,7 @@ static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, | |||
1697 | 1697 | ||
1698 | out: | 1698 | out: |
1699 | if (ret_val) | 1699 | if (ret_val) |
1700 | hw_dbg(hw, "NVM read error: %d\n", ret_val); | 1700 | e_dbg("NVM read error: %d\n", ret_val); |
1701 | 1701 | ||
1702 | return ret_val; | 1702 | return ret_val; |
1703 | } | 1703 | } |
@@ -1719,7 +1719,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) | |||
1719 | 1719 | ||
1720 | /* Check if the flash descriptor is valid */ | 1720 | /* Check if the flash descriptor is valid */ |
1721 | if (hsfsts.hsf_status.fldesvalid == 0) { | 1721 | if (hsfsts.hsf_status.fldesvalid == 0) { |
1722 | hw_dbg(hw, "Flash descriptor invalid. " | 1722 | e_dbg("Flash descriptor invalid. " |
1723 | "SW Sequencing must be used."); | 1723 | "SW Sequencing must be used."); |
1724 | return -E1000_ERR_NVM; | 1724 | return -E1000_ERR_NVM; |
1725 | } | 1725 | } |
@@ -1769,7 +1769,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) | |||
1769 | hsfsts.hsf_status.flcdone = 1; | 1769 | hsfsts.hsf_status.flcdone = 1; |
1770 | ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); | 1770 | ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); |
1771 | } else { | 1771 | } else { |
1772 | hw_dbg(hw, "Flash controller busy, cannot get access"); | 1772 | e_dbg("Flash controller busy, cannot get access"); |
1773 | } | 1773 | } |
1774 | } | 1774 | } |
1775 | 1775 | ||
@@ -1919,7 +1919,7 @@ static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, | |||
1919 | /* Repeat for some time before giving up. */ | 1919 | /* Repeat for some time before giving up. */ |
1920 | continue; | 1920 | continue; |
1921 | } else if (hsfsts.hsf_status.flcdone == 0) { | 1921 | } else if (hsfsts.hsf_status.flcdone == 0) { |
1922 | hw_dbg(hw, "Timeout error - flash cycle " | 1922 | e_dbg("Timeout error - flash cycle " |
1923 | "did not complete."); | 1923 | "did not complete."); |
1924 | break; | 1924 | break; |
1925 | } | 1925 | } |
@@ -1947,7 +1947,7 @@ static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, | |||
1947 | 1947 | ||
1948 | if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || | 1948 | if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || |
1949 | (words == 0)) { | 1949 | (words == 0)) { |
1950 | hw_dbg(hw, "nvm parameter(s) out of bounds\n"); | 1950 | e_dbg("nvm parameter(s) out of bounds\n"); |
1951 | return -E1000_ERR_NVM; | 1951 | return -E1000_ERR_NVM; |
1952 | } | 1952 | } |
1953 | 1953 | ||
@@ -1998,7 +1998,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) | |||
1998 | */ | 1998 | */ |
1999 | ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); | 1999 | ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); |
2000 | if (ret_val) { | 2000 | if (ret_val) { |
2001 | hw_dbg(hw, "Could not detect valid bank, assuming bank 0\n"); | 2001 | e_dbg("Could not detect valid bank, assuming bank 0\n"); |
2002 | bank = 0; | 2002 | bank = 0; |
2003 | } | 2003 | } |
2004 | 2004 | ||
@@ -2072,7 +2072,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) | |||
2072 | */ | 2072 | */ |
2073 | if (ret_val) { | 2073 | if (ret_val) { |
2074 | /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ | 2074 | /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ |
2075 | hw_dbg(hw, "Flash commit failed.\n"); | 2075 | e_dbg("Flash commit failed.\n"); |
2076 | nvm->ops.release_nvm(hw); | 2076 | nvm->ops.release_nvm(hw); |
2077 | goto out; | 2077 | goto out; |
2078 | } | 2078 | } |
@@ -2128,7 +2128,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) | |||
2128 | 2128 | ||
2129 | out: | 2129 | out: |
2130 | if (ret_val) | 2130 | if (ret_val) |
2131 | hw_dbg(hw, "NVM update error: %d\n", ret_val); | 2131 | e_dbg("NVM update error: %d\n", ret_val); |
2132 | 2132 | ||
2133 | return ret_val; | 2133 | return ret_val; |
2134 | } | 2134 | } |
@@ -2278,7 +2278,7 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, | |||
2278 | /* Repeat for some time before giving up. */ | 2278 | /* Repeat for some time before giving up. */ |
2279 | continue; | 2279 | continue; |
2280 | if (hsfsts.hsf_status.flcdone == 0) { | 2280 | if (hsfsts.hsf_status.flcdone == 0) { |
2281 | hw_dbg(hw, "Timeout error - flash cycle " | 2281 | e_dbg("Timeout error - flash cycle " |
2282 | "did not complete."); | 2282 | "did not complete."); |
2283 | break; | 2283 | break; |
2284 | } | 2284 | } |
@@ -2323,7 +2323,7 @@ static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, | |||
2323 | return ret_val; | 2323 | return ret_val; |
2324 | 2324 | ||
2325 | for (program_retries = 0; program_retries < 100; program_retries++) { | 2325 | for (program_retries = 0; program_retries < 100; program_retries++) { |
2326 | hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset); | 2326 | e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset); |
2327 | udelay(100); | 2327 | udelay(100); |
2328 | ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); | 2328 | ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); |
2329 | if (!ret_val) | 2329 | if (!ret_val) |
@@ -2458,7 +2458,7 @@ static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) | |||
2458 | 2458 | ||
2459 | ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); | 2459 | ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); |
2460 | if (ret_val) { | 2460 | if (ret_val) { |
2461 | hw_dbg(hw, "NVM Read Error\n"); | 2461 | e_dbg("NVM Read Error\n"); |
2462 | return ret_val; | 2462 | return ret_val; |
2463 | } | 2463 | } |
2464 | 2464 | ||
@@ -2588,10 +2588,10 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) | |||
2588 | */ | 2588 | */ |
2589 | ret_val = e1000e_disable_pcie_master(hw); | 2589 | ret_val = e1000e_disable_pcie_master(hw); |
2590 | if (ret_val) { | 2590 | if (ret_val) { |
2591 | hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); | 2591 | e_dbg("PCI-E Master disable polling has failed.\n"); |
2592 | } | 2592 | } |
2593 | 2593 | ||
2594 | hw_dbg(hw, "Masking off all interrupts\n"); | 2594 | e_dbg("Masking off all interrupts\n"); |
2595 | ew32(IMC, 0xffffffff); | 2595 | ew32(IMC, 0xffffffff); |
2596 | 2596 | ||
2597 | /* | 2597 | /* |
@@ -2643,7 +2643,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) | |||
2643 | } | 2643 | } |
2644 | ret_val = e1000_acquire_swflag_ich8lan(hw); | 2644 | ret_val = e1000_acquire_swflag_ich8lan(hw); |
2645 | /* Whether or not the swflag was acquired, we need to reset the part */ | 2645 | /* Whether or not the swflag was acquired, we need to reset the part */ |
2646 | hw_dbg(hw, "Issuing a global reset to ich8lan\n"); | 2646 | e_dbg("Issuing a global reset to ich8lan\n"); |
2647 | ew32(CTRL, (ctrl | E1000_CTRL_RST)); | 2647 | ew32(CTRL, (ctrl | E1000_CTRL_RST)); |
2648 | msleep(20); | 2648 | msleep(20); |
2649 | 2649 | ||
@@ -2663,7 +2663,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) | |||
2663 | * return with an error. This can happen in situations | 2663 | * return with an error. This can happen in situations |
2664 | * where there is no eeprom and prevents getting link. | 2664 | * where there is no eeprom and prevents getting link. |
2665 | */ | 2665 | */ |
2666 | hw_dbg(hw, "Auto Read Done did not complete\n"); | 2666 | e_dbg("Auto Read Done did not complete\n"); |
2667 | } | 2667 | } |
2668 | } | 2668 | } |
2669 | /* Dummy read to clear the phy wakeup bit after lcd reset */ | 2669 | /* Dummy read to clear the phy wakeup bit after lcd reset */ |
@@ -2725,7 +2725,7 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) | |||
2725 | /* Initialize identification LED */ | 2725 | /* Initialize identification LED */ |
2726 | ret_val = mac->ops.id_led_init(hw); | 2726 | ret_val = mac->ops.id_led_init(hw); |
2727 | if (ret_val) { | 2727 | if (ret_val) { |
2728 | hw_dbg(hw, "Error initializing identification LED\n"); | 2728 | e_dbg("Error initializing identification LED\n"); |
2729 | return ret_val; | 2729 | return ret_val; |
2730 | } | 2730 | } |
2731 | 2731 | ||
@@ -2733,7 +2733,7 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) | |||
2733 | e1000e_init_rx_addrs(hw, mac->rar_entry_count); | 2733 | e1000e_init_rx_addrs(hw, mac->rar_entry_count); |
2734 | 2734 | ||
2735 | /* Zero out the Multicast HASH table */ | 2735 | /* Zero out the Multicast HASH table */ |
2736 | hw_dbg(hw, "Zeroing the MTA\n"); | 2736 | e_dbg("Zeroing the MTA\n"); |
2737 | for (i = 0; i < mac->mta_reg_count; i++) | 2737 | for (i = 0; i < mac->mta_reg_count; i++) |
2738 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); | 2738 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); |
2739 | 2739 | ||
@@ -2879,7 +2879,7 @@ static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) | |||
2879 | */ | 2879 | */ |
2880 | hw->fc.current_mode = hw->fc.requested_mode; | 2880 | hw->fc.current_mode = hw->fc.requested_mode; |
2881 | 2881 | ||
2882 | hw_dbg(hw, "After fix-ups FlowControl is now = %x\n", | 2882 | e_dbg("After fix-ups FlowControl is now = %x\n", |
2883 | hw->fc.current_mode); | 2883 | hw->fc.current_mode); |
2884 | 2884 | ||
2885 | /* Continue to configure the copper link. */ | 2885 | /* Continue to configure the copper link. */ |
@@ -3094,7 +3094,7 @@ void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, | |||
3094 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | 3094 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
3095 | 3095 | ||
3096 | if (hw->mac.type != e1000_ich8lan) { | 3096 | if (hw->mac.type != e1000_ich8lan) { |
3097 | hw_dbg(hw, "Workaround applies to ICH8 only.\n"); | 3097 | e_dbg("Workaround applies to ICH8 only.\n"); |
3098 | return; | 3098 | return; |
3099 | } | 3099 | } |
3100 | 3100 | ||
@@ -3372,8 +3372,7 @@ static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) | |||
3372 | if (status & E1000_STATUS_PHYRA) | 3372 | if (status & E1000_STATUS_PHYRA) |
3373 | ew32(STATUS, status & ~E1000_STATUS_PHYRA); | 3373 | ew32(STATUS, status & ~E1000_STATUS_PHYRA); |
3374 | else | 3374 | else |
3375 | hw_dbg(hw, | 3375 | e_dbg("PHY Reset Asserted not set - needs delay\n"); |
3376 | "PHY Reset Asserted not set - needs delay\n"); | ||
3377 | } | 3376 | } |
3378 | 3377 | ||
3379 | e1000e_get_cfg_done(hw); | 3378 | e1000e_get_cfg_done(hw); |
@@ -3388,7 +3387,7 @@ static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) | |||
3388 | } else { | 3387 | } else { |
3389 | if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { | 3388 | if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { |
3390 | /* Maybe we should do a basic PHY config */ | 3389 | /* Maybe we should do a basic PHY config */ |
3391 | hw_dbg(hw, "EEPROM not present\n"); | 3390 | e_dbg("EEPROM not present\n"); |
3392 | return -E1000_ERR_CONFIG; | 3391 | return -E1000_ERR_CONFIG; |
3393 | } | 3392 | } |
3394 | } | 3393 | } |