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author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2008-05-09 18:24:09 -0400 |
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committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-05-09 18:24:09 -0400 |
commit | 1f2ee6496b1f71e9d5aa2448745e65fbafdc3bd5 (patch) | |
tree | 3f143311afca5e316afd06c2fc4f7d73b19cdcf0 /drivers/net/e1000e/hw.h | |
parent | 5bf6c6e30d8b71d092e8830208e182d84b907fcd (diff) | |
parent | da109897a142dd017172c0ce7abf0be8646f7109 (diff) |
Merge branch 'for-rmk' of git://git.kernel.org/pub/scm/linux/kernel/git/nico/orion into fixes
Diffstat (limited to 'drivers/net/e1000e/hw.h')
-rw-r--r-- | drivers/net/e1000e/hw.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/net/e1000e/hw.h b/drivers/net/e1000e/hw.h index a930e6d9cf02..74f263acb172 100644 --- a/drivers/net/e1000e/hw.h +++ b/drivers/net/e1000e/hw.h | |||
@@ -216,6 +216,21 @@ enum e1e_registers { | |||
216 | #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ | 216 | #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ |
217 | #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ | 217 | #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ |
218 | #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ | 218 | #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ |
219 | #define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */ | ||
220 | #define IGP_PAGE_SHIFT 5 | ||
221 | #define PHY_REG_MASK 0x1F | ||
222 | |||
223 | #define BM_WUC_PAGE 800 | ||
224 | #define BM_WUC_ADDRESS_OPCODE 0x11 | ||
225 | #define BM_WUC_DATA_OPCODE 0x12 | ||
226 | #define BM_WUC_ENABLE_PAGE 769 | ||
227 | #define BM_WUC_ENABLE_REG 17 | ||
228 | #define BM_WUC_ENABLE_BIT (1 << 2) | ||
229 | #define BM_WUC_HOST_WU_BIT (1 << 4) | ||
230 | |||
231 | #define BM_WUC PHY_REG(BM_WUC_PAGE, 1) | ||
232 | #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2) | ||
233 | #define BM_WUS PHY_REG(BM_WUC_PAGE, 3) | ||
219 | 234 | ||
220 | #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 | 235 | #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 |
221 | #define IGP01E1000_PHY_POLARITY_MASK 0x0078 | 236 | #define IGP01E1000_PHY_POLARITY_MASK 0x0078 |
@@ -331,10 +346,16 @@ enum e1e_registers { | |||
331 | #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 | 346 | #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 |
332 | #define E1000_DEV_ID_ICH8_IGP_M 0x104D | 347 | #define E1000_DEV_ID_ICH8_IGP_M 0x104D |
333 | #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD | 348 | #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD |
349 | #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 | ||
350 | #define E1000_DEV_ID_ICH9_IGP_M 0x10BF | ||
351 | #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB | ||
334 | #define E1000_DEV_ID_ICH9_IGP_C 0x294C | 352 | #define E1000_DEV_ID_ICH9_IGP_C 0x294C |
335 | #define E1000_DEV_ID_ICH9_IFE 0x10C0 | 353 | #define E1000_DEV_ID_ICH9_IFE 0x10C0 |
336 | #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 | 354 | #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 |
337 | #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 | 355 | #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 |
356 | #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC | ||
357 | #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD | ||
358 | #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE | ||
338 | 359 | ||
339 | #define E1000_FUNC_1 1 | 360 | #define E1000_FUNC_1 1 |
340 | 361 | ||
@@ -378,6 +399,7 @@ enum e1000_phy_type { | |||
378 | e1000_phy_gg82563, | 399 | e1000_phy_gg82563, |
379 | e1000_phy_igp_3, | 400 | e1000_phy_igp_3, |
380 | e1000_phy_ife, | 401 | e1000_phy_ife, |
402 | e1000_phy_bm, | ||
381 | }; | 403 | }; |
382 | 404 | ||
383 | enum e1000_bus_width { | 405 | enum e1000_bus_width { |