e1000e: reformat comment blocks, cosmetic changes only

Adjusting the comment blocks here to be code-style compliant. no
code changes.

Changed some copyright dates to 2008.

Indentation fixes.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>

1 files changed, 52 insertions, 37 deletions

diff --git a/drivers/net/e1000e/es2lan.c b/drivers/net/e1000e/es2lan.c
index 88657adf965f..265775447538 100644
--- a/drivers/net/e1000e/es2lan.c
+++ b/drivers/net/e1000e/es2lan.c
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   Intel PRO/1000 Linux driver
-  Copyright(c) 1999 - 2007 Intel Corporation.
+  Copyright(c) 1999 - 2008 Intel Corporation.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms and conditions of the GNU General Public License,
@@ -92,7 +92,8 @@
 /* In-Band Control Register (Page 194, Register 18) */
 #define GG82563_ICR_DIS_PADDING                  0x0010 /* Disable Padding */
 
-/* A table for the GG82563 cable length where the range is defined
+/*
+ * A table for the GG82563 cable length where the range is defined
  * with a lower bound at "index" and the upper bound at
  * "index + 5".
  */
@@ -167,12 +168,13 @@ static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
                 break;
         }
 
-        nvm->type              = e1000_nvm_eeprom_spi;
+        nvm->type = e1000_nvm_eeprom_spi;
 
         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
                           E1000_EECD_SIZE_EX_SHIFT);
 
-        /* Added to a constant, "size" becomes the left-shift value
+        /*
+         * Added to a constant, "size" becomes the left-shift value
          * for setting word_size.
          */
         size += NVM_WORD_SIZE_BASE_SHIFT;
@@ -208,8 +210,7 @@ static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter)
         /* Set rar entry count */
         mac->rar_entry_count = E1000_RAR_ENTRIES;
         /* Set if manageability features are enabled. */
-        mac->arc_subsystem_valid =
-                (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0;
+        mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0;
 
         /* check for link */
         switch (hw->media_type) {
@@ -344,8 +345,10 @@ static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
                 if (!(swfw_sync & (fwmask | swmask)))
                         break;
 
-                /* Firmware currently using resource (fwmask)
-                 * or other software thread using resource (swmask) */
+                /*
+                 * Firmware currently using resource (fwmask)
+                 * or other software thread using resource (swmask)
+                 */
                 e1000e_put_hw_semaphore(hw);
                 mdelay(5);
                 i++;
@@ -407,7 +410,8 @@ static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG)
                 page_select = GG82563_PHY_PAGE_SELECT;
         else
-                /* Use Alternative Page Select register to access
+                /*
+                 * Use Alternative Page Select register to access
                  * registers 30 and 31
                  */
                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
@@ -417,7 +421,8 @@ static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
         if (ret_val)
                 return ret_val;
 
-        /* The "ready" bit in the MDIC register may be incorrectly set
+        /*
+         * The "ready" bit in the MDIC register may be incorrectly set
          * before the device has completed the "Page Select" MDI
          * transaction.  So we wait 200us after each MDI command...
          */
@@ -462,7 +467,8 @@ static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG)
                 page_select = GG82563_PHY_PAGE_SELECT;
         else
-                /* Use Alternative Page Select register to access
+                /*
+                 * Use Alternative Page Select register to access
                  * registers 30 and 31
                  */
                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
@@ -473,7 +479,8 @@ static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
                 return ret_val;
 
 
-        /* The "ready" bit in the MDIC register may be incorrectly set
+        /*
+         * The "ready" bit in the MDIC register may be incorrectly set
          * before the device has completed the "Page Select" MDI
          * transaction.  So we wait 200us after each MDI command...
          */
@@ -554,7 +561,8 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
         u16 phy_data;
         bool link;
 
-        /* Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
+        /*
+         * Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
          * forced whenever speed and duplex are forced.
          */
         ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
@@ -593,7 +601,8 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
                         return ret_val;
 
                 if (!link) {
-                        /* We didn't get link.
+                        /*
+                         * We didn't get link.
                          * Reset the DSP and cross our fingers.
                          */
                         ret_val = e1000e_phy_reset_dsp(hw);
@@ -612,7 +621,8 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
         if (ret_val)
                 return ret_val;
 
-        /* Resetting the phy means we need to verify the TX_CLK corresponds
+        /*
+         * Resetting the phy means we need to verify the TX_CLK corresponds
          * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
          */
         phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
@@ -621,7 +631,8 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
         else
                 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
 
-        /* In addition, we must re-enable CRS on Tx for both half and full
+        /*
+         * In addition, we must re-enable CRS on Tx for both half and full
          * duplex.
          */
         phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
@@ -704,7 +715,8 @@ static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
         u32 icr;
         s32 ret_val;
 
-        /* Prevent the PCI-E bus from sticking if there is no TLP connection
+        /*
+         * Prevent the PCI-E bus from sticking if there is no TLP connection
          * on the last TLP read/write transaction when MAC is reset.
          */
         ret_val = e1000e_disable_pcie_master(hw);
@@ -808,7 +820,8 @@ static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
         reg_data &= ~0x00100000;
         E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
 
-        /* Clear all of the statistics registers (clear on read).  It is
+        /*
+         * Clear all of the statistics registers (clear on read).  It is
          * important that we do this after we have tried to establish link
          * because the symbol error count will increment wildly if there
          * is no link.
@@ -881,7 +894,8 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
         if (ret_val)
                 return ret_val;
 
-        /* Options:
+        /*
+         * Options:
          *   MDI/MDI-X = 0 (default)
          *   0 - Auto for all speeds
          *   1 - MDI mode
@@ -907,7 +921,8 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
                 break;
         }
 
-        /* Options:
+        /*
+         * Options:
          *   disable_polarity_correction = 0 (default)
          *       Automatic Correction for Reversed Cable Polarity
          *   0 - Disabled
@@ -928,10 +943,9 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
                 return ret_val;
         }
 
-        /* Bypass RX and TX FIFO's */
-        ret_val = e1000e_write_kmrn_reg(hw,
-                                E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
-                                E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
+        /* Bypass Rx and Tx FIFO's */
+        ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
+                                        E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
                                         E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
         if (ret_val)
                 return ret_val;
@@ -953,7 +967,8 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
         if (ret_val)
                 return ret_val;
 
-        /* Do not init these registers when the HW is in IAMT mode, since the
+        /*
+         * Do not init these registers when the HW is in IAMT mode, since the
          * firmware will have already initialized them.  We only initialize
          * them if the HW is not in IAMT mode.
          */
@@ -974,7 +989,8 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
                         return ret_val;
         }
 
-        /* Workaround: Disable padding in Kumeran interface in the MAC
+        /*
+         * Workaround: Disable padding in Kumeran interface in the MAC
          * and in the PHY to avoid CRC errors.
          */
         ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
@@ -1007,9 +1023,11 @@ static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
         ew32(CTRL, ctrl);
 
-        /* Set the mac to wait the maximum time between each
+        /*
+         * Set the mac to wait the maximum time between each
          * iteration and increase the max iterations when
-         * polling the phy; this fixes erroneous timeouts at 10Mbps. */
+         * polling the phy; this fixes erroneous timeouts at 10Mbps.
+         */
         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
         if (ret_val)
                 return ret_val;
@@ -1026,9 +1044,8 @@ static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
         if (ret_val)
                 return ret_val;
         reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
-        ret_val = e1000e_write_kmrn_reg(hw,
-                                       E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
-                                       reg_data);
+        ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
+                                        reg_data);
         if (ret_val)
                 return ret_val;
 
@@ -1056,9 +1073,8 @@ static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
         u16 reg_data;
 
         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
-        ret_val = e1000e_write_kmrn_reg(hw,
-                                       E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
-                                       reg_data);
+        ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
+                                        reg_data);
         if (ret_val)
                 return ret_val;
 
@@ -1096,9 +1112,8 @@ static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
         u32 tipg;
 
         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
-        ret_val = e1000e_write_kmrn_reg(hw,
-                                       E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
-                                       reg_data);
+        ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
+                                        reg_data);
         if (ret_val)
                 return ret_val;