diff options
| author | Auke Kok <auke-jan.h.kok@intel.com> | 2008-02-21 18:11:07 -0500 |
|---|---|---|
| committer | Jeff Garzik <jeff@garzik.org> | 2008-02-24 00:07:50 -0500 |
| commit | 489815ce224e75c2fcd5ebdfaa740d7f9a4f20d3 (patch) | |
| tree | e59754bc14703bc13edce3d642d3681a07693385 /drivers/net/e1000e/defines.h | |
| parent | de92d84ec2305c490aa1db33f6e40680f8c236a8 (diff) | |
e1000e: fix spelling errors in comments
Fix some spelling errors and inconsistencies in comment blocks.
Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/e1000e/defines.h')
| -rw-r--r-- | drivers/net/e1000e/defines.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/net/e1000e/defines.h b/drivers/net/e1000e/defines.h index 6232c3e96689..a4f511f549f7 100644 --- a/drivers/net/e1000e/defines.h +++ b/drivers/net/e1000e/defines.h | |||
| @@ -66,7 +66,7 @@ | |||
| 66 | #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ | 66 | #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ |
| 67 | 67 | ||
| 68 | /* Extended Device Control */ | 68 | /* Extended Device Control */ |
| 69 | #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ | 69 | #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Definable Pin 7 */ |
| 70 | #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ | 70 | #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ |
| 71 | #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ | 71 | #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ |
| 72 | #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 | 72 | #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 |
| @@ -75,12 +75,12 @@ | |||
| 75 | #define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ | 75 | #define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ |
| 76 | #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ | 76 | #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ |
| 77 | 77 | ||
| 78 | /* Receive Decriptor bit definitions */ | 78 | /* Receive Descriptor bit definitions */ |
| 79 | #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ | 79 | #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ |
| 80 | #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ | 80 | #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ |
| 81 | #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ | 81 | #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ |
| 82 | #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ | 82 | #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ |
| 83 | #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */ | 83 | #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ |
| 84 | #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ | 84 | #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ |
| 85 | #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ | 85 | #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ |
| 86 | #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ | 86 | #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ |
| @@ -223,7 +223,7 @@ | |||
| 223 | #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */ | 223 | #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */ |
| 224 | #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ | 224 | #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ |
| 225 | 225 | ||
| 226 | /* Constants used to intrepret the masked PCI-X bus speed. */ | 226 | /* Constants used to interpret the masked PCI-X bus speed. */ |
| 227 | 227 | ||
| 228 | #define HALF_DUPLEX 1 | 228 | #define HALF_DUPLEX 1 |
| 229 | #define FULL_DUPLEX 2 | 229 | #define FULL_DUPLEX 2 |
| @@ -517,7 +517,7 @@ | |||
| 517 | /* PHY 1000 MII Register/Bit Definitions */ | 517 | /* PHY 1000 MII Register/Bit Definitions */ |
| 518 | /* PHY Registers defined by IEEE */ | 518 | /* PHY Registers defined by IEEE */ |
| 519 | #define PHY_CONTROL 0x00 /* Control Register */ | 519 | #define PHY_CONTROL 0x00 /* Control Register */ |
| 520 | #define PHY_STATUS 0x01 /* Status Regiser */ | 520 | #define PHY_STATUS 0x01 /* Status Register */ |
| 521 | #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ | 521 | #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ |
| 522 | #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ | 522 | #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ |
| 523 | #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ | 523 | #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ |