diff options
author | Bruce Allan <bruce.w.allan@intel.com> | 2008-03-28 12:15:03 -0400 |
---|---|---|
committer | Jeff Garzik <jeff@garzik.org> | 2008-03-28 22:14:56 -0400 |
commit | ad68076e07fa01bd0c98278a959d0fd2bb26f1ac (patch) | |
tree | f0b664ecdb38478f9b995aff10dcb39a09221fb6 /drivers/net/e1000e/82571.c | |
parent | 652f093fdf14c7ca1e13c052da429ae385e4dc21 (diff) |
e1000e: reformat comment blocks, cosmetic changes only
Adjusting the comment blocks here to be code-style compliant. no
code changes.
Changed some copyright dates to 2008.
Indentation fixes.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/e1000e/82571.c')
-rw-r--r-- | drivers/net/e1000e/82571.c | 105 |
1 files changed, 67 insertions, 38 deletions
diff --git a/drivers/net/e1000e/82571.c b/drivers/net/e1000e/82571.c index 7fe20310eb5f..c58dc2e8de1e 100644 --- a/drivers/net/e1000e/82571.c +++ b/drivers/net/e1000e/82571.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /******************************************************************************* | 1 | /******************************************************************************* |
2 | 2 | ||
3 | Intel PRO/1000 Linux driver | 3 | Intel PRO/1000 Linux driver |
4 | Copyright(c) 1999 - 2007 Intel Corporation. | 4 | Copyright(c) 1999 - 2008 Intel Corporation. |
5 | 5 | ||
6 | This program is free software; you can redistribute it and/or modify it | 6 | This program is free software; you can redistribute it and/or modify it |
7 | under the terms and conditions of the GNU General Public License, | 7 | under the terms and conditions of the GNU General Public License, |
@@ -29,6 +29,9 @@ | |||
29 | /* | 29 | /* |
30 | * 82571EB Gigabit Ethernet Controller | 30 | * 82571EB Gigabit Ethernet Controller |
31 | * 82571EB Gigabit Ethernet Controller (Fiber) | 31 | * 82571EB Gigabit Ethernet Controller (Fiber) |
32 | * 82571EB Dual Port Gigabit Mezzanine Adapter | ||
33 | * 82571EB Quad Port Gigabit Mezzanine Adapter | ||
34 | * 82571PT Gigabit PT Quad Port Server ExpressModule | ||
32 | * 82572EI Gigabit Ethernet Controller (Copper) | 35 | * 82572EI Gigabit Ethernet Controller (Copper) |
33 | * 82572EI Gigabit Ethernet Controller (Fiber) | 36 | * 82572EI Gigabit Ethernet Controller (Fiber) |
34 | * 82572EI Gigabit Ethernet Controller | 37 | * 82572EI Gigabit Ethernet Controller |
@@ -150,7 +153,8 @@ static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) | |||
150 | if (((eecd >> 15) & 0x3) == 0x3) { | 153 | if (((eecd >> 15) & 0x3) == 0x3) { |
151 | nvm->type = e1000_nvm_flash_hw; | 154 | nvm->type = e1000_nvm_flash_hw; |
152 | nvm->word_size = 2048; | 155 | nvm->word_size = 2048; |
153 | /* Autonomous Flash update bit must be cleared due | 156 | /* |
157 | * Autonomous Flash update bit must be cleared due | ||
154 | * to Flash update issue. | 158 | * to Flash update issue. |
155 | */ | 159 | */ |
156 | eecd &= ~E1000_EECD_AUPDEN; | 160 | eecd &= ~E1000_EECD_AUPDEN; |
@@ -159,10 +163,11 @@ static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) | |||
159 | } | 163 | } |
160 | /* Fall Through */ | 164 | /* Fall Through */ |
161 | default: | 165 | default: |
162 | nvm->type = e1000_nvm_eeprom_spi; | 166 | nvm->type = e1000_nvm_eeprom_spi; |
163 | size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> | 167 | size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> |
164 | E1000_EECD_SIZE_EX_SHIFT); | 168 | E1000_EECD_SIZE_EX_SHIFT); |
165 | /* Added to a constant, "size" becomes the left-shift value | 169 | /* |
170 | * Added to a constant, "size" becomes the left-shift value | ||
166 | * for setting word_size. | 171 | * for setting word_size. |
167 | */ | 172 | */ |
168 | size += NVM_WORD_SIZE_BASE_SHIFT; | 173 | size += NVM_WORD_SIZE_BASE_SHIFT; |
@@ -208,8 +213,7 @@ static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter) | |||
208 | /* Set rar entry count */ | 213 | /* Set rar entry count */ |
209 | mac->rar_entry_count = E1000_RAR_ENTRIES; | 214 | mac->rar_entry_count = E1000_RAR_ENTRIES; |
210 | /* Set if manageability features are enabled. */ | 215 | /* Set if manageability features are enabled. */ |
211 | mac->arc_subsystem_valid = | 216 | mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0; |
212 | (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0; | ||
213 | 217 | ||
214 | /* check for link */ | 218 | /* check for link */ |
215 | switch (hw->media_type) { | 219 | switch (hw->media_type) { |
@@ -219,14 +223,18 @@ static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter) | |||
219 | func->get_link_up_info = e1000e_get_speed_and_duplex_copper; | 223 | func->get_link_up_info = e1000e_get_speed_and_duplex_copper; |
220 | break; | 224 | break; |
221 | case e1000_media_type_fiber: | 225 | case e1000_media_type_fiber: |
222 | func->setup_physical_interface = e1000_setup_fiber_serdes_link_82571; | 226 | func->setup_physical_interface = |
227 | e1000_setup_fiber_serdes_link_82571; | ||
223 | func->check_for_link = e1000e_check_for_fiber_link; | 228 | func->check_for_link = e1000e_check_for_fiber_link; |
224 | func->get_link_up_info = e1000e_get_speed_and_duplex_fiber_serdes; | 229 | func->get_link_up_info = |
230 | e1000e_get_speed_and_duplex_fiber_serdes; | ||
225 | break; | 231 | break; |
226 | case e1000_media_type_internal_serdes: | 232 | case e1000_media_type_internal_serdes: |
227 | func->setup_physical_interface = e1000_setup_fiber_serdes_link_82571; | 233 | func->setup_physical_interface = |
234 | e1000_setup_fiber_serdes_link_82571; | ||
228 | func->check_for_link = e1000e_check_for_serdes_link; | 235 | func->check_for_link = e1000e_check_for_serdes_link; |
229 | func->get_link_up_info = e1000e_get_speed_and_duplex_fiber_serdes; | 236 | func->get_link_up_info = |
237 | e1000e_get_speed_and_duplex_fiber_serdes; | ||
230 | break; | 238 | break; |
231 | default: | 239 | default: |
232 | return -E1000_ERR_CONFIG; | 240 | return -E1000_ERR_CONFIG; |
@@ -322,10 +330,12 @@ static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) | |||
322 | switch (hw->mac.type) { | 330 | switch (hw->mac.type) { |
323 | case e1000_82571: | 331 | case e1000_82571: |
324 | case e1000_82572: | 332 | case e1000_82572: |
325 | /* The 82571 firmware may still be configuring the PHY. | 333 | /* |
334 | * The 82571 firmware may still be configuring the PHY. | ||
326 | * In this case, we cannot access the PHY until the | 335 | * In this case, we cannot access the PHY until the |
327 | * configuration is done. So we explicitly set the | 336 | * configuration is done. So we explicitly set the |
328 | * PHY ID. */ | 337 | * PHY ID. |
338 | */ | ||
329 | phy->id = IGP01E1000_I_PHY_ID; | 339 | phy->id = IGP01E1000_I_PHY_ID; |
330 | break; | 340 | break; |
331 | case e1000_82573: | 341 | case e1000_82573: |
@@ -479,8 +489,10 @@ static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) | |||
479 | if (ret_val) | 489 | if (ret_val) |
480 | return ret_val; | 490 | return ret_val; |
481 | 491 | ||
482 | /* If our nvm is an EEPROM, then we're done | 492 | /* |
483 | * otherwise, commit the checksum to the flash NVM. */ | 493 | * If our nvm is an EEPROM, then we're done |
494 | * otherwise, commit the checksum to the flash NVM. | ||
495 | */ | ||
484 | if (hw->nvm.type != e1000_nvm_flash_hw) | 496 | if (hw->nvm.type != e1000_nvm_flash_hw) |
485 | return ret_val; | 497 | return ret_val; |
486 | 498 | ||
@@ -496,7 +508,8 @@ static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) | |||
496 | 508 | ||
497 | /* Reset the firmware if using STM opcode. */ | 509 | /* Reset the firmware if using STM opcode. */ |
498 | if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) { | 510 | if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) { |
499 | /* The enabling of and the actual reset must be done | 511 | /* |
512 | * The enabling of and the actual reset must be done | ||
500 | * in two write cycles. | 513 | * in two write cycles. |
501 | */ | 514 | */ |
502 | ew32(HICR, E1000_HICR_FW_RESET_ENABLE); | 515 | ew32(HICR, E1000_HICR_FW_RESET_ENABLE); |
@@ -557,8 +570,10 @@ static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, | |||
557 | u32 eewr = 0; | 570 | u32 eewr = 0; |
558 | s32 ret_val = 0; | 571 | s32 ret_val = 0; |
559 | 572 | ||
560 | /* A check for invalid values: offset too large, too many words, | 573 | /* |
561 | * and not enough words. */ | 574 | * A check for invalid values: offset too large, too many words, |
575 | * and not enough words. | ||
576 | */ | ||
562 | if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || | 577 | if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || |
563 | (words == 0)) { | 578 | (words == 0)) { |
564 | hw_dbg(hw, "nvm parameter(s) out of bounds\n"); | 579 | hw_dbg(hw, "nvm parameter(s) out of bounds\n"); |
@@ -645,30 +660,32 @@ static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) | |||
645 | } else { | 660 | } else { |
646 | data &= ~IGP02E1000_PM_D0_LPLU; | 661 | data &= ~IGP02E1000_PM_D0_LPLU; |
647 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | 662 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); |
648 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used | 663 | /* |
664 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | ||
649 | * during Dx states where the power conservation is most | 665 | * during Dx states where the power conservation is most |
650 | * important. During driver activity we should enable | 666 | * important. During driver activity we should enable |
651 | * SmartSpeed, so performance is maintained. */ | 667 | * SmartSpeed, so performance is maintained. |
668 | */ | ||
652 | if (phy->smart_speed == e1000_smart_speed_on) { | 669 | if (phy->smart_speed == e1000_smart_speed_on) { |
653 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | 670 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
654 | &data); | 671 | &data); |
655 | if (ret_val) | 672 | if (ret_val) |
656 | return ret_val; | 673 | return ret_val; |
657 | 674 | ||
658 | data |= IGP01E1000_PSCFR_SMART_SPEED; | 675 | data |= IGP01E1000_PSCFR_SMART_SPEED; |
659 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | 676 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
660 | data); | 677 | data); |
661 | if (ret_val) | 678 | if (ret_val) |
662 | return ret_val; | 679 | return ret_val; |
663 | } else if (phy->smart_speed == e1000_smart_speed_off) { | 680 | } else if (phy->smart_speed == e1000_smart_speed_off) { |
664 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | 681 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
665 | &data); | 682 | &data); |
666 | if (ret_val) | 683 | if (ret_val) |
667 | return ret_val; | 684 | return ret_val; |
668 | 685 | ||
669 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | 686 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
670 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | 687 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
671 | data); | 688 | data); |
672 | if (ret_val) | 689 | if (ret_val) |
673 | return ret_val; | 690 | return ret_val; |
674 | } | 691 | } |
@@ -693,7 +710,8 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw) | |||
693 | s32 ret_val; | 710 | s32 ret_val; |
694 | u16 i = 0; | 711 | u16 i = 0; |
695 | 712 | ||
696 | /* Prevent the PCI-E bus from sticking if there is no TLP connection | 713 | /* |
714 | * Prevent the PCI-E bus from sticking if there is no TLP connection | ||
697 | * on the last TLP read/write transaction when MAC is reset. | 715 | * on the last TLP read/write transaction when MAC is reset. |
698 | */ | 716 | */ |
699 | ret_val = e1000e_disable_pcie_master(hw); | 717 | ret_val = e1000e_disable_pcie_master(hw); |
@@ -709,8 +727,10 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw) | |||
709 | 727 | ||
710 | msleep(10); | 728 | msleep(10); |
711 | 729 | ||
712 | /* Must acquire the MDIO ownership before MAC reset. | 730 | /* |
713 | * Ownership defaults to firmware after a reset. */ | 731 | * Must acquire the MDIO ownership before MAC reset. |
732 | * Ownership defaults to firmware after a reset. | ||
733 | */ | ||
714 | if (hw->mac.type == e1000_82573) { | 734 | if (hw->mac.type == e1000_82573) { |
715 | extcnf_ctrl = er32(EXTCNF_CTRL); | 735 | extcnf_ctrl = er32(EXTCNF_CTRL); |
716 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | 736 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; |
@@ -747,7 +767,8 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw) | |||
747 | /* We don't want to continue accessing MAC registers. */ | 767 | /* We don't want to continue accessing MAC registers. */ |
748 | return ret_val; | 768 | return ret_val; |
749 | 769 | ||
750 | /* Phy configuration from NVM just starts after EECD_AUTO_RD is set. | 770 | /* |
771 | * Phy configuration from NVM just starts after EECD_AUTO_RD is set. | ||
751 | * Need to wait for Phy configuration completion before accessing | 772 | * Need to wait for Phy configuration completion before accessing |
752 | * NVM and Phy. | 773 | * NVM and Phy. |
753 | */ | 774 | */ |
@@ -793,7 +814,8 @@ static s32 e1000_init_hw_82571(struct e1000_hw *hw) | |||
793 | e1000e_clear_vfta(hw); | 814 | e1000e_clear_vfta(hw); |
794 | 815 | ||
795 | /* Setup the receive address. */ | 816 | /* Setup the receive address. */ |
796 | /* If, however, a locally administered address was assigned to the | 817 | /* |
818 | * If, however, a locally administered address was assigned to the | ||
797 | * 82571, we must reserve a RAR for it to work around an issue where | 819 | * 82571, we must reserve a RAR for it to work around an issue where |
798 | * resetting one port will reload the MAC on the other port. | 820 | * resetting one port will reload the MAC on the other port. |
799 | */ | 821 | */ |
@@ -830,7 +852,8 @@ static s32 e1000_init_hw_82571(struct e1000_hw *hw) | |||
830 | ew32(GCR, reg_data); | 852 | ew32(GCR, reg_data); |
831 | } | 853 | } |
832 | 854 | ||
833 | /* Clear all of the statistics registers (clear on read). It is | 855 | /* |
856 | * Clear all of the statistics registers (clear on read). It is | ||
834 | * important that we do this after we have tried to establish link | 857 | * important that we do this after we have tried to establish link |
835 | * because the symbol error count will increment wildly if there | 858 | * because the symbol error count will increment wildly if there |
836 | * is no link. | 859 | * is no link. |
@@ -922,7 +945,8 @@ void e1000e_clear_vfta(struct e1000_hw *hw) | |||
922 | 945 | ||
923 | if (hw->mac.type == e1000_82573) { | 946 | if (hw->mac.type == e1000_82573) { |
924 | if (hw->mng_cookie.vlan_id != 0) { | 947 | if (hw->mng_cookie.vlan_id != 0) { |
925 | /* The VFTA is a 4096b bit-field, each identifying | 948 | /* |
949 | * The VFTA is a 4096b bit-field, each identifying | ||
926 | * a single VLAN ID. The following operations | 950 | * a single VLAN ID. The following operations |
927 | * determine which 32b entry (i.e. offset) into the | 951 | * determine which 32b entry (i.e. offset) into the |
928 | * array we want to set the VLAN ID (i.e. bit) of | 952 | * array we want to set the VLAN ID (i.e. bit) of |
@@ -936,7 +960,8 @@ void e1000e_clear_vfta(struct e1000_hw *hw) | |||
936 | } | 960 | } |
937 | } | 961 | } |
938 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { | 962 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { |
939 | /* If the offset we want to clear is the same offset of the | 963 | /* |
964 | * If the offset we want to clear is the same offset of the | ||
940 | * manageability VLAN ID, then clear all bits except that of | 965 | * manageability VLAN ID, then clear all bits except that of |
941 | * the manageability unit. | 966 | * the manageability unit. |
942 | */ | 967 | */ |
@@ -984,7 +1009,8 @@ static void e1000_mc_addr_list_update_82571(struct e1000_hw *hw, | |||
984 | **/ | 1009 | **/ |
985 | static s32 e1000_setup_link_82571(struct e1000_hw *hw) | 1010 | static s32 e1000_setup_link_82571(struct e1000_hw *hw) |
986 | { | 1011 | { |
987 | /* 82573 does not have a word in the NVM to determine | 1012 | /* |
1013 | * 82573 does not have a word in the NVM to determine | ||
988 | * the default flow control setting, so we explicitly | 1014 | * the default flow control setting, so we explicitly |
989 | * set it to full. | 1015 | * set it to full. |
990 | */ | 1016 | */ |
@@ -1050,14 +1076,14 @@ static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) | |||
1050 | switch (hw->mac.type) { | 1076 | switch (hw->mac.type) { |
1051 | case e1000_82571: | 1077 | case e1000_82571: |
1052 | case e1000_82572: | 1078 | case e1000_82572: |
1053 | /* If SerDes loopback mode is entered, there is no form | 1079 | /* |
1080 | * If SerDes loopback mode is entered, there is no form | ||
1054 | * of reset to take the adapter out of that mode. So we | 1081 | * of reset to take the adapter out of that mode. So we |
1055 | * have to explicitly take the adapter out of loopback | 1082 | * have to explicitly take the adapter out of loopback |
1056 | * mode. This prevents drivers from twiddling their thumbs | 1083 | * mode. This prevents drivers from twiddling their thumbs |
1057 | * if another tool failed to take it out of loopback mode. | 1084 | * if another tool failed to take it out of loopback mode. |
1058 | */ | 1085 | */ |
1059 | ew32(SCTL, | 1086 | ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); |
1060 | E1000_SCTL_DISABLE_SERDES_LOOPBACK); | ||
1061 | break; | 1087 | break; |
1062 | default: | 1088 | default: |
1063 | break; | 1089 | break; |
@@ -1124,7 +1150,8 @@ void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state) | |||
1124 | 1150 | ||
1125 | /* If workaround is activated... */ | 1151 | /* If workaround is activated... */ |
1126 | if (state) | 1152 | if (state) |
1127 | /* Hold a copy of the LAA in RAR[14] This is done so that | 1153 | /* |
1154 | * Hold a copy of the LAA in RAR[14] This is done so that | ||
1128 | * between the time RAR[0] gets clobbered and the time it | 1155 | * between the time RAR[0] gets clobbered and the time it |
1129 | * gets fixed, the actual LAA is in one of the RARs and no | 1156 | * gets fixed, the actual LAA is in one of the RARs and no |
1130 | * incoming packets directed to this port are dropped. | 1157 | * incoming packets directed to this port are dropped. |
@@ -1152,7 +1179,8 @@ static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) | |||
1152 | if (nvm->type != e1000_nvm_flash_hw) | 1179 | if (nvm->type != e1000_nvm_flash_hw) |
1153 | return 0; | 1180 | return 0; |
1154 | 1181 | ||
1155 | /* Check bit 4 of word 10h. If it is 0, firmware is done updating | 1182 | /* |
1183 | * Check bit 4 of word 10h. If it is 0, firmware is done updating | ||
1156 | * 10h-12h. Checksum may need to be fixed. | 1184 | * 10h-12h. Checksum may need to be fixed. |
1157 | */ | 1185 | */ |
1158 | ret_val = e1000_read_nvm(hw, 0x10, 1, &data); | 1186 | ret_val = e1000_read_nvm(hw, 0x10, 1, &data); |
@@ -1160,7 +1188,8 @@ static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) | |||
1160 | return ret_val; | 1188 | return ret_val; |
1161 | 1189 | ||
1162 | if (!(data & 0x10)) { | 1190 | if (!(data & 0x10)) { |
1163 | /* Read 0x23 and check bit 15. This bit is a 1 | 1191 | /* |
1192 | * Read 0x23 and check bit 15. This bit is a 1 | ||
1164 | * when the checksum has already been fixed. If | 1193 | * when the checksum has already been fixed. If |
1165 | * the checksum is still wrong and this bit is a | 1194 | * the checksum is still wrong and this bit is a |
1166 | * 1, we need to return bad checksum. Otherwise, | 1195 | * 1, we need to return bad checksum. Otherwise, |