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authorAuke Kok <auke-jan.h.kok@intel.com>2007-09-17 15:30:59 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2007-10-10 19:50:40 -0400
commitbc7f75fa97884d41efbfde1397b621fefb2550b4 (patch)
tree037910bdb72ae1c1fc179f47beb1f9d00803dbf5 /drivers/net/e1000e/82571.c
parentcbdb9e43d1fc50cfa509b1006e7252dc4ea53aa0 (diff)
[E1000E]: New pci-express e1000 driver (currently for ICH9 devices only)
This driver implements support for the ICH9 on-board LAN ethernet device. The device is similar to ICH8. The driver encompasses code to support 82571/2/3, es2lan and ICH8 devices as well, but those device IDs are disabled and will be "lifted" from the e1000 driver over one at a time once this driver receives some more live time. Changes to the last snapshot posted are exclusively in the internal hardware API organization. Many thanks to Jeff Garzik for jumping in and getting this organized with a keen eye on the future layout. [ Integrated napi_struct patch from Auke as well... -DaveM ] Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> Signed-off-by: Jeff Garzik <jeff@garzik.org> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/e1000e/82571.c')
-rw-r--r--drivers/net/e1000e/82571.c1351
1 files changed, 1351 insertions, 0 deletions
diff --git a/drivers/net/e1000e/82571.c b/drivers/net/e1000e/82571.c
new file mode 100644
index 000000000000..cf70522fc851
--- /dev/null
+++ b/drivers/net/e1000e/82571.c
@@ -0,0 +1,1351 @@
1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/*
30 * 82571EB Gigabit Ethernet Controller
31 * 82571EB Gigabit Ethernet Controller (Fiber)
32 * 82572EI Gigabit Ethernet Controller (Copper)
33 * 82572EI Gigabit Ethernet Controller (Fiber)
34 * 82572EI Gigabit Ethernet Controller
35 * 82573V Gigabit Ethernet Controller (Copper)
36 * 82573E Gigabit Ethernet Controller (Copper)
37 * 82573L Gigabit Ethernet Controller
38 */
39
40#include <linux/netdevice.h>
41#include <linux/delay.h>
42#include <linux/pci.h>
43
44#include "e1000.h"
45
46#define ID_LED_RESERVED_F746 0xF746
47#define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
48 (ID_LED_OFF1_ON2 << 8) | \
49 (ID_LED_DEF1_DEF2 << 4) | \
50 (ID_LED_DEF1_DEF2))
51
52#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
53
54static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
55static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
56static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
57static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
58 u16 words, u16 *data);
59static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
60static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
61static s32 e1000_setup_link_82571(struct e1000_hw *hw);
62static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
63
64/**
65 * e1000_init_phy_params_82571 - Init PHY func ptrs.
66 * @hw: pointer to the HW structure
67 *
68 * This is a function pointer entry point called by the api module.
69 **/
70static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
71{
72 struct e1000_phy_info *phy = &hw->phy;
73 s32 ret_val;
74
75 if (hw->media_type != e1000_media_type_copper) {
76 phy->type = e1000_phy_none;
77 return 0;
78 }
79
80 phy->addr = 1;
81 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
82 phy->reset_delay_us = 100;
83
84 switch (hw->mac.type) {
85 case e1000_82571:
86 case e1000_82572:
87 phy->type = e1000_phy_igp_2;
88 break;
89 case e1000_82573:
90 phy->type = e1000_phy_m88;
91 break;
92 default:
93 return -E1000_ERR_PHY;
94 break;
95 }
96
97 /* This can only be done after all function pointers are setup. */
98 ret_val = e1000_get_phy_id_82571(hw);
99
100 /* Verify phy id */
101 switch (hw->mac.type) {
102 case e1000_82571:
103 case e1000_82572:
104 if (phy->id != IGP01E1000_I_PHY_ID)
105 return -E1000_ERR_PHY;
106 break;
107 case e1000_82573:
108 if (phy->id != M88E1111_I_PHY_ID)
109 return -E1000_ERR_PHY;
110 break;
111 default:
112 return -E1000_ERR_PHY;
113 break;
114 }
115
116 return 0;
117}
118
119/**
120 * e1000_init_nvm_params_82571 - Init NVM func ptrs.
121 * @hw: pointer to the HW structure
122 *
123 * This is a function pointer entry point called by the api module.
124 **/
125static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
126{
127 struct e1000_nvm_info *nvm = &hw->nvm;
128 u32 eecd = er32(EECD);
129 u16 size;
130
131 nvm->opcode_bits = 8;
132 nvm->delay_usec = 1;
133 switch (nvm->override) {
134 case e1000_nvm_override_spi_large:
135 nvm->page_size = 32;
136 nvm->address_bits = 16;
137 break;
138 case e1000_nvm_override_spi_small:
139 nvm->page_size = 8;
140 nvm->address_bits = 8;
141 break;
142 default:
143 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
144 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
145 break;
146 }
147
148 switch (hw->mac.type) {
149 case e1000_82573:
150 if (((eecd >> 15) & 0x3) == 0x3) {
151 nvm->type = e1000_nvm_flash_hw;
152 nvm->word_size = 2048;
153 /* Autonomous Flash update bit must be cleared due
154 * to Flash update issue.
155 */
156 eecd &= ~E1000_EECD_AUPDEN;
157 ew32(EECD, eecd);
158 break;
159 }
160 /* Fall Through */
161 default:
162 nvm->type = e1000_nvm_eeprom_spi;
163 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
164 E1000_EECD_SIZE_EX_SHIFT);
165 /* Added to a constant, "size" becomes the left-shift value
166 * for setting word_size.
167 */
168 size += NVM_WORD_SIZE_BASE_SHIFT;
169 nvm->word_size = 1 << size;
170 break;
171 }
172
173 return 0;
174}
175
176/**
177 * e1000_init_mac_params_82571 - Init MAC func ptrs.
178 * @hw: pointer to the HW structure
179 *
180 * This is a function pointer entry point called by the api module.
181 **/
182static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter)
183{
184 struct e1000_hw *hw = &adapter->hw;
185 struct e1000_mac_info *mac = &hw->mac;
186 struct e1000_mac_operations *func = &mac->ops;
187
188 /* Set media type */
189 switch (adapter->pdev->device) {
190 case E1000_DEV_ID_82571EB_FIBER:
191 case E1000_DEV_ID_82572EI_FIBER:
192 case E1000_DEV_ID_82571EB_QUAD_FIBER:
193 hw->media_type = e1000_media_type_fiber;
194 break;
195 case E1000_DEV_ID_82571EB_SERDES:
196 case E1000_DEV_ID_82572EI_SERDES:
197 hw->media_type = e1000_media_type_internal_serdes;
198 break;
199 default:
200 hw->media_type = e1000_media_type_copper;
201 break;
202 }
203
204 /* Set mta register count */
205 mac->mta_reg_count = 128;
206 /* Set rar entry count */
207 mac->rar_entry_count = E1000_RAR_ENTRIES;
208 /* Set if manageability features are enabled. */
209 mac->arc_subsystem_valid =
210 (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0;
211
212 /* check for link */
213 switch (hw->media_type) {
214 case e1000_media_type_copper:
215 func->setup_physical_interface = e1000_setup_copper_link_82571;
216 func->check_for_link = e1000e_check_for_copper_link;
217 func->get_link_up_info = e1000e_get_speed_and_duplex_copper;
218 break;
219 case e1000_media_type_fiber:
220 func->setup_physical_interface = e1000_setup_fiber_serdes_link_82571;
221 func->check_for_link = e1000e_check_for_fiber_link;
222 func->get_link_up_info = e1000e_get_speed_and_duplex_fiber_serdes;
223 break;
224 case e1000_media_type_internal_serdes:
225 func->setup_physical_interface = e1000_setup_fiber_serdes_link_82571;
226 func->check_for_link = e1000e_check_for_serdes_link;
227 func->get_link_up_info = e1000e_get_speed_and_duplex_fiber_serdes;
228 break;
229 default:
230 return -E1000_ERR_CONFIG;
231 break;
232 }
233
234 return 0;
235}
236
237static s32 e1000_get_invariants_82571(struct e1000_adapter *adapter)
238{
239 struct e1000_hw *hw = &adapter->hw;
240 static int global_quad_port_a; /* global port a indication */
241 struct pci_dev *pdev = adapter->pdev;
242 u16 eeprom_data = 0;
243 int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
244 s32 rc;
245
246 rc = e1000_init_mac_params_82571(adapter);
247 if (rc)
248 return rc;
249
250 rc = e1000_init_nvm_params_82571(hw);
251 if (rc)
252 return rc;
253
254 rc = e1000_init_phy_params_82571(hw);
255 if (rc)
256 return rc;
257
258 /* tag quad port adapters first, it's used below */
259 switch (pdev->device) {
260 case E1000_DEV_ID_82571EB_QUAD_COPPER:
261 case E1000_DEV_ID_82571EB_QUAD_FIBER:
262 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
263 adapter->flags |= FLAG_IS_QUAD_PORT;
264 /* mark the first port */
265 if (global_quad_port_a == 0)
266 adapter->flags |= FLAG_IS_QUAD_PORT_A;
267 /* Reset for multiple quad port adapters */
268 global_quad_port_a++;
269 if (global_quad_port_a == 4)
270 global_quad_port_a = 0;
271 break;
272 default:
273 break;
274 }
275
276 switch (adapter->hw.mac.type) {
277 case e1000_82571:
278 /* these dual ports don't have WoL on port B at all */
279 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
280 (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
281 (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
282 (is_port_b))
283 adapter->flags &= ~FLAG_HAS_WOL;
284 /* quad ports only support WoL on port A */
285 if (adapter->flags & FLAG_IS_QUAD_PORT &&
286 (!adapter->flags & FLAG_IS_QUAD_PORT_A))
287 adapter->flags &= ~FLAG_HAS_WOL;
288 break;
289
290 case e1000_82573:
291 if (pdev->device == E1000_DEV_ID_82573L) {
292 e1000_read_nvm(&adapter->hw, NVM_INIT_3GIO_3, 1,
293 &eeprom_data);
294 if (eeprom_data & NVM_WORD1A_ASPM_MASK)
295 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
296 }
297 break;
298 default:
299 break;
300 }
301
302 return 0;
303}
304
305/**
306 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
307 * @hw: pointer to the HW structure
308 *
309 * Reads the PHY registers and stores the PHY ID and possibly the PHY
310 * revision in the hardware structure.
311 **/
312static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
313{
314 struct e1000_phy_info *phy = &hw->phy;
315
316 switch (hw->mac.type) {
317 case e1000_82571:
318 case e1000_82572:
319 /* The 82571 firmware may still be configuring the PHY.
320 * In this case, we cannot access the PHY until the
321 * configuration is done. So we explicitly set the
322 * PHY ID. */
323 phy->id = IGP01E1000_I_PHY_ID;
324 break;
325 case e1000_82573:
326 return e1000e_get_phy_id(hw);
327 break;
328 default:
329 return -E1000_ERR_PHY;
330 break;
331 }
332
333 return 0;
334}
335
336/**
337 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
338 * @hw: pointer to the HW structure
339 *
340 * Acquire the HW semaphore to access the PHY or NVM
341 **/
342static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
343{
344 u32 swsm;
345 s32 timeout = hw->nvm.word_size + 1;
346 s32 i = 0;
347
348 /* Get the FW semaphore. */
349 for (i = 0; i < timeout; i++) {
350 swsm = er32(SWSM);
351 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
352
353 /* Semaphore acquired if bit latched */
354 if (er32(SWSM) & E1000_SWSM_SWESMBI)
355 break;
356
357 udelay(50);
358 }
359
360 if (i == timeout) {
361 /* Release semaphores */
362 e1000e_put_hw_semaphore(hw);
363 hw_dbg(hw, "Driver can't access the NVM\n");
364 return -E1000_ERR_NVM;
365 }
366
367 return 0;
368}
369
370/**
371 * e1000_put_hw_semaphore_82571 - Release hardware semaphore
372 * @hw: pointer to the HW structure
373 *
374 * Release hardware semaphore used to access the PHY or NVM
375 **/
376static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
377{
378 u32 swsm;
379
380 swsm = er32(SWSM);
381
382 swsm &= ~E1000_SWSM_SWESMBI;
383
384 ew32(SWSM, swsm);
385}
386
387/**
388 * e1000_acquire_nvm_82571 - Request for access to the EEPROM
389 * @hw: pointer to the HW structure
390 *
391 * To gain access to the EEPROM, first we must obtain a hardware semaphore.
392 * Then for non-82573 hardware, set the EEPROM access request bit and wait
393 * for EEPROM access grant bit. If the access grant bit is not set, release
394 * hardware semaphore.
395 **/
396static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
397{
398 s32 ret_val;
399
400 ret_val = e1000_get_hw_semaphore_82571(hw);
401 if (ret_val)
402 return ret_val;
403
404 if (hw->mac.type != e1000_82573)
405 ret_val = e1000e_acquire_nvm(hw);
406
407 if (ret_val)
408 e1000_put_hw_semaphore_82571(hw);
409
410 return ret_val;
411}
412
413/**
414 * e1000_release_nvm_82571 - Release exclusive access to EEPROM
415 * @hw: pointer to the HW structure
416 *
417 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
418 **/
419static void e1000_release_nvm_82571(struct e1000_hw *hw)
420{
421 e1000e_release_nvm(hw);
422 e1000_put_hw_semaphore_82571(hw);
423}
424
425/**
426 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
427 * @hw: pointer to the HW structure
428 * @offset: offset within the EEPROM to be written to
429 * @words: number of words to write
430 * @data: 16 bit word(s) to be written to the EEPROM
431 *
432 * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
433 *
434 * If e1000e_update_nvm_checksum is not called after this function, the
435 * EEPROM will most likley contain an invalid checksum.
436 **/
437static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
438 u16 *data)
439{
440 s32 ret_val;
441
442 switch (hw->mac.type) {
443 case e1000_82573:
444 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
445 break;
446 case e1000_82571:
447 case e1000_82572:
448 ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
449 break;
450 default:
451 ret_val = -E1000_ERR_NVM;
452 break;
453 }
454
455 return ret_val;
456}
457
458/**
459 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum
460 * @hw: pointer to the HW structure
461 *
462 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
463 * up to the checksum. Then calculates the EEPROM checksum and writes the
464 * value to the EEPROM.
465 **/
466static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
467{
468 u32 eecd;
469 s32 ret_val;
470 u16 i;
471
472 ret_val = e1000e_update_nvm_checksum_generic(hw);
473 if (ret_val)
474 return ret_val;
475
476 /* If our nvm is an EEPROM, then we're done
477 * otherwise, commit the checksum to the flash NVM. */
478 if (hw->nvm.type != e1000_nvm_flash_hw)
479 return ret_val;
480
481 /* Check for pending operations. */
482 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
483 msleep(1);
484 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
485 break;
486 }
487
488 if (i == E1000_FLASH_UPDATES)
489 return -E1000_ERR_NVM;
490
491 /* Reset the firmware if using STM opcode. */
492 if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
493 /* The enabling of and the actual reset must be done
494 * in two write cycles.
495 */
496 ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
497 e1e_flush();
498 ew32(HICR, E1000_HICR_FW_RESET);
499 }
500
501 /* Commit the write to flash */
502 eecd = er32(EECD) | E1000_EECD_FLUPD;
503 ew32(EECD, eecd);
504
505 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
506 msleep(1);
507 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
508 break;
509 }
510
511 if (i == E1000_FLASH_UPDATES)
512 return -E1000_ERR_NVM;
513
514 return 0;
515}
516
517/**
518 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
519 * @hw: pointer to the HW structure
520 *
521 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
522 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
523 **/
524static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
525{
526 if (hw->nvm.type == e1000_nvm_flash_hw)
527 e1000_fix_nvm_checksum_82571(hw);
528
529 return e1000e_validate_nvm_checksum_generic(hw);
530}
531
532/**
533 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
534 * @hw: pointer to the HW structure
535 * @offset: offset within the EEPROM to be written to
536 * @words: number of words to write
537 * @data: 16 bit word(s) to be written to the EEPROM
538 *
539 * After checking for invalid values, poll the EEPROM to ensure the previous
540 * command has completed before trying to write the next word. After write
541 * poll for completion.
542 *
543 * If e1000e_update_nvm_checksum is not called after this function, the
544 * EEPROM will most likley contain an invalid checksum.
545 **/
546static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
547 u16 words, u16 *data)
548{
549 struct e1000_nvm_info *nvm = &hw->nvm;
550 u32 i;
551 u32 eewr = 0;
552 s32 ret_val = 0;
553
554 /* A check for invalid values: offset too large, too many words,
555 * and not enough words. */
556 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
557 (words == 0)) {
558 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
559 return -E1000_ERR_NVM;
560 }
561
562 for (i = 0; i < words; i++) {
563 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
564 ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
565 E1000_NVM_RW_REG_START;
566
567 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
568 if (ret_val)
569 break;
570
571 ew32(EEWR, eewr);
572
573 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
574 if (ret_val)
575 break;
576 }
577
578 return ret_val;
579}
580
581/**
582 * e1000_get_cfg_done_82571 - Poll for configuration done
583 * @hw: pointer to the HW structure
584 *
585 * Reads the management control register for the config done bit to be set.
586 **/
587static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
588{
589 s32 timeout = PHY_CFG_TIMEOUT;
590
591 while (timeout) {
592 if (er32(EEMNGCTL) &
593 E1000_NVM_CFG_DONE_PORT_0)
594 break;
595 msleep(1);
596 timeout--;
597 }
598 if (!timeout) {
599 hw_dbg(hw, "MNG configuration cycle has not completed.\n");
600 return -E1000_ERR_RESET;
601 }
602
603 return 0;
604}
605
606/**
607 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
608 * @hw: pointer to the HW structure
609 * @active: TRUE to enable LPLU, FALSE to disable
610 *
611 * Sets the LPLU D0 state according to the active flag. When activating LPLU
612 * this function also disables smart speed and vice versa. LPLU will not be
613 * activated unless the device autonegotiation advertisement meets standards
614 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function
615 * pointer entry point only called by PHY setup routines.
616 **/
617static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
618{
619 struct e1000_phy_info *phy = &hw->phy;
620 s32 ret_val;
621 u16 data;
622
623 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
624 if (ret_val)
625 return ret_val;
626
627 if (active) {
628 data |= IGP02E1000_PM_D0_LPLU;
629 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
630 if (ret_val)
631 return ret_val;
632
633 /* When LPLU is enabled, we should disable SmartSpeed */
634 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
635 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
636 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
637 if (ret_val)
638 return ret_val;
639 } else {
640 data &= ~IGP02E1000_PM_D0_LPLU;
641 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
642 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
643 * during Dx states where the power conservation is most
644 * important. During driver activity we should enable
645 * SmartSpeed, so performance is maintained. */
646 if (phy->smart_speed == e1000_smart_speed_on) {
647 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
648 &data);
649 if (ret_val)
650 return ret_val;
651
652 data |= IGP01E1000_PSCFR_SMART_SPEED;
653 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
654 data);
655 if (ret_val)
656 return ret_val;
657 } else if (phy->smart_speed == e1000_smart_speed_off) {
658 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
659 &data);
660 if (ret_val)
661 return ret_val;
662
663 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
664 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
665 data);
666 if (ret_val)
667 return ret_val;
668 }
669 }
670
671 return 0;
672}
673
674/**
675 * e1000_reset_hw_82571 - Reset hardware
676 * @hw: pointer to the HW structure
677 *
678 * This resets the hardware into a known state. This is a
679 * function pointer entry point called by the api module.
680 **/
681static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
682{
683 u32 ctrl;
684 u32 extcnf_ctrl;
685 u32 ctrl_ext;
686 u32 icr;
687 s32 ret_val;
688 u16 i = 0;
689
690 /* Prevent the PCI-E bus from sticking if there is no TLP connection
691 * on the last TLP read/write transaction when MAC is reset.
692 */
693 ret_val = e1000e_disable_pcie_master(hw);
694 if (ret_val)
695 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
696
697 hw_dbg(hw, "Masking off all interrupts\n");
698 ew32(IMC, 0xffffffff);
699
700 ew32(RCTL, 0);
701 ew32(TCTL, E1000_TCTL_PSP);
702 e1e_flush();
703
704 msleep(10);
705
706 /* Must acquire the MDIO ownership before MAC reset.
707 * Ownership defaults to firmware after a reset. */
708 if (hw->mac.type == e1000_82573) {
709 extcnf_ctrl = er32(EXTCNF_CTRL);
710 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
711
712 do {
713 ew32(EXTCNF_CTRL, extcnf_ctrl);
714 extcnf_ctrl = er32(EXTCNF_CTRL);
715
716 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
717 break;
718
719 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
720
721 msleep(2);
722 i++;
723 } while (i < MDIO_OWNERSHIP_TIMEOUT);
724 }
725
726 ctrl = er32(CTRL);
727
728 hw_dbg(hw, "Issuing a global reset to MAC\n");
729 ew32(CTRL, ctrl | E1000_CTRL_RST);
730
731 if (hw->nvm.type == e1000_nvm_flash_hw) {
732 udelay(10);
733 ctrl_ext = er32(CTRL_EXT);
734 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
735 ew32(CTRL_EXT, ctrl_ext);
736 e1e_flush();
737 }
738
739 ret_val = e1000e_get_auto_rd_done(hw);
740 if (ret_val)
741 /* We don't want to continue accessing MAC registers. */
742 return ret_val;
743
744 /* Phy configuration from NVM just starts after EECD_AUTO_RD is set.
745 * Need to wait for Phy configuration completion before accessing
746 * NVM and Phy.
747 */
748 if (hw->mac.type == e1000_82573)
749 msleep(25);
750
751 /* Clear any pending interrupt events. */
752 ew32(IMC, 0xffffffff);
753 icr = er32(ICR);
754
755 return 0;
756}
757
758/**
759 * e1000_init_hw_82571 - Initialize hardware
760 * @hw: pointer to the HW structure
761 *
762 * This inits the hardware readying it for operation.
763 **/
764static s32 e1000_init_hw_82571(struct e1000_hw *hw)
765{
766 struct e1000_mac_info *mac = &hw->mac;
767 u32 reg_data;
768 s32 ret_val;
769 u16 i;
770 u16 rar_count = mac->rar_entry_count;
771
772 e1000_initialize_hw_bits_82571(hw);
773
774 /* Initialize identification LED */
775 ret_val = e1000e_id_led_init(hw);
776 if (ret_val) {
777 hw_dbg(hw, "Error initializing identification LED\n");
778 return ret_val;
779 }
780
781 /* Disabling VLAN filtering */
782 hw_dbg(hw, "Initializing the IEEE VLAN\n");
783 e1000e_clear_vfta(hw);
784
785 /* Setup the receive address. */
786 /* If, however, a locally administered address was assigned to the
787 * 82571, we must reserve a RAR for it to work around an issue where
788 * resetting one port will reload the MAC on the other port.
789 */
790 if (e1000e_get_laa_state_82571(hw))
791 rar_count--;
792 e1000e_init_rx_addrs(hw, rar_count);
793
794 /* Zero out the Multicast HASH table */
795 hw_dbg(hw, "Zeroing the MTA\n");
796 for (i = 0; i < mac->mta_reg_count; i++)
797 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
798
799 /* Setup link and flow control */
800 ret_val = e1000_setup_link_82571(hw);
801
802 /* Set the transmit descriptor write-back policy */
803 reg_data = er32(TXDCTL);
804 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
805 E1000_TXDCTL_FULL_TX_DESC_WB |
806 E1000_TXDCTL_COUNT_DESC;
807 ew32(TXDCTL, reg_data);
808
809 /* ...for both queues. */
810 if (mac->type != e1000_82573) {
811 reg_data = er32(TXDCTL1);
812 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
813 E1000_TXDCTL_FULL_TX_DESC_WB |
814 E1000_TXDCTL_COUNT_DESC;
815 ew32(TXDCTL1, reg_data);
816 } else {
817 e1000e_enable_tx_pkt_filtering(hw);
818 reg_data = er32(GCR);
819 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
820 ew32(GCR, reg_data);
821 }
822
823 /* Clear all of the statistics registers (clear on read). It is
824 * important that we do this after we have tried to establish link
825 * because the symbol error count will increment wildly if there
826 * is no link.
827 */
828 e1000_clear_hw_cntrs_82571(hw);
829
830 return ret_val;
831}
832
833/**
834 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
835 * @hw: pointer to the HW structure
836 *
837 * Initializes required hardware-dependent bits needed for normal operation.
838 **/
839static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
840{
841 u32 reg;
842
843 /* Transmit Descriptor Control 0 */
844 reg = er32(TXDCTL);
845 reg |= (1 << 22);
846 ew32(TXDCTL, reg);
847
848 /* Transmit Descriptor Control 1 */
849 reg = er32(TXDCTL1);
850 reg |= (1 << 22);
851 ew32(TXDCTL1, reg);
852
853 /* Transmit Arbitration Control 0 */
854 reg = er32(TARC0);
855 reg &= ~(0xF << 27); /* 30:27 */
856 switch (hw->mac.type) {
857 case e1000_82571:
858 case e1000_82572:
859 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
860 break;
861 default:
862 break;
863 }
864 ew32(TARC0, reg);
865
866 /* Transmit Arbitration Control 1 */
867 reg = er32(TARC1);
868 switch (hw->mac.type) {
869 case e1000_82571:
870 case e1000_82572:
871 reg &= ~((1 << 29) | (1 << 30));
872 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
873 if (er32(TCTL) & E1000_TCTL_MULR)
874 reg &= ~(1 << 28);
875 else
876 reg |= (1 << 28);
877 ew32(TARC1, reg);
878 break;
879 default:
880 break;
881 }
882
883 /* Device Control */
884 if (hw->mac.type == e1000_82573) {
885 reg = er32(CTRL);
886 reg &= ~(1 << 29);
887 ew32(CTRL, reg);
888 }
889
890 /* Extended Device Control */
891 if (hw->mac.type == e1000_82573) {
892 reg = er32(CTRL_EXT);
893 reg &= ~(1 << 23);
894 reg |= (1 << 22);
895 ew32(CTRL_EXT, reg);
896 }
897}
898
899/**
900 * e1000e_clear_vfta - Clear VLAN filter table
901 * @hw: pointer to the HW structure
902 *
903 * Clears the register array which contains the VLAN filter table by
904 * setting all the values to 0.
905 **/
906void e1000e_clear_vfta(struct e1000_hw *hw)
907{
908 u32 offset;
909 u32 vfta_value = 0;
910 u32 vfta_offset = 0;
911 u32 vfta_bit_in_reg = 0;
912
913 if (hw->mac.type == e1000_82573) {
914 if (hw->mng_cookie.vlan_id != 0) {
915 /* The VFTA is a 4096b bit-field, each identifying
916 * a single VLAN ID. The following operations
917 * determine which 32b entry (i.e. offset) into the
918 * array we want to set the VLAN ID (i.e. bit) of
919 * the manageability unit.
920 */
921 vfta_offset = (hw->mng_cookie.vlan_id >>
922 E1000_VFTA_ENTRY_SHIFT) &
923 E1000_VFTA_ENTRY_MASK;
924 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
925 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
926 }
927 }
928 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
929 /* If the offset we want to clear is the same offset of the
930 * manageability VLAN ID, then clear all bits except that of
931 * the manageability unit.
932 */
933 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
934 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
935 e1e_flush();
936 }
937}
938
939/**
940 * e1000_mc_addr_list_update_82571 - Update Multicast addresses
941 * @hw: pointer to the HW structure
942 * @mc_addr_list: array of multicast addresses to program
943 * @mc_addr_count: number of multicast addresses to program
944 * @rar_used_count: the first RAR register free to program
945 * @rar_count: total number of supported Receive Address Registers
946 *
947 * Updates the Receive Address Registers and Multicast Table Array.
948 * The caller must have a packed mc_addr_list of multicast addresses.
949 * The parameter rar_count will usually be hw->mac.rar_entry_count
950 * unless there are workarounds that change this.
951 **/
952static void e1000_mc_addr_list_update_82571(struct e1000_hw *hw,
953 u8 *mc_addr_list,
954 u32 mc_addr_count,
955 u32 rar_used_count,
956 u32 rar_count)
957{
958 if (e1000e_get_laa_state_82571(hw))
959 rar_count--;
960
961 e1000e_mc_addr_list_update_generic(hw, mc_addr_list, mc_addr_count,
962 rar_used_count, rar_count);
963}
964
965/**
966 * e1000_setup_link_82571 - Setup flow control and link settings
967 * @hw: pointer to the HW structure
968 *
969 * Determines which flow control settings to use, then configures flow
970 * control. Calls the appropriate media-specific link configuration
971 * function. Assuming the adapter has a valid link partner, a valid link
972 * should be established. Assumes the hardware has previously been reset
973 * and the transmitter and receiver are not enabled.
974 **/
975static s32 e1000_setup_link_82571(struct e1000_hw *hw)
976{
977 /* 82573 does not have a word in the NVM to determine
978 * the default flow control setting, so we explicitly
979 * set it to full.
980 */
981 if (hw->mac.type == e1000_82573)
982 hw->mac.fc = e1000_fc_full;
983
984 return e1000e_setup_link(hw);
985}
986
987/**
988 * e1000_setup_copper_link_82571 - Configure copper link settings
989 * @hw: pointer to the HW structure
990 *
991 * Configures the link for auto-neg or forced speed and duplex. Then we check
992 * for link, once link is established calls to configure collision distance
993 * and flow control are called.
994 **/
995static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
996{
997 u32 ctrl;
998 u32 led_ctrl;
999 s32 ret_val;
1000
1001 ctrl = er32(CTRL);
1002 ctrl |= E1000_CTRL_SLU;
1003 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1004 ew32(CTRL, ctrl);
1005
1006 switch (hw->phy.type) {
1007 case e1000_phy_m88:
1008 ret_val = e1000e_copper_link_setup_m88(hw);
1009 break;
1010 case e1000_phy_igp_2:
1011 ret_val = e1000e_copper_link_setup_igp(hw);
1012 /* Setup activity LED */
1013 led_ctrl = er32(LEDCTL);
1014 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1015 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1016 ew32(LEDCTL, led_ctrl);
1017 break;
1018 default:
1019 return -E1000_ERR_PHY;
1020 break;
1021 }
1022
1023 if (ret_val)
1024 return ret_val;
1025
1026 ret_val = e1000e_setup_copper_link(hw);
1027
1028 return ret_val;
1029}
1030
1031/**
1032 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1033 * @hw: pointer to the HW structure
1034 *
1035 * Configures collision distance and flow control for fiber and serdes links.
1036 * Upon successful setup, poll for link.
1037 **/
1038static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1039{
1040 switch (hw->mac.type) {
1041 case e1000_82571:
1042 case e1000_82572:
1043 /* If SerDes loopback mode is entered, there is no form
1044 * of reset to take the adapter out of that mode. So we
1045 * have to explicitly take the adapter out of loopback
1046 * mode. This prevents drivers from twidling their thumbs
1047 * if another tool failed to take it out of loopback mode.
1048 */
1049 ew32(SCTL,
1050 E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1051 break;
1052 default:
1053 break;
1054 }
1055
1056 return e1000e_setup_fiber_serdes_link(hw);
1057}
1058
1059/**
1060 * e1000_valid_led_default_82571 - Verify a valid default LED config
1061 * @hw: pointer to the HW structure
1062 * @data: pointer to the NVM (EEPROM)
1063 *
1064 * Read the EEPROM for the current default LED configuration. If the
1065 * LED configuration is not valid, set to a valid LED configuration.
1066 **/
1067static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1068{
1069 s32 ret_val;
1070
1071 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1072 if (ret_val) {
1073 hw_dbg(hw, "NVM Read Error\n");
1074 return ret_val;
1075 }
1076
1077 if (hw->mac.type == e1000_82573 &&
1078 *data == ID_LED_RESERVED_F746)
1079 *data = ID_LED_DEFAULT_82573;
1080 else if (*data == ID_LED_RESERVED_0000 ||
1081 *data == ID_LED_RESERVED_FFFF)
1082 *data = ID_LED_DEFAULT;
1083
1084 return 0;
1085}
1086
1087/**
1088 * e1000e_get_laa_state_82571 - Get locally administered address state
1089 * @hw: pointer to the HW structure
1090 *
1091 * Retrieve and return the current locally administed address state.
1092 **/
1093bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1094{
1095 if (hw->mac.type != e1000_82571)
1096 return 0;
1097
1098 return hw->dev_spec.e82571.laa_is_present;
1099}
1100
1101/**
1102 * e1000e_set_laa_state_82571 - Set locally administered address state
1103 * @hw: pointer to the HW structure
1104 * @state: enable/disable locally administered address
1105 *
1106 * Enable/Disable the current locally administed address state.
1107 **/
1108void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1109{
1110 if (hw->mac.type != e1000_82571)
1111 return;
1112
1113 hw->dev_spec.e82571.laa_is_present = state;
1114
1115 /* If workaround is activated... */
1116 if (state)
1117 /* Hold a copy of the LAA in RAR[14] This is done so that
1118 * between the time RAR[0] gets clobbered and the time it
1119 * gets fixed, the actual LAA is in one of the RARs and no
1120 * incoming packets directed to this port are dropped.
1121 * Eventually the LAA will be in RAR[0] and RAR[14].
1122 */
1123 e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1);
1124}
1125
1126/**
1127 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1128 * @hw: pointer to the HW structure
1129 *
1130 * Verifies that the EEPROM has completed the update. After updating the
1131 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If
1132 * the checksum fix is not implemented, we need to set the bit and update
1133 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
1134 * we need to return bad checksum.
1135 **/
1136static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1137{
1138 struct e1000_nvm_info *nvm = &hw->nvm;
1139 s32 ret_val;
1140 u16 data;
1141
1142 if (nvm->type != e1000_nvm_flash_hw)
1143 return 0;
1144
1145 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
1146 * 10h-12h. Checksum may need to be fixed.
1147 */
1148 ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
1149 if (ret_val)
1150 return ret_val;
1151
1152 if (!(data & 0x10)) {
1153 /* Read 0x23 and check bit 15. This bit is a 1
1154 * when the checksum has already been fixed. If
1155 * the checksum is still wrong and this bit is a
1156 * 1, we need to return bad checksum. Otherwise,
1157 * we need to set this bit to a 1 and update the
1158 * checksum.
1159 */
1160 ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
1161 if (ret_val)
1162 return ret_val;
1163
1164 if (!(data & 0x8000)) {
1165 data |= 0x8000;
1166 ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
1167 if (ret_val)
1168 return ret_val;
1169 ret_val = e1000e_update_nvm_checksum(hw);
1170 }
1171 }
1172
1173 return 0;
1174}
1175
1176/**
1177 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1178 * @hw: pointer to the HW structure
1179 *
1180 * Clears the hardware counters by reading the counter registers.
1181 **/
1182static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1183{
1184 u32 temp;
1185
1186 e1000e_clear_hw_cntrs_base(hw);
1187
1188 temp = er32(PRC64);
1189 temp = er32(PRC127);
1190 temp = er32(PRC255);
1191 temp = er32(PRC511);
1192 temp = er32(PRC1023);
1193 temp = er32(PRC1522);
1194 temp = er32(PTC64);
1195 temp = er32(PTC127);
1196 temp = er32(PTC255);
1197 temp = er32(PTC511);
1198 temp = er32(PTC1023);
1199 temp = er32(PTC1522);
1200
1201 temp = er32(ALGNERRC);
1202 temp = er32(RXERRC);
1203 temp = er32(TNCRS);
1204 temp = er32(CEXTERR);
1205 temp = er32(TSCTC);
1206 temp = er32(TSCTFC);
1207
1208 temp = er32(MGTPRC);
1209 temp = er32(MGTPDC);
1210 temp = er32(MGTPTC);
1211
1212 temp = er32(IAC);
1213 temp = er32(ICRXOC);
1214
1215 temp = er32(ICRXPTC);
1216 temp = er32(ICRXATC);
1217 temp = er32(ICTXPTC);
1218 temp = er32(ICTXATC);
1219 temp = er32(ICTXQEC);
1220 temp = er32(ICTXQMTC);
1221 temp = er32(ICRXDMTC);
1222}
1223
1224static struct e1000_mac_operations e82571_mac_ops = {
1225 .mng_mode_enab = E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT,
1226 /* .check_for_link: media type dependent */
1227 .cleanup_led = e1000e_cleanup_led_generic,
1228 .clear_hw_cntrs = e1000_clear_hw_cntrs_82571,
1229 .get_bus_info = e1000e_get_bus_info_pcie,
1230 /* .get_link_up_info: media type dependent */
1231 .led_on = e1000e_led_on_generic,
1232 .led_off = e1000e_led_off_generic,
1233 .mc_addr_list_update = e1000_mc_addr_list_update_82571,
1234 .reset_hw = e1000_reset_hw_82571,
1235 .init_hw = e1000_init_hw_82571,
1236 .setup_link = e1000_setup_link_82571,
1237 /* .setup_physical_interface: media type dependent */
1238};
1239
1240static struct e1000_phy_operations e82_phy_ops_igp = {
1241 .acquire_phy = e1000_get_hw_semaphore_82571,
1242 .check_reset_block = e1000e_check_reset_block_generic,
1243 .commit_phy = NULL,
1244 .force_speed_duplex = e1000e_phy_force_speed_duplex_igp,
1245 .get_cfg_done = e1000_get_cfg_done_82571,
1246 .get_cable_length = e1000e_get_cable_length_igp_2,
1247 .get_phy_info = e1000e_get_phy_info_igp,
1248 .read_phy_reg = e1000e_read_phy_reg_igp,
1249 .release_phy = e1000_put_hw_semaphore_82571,
1250 .reset_phy = e1000e_phy_hw_reset_generic,
1251 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1252 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1253 .write_phy_reg = e1000e_write_phy_reg_igp,
1254};
1255
1256static struct e1000_phy_operations e82_phy_ops_m88 = {
1257 .acquire_phy = e1000_get_hw_semaphore_82571,
1258 .check_reset_block = e1000e_check_reset_block_generic,
1259 .commit_phy = e1000e_phy_sw_reset,
1260 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1261 .get_cfg_done = e1000e_get_cfg_done,
1262 .get_cable_length = e1000e_get_cable_length_m88,
1263 .get_phy_info = e1000e_get_phy_info_m88,
1264 .read_phy_reg = e1000e_read_phy_reg_m88,
1265 .release_phy = e1000_put_hw_semaphore_82571,
1266 .reset_phy = e1000e_phy_hw_reset_generic,
1267 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1268 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1269 .write_phy_reg = e1000e_write_phy_reg_m88,
1270};
1271
1272static struct e1000_nvm_operations e82571_nvm_ops = {
1273 .acquire_nvm = e1000_acquire_nvm_82571,
1274 .read_nvm = e1000e_read_nvm_spi,
1275 .release_nvm = e1000_release_nvm_82571,
1276 .update_nvm = e1000_update_nvm_checksum_82571,
1277 .valid_led_default = e1000_valid_led_default_82571,
1278 .validate_nvm = e1000_validate_nvm_checksum_82571,
1279 .write_nvm = e1000_write_nvm_82571,
1280};
1281
1282static struct e1000_nvm_operations e82573_nvm_ops = {
1283 .acquire_nvm = e1000_acquire_nvm_82571,
1284 .read_nvm = e1000e_read_nvm_eerd,
1285 .release_nvm = e1000_release_nvm_82571,
1286 .update_nvm = e1000_update_nvm_checksum_82571,
1287 .valid_led_default = e1000_valid_led_default_82571,
1288 .validate_nvm = e1000_validate_nvm_checksum_82571,
1289 .write_nvm = e1000_write_nvm_82571,
1290};
1291
1292struct e1000_info e1000_82571_info = {
1293 .mac = e1000_82571,
1294 .flags = FLAG_HAS_HW_VLAN_FILTER
1295 | FLAG_HAS_JUMBO_FRAMES
1296 | FLAG_HAS_STATS_PTC_PRC
1297 | FLAG_HAS_WOL
1298 | FLAG_APME_IN_CTRL3
1299 | FLAG_RX_CSUM_ENABLED
1300 | FLAG_HAS_CTRLEXT_ON_LOAD
1301 | FLAG_HAS_STATS_ICR_ICT
1302 | FLAG_HAS_SMART_POWER_DOWN
1303 | FLAG_RESET_OVERWRITES_LAA /* errata */
1304 | FLAG_TARC_SPEED_MODE_BIT /* errata */
1305 | FLAG_APME_CHECK_PORT_B,
1306 .pba = 38,
1307 .get_invariants = e1000_get_invariants_82571,
1308 .mac_ops = &e82571_mac_ops,
1309 .phy_ops = &e82_phy_ops_igp,
1310 .nvm_ops = &e82571_nvm_ops,
1311};
1312
1313struct e1000_info e1000_82572_info = {
1314 .mac = e1000_82572,
1315 .flags = FLAG_HAS_HW_VLAN_FILTER
1316 | FLAG_HAS_JUMBO_FRAMES
1317 | FLAG_HAS_STATS_PTC_PRC
1318 | FLAG_HAS_WOL
1319 | FLAG_APME_IN_CTRL3
1320 | FLAG_RX_CSUM_ENABLED
1321 | FLAG_HAS_CTRLEXT_ON_LOAD
1322 | FLAG_HAS_STATS_ICR_ICT
1323 | FLAG_TARC_SPEED_MODE_BIT, /* errata */
1324 .pba = 38,
1325 .get_invariants = e1000_get_invariants_82571,
1326 .mac_ops = &e82571_mac_ops,
1327 .phy_ops = &e82_phy_ops_igp,
1328 .nvm_ops = &e82571_nvm_ops,
1329};
1330
1331struct e1000_info e1000_82573_info = {
1332 .mac = e1000_82573,
1333 .flags = FLAG_HAS_HW_VLAN_FILTER
1334 | FLAG_HAS_JUMBO_FRAMES
1335 | FLAG_HAS_STATS_PTC_PRC
1336 | FLAG_HAS_WOL
1337 | FLAG_APME_IN_CTRL3
1338 | FLAG_RX_CSUM_ENABLED
1339 | FLAG_HAS_STATS_ICR_ICT
1340 | FLAG_HAS_SMART_POWER_DOWN
1341 | FLAG_HAS_AMT
1342 | FLAG_HAS_ASPM
1343 | FLAG_HAS_ERT
1344 | FLAG_HAS_SWSM_ON_LOAD,
1345 .pba = 20,
1346 .get_invariants = e1000_get_invariants_82571,
1347 .mac_ops = &e82571_mac_ops,
1348 .phy_ops = &e82_phy_ops_m88,
1349 .nvm_ops = &e82573_nvm_ops,
1350};
1351
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-05 06:09:13 -0500