e1000: add mmiowb() for IA64 to sync tail writes

IA64 SMP systems were seeing TX issues with multiple cpu's attempting
to write tail registers unordered. This mmiowb() fixes the issue.

Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>

1 files changed, 3 insertions, 0 deletions

diff --git a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c
index 93b97c6b8a63..681b738c6dac 100644
--- a/drivers/net/e1000/e1000_main.c
+++ b/drivers/net/e1000/e1000_main.c
@@ -2867,6 +2867,9 @@ e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
 
         tx_ring->next_to_use = i;
         writel(i, adapter->hw.hw_addr + tx_ring->tdt);
+        /* we need this if more than one processor can write to our tail
+         * at a time, it syncronizes IO on IA64/Altix systems */
+        mmiowb();
 }
 
 /**