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authorJeff Kirsher <jeffrey.t.kirsher@intel.com>2006-09-27 15:54:05 -0400
committerAuke Kok <juke-jan.h.kok@intel.com>2006-09-27 15:54:05 -0400
commit2a88c17371c3c263c28330093a4cd21bbeceb677 (patch)
treee0d91f7306f8a1accf737a0045b76bee339eb108 /drivers/net/e1000
parent1314bbf3a3d911218fc153e14873e2e384d08084 (diff)
e1000: rework polarity, NVM, eeprom code and fixes.
Several minor issues exist in the low-level device handling code of e1000. The NVM and EEPROM writing/reading code was updated which fixes unneeded delays, adds proper eeprom aqcuiring steps and handle shadow ram and flash access. Minor cosmetic adjustments to the polarity code adding symbols. PHY reset code mistakenly distinguished between MAC types instead of PHY types, and was fixes. Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>
Diffstat (limited to 'drivers/net/e1000')
-rw-r--r--drivers/net/e1000/e1000_hw.c290
-rw-r--r--drivers/net/e1000/e1000_hw.h10
2 files changed, 155 insertions, 145 deletions
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index 48aff8d054f9..65077f39da69 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -662,19 +662,12 @@ e1000_reset_hw(struct e1000_hw *hw)
662 E1000_WRITE_FLUSH(hw); 662 E1000_WRITE_FLUSH(hw);
663 } 663 }
664 /* fall through */ 664 /* fall through */
665 case e1000_82571: 665 default:
666 case e1000_82572: 666 /* Auto read done will delay 5ms or poll based on mac type */
667 case e1000_ich8lan:
668 case e1000_80003es2lan:
669 ret_val = e1000_get_auto_rd_done(hw); 667 ret_val = e1000_get_auto_rd_done(hw);
670 if (ret_val) 668 if (ret_val)
671 /* We don't want to continue accessing MAC registers. */
672 return ret_val; 669 return ret_val;
673 break; 670 break;
674 default:
675 /* Wait for EEPROM reload (it happens automatically) */
676 msleep(5);
677 break;
678 } 671 }
679 672
680 /* Disable HW ARPs on ASF enabled adapters */ 673 /* Disable HW ARPs on ASF enabled adapters */
@@ -3809,7 +3802,7 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3809 swfw = E1000_SWFW_PHY0_SM; 3802 swfw = E1000_SWFW_PHY0_SM;
3810 } 3803 }
3811 if (e1000_swfw_sync_acquire(hw, swfw)) { 3804 if (e1000_swfw_sync_acquire(hw, swfw)) {
3812 e1000_release_software_semaphore(hw); 3805 DEBUGOUT("Unable to acquire swfw sync\n");
3813 return -E1000_ERR_SWFW_SYNC; 3806 return -E1000_ERR_SWFW_SYNC;
3814 } 3807 }
3815 /* Read the device control register and assert the E1000_CTRL_PHY_RST 3808 /* Read the device control register and assert the E1000_CTRL_PHY_RST
@@ -3891,11 +3884,11 @@ e1000_phy_reset(struct e1000_hw *hw)
3891 if (ret_val) 3884 if (ret_val)
3892 return E1000_SUCCESS; 3885 return E1000_SUCCESS;
3893 3886
3894 switch (hw->mac_type) { 3887 switch (hw->phy_type) {
3895 case e1000_82541_rev_2: 3888 case e1000_phy_igp:
3896 case e1000_82571: 3889 case e1000_phy_igp_2:
3897 case e1000_82572: 3890 case e1000_phy_igp_3:
3898 case e1000_ich8lan: 3891 case e1000_phy_ife:
3899 ret_val = e1000_phy_hw_reset(hw); 3892 ret_val = e1000_phy_hw_reset(hw);
3900 if (ret_val) 3893 if (ret_val)
3901 return ret_val; 3894 return ret_val;
@@ -4043,6 +4036,9 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
4043 4036
4044 DEBUGFUNC("e1000_detect_gig_phy"); 4037 DEBUGFUNC("e1000_detect_gig_phy");
4045 4038
4039 if (hw->phy_id != 0)
4040 return E1000_SUCCESS;
4041
4046 /* The 82571 firmware may still be configuring the PHY. In this 4042 /* The 82571 firmware may still be configuring the PHY. In this
4047 * case, we cannot access the PHY until the configuration is done. So 4043 * case, we cannot access the PHY until the configuration is done. So
4048 * we explicitly set the PHY values. */ 4044 * we explicitly set the PHY values. */
@@ -4964,44 +4960,43 @@ e1000_read_eeprom(struct e1000_hw *hw,
4964{ 4960{
4965 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4961 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4966 uint32_t i = 0; 4962 uint32_t i = 0;
4967 int32_t ret_val;
4968 4963
4969 DEBUGFUNC("e1000_read_eeprom"); 4964 DEBUGFUNC("e1000_read_eeprom");
4970 4965
4966 /* If eeprom is not yet detected, do so now */
4967 if (eeprom->word_size == 0)
4968 e1000_init_eeprom_params(hw);
4969
4971 /* A check for invalid values: offset too large, too many words, and not 4970 /* A check for invalid values: offset too large, too many words, and not
4972 * enough words. 4971 * enough words.
4973 */ 4972 */
4974 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || 4973 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
4975 (words == 0)) { 4974 (words == 0)) {
4976 DEBUGOUT("\"words\" parameter out of bounds\n"); 4975 DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size);
4977 return -E1000_ERR_EEPROM; 4976 return -E1000_ERR_EEPROM;
4978 } 4977 }
4979 4978
4980 /* FLASH reads without acquiring the semaphore are safe */ 4979 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
4980 * directly. In this case, we need to acquire the EEPROM so that
4981 * FW or other port software does not interrupt.
4982 */
4981 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE && 4983 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
4982 hw->eeprom.use_eerd == FALSE) { 4984 hw->eeprom.use_eerd == FALSE) {
4983 switch (hw->mac_type) { 4985 /* Prepare the EEPROM for bit-bang reading */
4984 case e1000_80003es2lan: 4986 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4985 break; 4987 return -E1000_ERR_EEPROM;
4986 default:
4987 /* Prepare the EEPROM for reading */
4988 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4989 return -E1000_ERR_EEPROM;
4990 break;
4991 }
4992 } 4988 }
4993 4989
4994 if (eeprom->use_eerd == TRUE) { 4990 /* Eerd register EEPROM access requires no eeprom aquire/release */
4995 ret_val = e1000_read_eeprom_eerd(hw, offset, words, data); 4991 if (eeprom->use_eerd == TRUE)
4996 if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) || 4992 return e1000_read_eeprom_eerd(hw, offset, words, data);
4997 (hw->mac_type != e1000_82573))
4998 e1000_release_eeprom(hw);
4999 return ret_val;
5000 }
5001 4993
4994 /* ICH EEPROM access is done via the ICH flash controller */
5002 if (eeprom->type == e1000_eeprom_ich8) 4995 if (eeprom->type == e1000_eeprom_ich8)
5003 return e1000_read_eeprom_ich8(hw, offset, words, data); 4996 return e1000_read_eeprom_ich8(hw, offset, words, data);
5004 4997
4998 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
4999 * acquired the EEPROM at this point, so any returns should relase it */
5005 if (eeprom->type == e1000_eeprom_spi) { 5000 if (eeprom->type == e1000_eeprom_spi) {
5006 uint16_t word_in; 5001 uint16_t word_in;
5007 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 5002 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
@@ -5316,6 +5311,10 @@ e1000_write_eeprom(struct e1000_hw *hw,
5316 5311
5317 DEBUGFUNC("e1000_write_eeprom"); 5312 DEBUGFUNC("e1000_write_eeprom");
5318 5313
5314 /* If eeprom is not yet detected, do so now */
5315 if (eeprom->word_size == 0)
5316 e1000_init_eeprom_params(hw);
5317
5319 /* A check for invalid values: offset too large, too many words, and not 5318 /* A check for invalid values: offset too large, too many words, and not
5320 * enough words. 5319 * enough words.
5321 */ 5320 */
@@ -5521,10 +5520,8 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
5521 int32_t error = E1000_SUCCESS; 5520 int32_t error = E1000_SUCCESS;
5522 uint32_t old_bank_offset = 0; 5521 uint32_t old_bank_offset = 0;
5523 uint32_t new_bank_offset = 0; 5522 uint32_t new_bank_offset = 0;
5524 uint32_t sector_retries = 0;
5525 uint8_t low_byte = 0; 5523 uint8_t low_byte = 0;
5526 uint8_t high_byte = 0; 5524 uint8_t high_byte = 0;
5527 uint8_t temp_byte = 0;
5528 boolean_t sector_write_failed = FALSE; 5525 boolean_t sector_write_failed = FALSE;
5529 5526
5530 if (hw->mac_type == e1000_82573) { 5527 if (hw->mac_type == e1000_82573) {
@@ -5577,41 +5574,46 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
5577 e1000_erase_ich8_4k_segment(hw, 0); 5574 e1000_erase_ich8_4k_segment(hw, 0);
5578 } 5575 }
5579 5576
5580 do { 5577 sector_write_failed = FALSE;
5581 sector_write_failed = FALSE; 5578 /* Loop for every byte in the shadow RAM,
5582 /* Loop for every byte in the shadow RAM, 5579 * which is in units of words. */
5583 * which is in units of words. */ 5580 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5584 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 5581 /* Determine whether to write the value stored
5585 /* Determine whether to write the value stored 5582 * in the other NVM bank or a modified value stored
5586 * in the other NVM bank or a modified value stored 5583 * in the shadow RAM */
5587 * in the shadow RAM */ 5584 if (hw->eeprom_shadow_ram[i].modified == TRUE) {
5588 if (hw->eeprom_shadow_ram[i].modified == TRUE) { 5585 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word;
5589 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word; 5586 udelay(100);
5590 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset, 5587 error = e1000_verify_write_ich8_byte(hw,
5591 &temp_byte); 5588 (i << 1) + new_bank_offset, low_byte);
5592 udelay(100); 5589
5593 error = e1000_verify_write_ich8_byte(hw, 5590 if (error != E1000_SUCCESS)
5594 (i << 1) + new_bank_offset, 5591 sector_write_failed = TRUE;
5595 low_byte); 5592 else {
5596 if (error != E1000_SUCCESS)
5597 sector_write_failed = TRUE;
5598 high_byte = 5593 high_byte =
5599 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8); 5594 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
5600 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5601 &temp_byte);
5602 udelay(100);
5603 } else {
5604 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5605 &low_byte);
5606 udelay(100); 5595 udelay(100);
5607 error = e1000_verify_write_ich8_byte(hw, 5596 }
5608 (i << 1) + new_bank_offset, low_byte); 5597 } else {
5609 if (error != E1000_SUCCESS) 5598 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5610 sector_write_failed = TRUE; 5599 &low_byte);
5600 udelay(100);
5601 error = e1000_verify_write_ich8_byte(hw,
5602 (i << 1) + new_bank_offset, low_byte);
5603
5604 if (error != E1000_SUCCESS)
5605 sector_write_failed = TRUE;
5606 else {
5611 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1, 5607 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5612 &high_byte); 5608 &high_byte);
5609 udelay(100);
5613 } 5610 }
5611 }
5614 5612
5613 /* If the write of the low byte was successful, go ahread and
5614 * write the high byte while checking to make sure that if it
5615 * is the signature byte, then it is handled properly */
5616 if (sector_write_failed == FALSE) {
5615 /* If the word is 0x13, then make sure the signature bits 5617 /* If the word is 0x13, then make sure the signature bits
5616 * (15:14) are 11b until the commit has completed. 5618 * (15:14) are 11b until the commit has completed.
5617 * This will allow us to write 10b which indicates the 5619 * This will allow us to write 10b which indicates the
@@ -5622,45 +5624,45 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
5622 high_byte = E1000_ICH8_NVM_SIG_MASK | high_byte; 5624 high_byte = E1000_ICH8_NVM_SIG_MASK | high_byte;
5623 5625
5624 error = e1000_verify_write_ich8_byte(hw, 5626 error = e1000_verify_write_ich8_byte(hw,
5625 (i << 1) + new_bank_offset + 1, high_byte); 5627 (i << 1) + new_bank_offset + 1, high_byte);
5626 if (error != E1000_SUCCESS) 5628 if (error != E1000_SUCCESS)
5627 sector_write_failed = TRUE; 5629 sector_write_failed = TRUE;
5628 5630
5629 if (sector_write_failed == FALSE) { 5631 } else {
5630 /* Clear the now not used entry in the cache */ 5632 /* If the write failed then break from the loop and
5631 hw->eeprom_shadow_ram[i].modified = FALSE; 5633 * return an error */
5632 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; 5634 break;
5633 }
5634 } 5635 }
5636 }
5635 5637
5636 /* Don't bother writing the segment valid bits if sector 5638 /* Don't bother writing the segment valid bits if sector
5637 * programming failed. */ 5639 * programming failed. */
5638 if (sector_write_failed == FALSE) { 5640 if (sector_write_failed == FALSE) {
5639 /* Finally validate the new segment by setting bit 15:14 5641 /* Finally validate the new segment by setting bit 15:14
5640 * to 10b in word 0x13 , this can be done without an 5642 * to 10b in word 0x13 , this can be done without an
5641 * erase as well since these bits are 11 to start with 5643 * erase as well since these bits are 11 to start with
5642 * and we need to change bit 14 to 0b */ 5644 * and we need to change bit 14 to 0b */
5643 e1000_read_ich8_byte(hw, 5645 e1000_read_ich8_byte(hw,
5644 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset, 5646 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5645 &high_byte); 5647 &high_byte);
5646 high_byte &= 0xBF; 5648 high_byte &= 0xBF;
5649 error = e1000_verify_write_ich8_byte(hw,
5650 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte);
5651 /* And invalidate the previously valid segment by setting
5652 * its signature word (0x13) high_byte to 0b. This can be
5653 * done without an erase because flash erase sets all bits
5654 * to 1's. We can write 1's to 0's without an erase */
5655 if (error == E1000_SUCCESS) {
5647 error = e1000_verify_write_ich8_byte(hw, 5656 error = e1000_verify_write_ich8_byte(hw,
5648 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset, 5657 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0);
5649 high_byte); 5658 }
5650 if (error != E1000_SUCCESS)
5651 sector_write_failed = TRUE;
5652 5659
5653 /* And invalidate the previously valid segment by setting 5660 /* Clear the now not used entry in the cache */
5654 * its signature word (0x13) high_byte to 0b. This can be 5661 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5655 * done without an erase because flash erase sets all bits 5662 hw->eeprom_shadow_ram[i].modified = FALSE;
5656 * to 1's. We can write 1's to 0's without an erase */ 5663 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
5657 error = e1000_verify_write_ich8_byte(hw,
5658 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + old_bank_offset,
5659 0);
5660 if (error != E1000_SUCCESS)
5661 sector_write_failed = TRUE;
5662 } 5664 }
5663 } while (++sector_retries < 10 && sector_write_failed == TRUE); 5665 }
5664 } 5666 }
5665 5667
5666 return error; 5668 return error;
@@ -8758,20 +8760,22 @@ static int32_t
8758e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte) 8760e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte)
8759{ 8761{
8760 int32_t error = E1000_SUCCESS; 8762 int32_t error = E1000_SUCCESS;
8761 int32_t program_retries; 8763 int32_t program_retries = 0;
8762 uint8_t temp_byte;
8763 8764
8764 e1000_write_ich8_byte(hw, index, byte); 8765 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index);
8765 udelay(100);
8766 8766
8767 for (program_retries = 0; program_retries < 100; program_retries++) { 8767 error = e1000_write_ich8_byte(hw, index, byte);
8768 e1000_read_ich8_byte(hw, index, &temp_byte); 8768
8769 if (temp_byte == byte) 8769 if (error != E1000_SUCCESS) {
8770 break; 8770 for (program_retries = 0; program_retries < 100; program_retries++) {
8771 udelay(10); 8771 DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", byte, index);
8772 e1000_write_ich8_byte(hw, index, byte); 8772 error = e1000_write_ich8_byte(hw, index, byte);
8773 udelay(100); 8773 udelay(100);
8774 if (error == E1000_SUCCESS)
8775 break;
8776 }
8774 } 8777 }
8778
8775 if (program_retries == 100) 8779 if (program_retries == 100)
8776 error = E1000_ERR_EEPROM; 8780 error = E1000_ERR_EEPROM;
8777 8781
@@ -8812,39 +8816,27 @@ e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data)
8812} 8816}
8813 8817
8814/****************************************************************************** 8818/******************************************************************************
8815 * Writes a word to the NVM using the ICH8 flash access registers. 8819 * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0
8820 * based.
8816 * 8821 *
8817 * hw - pointer to e1000_hw structure 8822 * hw - pointer to e1000_hw structure
8818 * index - The starting byte index of the word to read. 8823 * bank - 0 for first bank, 1 for second bank
8819 * data - The word to write to the NVM.
8820 *****************************************************************************/
8821#if 0
8822int32_t
8823e1000_write_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t data)
8824{
8825 int32_t status = E1000_SUCCESS;
8826 status = e1000_write_ich8_data(hw, index, 2, data);
8827 return status;
8828}
8829#endif /* 0 */
8830
8831/******************************************************************************
8832 * Erases the bank specified. Each bank is a 4k block. Segments are 0 based.
8833 * segment N is 4096 * N + flash_reg_addr.
8834 * 8824 *
8835 * hw - pointer to e1000_hw structure 8825 * Note that this function may actually erase as much as 8 or 64 KBytes. The
8836 * segment - 0 for first segment, 1 for second segment, etc. 8826 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the
8827 * bank size may be 4, 8 or 64 KBytes
8837 *****************************************************************************/ 8828 *****************************************************************************/
8838static int32_t 8829int32_t
8839e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t segment) 8830e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank)
8840{ 8831{
8841 union ich8_hws_flash_status hsfsts; 8832 union ich8_hws_flash_status hsfsts;
8842 union ich8_hws_flash_ctrl hsflctl; 8833 union ich8_hws_flash_ctrl hsflctl;
8843 uint32_t flash_linear_address; 8834 uint32_t flash_linear_address;
8844 int32_t count = 0; 8835 int32_t count = 0;
8845 int32_t error = E1000_ERR_EEPROM; 8836 int32_t error = E1000_ERR_EEPROM;
8846 int32_t iteration, seg_size; 8837 int32_t iteration;
8847 int32_t sector_size; 8838 int32_t sub_sector_size = 0;
8839 int32_t bank_size;
8848 int32_t j = 0; 8840 int32_t j = 0;
8849 int32_t error_flag = 0; 8841 int32_t error_flag = 0;
8850 8842
@@ -8853,22 +8845,27 @@ e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t segment)
8853 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */ 8845 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
8854 /* 00: The Hw sector is 256 bytes, hence we need to erase 16 8846 /* 00: The Hw sector is 256 bytes, hence we need to erase 16
8855 * consecutive sectors. The start index for the nth Hw sector can be 8847 * consecutive sectors. The start index for the nth Hw sector can be
8856 * calculated as = segment * 4096 + n * 256 8848 * calculated as bank * 4096 + n * 256
8857 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 8849 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
8858 * The start index for the nth Hw sector can be calculated 8850 * The start index for the nth Hw sector can be calculated
8859 * as = segment * 4096 8851 * as bank * 4096
8860 * 10: Error condition 8852 * 10: The HW sector is 8K bytes
8861 * 11: The Hw sector size is much bigger than the size asked to 8853 * 11: The Hw sector size is 64K bytes */
8862 * erase...error condition */
8863 if (hsfsts.hsf_status.berasesz == 0x0) { 8854 if (hsfsts.hsf_status.berasesz == 0x0) {
8864 /* Hw sector size 256 */ 8855 /* Hw sector size 256 */
8865 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_256; 8856 sub_sector_size = ICH8_FLASH_SEG_SIZE_256;
8857 bank_size = ICH8_FLASH_SECTOR_SIZE;
8866 iteration = ICH8_FLASH_SECTOR_SIZE / ICH8_FLASH_SEG_SIZE_256; 8858 iteration = ICH8_FLASH_SECTOR_SIZE / ICH8_FLASH_SEG_SIZE_256;
8867 } else if (hsfsts.hsf_status.berasesz == 0x1) { 8859 } else if (hsfsts.hsf_status.berasesz == 0x1) {
8868 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_4K; 8860 bank_size = ICH8_FLASH_SEG_SIZE_4K;
8861 iteration = 1;
8862 } else if (hw->mac_type != e1000_ich8lan &&
8863 hsfsts.hsf_status.berasesz == 0x2) {
8864 /* 8K erase size invalid for ICH8 - added in for ICH9 */
8865 bank_size = ICH9_FLASH_SEG_SIZE_8K;
8869 iteration = 1; 8866 iteration = 1;
8870 } else if (hsfsts.hsf_status.berasesz == 0x3) { 8867 } else if (hsfsts.hsf_status.berasesz == 0x3) {
8871 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_64K; 8868 bank_size = ICH8_FLASH_SEG_SIZE_64K;
8872 iteration = 1; 8869 iteration = 1;
8873 } else { 8870 } else {
8874 return error; 8871 return error;
@@ -8892,16 +8889,15 @@ e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t segment)
8892 8889
8893 /* Write the last 24 bits of an index within the block into Flash 8890 /* Write the last 24 bits of an index within the block into Flash
8894 * Linear address field in Flash Address. This probably needs to 8891 * Linear address field in Flash Address. This probably needs to
8895 * be calculated here based off the on-chip segment size and the 8892 * be calculated here based off the on-chip erase sector size and
8896 * software segment size assumed (4K) */ 8893 * the software bank size (4, 8 or 64 KBytes) */
8897 /* TBD */ 8894 flash_linear_address = bank * bank_size + j * sub_sector_size;
8898 flash_linear_address = segment * sector_size + j * seg_size;
8899 flash_linear_address &= ICH8_FLASH_LINEAR_ADDR_MASK;
8900 flash_linear_address += hw->flash_base_addr; 8895 flash_linear_address += hw->flash_base_addr;
8896 flash_linear_address &= ICH8_FLASH_LINEAR_ADDR_MASK;
8901 8897
8902 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address); 8898 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8903 8899
8904 error = e1000_ich8_flash_cycle(hw, 1000000); 8900 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_ERASE_TIMEOUT);
8905 /* Check if FCERR is set to 1. If 1, clear it and try the whole 8901 /* Check if FCERR is set to 1. If 1, clear it and try the whole
8906 * sequence a few more times else Done */ 8902 * sequence a few more times else Done */
8907 if (error == E1000_SUCCESS) { 8903 if (error == E1000_SUCCESS) {
@@ -8959,6 +8955,14 @@ e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
8959} 8955}
8960 8956
8961 8957
8958/******************************************************************************
8959 * This function initializes the PHY from the NVM on ICH8 platforms. This
8960 * is needed due to an issue where the NVM configuration is not properly
8961 * autoloaded after power transitions. Therefore, after each PHY reset, we
8962 * will load the configuration data out of the NVM manually.
8963 *
8964 * hw: Struct containing variables accessed by shared code
8965 *****************************************************************************/
8962static int32_t 8966static int32_t
8963e1000_init_lcd_from_nvm(struct e1000_hw *hw) 8967e1000_init_lcd_from_nvm(struct e1000_hw *hw)
8964{ 8968{
diff --git a/drivers/net/e1000/e1000_hw.h b/drivers/net/e1000/e1000_hw.h
index a523ffab3527..112447fd8bf2 100644
--- a/drivers/net/e1000/e1000_hw.h
+++ b/drivers/net/e1000/e1000_hw.h
@@ -301,6 +301,9 @@ typedef enum {
301#define E1000_BLK_PHY_RESET 12 301#define E1000_BLK_PHY_RESET 12
302#define E1000_ERR_SWFW_SYNC 13 302#define E1000_ERR_SWFW_SYNC 13
303 303
304#define E1000_BYTE_SWAP_WORD(_value) ((((_value) & 0x00ff) << 8) | \
305 (((_value) & 0xff00) >> 8))
306
304/* Function prototypes */ 307/* Function prototypes */
305/* Initialization */ 308/* Initialization */
306int32_t e1000_reset_hw(struct e1000_hw *hw); 309int32_t e1000_reset_hw(struct e1000_hw *hw);
@@ -3128,6 +3131,7 @@ struct e1000_host_command_info {
3128/* I = Integrated 3131/* I = Integrated
3129 * E = External 3132 * E = External
3130 */ 3133 */
3134#define M88_VENDOR 0x0141
3131#define M88E1000_E_PHY_ID 0x01410C50 3135#define M88E1000_E_PHY_ID 0x01410C50
3132#define M88E1000_I_PHY_ID 0x01410C30 3136#define M88E1000_I_PHY_ID 0x01410C30
3133#define M88E1011_I_PHY_ID 0x01410C20 3137#define M88E1011_I_PHY_ID 0x01410C20
@@ -3252,10 +3256,12 @@ struct e1000_host_command_info {
3252#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ 3256#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
3253#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ 3257#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
3254 3258
3255#define ICH8_FLASH_COMMAND_TIMEOUT 500 /* 500 ms , should be adjusted */ 3259#define ICH8_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */
3256#define ICH8_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles , should be adjusted */ 3260#define ICH8_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */
3261#define ICH8_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */
3257#define ICH8_FLASH_SEG_SIZE_256 256 3262#define ICH8_FLASH_SEG_SIZE_256 256
3258#define ICH8_FLASH_SEG_SIZE_4K 4096 3263#define ICH8_FLASH_SEG_SIZE_4K 4096
3264#define ICH9_FLASH_SEG_SIZE_8K 8192
3259#define ICH8_FLASH_SEG_SIZE_64K 65536 3265#define ICH8_FLASH_SEG_SIZE_64K 65536
3260 3266
3261#define ICH8_CYCLE_READ 0x0 3267#define ICH8_CYCLE_READ 0x0